// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
// Date        : Tue May 18 10:14:36 2021
// Host        : justin-desktop running 64-bit unknown
// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mig_7series_0_sim_netlist.v
// Design      : mig_7series_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a100tftg256-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
   (ddr3_dq,
    ddr3_dqs_n,
    ddr3_dqs_p,
    ddr3_addr,
    ddr3_ba,
    ddr3_ras_n,
    ddr3_cas_n,
    ddr3_we_n,
    ddr3_reset_n,
    ddr3_ck_p,
    ddr3_ck_n,
    ddr3_cke,
    ddr3_cs_n,
    ddr3_dm,
    ddr3_odt,
    sys_clk_i,
    clk_ref_i,
    app_addr,
    app_cmd,
    app_en,
    app_wdf_data,
    app_wdf_end,
    app_wdf_mask,
    app_wdf_wren,
    app_rd_data,
    app_rd_data_end,
    app_rd_data_valid,
    app_rdy,
    app_wdf_rdy,
    app_sr_req,
    app_ref_req,
    app_zq_req,
    app_sr_active,
    app_ref_ack,
    app_zq_ack,
    ui_clk,
    ui_clk_sync_rst,
    init_calib_complete,
    device_temp,
    sys_rst);
  inout [15:0]ddr3_dq;
  inout [1:0]ddr3_dqs_n;
  inout [1:0]ddr3_dqs_p;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output ddr3_ras_n;
  output ddr3_cas_n;
  output ddr3_we_n;
  output ddr3_reset_n;
  output [0:0]ddr3_ck_p;
  output [0:0]ddr3_ck_n;
  output [0:0]ddr3_cke;
  output [0:0]ddr3_cs_n;
  output [1:0]ddr3_dm;
  output [0:0]ddr3_odt;
  input sys_clk_i;
  input clk_ref_i;
  input [27:0]app_addr;
  input [2:0]app_cmd;
  input app_en;
  input [127:0]app_wdf_data;
  input app_wdf_end;
  input [15:0]app_wdf_mask;
  input app_wdf_wren;
  output [127:0]app_rd_data;
  output app_rd_data_end;
  output app_rd_data_valid;
  output app_rdy;
  output app_wdf_rdy;
  input app_sr_req;
  input app_ref_req;
  input app_zq_req;
  output app_sr_active;
  output app_ref_ack;
  output app_zq_ack;
  output ui_clk;
  output ui_clk_sync_rst;
  output init_calib_complete;
  output [11:0]device_temp;
  input sys_rst;

  wire [27:0]app_addr;
  wire [2:0]app_cmd;
  wire app_en;
  wire [127:0]app_rd_data;
  wire app_rd_data_end;
  wire app_rd_data_valid;
  wire app_rdy;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire [127:0]app_wdf_data;
  wire app_wdf_end;
  wire [15:0]app_wdf_mask;
  wire app_wdf_rdy;
  wire app_wdf_wren;
  wire app_zq_ack;
  wire app_zq_req;
  wire clk_ref_i;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [13:0]ddr3_addr;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [2:0]ddr3_ba;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire ddr3_cas_n;
  (* SLEW = "SLOW" *) wire [0:0]ddr3_ck_n;
  (* SLEW = "SLOW" *) wire [0:0]ddr3_ck_p;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [0:0]ddr3_cke;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [0:0]ddr3_cs_n;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [1:0]ddr3_dm;
  (* DRIVE = "12" *) (* IBUF_LOW_PWR = 0 *) (* SLEW = "SLOW" *) wire [15:0]ddr3_dq;
  (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) (* SLEW = "SLOW" *) wire [1:0]ddr3_dqs_n;
  (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) (* SLEW = "SLOW" *) wire [1:0]ddr3_dqs_p;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [0:0]ddr3_odt;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire ddr3_ras_n;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire ddr3_reset_n;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire ddr3_we_n;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_1 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_3 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_3 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_4 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_5 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_0 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_1 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1 ;
  wire [11:0]device_temp;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete;
  wire sys_clk_i;
  wire sys_rst;
  wire [40:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address ;
  wire [8:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank ;
  wire [1:1]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cas_n ;
  wire [3:3]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke ;
  wire [1:1]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cs_n ;
  wire [1:1]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_ras_n ;
  wire [1:1]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_we_n ;
  wire [127:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata ;
  wire [75:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr ;
  wire [1:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in ;
  (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ;
  wire [1:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ;
  wire [79:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;
  wire [79:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r ;
  wire [1:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in ;
  (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ;
  wire [1:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ;
  wire [79:8]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ;
  wire [3:0]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ;
  wire [79:6]\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r ;
  wire u_mig_7series_0_mig_n_11;
  wire u_mig_7series_0_mig_n_111;
  wire u_mig_7series_0_mig_n_112;
  wire u_mig_7series_0_mig_n_113;
  wire u_mig_7series_0_mig_n_114;
  wire u_mig_7series_0_mig_n_115;
  wire u_mig_7series_0_mig_n_116;
  wire u_mig_7series_0_mig_n_117;
  wire u_mig_7series_0_mig_n_118;
  wire u_mig_7series_0_mig_n_12;
  wire u_mig_7series_0_mig_n_13;
  wire u_mig_7series_0_mig_n_14;
  wire u_mig_7series_0_mig_n_18;
  wire u_mig_7series_0_mig_n_183;
  wire u_mig_7series_0_mig_n_184;
  wire u_mig_7series_0_mig_n_185;
  wire u_mig_7series_0_mig_n_186;
  wire u_mig_7series_0_mig_n_187;
  wire u_mig_7series_0_mig_n_188;
  wire u_mig_7series_0_mig_n_189;
  wire u_mig_7series_0_mig_n_19;
  wire u_mig_7series_0_mig_n_190;
  wire u_mig_7series_0_mig_n_20;
  wire u_mig_7series_0_mig_n_21;
  wire u_mig_7series_0_mig_n_63;
  wire u_mig_7series_0_mig_n_67;
  wire u_mig_7series_0_mig_n_71;
  wire u_mig_7series_0_mig_n_73;
  wire u_mig_7series_0_mig_n_74;
  wire u_mig_7series_0_mig_n_76;
  wire u_mig_7series_0_mig_n_77;
  wire u_mig_7series_0_mig_n_79;
  wire u_mig_7series_0_mig_n_81;
  wire u_mig_7series_0_mig_n_85;
  wire u_mig_7series_0_mig_n_89;
  wire u_mig_7series_0_mig_n_94;
  wire u_mig_7series_0_mig_n_95;
  wire u_mig_7series_0_mig_n_99;
  wire ui_clk;
  wire ui_clk_sync_rst;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOA_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOA_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOA_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOA_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOA_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOA_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOA_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED ;
  wire [1:0]\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED ;

  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [5],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [2]}),
        .DIB({u_mig_7series_0_mig_n_99,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [8]}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [1:0]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [3:2]),
        .DOC(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cs_n ,u_mig_7series_0_mig_n_94}),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOA_UNCONNECTED [1:0]),
        .DOB(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOB_UNCONNECTED [1:0]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [17:16]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b1,u_mig_7series_0_mig_n_77}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [19:18]),
        .DOB(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOB_UNCONNECTED [1:0]),
        .DOC(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [17],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [3]}),
        .DIB({u_mig_7series_0_mig_n_89,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [31]}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [25:24]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [27:26]),
        .DOC(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [26],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [12]}),
        .DIC({u_mig_7series_0_mig_n_85,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [40]}),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOA_UNCONNECTED [1:0]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [33:32]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [35:34]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [14],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [0]}),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOA_UNCONNECTED [1:0]),
        .DOB(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOB_UNCONNECTED [1:0]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [41:40]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({u_mig_7series_0_mig_n_81,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [28]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke ,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke }),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke ,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke }),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [43:42]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [45:44]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [47:46]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_ras_n ,u_mig_7series_0_mig_n_79}),
        .DIB({1'b1,u_mig_7series_0_mig_n_77}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cas_n ,u_mig_7series_0_mig_n_76}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [49:48]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [51:50]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [53:52]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b1,u_mig_7series_0_mig_n_74}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_we_n ,u_mig_7series_0_mig_n_73}),
        .DIC({1'b1,u_mig_7series_0_mig_n_71}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [55:54]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [57:56]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [59:58]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [3],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [0]}),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOA_UNCONNECTED [1:0]),
        .DOB(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOB_UNCONNECTED [1:0]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [65:64]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({u_mig_7series_0_mig_n_67,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [6]}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [67:66]),
        .DOB(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOB_UNCONNECTED [1:0]),
        .DOC(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [4],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [1]}),
        .DIC({u_mig_7series_0_mig_n_95,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [7]}),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOA_UNCONNECTED [1:0]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [9:8]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [11:10]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 
       (.ADDRA({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRB({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRC({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr }),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [24],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [10]}),
        .DIB({u_mig_7series_0_mig_n_63,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [38]}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [73:72]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [75:74]),
        .DOC(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [1:0]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [3:2]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [5:4]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [1:0]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [3:2]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [5:4]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_0_5_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [13:12]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [15:14]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [17:16]),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_1 }),
        .DOB({\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_2 ,\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_n_3 }),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [17:16]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [19:18]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [21:20]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [23:22]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [19:18]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [21:20]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [23:22]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [25:24]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [27:26]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [29:28]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [25:24]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [27:26]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [29:28]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [31:30]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [33:32]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [35:34]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [31:30]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [33:32]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [35:34]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [37:36]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [39:38]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [41:40]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [37:36]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [39:38]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [41:40]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [43:42]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [45:44]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [47:46]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [43:42]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [45:44]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [47:46]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [49:48]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [51:50]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [53:52]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [49:48]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [51:50]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [53:52]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [55:54]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [57:56]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [59:58]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [55:54]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [57:56]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [59:58]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [61:60]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [63:62]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [65:64]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [61:60]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [63:62]),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [7:6]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [9:8]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [11:10]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [7:6]),
        .DOB({\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_2 ,\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_3 }),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [73:72]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [75:74]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [77:76]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [73:72]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [75:74]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [77:76]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [79:78]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [79:78]),
        .DOB(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOB_UNCONNECTED [1:0]),
        .DOC(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [20],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [4]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [52],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [36]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [84],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [68]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_1 }),
        .DOB({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_2 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_3 }),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_0_5_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [22],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [6]}),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOA_UNCONNECTED [1:0]),
        .DOB(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOB_UNCONNECTED [1:0]),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [54],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [38]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [86],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [70]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [118],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [102]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 }),
        .DOB({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 }),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [19],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [3]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [51],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [35]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [83],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [67]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 }),
        .DOB({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 }),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [115],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [99]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [17],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [1]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [49],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [33]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 }),
        .DOB({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 }),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [81],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [65]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [113],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [97]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [21],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [5]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 }),
        .DOB({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 }),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [53],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [37]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [85],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [69]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [117],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [101]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 }),
        .DOB({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 }),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [18],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [2]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [50],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [34]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [82],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [66]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 }),
        .DOB({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 }),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [114],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [98]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [23],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [7]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [55],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [39]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 }),
        .DOB({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 }),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [87],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [71]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [119],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [103]}),
        .DIC({u_mig_7series_0_mig_n_117,u_mig_7series_0_mig_n_118}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1 }),
        .DOB({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3 }),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({u_mig_7series_0_mig_n_115,u_mig_7series_0_mig_n_116}),
        .DIB({u_mig_7series_0_mig_n_113,u_mig_7series_0_mig_n_114}),
        .DIC({u_mig_7series_0_mig_n_111,u_mig_7series_0_mig_n_112}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1 }),
        .DOB({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3 }),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [116],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [100]}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_1 }),
        .DOB(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOB_UNCONNECTED [1:0]),
        .DOC(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [16],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [0]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [48],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [32]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [80],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [64]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1 }),
        .DOB({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3 }),
        .DOC({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5 }),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_14,u_mig_7series_0_mig_n_13,u_mig_7series_0_mig_n_12,u_mig_7series_0_mig_n_11}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [112],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [96]}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0 ,\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1 }),
        .DOB(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED [1:0]),
        .DOC(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [13:12]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [15:14]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [17:16]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [13:12]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [15:14]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [17:16]),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [19:18]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [21:20]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [23:22]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [19:18]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [21:20]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [23:22]),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [25:24]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [27:26]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [29:28]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [25:24]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [27:26]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [29:28]),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [31:30]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [33:32]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [35:34]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [31:30]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [33:32]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [35:34]),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [37:36]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [39:38]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [41:40]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [37:36]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [39:38]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [41:40]),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [43:42]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [45:44]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [47:46]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [43:42]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [45:44]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [47:46]),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [49:48]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [51:50]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [53:52]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [49:48]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [51:50]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [53:52]),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [55:54]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [57:56]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [59:58]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [55:54]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [57:56]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [59:58]),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [61:60]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [63:62]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [65:64]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [61:60]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [63:62]),
        .DOC({\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_n_5 }),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [7:6]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [9:8]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [11:10]),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_n_1 }),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [9:8]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [11:10]),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [73:72]),
        .DIB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [75:74]),
        .DIC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [77:76]),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [73:72]),
        .DOB(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [75:74]),
        .DOC(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [77:76]),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_72_77_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79 
       (.ADDRA({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRB({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRC({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in }),
        .ADDRD({1'b0,1'b0,1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr }),
        .DIA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [79:78]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [79:78]),
        .DOB(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOB_UNCONNECTED [1:0]),
        .DOC(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg_0_3_78_79_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [88],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [72]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [120],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [104]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [28],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [12]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1 }),
        .DOB({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3 }),
        .DOC({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 }),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [60],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [44]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [92],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [76]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [124],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [108]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 }),
        .DOB({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 }),
        .DOC({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 }),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [30],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [14]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [62],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [46]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [94],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [78]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 }),
        .DOB({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 }),
        .DOC({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 }),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [126],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [110]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [25],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [9]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [57],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [41]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 }),
        .DOB({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 }),
        .DOC({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 }),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [89],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [73]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [121],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [105]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [27],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [11]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 }),
        .DOB({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 }),
        .DOC({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 }),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [59],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [43]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [91],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [75]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [123],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [107]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 }),
        .DOB({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 }),
        .DOC({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 }),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [31],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [15]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [63],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [47]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [95],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [79]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_1 }),
        .DOB({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_3 }),
        .DOC({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_n_5 }),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [127],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [111]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [29],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [13]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [61],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [45]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_1 }),
        .DOB({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_3 }),
        .DOC({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_n_5 }),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [93],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [77]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [125],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [109]}),
        .DIC({u_mig_7series_0_mig_n_189,u_mig_7series_0_mig_n_190}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_1 }),
        .DOB({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_3 }),
        .DOC({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_n_5 }),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_60_65_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({u_mig_7series_0_mig_n_187,u_mig_7series_0_mig_n_188}),
        .DIB({u_mig_7series_0_mig_n_185,u_mig_7series_0_mig_n_186}),
        .DIC({u_mig_7series_0_mig_n_183,u_mig_7series_0_mig_n_184}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_1 }),
        .DOB({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_3 }),
        .DOC({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_n_5 }),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({1'b0,1'b0}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [24],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [8]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [56],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [40]}),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOA_UNCONNECTED [1:0]),
        .DOB({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3 }),
        .DOC({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5 }),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [26],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [10]}),
        .DIB({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [58],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [42]}),
        .DIC({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [90],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [74]}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_1 }),
        .DOB({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_3 }),
        .DOC({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_n_5 }),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79 
       (.ADDRA({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRB({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRC({1'b0,u_mig_7series_0_mig_n_21,u_mig_7series_0_mig_n_20,u_mig_7series_0_mig_n_19,u_mig_7series_0_mig_n_18}),
        .ADDRD({1'b0,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr }),
        .DIA({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [122],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [106]}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_n_1 }),
        .DOB(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOB_UNCONNECTED [1:0]),
        .DOC(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOC_UNCONNECTED [1:0]),
        .DOD(\NLW_ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_78_79_DOD_UNCONNECTED [1:0]),
        .WCLK(ui_clk),
        .WE(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_0_mig u_mig_7series_0_mig
       (.CLKB0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),
        .CLKB0_4(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ),
        .Q(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ),
        .app_addr(app_addr[26:0]),
        .app_cmd(app_cmd[1:0]),
        .app_en(app_en),
        .app_rd_data(app_rd_data),
        .\app_rd_data[112] ({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [79:72],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [63:16],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [7:0]}),
        .app_rd_data_end(app_rd_data_end),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rdy_r_reg(app_rdy),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_wdf_data(app_wdf_data),
        .app_wdf_end(app_wdf_end),
        .app_wdf_mask(app_wdf_mask),
        .app_wdf_rdy(app_wdf_rdy),
        .app_wdf_wren(app_wdf_wren),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .clk_ref_i(clk_ref_i),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out({ddr3_ck_n,ddr3_ck_p}),
        .\device_temp_r_reg[11] (device_temp),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [79:72],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/rd_data_r [65:0]}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [79:72],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/rd_data_r [65:6]}),
        .\gen_mmcm.mmcm_i (ui_clk),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [79:72],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_out [63:8]}),
        .init_calib_complete(init_calib_complete),
        .init_calib_complete_reg_rep__0({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [112],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [96],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [80],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [64],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [48],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [32],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [16],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [0],u_mig_7series_0_mig_n_111,u_mig_7series_0_mig_n_112,u_mig_7series_0_mig_n_113,u_mig_7series_0_mig_n_114,u_mig_7series_0_mig_n_115,u_mig_7series_0_mig_n_116,u_mig_7series_0_mig_n_117,u_mig_7series_0_mig_n_118,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [119],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [103],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [87],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [71],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [55],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [39],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [23],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [7],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [114],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [98],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [82],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [66],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [50],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [34],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [18],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [2],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [117],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [101],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [85],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [69],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [53],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [37],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [21],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [5],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [113],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [97],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [81],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [65],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [49],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [33],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [17],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [1],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [115],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [99],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [83],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [67],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [51],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [35],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [19],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [3],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [118],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [102],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [86],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [70],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [54],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [38],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [22],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [6],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [116],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [100],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [84],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [68],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [52],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [36],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [20],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [4]}),
        .iserdes_clk(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),
        .iserdes_clk_0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ),
        .mem_out({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [75:72],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [67:64],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [59:40],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [35:32],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [27:24],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [19:16],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [11:8],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_out [3:0]}),
        .out(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in ),
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,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_5 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_3 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_42_47_n_1 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_5 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_3 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_36_41_n_1 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_5 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_3 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35_n_1 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_5 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_3 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29_n_1 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_5 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_3 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_18_23_n_1 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_5 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_3 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_0 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_12_17_n_1 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_4 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_5 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_2 ,\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_6_11_n_3 }),
        .p_1_in(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en ),
        .phy_dout({u_mig_7series_0_mig_n_63,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [38],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [24],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [10],u_mig_7series_0_mig_n_67,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [6],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [3],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [0],u_mig_7series_0_mig_n_71,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_we_n ,u_mig_7series_0_mig_n_73,u_mig_7series_0_mig_n_74,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cas_n ,u_mig_7series_0_mig_n_76,u_mig_7series_0_mig_n_77,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_ras_n ,u_mig_7series_0_mig_n_79,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cke ,u_mig_7series_0_mig_n_81,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [28],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [14],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [0],u_mig_7series_0_mig_n_85,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [40],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [26],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [12],u_mig_7series_0_mig_n_89,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [31],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [17],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_address [3],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_cs_n ,u_mig_7series_0_mig_n_94,u_mig_7series_0_mig_n_95,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [7],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [4],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [1],u_mig_7series_0_mig_n_99,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [8],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [5],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_bank [2]}),
        .rd_ptr(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/rd_ptr ),
        .\rd_ptr_reg[0] (u_mig_7series_0_mig_n_11),
        .\rd_ptr_reg[0]_0 (u_mig_7series_0_mig_n_18),
        .\rd_ptr_reg[1] (u_mig_7series_0_mig_n_12),
        .\rd_ptr_reg[1]_0 (u_mig_7series_0_mig_n_19),
        .\rd_ptr_reg[2] (u_mig_7series_0_mig_n_13),
        .\rd_ptr_reg[2]_0 (u_mig_7series_0_mig_n_20),
        .\rd_ptr_reg[3] (u_mig_7series_0_mig_n_14),
        .\rd_ptr_reg[3]_0 (u_mig_7series_0_mig_n_21),
        .\rd_ptr_timing_reg[1] (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/p_0_in ),
        .rstdiv0_sync_r1_reg_rep(ui_clk_sync_rst),
        .sys_clk_i(sys_clk_i),
        .sys_rst(sys_rst),
        .wr_en(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),
        .wr_en_2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),
        .wr_en_3(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en ),
        .wr_ptr(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr ),
        .wr_ptr_1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_ptr ),
        .\wr_ptr_reg[3] (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ),
        .\wr_ptr_reg[3]_0 (\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr ),
        .\write_buffer.wr_buf_out_data_reg[122] ({\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [122],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [106],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [90],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [74],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [58],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [42],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [26],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [10],u_mig_7series_0_mig_n_183,u_mig_7series_0_mig_n_184,u_mig_7series_0_mig_n_185,u_mig_7series_0_mig_n_186,u_mig_7series_0_mig_n_187,u_mig_7series_0_mig_n_188,u_mig_7series_0_mig_n_189,u_mig_7series_0_mig_n_190,\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [125],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [109],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [93],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [77],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [61],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [45],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [29],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [13],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [127],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [111],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [95],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [79],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [63],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [47],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [31],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [15],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [123],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [107],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [91],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [75],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [59],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [43],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [27],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [11],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [121],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [105],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [89],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [73],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [57],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [41],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [25],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [9],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [126],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [110],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [94],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [78],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [62],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [46],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [30],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [14],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [124],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [108],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [92],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [76],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [60],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [44],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [28],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [12],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [120],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [104],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [88],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [72],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [56],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [40],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [24],\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/mux_wrdata [8]}));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_0_mig
   (\gen_mmcm.mmcm_i ,
    app_ref_ack,
    app_zq_ack,
    rstdiv0_sync_r1_reg_rep,
    rd_ptr,
    out,
    iserdes_clk,
    \rd_ptr_reg[0] ,
    \rd_ptr_reg[1] ,
    \rd_ptr_reg[2] ,
    \rd_ptr_reg[3] ,
    \rd_ptr_timing_reg[1] ,
    iserdes_clk_0,
    \rd_ptr_reg[0]_0 ,
    \rd_ptr_reg[1]_0 ,
    \rd_ptr_reg[2]_0 ,
    \rd_ptr_reg[3]_0 ,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_reset_n,
    ddr3_dm,
    ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    app_sr_active,
    app_rdy_r_reg,
    app_wdf_rdy,
    \device_temp_r_reg[11] ,
    phy_dout,
    init_calib_complete_reg_rep__0,
    \write_buffer.wr_buf_out_data_reg[122] ,
    app_rd_data_end,
    Q,
    wr_ptr,
    \wr_ptr_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    wr_ptr_1,
    \wr_ptr_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    app_rd_data,
    p_1_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    app_rd_data_valid,
    wr_en,
    wr_en_2,
    wr_en_3,
    ddr_ck_out,
    init_calib_complete,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    CLKB0,
    CLKB0_4,
    clk_ref_i,
    sys_rst,
    app_zq_req,
    app_sr_req,
    mem_out,
    app_addr,
    app_cmd,
    app_wdf_data,
    app_wdf_mask,
    sys_clk_i,
    \app_rd_data[112] ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    app_ref_req,
    out_fifo,
    out_fifo_0,
    app_en,
    app_wdf_wren,
    app_wdf_end);
  output \gen_mmcm.mmcm_i ;
  output app_ref_ack;
  output app_zq_ack;
  output rstdiv0_sync_r1_reg_rep;
  output [3:0]rd_ptr;
  output [1:0]out;
  output iserdes_clk;
  output \rd_ptr_reg[0] ;
  output \rd_ptr_reg[1] ;
  output \rd_ptr_reg[2] ;
  output \rd_ptr_reg[3] ;
  output [1:0]\rd_ptr_timing_reg[1] ;
  output iserdes_clk_0;
  output \rd_ptr_reg[0]_0 ;
  output \rd_ptr_reg[1]_0 ;
  output \rd_ptr_reg[2]_0 ;
  output \rd_ptr_reg[3]_0 ;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output ddr3_reset_n;
  output [1:0]ddr3_dm;
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output app_sr_active;
  output app_rdy_r_reg;
  output app_wdf_rdy;
  output [11:0]\device_temp_r_reg[11] ;
  output [39:0]phy_dout;
  output [71:0]init_calib_complete_reg_rep__0;
  output [71:0]\write_buffer.wr_buf_out_data_reg[122] ;
  output app_rd_data_end;
  output [3:0]Q;
  output [1:0]wr_ptr;
  output [3:0]\wr_ptr_reg[3] ;
  output [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output [1:0]wr_ptr_1;
  output [3:0]\wr_ptr_reg[3]_0 ;
  output [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output [127:0]app_rd_data;
  output p_1_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output app_rd_data_valid;
  output wr_en;
  output wr_en_2;
  output wr_en_3;
  output [1:0]ddr_ck_out;
  output init_calib_complete;
  inout [15:0]ddr3_dq;
  inout [1:0]ddr3_dqs_p;
  inout [1:0]ddr3_dqs_n;
  input CLKB0;
  input CLKB0_4;
  input clk_ref_i;
  input sys_rst;
  input app_zq_req;
  input app_sr_req;
  input [47:0]mem_out;
  input [26:0]app_addr;
  input [1:0]app_cmd;
  input [127:0]app_wdf_data;
  input [15:0]app_wdf_mask;
  input sys_clk_i;
  input [63:0]\app_rd_data[112] ;
  input [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input app_ref_req;
  input [71:0]out_fifo;
  input [71:0]out_fifo_0;
  input app_en;
  input app_wdf_wren;
  input app_wdf_end;

  wire CLKB0;
  wire CLKB0_4;
  wire [3:0]Q;
  wire [26:0]app_addr;
  wire [1:0]app_cmd;
  wire app_en;
  wire [127:0]app_rd_data;
  wire [63:0]\app_rd_data[112] ;
  wire app_rd_data_end;
  wire app_rd_data_valid;
  wire app_rdy_r_reg;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire [127:0]app_wdf_data;
  wire app_wdf_end;
  wire [15:0]app_wdf_mask;
  wire app_wdf_rdy;
  wire app_wdf_wren;
  wire app_zq_ack;
  wire app_zq_req;
  wire clk_ref_i;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [1:0]ddr3_dm;
  wire [15:0]ddr3_dq;
  wire [1:0]ddr3_dqs_n;
  wire [1:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire [11:0]\device_temp_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire freq_refclk;
  wire \gen_mmcm.mmcm_i ;
  wire [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire init_calib_complete;
  wire [71:0]init_calib_complete_reg_rep__0;
  wire iserdes_clk;
  wire iserdes_clk_0;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0 ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0 ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ;
  wire [11:0]\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/po_cnt_dec ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/RST0 ;
  wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ;
  wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ;
  wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ;
  wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ;
  wire \mem_intfc0/mc0/bank_mach0/insert_maint_r ;
  wire [47:0]mem_out;
  wire mem_refclk;
  wire mmcm_clk;
  wire [1:0]out;
  wire [71:0]out_fifo;
  wire [71:0]out_fifo_0;
  wire p_1_in;
  wire [39:0]phy_dout;
  wire pll_locked;
  wire [3:0]rd_ptr;
  wire \rd_ptr_reg[0] ;
  wire \rd_ptr_reg[0]_0 ;
  wire \rd_ptr_reg[1] ;
  wire \rd_ptr_reg[1]_0 ;
  wire \rd_ptr_reg[2] ;
  wire \rd_ptr_reg[2]_0 ;
  wire \rd_ptr_reg[3] ;
  wire \rd_ptr_reg[3]_0 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire ref_dll_lock;
  wire rst_tmp;
  wire rstdiv0_sync_r1_reg_rep;
  wire sync_pulse;
  wire sys_clk_i;
  wire sys_rst;
  wire sys_rst_o;
  wire u_ddr3_infrastructure_n_0;
  wire u_ddr3_infrastructure_n_10;
  wire u_ddr3_infrastructure_n_11;
  wire u_ddr3_infrastructure_n_12;
  wire u_ddr3_infrastructure_n_13;
  wire u_ddr3_infrastructure_n_14;
  wire u_ddr3_infrastructure_n_15;
  wire u_ddr3_infrastructure_n_16;
  wire u_ddr3_infrastructure_n_17;
  wire u_ddr3_infrastructure_n_18;
  wire u_ddr3_infrastructure_n_19;
  wire u_ddr3_infrastructure_n_20;
  wire u_ddr3_infrastructure_n_21;
  wire u_ddr3_infrastructure_n_22;
  wire u_ddr3_infrastructure_n_23;
  wire u_ddr3_infrastructure_n_24;
  wire u_ddr3_infrastructure_n_25;
  wire u_ddr3_infrastructure_n_27;
  wire u_ddr3_infrastructure_n_28;
  wire u_ddr3_infrastructure_n_29;
  wire u_ddr3_infrastructure_n_30;
  wire u_ddr3_infrastructure_n_31;
  wire u_ddr3_infrastructure_n_32;
  wire u_ddr3_infrastructure_n_33;
  wire u_ddr3_infrastructure_n_36;
  wire u_ddr3_infrastructure_n_37;
  wire u_ddr3_infrastructure_n_38;
  wire u_ddr3_infrastructure_n_39;
  wire u_ddr3_infrastructure_n_7;
  wire u_ddr3_infrastructure_n_8;
  wire u_ddr3_infrastructure_n_9;
  wire u_memc_ui_top_std_n_444;
  wire u_memc_ui_top_std_n_57;
  wire u_memc_ui_top_std_n_58;
  wire wr_en;
  wire wr_en_2;
  wire wr_en_3;
  wire [1:0]wr_ptr;
  wire [1:0]wr_ptr_1;
  wire [3:0]\wr_ptr_reg[3] ;
  wire [3:0]\wr_ptr_reg[3]_0 ;
  wire [71:0]\write_buffer.wr_buf_out_data_reg[122] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_tempmon \temp_mon_enabled.u_tempmon 
       (.D(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ),
        .clk_ref_i(clk_ref_i),
        .\device_temp_r_reg[11]_0 (\gen_mmcm.mmcm_i ),
        .in0(rstdiv0_sync_r1_reg_rep),
        .out(\device_temp_r_reg[11] ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_clk_ibuf u_ddr3_clk_ibuf
       (.mmcm_clk(mmcm_clk),
        .sys_clk_i(sys_clk_i));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_infrastructure u_ddr3_infrastructure
       (.AS(sys_rst_o),
        .CLK(\gen_mmcm.mmcm_i ),
        .RST0(\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/RST0 ),
        .SR(u_ddr3_infrastructure_n_7),
        .SS(u_ddr3_infrastructure_n_32),
        .bm_end_r1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_0(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_2(\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_reg(u_ddr3_infrastructure_n_27),
        .bm_end_r1_reg_0(u_ddr3_infrastructure_n_28),
        .bm_end_r1_reg_1(u_ddr3_infrastructure_n_29),
        .bm_end_r1_reg_2(u_ddr3_infrastructure_n_30),
        .\cnt_shift_r_reg[0] (u_memc_ui_top_std_n_58),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[4] (u_memc_ui_top_std_n_444),
        .freq_refclk(freq_refclk),
        .\gen_mmcm.mmcm_i_i_1_0 (u_ddr3_infrastructure_n_0),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (u_ddr3_infrastructure_n_31),
        .in0(rstdiv0_sync_r1_reg_rep),
        .insert_maint_r(\mem_intfc0/mc0/bank_mach0/insert_maint_r ),
        .mem_refclk(mem_refclk),
        .mmcm_clk(mmcm_clk),
        .new_cnt_cpt_r_reg(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0 ),
        .pi_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ),
        .pi_cnt_dec_reg(u_ddr3_infrastructure_n_37),
        .pll_locked(pll_locked),
        .po_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ),
        .po_cnt_dec_3(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/po_cnt_dec ),
        .po_cnt_dec_reg(u_ddr3_infrastructure_n_33),
        .prbs_rdlvl_done_pulse(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse ),
        .prbs_rdlvl_done_pulse_reg(u_ddr3_infrastructure_n_39),
        .rdlvl_stg1_start_reg(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0 ),
        .rst_tmp(rst_tmp),
        .rstdiv0_sync_r1_reg_rep__10_0({u_ddr3_infrastructure_n_17,u_ddr3_infrastructure_n_18,u_ddr3_infrastructure_n_19,u_ddr3_infrastructure_n_20}),
        .rstdiv0_sync_r1_reg_rep__14_0(u_ddr3_infrastructure_n_21),
        .rstdiv0_sync_r1_reg_rep__15_0(u_ddr3_infrastructure_n_22),
        .rstdiv0_sync_r1_reg_rep__15_1(u_ddr3_infrastructure_n_38),
        .rstdiv0_sync_r1_reg_rep__16_0(u_ddr3_infrastructure_n_23),
        .rstdiv0_sync_r1_reg_rep__17_0(u_ddr3_infrastructure_n_24),
        .rstdiv0_sync_r1_reg_rep__18_0(u_ddr3_infrastructure_n_25),
        .rstdiv0_sync_r1_reg_rep__1_0(u_ddr3_infrastructure_n_8),
        .rstdiv0_sync_r1_reg_rep__2_0(u_ddr3_infrastructure_n_9),
        .rstdiv0_sync_r1_reg_rep__4_0({u_ddr3_infrastructure_n_10,u_ddr3_infrastructure_n_11}),
        .rstdiv0_sync_r1_reg_rep__6_0({u_ddr3_infrastructure_n_12,u_ddr3_infrastructure_n_13}),
        .rstdiv0_sync_r1_reg_rep__7_0(u_ddr3_infrastructure_n_14),
        .rstdiv0_sync_r1_reg_rep__8_0(u_ddr3_infrastructure_n_15),
        .rstdiv0_sync_r1_reg_rep__9_0(u_ddr3_infrastructure_n_16),
        .samp_edge_cnt0_en_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ),
        .samp_edge_cnt0_en_r_reg(u_ddr3_infrastructure_n_36),
        .sync_pulse(sync_pulse),
        .\tap_cnt_cpt_r_reg[5] (u_memc_ui_top_std_n_57));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_iodelay_ctrl u_iodelay_ctrl
       (.AS(sys_rst_o),
        .clk_ref_i(clk_ref_i),
        .ref_dll_lock(ref_dll_lock),
        .rst_tmp(rst_tmp),
        .\rstdiv2_sync_r_reg[11] (u_ddr3_infrastructure_n_0),
        .sys_rst(sys_rst));
  (* X_CORE_INFO = "mig_7series_v4_2_ddr3_7Series, mig_7series_0, 2018.3" *) 
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_memc_ui_top_std u_memc_ui_top_std
       (.A_rst_primitives_reg(iserdes_clk),
        .A_rst_primitives_reg_0(iserdes_clk_0),
        .CLK(\gen_mmcm.mmcm_i ),
        .CLKB0(CLKB0),
        .CLKB0_4(CLKB0_4),
        .D(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ),
        .E(app_rdy_r_reg),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .RST0(\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/RST0 ),
        .SR(u_ddr3_infrastructure_n_7),
        .SS(u_ddr3_infrastructure_n_32),
        .app_addr(app_addr),
        .app_cmd(app_cmd),
        .app_en(app_en),
        .app_rd_data(app_rd_data),
        .\app_rd_data[112] (\app_rd_data[112] ),
        .app_rd_data_end(app_rd_data_end),
        .app_rd_data_valid(app_rd_data_valid),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_wdf_data(app_wdf_data),
        .app_wdf_end(app_wdf_end),
        .app_wdf_mask(app_wdf_mask),
        .app_wdf_rdy(app_wdf_rdy),
        .app_wdf_wren(app_wdf_wren),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .bm_end_r1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_0(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_2(\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ),
        .\cnt_pwron_ce_r_reg[9] ({u_ddr3_infrastructure_n_17,u_ddr3_infrastructure_n_18,u_ddr3_infrastructure_n_19,u_ddr3_infrastructure_n_20}),
        .\cnt_shift_r_reg[0] (\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0 ),
        .complex_row0_rd_done_reg(u_ddr3_infrastructure_n_39),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out(ddr_ck_out),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[2] (u_ddr3_infrastructure_n_14),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[4] (u_ddr3_infrastructure_n_38),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\idelay_tap_cnt_r_reg[0][1][4] (u_ddr3_infrastructure_n_22),
        .in0(rstdiv0_sync_r1_reg_rep),
        .\inhbt_act_faw.faw_cnt_r_reg[2] (u_ddr3_infrastructure_n_23),
        .init_calib_complete(init_calib_complete),
        .init_calib_complete_reg(u_ddr3_infrastructure_n_15),
        .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0),
        .\init_state_r_reg[2] (u_memc_ui_top_std_n_444),
        .insert_maint_r(\mem_intfc0/mc0/bank_mach0/insert_maint_r ),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .new_cnt_cpt_r_reg(u_memc_ui_top_std_n_57),
        .out(out),
        .out_fifo(out_fifo),
        .out_fifo_0(out_fifo_0),
        .p_1_in(p_1_in),
        .phy_dout(phy_dout),
        .pi_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ),
        .pi_f_dec_reg(u_ddr3_infrastructure_n_16),
        .pll_locked(pll_locked),
        .po_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ),
        .po_cnt_dec_3(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/po_cnt_dec ),
        .prbs_rdlvl_done_pulse(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse ),
        .ras_timer_zero_r_reg(u_ddr3_infrastructure_n_27),
        .ras_timer_zero_r_reg_0(u_ddr3_infrastructure_n_28),
        .ras_timer_zero_r_reg_1(u_ddr3_infrastructure_n_29),
        .ras_timer_zero_r_reg_2(u_ddr3_infrastructure_n_30),
        .\rd_ptr_reg[0] (rd_ptr[0]),
        .\rd_ptr_reg[0]_0 (\rd_ptr_reg[0] ),
        .\rd_ptr_reg[0]_1 (\rd_ptr_reg[0]_0 ),
        .\rd_ptr_reg[0]_2 (u_ddr3_infrastructure_n_8),
        .\rd_ptr_reg[1] (rd_ptr[1]),
        .\rd_ptr_reg[1]_0 (\rd_ptr_reg[1] ),
        .\rd_ptr_reg[1]_1 (\rd_ptr_reg[1]_0 ),
        .\rd_ptr_reg[2] (rd_ptr[2]),
        .\rd_ptr_reg[2]_0 (\rd_ptr_reg[2] ),
        .\rd_ptr_reg[2]_1 (\rd_ptr_reg[2]_0 ),
        .\rd_ptr_reg[3] (rd_ptr[3]),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ),
        .\rd_ptr_reg[3]_1 (\rd_ptr_reg[3]_0 ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .\rdlvl_dqs_tap_cnt_r_reg[0][1][4] ({u_ddr3_infrastructure_n_12,u_ddr3_infrastructure_n_13}),
        .rdlvl_stg1_start_reg(u_memc_ui_top_std_n_58),
        .ref_dll_lock(ref_dll_lock),
        .reset_reg_0(u_ddr3_infrastructure_n_25),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (u_ddr3_infrastructure_n_31),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (u_ddr3_infrastructure_n_24),
        .\rtp_timer_r_reg[0] (u_ddr3_infrastructure_n_21),
        .samp_edge_cnt0_en_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ),
        .\samp_edge_cnt1_r_reg[0] (u_ddr3_infrastructure_n_36),
        .\smallest_reg[1][0] ({u_ddr3_infrastructure_n_10,u_ddr3_infrastructure_n_11}),
        .sync_pulse(sync_pulse),
        .\tap_cnt_cpt_r_reg[5] (\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0 ),
        .\wait_cnt_r_reg[0] (u_ddr3_infrastructure_n_33),
        .\wait_cnt_r_reg[0]_0 (u_ddr3_infrastructure_n_37),
        .wr_en(wr_en),
        .wr_en_2(wr_en_2),
        .wr_en_3(wr_en_3),
        .\wr_ptr_reg[0] (wr_ptr[0]),
        .\wr_ptr_reg[0]_0 (wr_ptr_1[0]),
        .\wr_ptr_reg[1] (wr_ptr[1]),
        .\wr_ptr_reg[1]_0 (wr_ptr_1[1]),
        .\wr_ptr_reg[3] (Q),
        .\wr_ptr_reg[3]_0 (\wr_ptr_reg[3] ),
        .\wr_ptr_reg[3]_1 (\wr_ptr_reg[3]_0 ),
        .\wr_ptr_timing_reg[2] (u_ddr3_infrastructure_n_9),
        .\write_buffer.wr_buf_out_data_reg[122] (\write_buffer.wr_buf_out_data_reg[122] ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_arb_mux
   (granted_col_r_reg,
    insert_maint_r1_lcl_reg,
    DIC,
    col_rd_wr,
    cke_r,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ,
    \grant_r_reg[1] ,
    Q,
    granted_col_r_reg_0,
    D,
    \grant_r_reg[3] ,
    \rnk_config_r_reg[0] ,
    \grant_r_reg[3]_0 ,
    \wr_this_rank_r_reg[0] ,
    \wr_this_rank_r_reg[0]_0 ,
    granted_col_r_reg_1,
    I119,
    granted_col_r_reg_2,
    \periodic_rd_generation.read_this_rank_r_reg ,
    \periodic_rd_generation.read_this_rank ,
    E,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    \last_master_r_reg[1] ,
    rd_wr_r_lcl_reg,
    \wtr_timer.wtr_cnt_r_reg[1]_0 ,
    \grant_r_reg[2] ,
    \rnk_config_strobe_r_reg[0] ,
    override_demand_ns,
    \grant_r_reg[0] ,
    \grant_r_reg[3]_1 ,
    \grant_r_reg[3]_2 ,
    I118,
    mc_cas_n_ns,
    mc_ras_n_ns,
    col_wr_data_buf_addr,
    act_this_rank,
    \grant_r_reg[0]_0 ,
    \grant_r_reg[3]_3 ,
    CLK,
    rnk_config_strobe_ns,
    insert_maint_r1_lcl_reg_0,
    \pre_4_1_1T_arb.granted_pre_ns ,
    SR,
    I120,
    in0,
    \cmd_pipe_plus.mc_data_offset_reg[5] ,
    rd_wr_r,
    \col_mux.col_periodic_rd_r_reg ,
    \grant_r_reg[0]_1 ,
    \grant_r_reg[0]_2 ,
    \grant_r_reg[1]_0 ,
    \grant_r_reg[0]_3 ,
    \cmd_pipe_plus.mc_cas_n_reg[0] ,
    \last_master_r_reg[0] ,
    \grant_r[2]_i_3 ,
    \grant_r[2]_i_3_0 ,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    \periodic_rd_generation.read_this_rank_r ,
    rd_this_rank_r,
    req_periodic_rd_r,
    granted_col_r_reg_3,
    granted_col_r_reg_4,
    \grant_r_reg[0]_4 ,
    \grant_r_reg[1]_1 ,
    granted_col_r_reg_5,
    granted_col_r_reg_6,
    granted_col_r_reg_7,
    \grant_r_reg[3]_4 ,
    col_wait_r,
    \grant_r_reg[3]_5 ,
    col_wait_r_0,
    \grant_r_reg[3]_6 ,
    wr_this_rank_r,
    \grant_r_reg[2]_0 ,
    req_bank_rdy_ns,
    req_bank_rdy_ns_1,
    \grant_r_reg[1]_2 ,
    \grant_r[3]_i_4 ,
    ofs_rdy_r,
    \grant_r[3]_i_4_0 ,
    \grant_r_reg[0]_5 ,
    req_bank_rdy_ns_2,
    \grant_r[2]_i_3_1 ,
    ofs_rdy_r_3,
    req_bank_rdy_ns_4,
    \grant_r_reg[3]_7 ,
    demand_act_priority_r,
    granted_row_r_reg,
    granted_row_r_reg_0,
    \grant_r_reg[0]_6 ,
    \grant_r_reg[0]_7 ,
    \grant_r_reg[0]_8 ,
    \grant_r_reg[1]_3 ,
    demand_act_priority_r_5,
    \grant_r_reg[3]_8 ,
    \grant_r_reg[3]_9 ,
    demand_act_priority_r_6,
    \grant_r_reg[3]_10 ,
    \grant_r_reg[3]_11 ,
    ofs_rdy_r_7,
    override_demand_r,
    demand_act_priority_r_8,
    \grant_r_reg[3]_12 ,
    \grant_r_reg[3]_13 ,
    req_row_r,
    \cmd_pipe_plus.mc_address_reg[41] ,
    \cmd_pipe_plus.mc_address_reg[10] ,
    row_cmd_wr,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    \cmd_pipe_plus.mc_bank_reg[2]_0 ,
    \cmd_pipe_plus.mc_bank_reg[2]_1 ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    maint_rank_r,
    maint_srx_r,
    maint_zq_r,
    inhbt_act_faw_r,
    req_data_buf_addr_r,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,
    act_this_rank_r,
    \cmd_pipe_plus.mc_address_reg[23] ,
    \cmd_pipe_plus.mc_address_reg[23]_0 ,
    \cmd_pipe_plus.mc_address_reg[23]_1 ,
    \cmd_pipe_plus.mc_address_reg[23]_2 ,
    auto_pre_r,
    auto_pre_r_9,
    auto_pre_r_10,
    auto_pre_r_11);
  output granted_col_r_reg;
  output insert_maint_r1_lcl_reg;
  output [0:0]DIC;
  output col_rd_wr;
  output cke_r;
  output [3:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  output \grant_r_reg[1] ;
  output [3:0]Q;
  output granted_col_r_reg_0;
  output [2:0]D;
  output [3:0]\grant_r_reg[3] ;
  output \rnk_config_r_reg[0] ;
  output [3:0]\grant_r_reg[3]_0 ;
  output \wr_this_rank_r_reg[0] ;
  output \wr_this_rank_r_reg[0]_0 ;
  output granted_col_r_reg_1;
  output [0:0]I119;
  output [0:0]granted_col_r_reg_2;
  output \periodic_rd_generation.read_this_rank_r_reg ;
  output \periodic_rd_generation.read_this_rank ;
  output [0:0]E;
  output \wtr_timer.wtr_cnt_r_reg[1] ;
  output \last_master_r_reg[1] ;
  output rd_wr_r_lcl_reg;
  output \wtr_timer.wtr_cnt_r_reg[1]_0 ;
  output \grant_r_reg[2] ;
  output \rnk_config_strobe_r_reg[0] ;
  output override_demand_ns;
  output \grant_r_reg[0] ;
  output [38:0]\grant_r_reg[3]_1 ;
  output [8:0]\grant_r_reg[3]_2 ;
  output [0:0]I118;
  output [2:0]mc_cas_n_ns;
  output [1:0]mc_ras_n_ns;
  output [3:0]col_wr_data_buf_addr;
  output act_this_rank;
  output \grant_r_reg[0]_0 ;
  output \grant_r_reg[3]_3 ;
  input CLK;
  input rnk_config_strobe_ns;
  input insert_maint_r1_lcl_reg_0;
  input \pre_4_1_1T_arb.granted_pre_ns ;
  input [0:0]SR;
  input [0:0]I120;
  input in0;
  input [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ;
  input [3:0]rd_wr_r;
  input \col_mux.col_periodic_rd_r_reg ;
  input \grant_r_reg[0]_1 ;
  input \grant_r_reg[0]_2 ;
  input \grant_r_reg[1]_0 ;
  input \grant_r_reg[0]_3 ;
  input \cmd_pipe_plus.mc_cas_n_reg[0] ;
  input \last_master_r_reg[0] ;
  input \grant_r[2]_i_3 ;
  input [0:0]\grant_r[2]_i_3_0 ;
  input \cmd_pipe_plus.mc_odt_reg[0] ;
  input \periodic_rd_generation.read_this_rank_r ;
  input [3:0]rd_this_rank_r;
  input [3:0]req_periodic_rd_r;
  input granted_col_r_reg_3;
  input granted_col_r_reg_4;
  input \grant_r_reg[0]_4 ;
  input \grant_r_reg[1]_1 ;
  input granted_col_r_reg_5;
  input granted_col_r_reg_6;
  input granted_col_r_reg_7;
  input \grant_r_reg[3]_4 ;
  input col_wait_r;
  input \grant_r_reg[3]_5 ;
  input col_wait_r_0;
  input \grant_r_reg[3]_6 ;
  input [3:0]wr_this_rank_r;
  input \grant_r_reg[2]_0 ;
  input req_bank_rdy_ns;
  input req_bank_rdy_ns_1;
  input \grant_r_reg[1]_2 ;
  input \grant_r[3]_i_4 ;
  input ofs_rdy_r;
  input \grant_r[3]_i_4_0 ;
  input \grant_r_reg[0]_5 ;
  input req_bank_rdy_ns_2;
  input \grant_r[2]_i_3_1 ;
  input ofs_rdy_r_3;
  input req_bank_rdy_ns_4;
  input \grant_r_reg[3]_7 ;
  input demand_act_priority_r;
  input granted_row_r_reg;
  input granted_row_r_reg_0;
  input \grant_r_reg[0]_6 ;
  input \grant_r_reg[0]_7 ;
  input \grant_r_reg[0]_8 ;
  input \grant_r_reg[1]_3 ;
  input demand_act_priority_r_5;
  input \grant_r_reg[3]_8 ;
  input \grant_r_reg[3]_9 ;
  input demand_act_priority_r_6;
  input \grant_r_reg[3]_10 ;
  input \grant_r_reg[3]_11 ;
  input ofs_rdy_r_7;
  input override_demand_r;
  input demand_act_priority_r_8;
  input \grant_r_reg[3]_12 ;
  input \grant_r_reg[3]_13 ;
  input [38:0]req_row_r;
  input [16:0]\cmd_pipe_plus.mc_address_reg[41] ;
  input \cmd_pipe_plus.mc_address_reg[10] ;
  input [3:0]row_cmd_wr;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  input maint_rank_r;
  input maint_srx_r;
  input maint_zq_r;
  input inhbt_act_faw_r;
  input [15:0]req_data_buf_addr_r;
  input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  input [3:0]act_this_rank_r;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_0 ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_1 ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_2 ;
  input auto_pre_r;
  input auto_pre_r_9;
  input auto_pre_r_10;
  input auto_pre_r_11;

  wire CLK;
  wire [2:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire [0:0]I118;
  wire [0:0]I119;
  wire [0:0]I120;
  wire [3:0]Q;
  wire [0:0]SR;
  wire act_this_rank;
  wire [3:0]act_this_rank_r;
  wire auto_pre_r;
  wire auto_pre_r_10;
  wire auto_pre_r_11;
  wire auto_pre_r_9;
  wire cke_r;
  wire \cmd_pipe_plus.mc_address_reg[10] ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_0 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_1 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_2 ;
  wire [16:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire \cmd_pipe_plus.mc_cas_n_reg[0] ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ;
  wire \cmd_pipe_plus.mc_odt_reg[0] ;
  wire \col_mux.col_periodic_rd_r ;
  wire \col_mux.col_periodic_rd_r_reg ;
  wire col_rd_wr;
  wire col_rd_wr_r;
  wire col_wait_r;
  wire col_wait_r_0;
  wire [3:0]col_wr_data_buf_addr;
  wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  wire demand_act_priority_r;
  wire demand_act_priority_r_5;
  wire demand_act_priority_r_6;
  wire demand_act_priority_r_8;
  wire \grant_r[2]_i_3 ;
  wire [0:0]\grant_r[2]_i_3_0 ;
  wire \grant_r[2]_i_3_1 ;
  wire \grant_r[3]_i_4 ;
  wire \grant_r[3]_i_4_0 ;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[0]_2 ;
  wire \grant_r_reg[0]_3 ;
  wire \grant_r_reg[0]_4 ;
  wire \grant_r_reg[0]_5 ;
  wire \grant_r_reg[0]_6 ;
  wire \grant_r_reg[0]_7 ;
  wire \grant_r_reg[0]_8 ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[1]_1 ;
  wire \grant_r_reg[1]_2 ;
  wire \grant_r_reg[1]_3 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[2]_0 ;
  wire [3:0]\grant_r_reg[3] ;
  wire [3:0]\grant_r_reg[3]_0 ;
  wire [38:0]\grant_r_reg[3]_1 ;
  wire \grant_r_reg[3]_10 ;
  wire \grant_r_reg[3]_11 ;
  wire \grant_r_reg[3]_12 ;
  wire \grant_r_reg[3]_13 ;
  wire [8:0]\grant_r_reg[3]_2 ;
  wire \grant_r_reg[3]_3 ;
  wire \grant_r_reg[3]_4 ;
  wire \grant_r_reg[3]_5 ;
  wire \grant_r_reg[3]_6 ;
  wire \grant_r_reg[3]_7 ;
  wire \grant_r_reg[3]_8 ;
  wire \grant_r_reg[3]_9 ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire [0:0]granted_col_r_reg_2;
  wire granted_col_r_reg_3;
  wire granted_col_r_reg_4;
  wire granted_col_r_reg_5;
  wire granted_col_r_reg_6;
  wire granted_col_r_reg_7;
  wire granted_row_r_reg;
  wire granted_row_r_reg_0;
  wire in0;
  wire inhbt_act_faw_r;
  wire insert_maint_r1_lcl_reg;
  wire insert_maint_r1_lcl_reg_0;
  wire \last_master_r_reg[0] ;
  wire \last_master_r_reg[1] ;
  wire maint_rank_r;
  wire maint_srx_r;
  wire maint_zq_r;
  wire [2:0]mc_cas_n_ns;
  wire [3:3]mc_data_offset1;
  wire [1:0]mc_ras_n_ns;
  wire ofs_rdy_r;
  wire ofs_rdy_r_3;
  wire ofs_rdy_r_7;
  wire override_demand_ns;
  wire override_demand_r;
  wire \periodic_rd_generation.read_this_rank ;
  wire \periodic_rd_generation.read_this_rank_r ;
  wire \periodic_rd_generation.read_this_rank_r_reg ;
  wire \pre_4_1_1T_arb.granted_pre_ns ;
  wire [3:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  wire [3:0]rd_this_rank_r;
  wire [3:0]rd_wr_r;
  wire rd_wr_r_lcl_reg;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_ns_1;
  wire req_bank_rdy_ns_2;
  wire req_bank_rdy_ns_4;
  wire [15:0]req_data_buf_addr_r;
  wire [3:0]req_periodic_rd_r;
  wire [38:0]req_row_r;
  wire rnk_config_0;
  wire rnk_config_r;
  wire \rnk_config_r_reg[0] ;
  wire rnk_config_strobe_ns;
  wire \rnk_config_strobe_r_reg[0] ;
  wire [3:0]row_cmd_wr;
  wire [3:0]wr_this_rank_r;
  wire \wr_this_rank_r_reg[0] ;
  wire \wr_this_rank_r_reg[0]_0 ;
  wire \wtr_timer.wtr_cnt_r_reg[1] ;
  wire \wtr_timer.wtr_cnt_r_reg[1]_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_arb_row_col arb_row_col0
       (.CLK(CLK),
        .D(D),
        .DIC(DIC),
        .E(E),
        .I118(I118),
        .I119(I119),
        .O(mc_data_offset1),
        .Q(Q),
        .act_this_rank(act_this_rank),
        .act_this_rank_r(act_this_rank_r),
        .auto_pre_r(auto_pre_r),
        .auto_pre_r_10(auto_pre_r_10),
        .auto_pre_r_11(auto_pre_r_11),
        .auto_pre_r_9(auto_pre_r_9),
        .\cmd_pipe_plus.mc_address_reg[10] (\cmd_pipe_plus.mc_address_reg[10] ),
        .\cmd_pipe_plus.mc_address_reg[23] (\cmd_pipe_plus.mc_address_reg[23] ),
        .\cmd_pipe_plus.mc_address_reg[23]_0 (\cmd_pipe_plus.mc_address_reg[23]_0 ),
        .\cmd_pipe_plus.mc_address_reg[23]_1 (\cmd_pipe_plus.mc_address_reg[23]_1 ),
        .\cmd_pipe_plus.mc_address_reg[23]_2 (\cmd_pipe_plus.mc_address_reg[23]_2 ),
        .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] ),
        .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\cmd_pipe_plus.mc_bank_reg[2]_0 (\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .\cmd_pipe_plus.mc_bank_reg[2]_1 (\cmd_pipe_plus.mc_bank_reg[2]_1 ),
        .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\cmd_pipe_plus.mc_cas_n_reg[0] (\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .\cmd_pipe_plus.mc_odt_reg[0] (\cmd_pipe_plus.mc_odt_reg[0] ),
        .\col_mux.col_periodic_rd_r (\col_mux.col_periodic_rd_r ),
        .\col_mux.col_periodic_rd_r_reg (\col_mux.col_periodic_rd_r_reg ),
        .col_rd_wr(col_rd_wr),
        .col_rd_wr_r(col_rd_wr_r),
        .col_wait_r(col_wait_r),
        .col_wait_r_0(col_wait_r_0),
        .col_wr_data_buf_addr(col_wr_data_buf_addr),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ),
        .demand_act_priority_r(demand_act_priority_r),
        .demand_act_priority_r_5(demand_act_priority_r_5),
        .demand_act_priority_r_6(demand_act_priority_r_6),
        .demand_act_priority_r_8(demand_act_priority_r_8),
        .\genblk3[1].rnk_config_strobe_r_reg[1]_0 (override_demand_ns),
        .\grant_r[2]_i_3 (\grant_r[2]_i_3 ),
        .\grant_r[2]_i_3_0 (\grant_r[2]_i_3_0 ),
        .\grant_r[2]_i_3_1 (\grant_r[2]_i_3_1 ),
        .\grant_r[3]_i_4 (\grant_r[3]_i_4 ),
        .\grant_r[3]_i_4_0 (\grant_r[3]_i_4_0 ),
        .\grant_r_reg[0] (\grant_r_reg[0] ),
        .\grant_r_reg[0]_0 (\grant_r_reg[0]_0 ),
        .\grant_r_reg[0]_1 (\grant_r_reg[0]_1 ),
        .\grant_r_reg[0]_2 (\grant_r_reg[0]_2 ),
        .\grant_r_reg[0]_3 (\grant_r_reg[0]_3 ),
        .\grant_r_reg[0]_4 (\grant_r_reg[0]_4 ),
        .\grant_r_reg[0]_5 (\grant_r_reg[0]_5 ),
        .\grant_r_reg[0]_6 (\grant_r_reg[0]_6 ),
        .\grant_r_reg[0]_7 (\grant_r_reg[0]_7 ),
        .\grant_r_reg[0]_8 (\grant_r_reg[0]_8 ),
        .\grant_r_reg[1] (\grant_r_reg[1] ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1]_0 ),
        .\grant_r_reg[1]_1 (\grant_r_reg[1]_1 ),
        .\grant_r_reg[1]_2 (\grant_r_reg[1]_2 ),
        .\grant_r_reg[1]_3 (\grant_r_reg[1]_3 ),
        .\grant_r_reg[2] (\grant_r_reg[2] ),
        .\grant_r_reg[2]_0 (\grant_r_reg[2]_0 ),
        .\grant_r_reg[3] (\grant_r_reg[3] ),
        .\grant_r_reg[3]_0 (\grant_r_reg[3]_0 ),
        .\grant_r_reg[3]_1 (\grant_r_reg[3]_1 ),
        .\grant_r_reg[3]_10 (\grant_r_reg[3]_10 ),
        .\grant_r_reg[3]_11 (\grant_r_reg[3]_11 ),
        .\grant_r_reg[3]_12 (\grant_r_reg[3]_12 ),
        .\grant_r_reg[3]_13 (\grant_r_reg[3]_13 ),
        .\grant_r_reg[3]_2 (\grant_r_reg[3]_2 ),
        .\grant_r_reg[3]_3 (\grant_r_reg[3]_3 ),
        .\grant_r_reg[3]_4 (\grant_r_reg[3]_4 ),
        .\grant_r_reg[3]_5 (\grant_r_reg[3]_5 ),
        .\grant_r_reg[3]_6 (\grant_r_reg[3]_6 ),
        .\grant_r_reg[3]_7 (\grant_r_reg[3]_7 ),
        .\grant_r_reg[3]_8 (\grant_r_reg[3]_8 ),
        .\grant_r_reg[3]_9 (\grant_r_reg[3]_9 ),
        .granted_col_r_reg_0(granted_col_r_reg),
        .granted_col_r_reg_1(granted_col_r_reg_0),
        .granted_col_r_reg_2(granted_col_r_reg_1),
        .granted_col_r_reg_3(granted_col_r_reg_2),
        .granted_col_r_reg_4(granted_col_r_reg_3),
        .granted_col_r_reg_5(granted_col_r_reg_4),
        .granted_col_r_reg_6(granted_col_r_reg_5),
        .granted_col_r_reg_7(granted_col_r_reg_6),
        .granted_col_r_reg_8(granted_col_r_reg_7),
        .granted_row_r_reg_0(granted_row_r_reg),
        .granted_row_r_reg_1(granted_row_r_reg_0),
        .in0(in0),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .insert_maint_r1_lcl_reg_0(insert_maint_r1_lcl_reg),
        .insert_maint_r1_lcl_reg_1(insert_maint_r1_lcl_reg_0),
        .\last_master_r_reg[0] (\last_master_r_reg[0] ),
        .\last_master_r_reg[1] (\last_master_r_reg[1] ),
        .maint_rank_r(maint_rank_r),
        .maint_srx_r(maint_srx_r),
        .maint_zq_r(maint_zq_r),
        .mc_cas_n_ns(mc_cas_n_ns),
        .mc_ras_n_ns(mc_ras_n_ns),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r_3(ofs_rdy_r_3),
        .ofs_rdy_r_7(ofs_rdy_r_7),
        .override_demand_r(override_demand_r),
        .\periodic_rd_generation.read_this_rank (\periodic_rd_generation.read_this_rank ),
        .\periodic_rd_generation.read_this_rank_r (\periodic_rd_generation.read_this_rank_r ),
        .\periodic_rd_generation.read_this_rank_r_reg (\periodic_rd_generation.read_this_rank_r_reg ),
        .\pre_4_1_1T_arb.granted_pre_ns (\pre_4_1_1T_arb.granted_pre_ns ),
        .rd_this_rank_r(rd_this_rank_r),
        .rd_wr_r(rd_wr_r),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_bank_rdy_ns_1(req_bank_rdy_ns_1),
        .req_bank_rdy_ns_2(req_bank_rdy_ns_2),
        .req_bank_rdy_ns_4(req_bank_rdy_ns_4),
        .req_data_buf_addr_r(req_data_buf_addr_r),
        .req_periodic_rd_r(req_periodic_rd_r),
        .req_row_r(req_row_r),
        .rnk_config_0(rnk_config_0),
        .rnk_config_r(rnk_config_r),
        .\rnk_config_r_reg[0] (\rnk_config_r_reg[0] ),
        .rnk_config_strobe_ns(rnk_config_strobe_ns),
        .\rnk_config_strobe_r_reg[0]_0 (\rnk_config_strobe_r_reg[0] ),
        .row_cmd_wr(row_cmd_wr),
        .wr_this_rank_r(wr_this_rank_r),
        .\wr_this_rank_r_reg[0] (\wr_this_rank_r_reg[0] ),
        .\wr_this_rank_r_reg[0]_0 (\wr_this_rank_r_reg[0]_0 ),
        .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] ),
        .\wtr_timer.wtr_cnt_r_reg[1]_0 (\wtr_timer.wtr_cnt_r_reg[1]_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_arb_select arb_select0
       (.CLK(CLK),
        .DIC(DIC),
        .I120(I120),
        .O(mc_data_offset1),
        .SR(SR),
        .cke_r(cke_r),
        .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5] ),
        .\col_mux.col_periodic_rd_r (\col_mux.col_periodic_rd_r ),
        .col_rd_wr(col_rd_wr),
        .col_rd_wr_r(col_rd_wr_r),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] (\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ),
        .rnk_config_0(rnk_config_0),
        .rnk_config_r(rnk_config_r));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_arb_row_col
   (granted_col_r_reg_0,
    insert_maint_r1_lcl_reg_0,
    \grant_r_reg[1] ,
    Q,
    granted_col_r_reg_1,
    D,
    \grant_r_reg[3] ,
    \rnk_config_r_reg[0] ,
    \grant_r_reg[3]_0 ,
    \wr_this_rank_r_reg[0] ,
    \wr_this_rank_r_reg[0]_0 ,
    granted_col_r_reg_2,
    I119,
    granted_col_r_reg_3,
    \periodic_rd_generation.read_this_rank_r_reg ,
    \periodic_rd_generation.read_this_rank ,
    DIC,
    E,
    col_rd_wr,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    \last_master_r_reg[1] ,
    rd_wr_r_lcl_reg,
    \wtr_timer.wtr_cnt_r_reg[1]_0 ,
    \grant_r_reg[2] ,
    \rnk_config_strobe_r_reg[0]_0 ,
    \genblk3[1].rnk_config_strobe_r_reg[1]_0 ,
    \grant_r_reg[0] ,
    \grant_r_reg[3]_1 ,
    \grant_r_reg[3]_2 ,
    I118,
    mc_cas_n_ns,
    mc_ras_n_ns,
    rnk_config_0,
    col_wr_data_buf_addr,
    act_this_rank,
    \grant_r_reg[0]_0 ,
    \grant_r_reg[3]_3 ,
    CLK,
    rnk_config_strobe_ns,
    insert_maint_r1_lcl_reg_1,
    \pre_4_1_1T_arb.granted_pre_ns ,
    in0,
    rd_wr_r,
    \col_mux.col_periodic_rd_r_reg ,
    \grant_r_reg[0]_1 ,
    \grant_r_reg[0]_2 ,
    \grant_r_reg[1]_0 ,
    \grant_r_reg[0]_3 ,
    \cmd_pipe_plus.mc_cas_n_reg[0] ,
    rnk_config_r,
    \last_master_r_reg[0] ,
    \grant_r[2]_i_3 ,
    \grant_r[2]_i_3_0 ,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    O,
    \periodic_rd_generation.read_this_rank_r ,
    rd_this_rank_r,
    req_periodic_rd_r,
    col_rd_wr_r,
    granted_col_r_reg_4,
    granted_col_r_reg_5,
    \grant_r_reg[0]_4 ,
    \grant_r_reg[1]_1 ,
    granted_col_r_reg_6,
    granted_col_r_reg_7,
    granted_col_r_reg_8,
    \grant_r_reg[3]_4 ,
    col_wait_r,
    \grant_r_reg[3]_5 ,
    col_wait_r_0,
    \grant_r_reg[3]_6 ,
    \col_mux.col_periodic_rd_r ,
    wr_this_rank_r,
    \grant_r_reg[2]_0 ,
    req_bank_rdy_ns,
    req_bank_rdy_ns_1,
    \grant_r_reg[1]_2 ,
    \grant_r[3]_i_4 ,
    ofs_rdy_r,
    \grant_r[3]_i_4_0 ,
    \grant_r_reg[0]_5 ,
    req_bank_rdy_ns_2,
    \grant_r[2]_i_3_1 ,
    ofs_rdy_r_3,
    req_bank_rdy_ns_4,
    \grant_r_reg[3]_7 ,
    demand_act_priority_r,
    granted_row_r_reg_0,
    granted_row_r_reg_1,
    \grant_r_reg[0]_6 ,
    \grant_r_reg[0]_7 ,
    \grant_r_reg[0]_8 ,
    \grant_r_reg[1]_3 ,
    demand_act_priority_r_5,
    \grant_r_reg[3]_8 ,
    \grant_r_reg[3]_9 ,
    demand_act_priority_r_6,
    \grant_r_reg[3]_10 ,
    \grant_r_reg[3]_11 ,
    ofs_rdy_r_7,
    override_demand_r,
    demand_act_priority_r_8,
    \grant_r_reg[3]_12 ,
    \grant_r_reg[3]_13 ,
    req_row_r,
    \cmd_pipe_plus.mc_address_reg[41] ,
    \cmd_pipe_plus.mc_address_reg[10] ,
    row_cmd_wr,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    \cmd_pipe_plus.mc_bank_reg[2]_0 ,
    \cmd_pipe_plus.mc_bank_reg[2]_1 ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    maint_rank_r,
    maint_srx_r,
    maint_zq_r,
    inhbt_act_faw_r,
    req_data_buf_addr_r,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,
    act_this_rank_r,
    \cmd_pipe_plus.mc_address_reg[23] ,
    \cmd_pipe_plus.mc_address_reg[23]_0 ,
    \cmd_pipe_plus.mc_address_reg[23]_1 ,
    \cmd_pipe_plus.mc_address_reg[23]_2 ,
    auto_pre_r,
    auto_pre_r_9,
    auto_pre_r_10,
    auto_pre_r_11);
  output granted_col_r_reg_0;
  output insert_maint_r1_lcl_reg_0;
  output \grant_r_reg[1] ;
  output [3:0]Q;
  output granted_col_r_reg_1;
  output [2:0]D;
  output [3:0]\grant_r_reg[3] ;
  output \rnk_config_r_reg[0] ;
  output [3:0]\grant_r_reg[3]_0 ;
  output \wr_this_rank_r_reg[0] ;
  output \wr_this_rank_r_reg[0]_0 ;
  output granted_col_r_reg_2;
  output [0:0]I119;
  output [0:0]granted_col_r_reg_3;
  output \periodic_rd_generation.read_this_rank_r_reg ;
  output \periodic_rd_generation.read_this_rank ;
  output [0:0]DIC;
  output [0:0]E;
  output col_rd_wr;
  output \wtr_timer.wtr_cnt_r_reg[1] ;
  output [0:0]\last_master_r_reg[1] ;
  output rd_wr_r_lcl_reg;
  output \wtr_timer.wtr_cnt_r_reg[1]_0 ;
  output \grant_r_reg[2] ;
  output \rnk_config_strobe_r_reg[0]_0 ;
  output \genblk3[1].rnk_config_strobe_r_reg[1]_0 ;
  output \grant_r_reg[0] ;
  output [38:0]\grant_r_reg[3]_1 ;
  output [8:0]\grant_r_reg[3]_2 ;
  output [0:0]I118;
  output [2:0]mc_cas_n_ns;
  output [1:0]mc_ras_n_ns;
  output rnk_config_0;
  output [3:0]col_wr_data_buf_addr;
  output act_this_rank;
  output \grant_r_reg[0]_0 ;
  output \grant_r_reg[3]_3 ;
  input CLK;
  input rnk_config_strobe_ns;
  input insert_maint_r1_lcl_reg_1;
  input \pre_4_1_1T_arb.granted_pre_ns ;
  input in0;
  input [3:0]rd_wr_r;
  input \col_mux.col_periodic_rd_r_reg ;
  input \grant_r_reg[0]_1 ;
  input \grant_r_reg[0]_2 ;
  input \grant_r_reg[1]_0 ;
  input \grant_r_reg[0]_3 ;
  input \cmd_pipe_plus.mc_cas_n_reg[0] ;
  input rnk_config_r;
  input \last_master_r_reg[0] ;
  input \grant_r[2]_i_3 ;
  input [0:0]\grant_r[2]_i_3_0 ;
  input \cmd_pipe_plus.mc_odt_reg[0] ;
  input [0:0]O;
  input \periodic_rd_generation.read_this_rank_r ;
  input [3:0]rd_this_rank_r;
  input [3:0]req_periodic_rd_r;
  input col_rd_wr_r;
  input granted_col_r_reg_4;
  input granted_col_r_reg_5;
  input \grant_r_reg[0]_4 ;
  input \grant_r_reg[1]_1 ;
  input granted_col_r_reg_6;
  input granted_col_r_reg_7;
  input granted_col_r_reg_8;
  input \grant_r_reg[3]_4 ;
  input col_wait_r;
  input \grant_r_reg[3]_5 ;
  input col_wait_r_0;
  input \grant_r_reg[3]_6 ;
  input \col_mux.col_periodic_rd_r ;
  input [3:0]wr_this_rank_r;
  input \grant_r_reg[2]_0 ;
  input req_bank_rdy_ns;
  input req_bank_rdy_ns_1;
  input \grant_r_reg[1]_2 ;
  input \grant_r[3]_i_4 ;
  input ofs_rdy_r;
  input \grant_r[3]_i_4_0 ;
  input \grant_r_reg[0]_5 ;
  input req_bank_rdy_ns_2;
  input \grant_r[2]_i_3_1 ;
  input ofs_rdy_r_3;
  input req_bank_rdy_ns_4;
  input \grant_r_reg[3]_7 ;
  input demand_act_priority_r;
  input granted_row_r_reg_0;
  input granted_row_r_reg_1;
  input \grant_r_reg[0]_6 ;
  input \grant_r_reg[0]_7 ;
  input \grant_r_reg[0]_8 ;
  input \grant_r_reg[1]_3 ;
  input demand_act_priority_r_5;
  input \grant_r_reg[3]_8 ;
  input \grant_r_reg[3]_9 ;
  input demand_act_priority_r_6;
  input \grant_r_reg[3]_10 ;
  input \grant_r_reg[3]_11 ;
  input ofs_rdy_r_7;
  input override_demand_r;
  input demand_act_priority_r_8;
  input \grant_r_reg[3]_12 ;
  input \grant_r_reg[3]_13 ;
  input [38:0]req_row_r;
  input [16:0]\cmd_pipe_plus.mc_address_reg[41] ;
  input \cmd_pipe_plus.mc_address_reg[10] ;
  input [3:0]row_cmd_wr;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  input maint_rank_r;
  input maint_srx_r;
  input maint_zq_r;
  input inhbt_act_faw_r;
  input [15:0]req_data_buf_addr_r;
  input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  input [3:0]act_this_rank_r;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_0 ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_1 ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_2 ;
  input auto_pre_r;
  input auto_pre_r_9;
  input auto_pre_r_10;
  input auto_pre_r_11;

  wire CLK;
  wire [2:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire [0:0]I118;
  wire [0:0]I119;
  wire [0:0]O;
  wire [3:0]Q;
  wire act_this_rank;
  wire [3:0]act_this_rank_r;
  wire auto_pre_r;
  wire auto_pre_r_10;
  wire auto_pre_r_11;
  wire auto_pre_r_9;
  wire \cmd_pipe_plus.mc_address_reg[10] ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_0 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_1 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_2 ;
  wire [16:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire \cmd_pipe_plus.mc_cas_n_reg[0] ;
  wire \cmd_pipe_plus.mc_odt_reg[0] ;
  wire \cmd_pipe_plus.mc_we_n[0]_i_5_n_0 ;
  wire \col_mux.col_periodic_rd_r ;
  wire \col_mux.col_periodic_rd_r_reg ;
  wire col_rd_wr;
  wire col_rd_wr_r;
  wire col_wait_r;
  wire col_wait_r_0;
  wire [3:0]col_wr_data_buf_addr;
  wire config_arb0_n_2;
  wire config_arb0_n_4;
  wire cs_en2;
  wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  wire demand_act_priority_r;
  wire demand_act_priority_r_5;
  wire demand_act_priority_r_6;
  wire demand_act_priority_r_8;
  wire \genblk3[1].rnk_config_strobe_r_reg ;
  wire \genblk3[1].rnk_config_strobe_r_reg[1]_0 ;
  wire \genblk3[2].rnk_config_strobe_r_reg ;
  wire \grant_r[2]_i_3 ;
  wire [0:0]\grant_r[2]_i_3_0 ;
  wire \grant_r[2]_i_3_1 ;
  wire \grant_r[3]_i_4 ;
  wire \grant_r[3]_i_4_0 ;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[0]_2 ;
  wire \grant_r_reg[0]_3 ;
  wire \grant_r_reg[0]_4 ;
  wire \grant_r_reg[0]_5 ;
  wire \grant_r_reg[0]_6 ;
  wire \grant_r_reg[0]_7 ;
  wire \grant_r_reg[0]_8 ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[1]_1 ;
  wire \grant_r_reg[1]_2 ;
  wire \grant_r_reg[1]_3 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[2]_0 ;
  wire [3:0]\grant_r_reg[3] ;
  wire [3:0]\grant_r_reg[3]_0 ;
  wire [38:0]\grant_r_reg[3]_1 ;
  wire \grant_r_reg[3]_10 ;
  wire \grant_r_reg[3]_11 ;
  wire \grant_r_reg[3]_12 ;
  wire \grant_r_reg[3]_13 ;
  wire [8:0]\grant_r_reg[3]_2 ;
  wire \grant_r_reg[3]_3 ;
  wire \grant_r_reg[3]_4 ;
  wire \grant_r_reg[3]_5 ;
  wire \grant_r_reg[3]_6 ;
  wire \grant_r_reg[3]_7 ;
  wire \grant_r_reg[3]_8 ;
  wire \grant_r_reg[3]_9 ;
  wire granted_col_ns;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire granted_col_r_reg_2;
  wire [0:0]granted_col_r_reg_3;
  wire granted_col_r_reg_4;
  wire granted_col_r_reg_5;
  wire granted_col_r_reg_6;
  wire granted_col_r_reg_7;
  wire granted_col_r_reg_8;
  wire granted_row_ns;
  wire granted_row_r_reg_0;
  wire granted_row_r_reg_1;
  wire in0;
  wire inhbt_act_faw_r;
  wire insert_maint_r1_lcl_reg_0;
  wire insert_maint_r1_lcl_reg_1;
  wire \last_master_r_reg[0] ;
  wire [0:0]\last_master_r_reg[1] ;
  wire maint_rank_r;
  wire maint_srx_r;
  wire maint_zq_r;
  wire [2:0]mc_cas_n_ns;
  wire [1:0]mc_ras_n_ns;
  wire ofs_rdy_r;
  wire ofs_rdy_r_3;
  wire ofs_rdy_r_7;
  wire override_demand_r;
  wire \periodic_rd_generation.read_this_rank ;
  wire \periodic_rd_generation.read_this_rank_r ;
  wire \periodic_rd_generation.read_this_rank_r_reg ;
  wire \pre_4_1_1T_arb.granted_pre_ns ;
  wire [3:0]rd_this_rank_r;
  wire [3:0]rd_wr_r;
  wire rd_wr_r_lcl_reg;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_ns_1;
  wire req_bank_rdy_ns_2;
  wire req_bank_rdy_ns_4;
  wire [15:0]req_data_buf_addr_r;
  wire [3:0]req_periodic_rd_r;
  wire [38:0]req_row_r;
  wire rnk_config_0;
  wire rnk_config_r;
  wire \rnk_config_r_reg[0] ;
  wire rnk_config_strobe;
  wire rnk_config_strobe_ns;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire rnk_config_valid_r;
  wire rnk_config_valid_r_lcl_i_1_n_0;
  wire [3:0]row_cmd_wr;
  wire sent_row;
  wire [3:0]wr_this_rank_r;
  wire \wr_this_rank_r_reg[0] ;
  wire \wr_this_rank_r_reg[0]_0 ;
  wire \wtr_timer.wtr_cnt_r_reg[1] ;
  wire \wtr_timer.wtr_cnt_r_reg[1]_0 ;

  LUT1 #(
    .INIT(2'h1)) 
    \cmd_pipe_plus.mc_cas_n[1]_i_1 
       (.I0(granted_col_r_reg_0),
        .O(mc_cas_n_ns[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_pipe_plus.mc_ras_n[2]_i_1 
       (.I0(cs_en2),
        .O(mc_ras_n_ns[1]));
  LUT2 #(
    .INIT(4'h1)) 
    \cmd_pipe_plus.mc_we_n[0]_i_5 
       (.I0(insert_maint_r1_lcl_reg_0),
        .I1(sent_row),
        .O(\cmd_pipe_plus.mc_we_n[0]_i_5_n_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_round_robin_arb__parameterized1 col_arb0
       (.CLK(CLK),
        .D(D[1]),
        .DIC(DIC),
        .E(E),
        .I119(I119),
        .O(O),
        .Q(Q),
        .auto_pre_r(auto_pre_r),
        .auto_pre_r_10(auto_pre_r_10),
        .auto_pre_r_11(auto_pre_r_11),
        .auto_pre_r_9(auto_pre_r_9),
        .\cmd_pipe_plus.mc_address_reg[23] (\cmd_pipe_plus.mc_address_reg[23] ),
        .\cmd_pipe_plus.mc_address_reg[23]_0 (\cmd_pipe_plus.mc_address_reg[23]_0 ),
        .\cmd_pipe_plus.mc_address_reg[23]_1 (\cmd_pipe_plus.mc_address_reg[23]_1 ),
        .\cmd_pipe_plus.mc_address_reg[23]_2 (\cmd_pipe_plus.mc_address_reg[23]_2 ),
        .\cmd_pipe_plus.mc_bank_reg[5] (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\cmd_pipe_plus.mc_bank_reg[5]_0 (\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .\cmd_pipe_plus.mc_bank_reg[5]_1 (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\cmd_pipe_plus.mc_bank_reg[5]_2 (\cmd_pipe_plus.mc_bank_reg[2]_1 ),
        .\cmd_pipe_plus.mc_data_offset_reg[3] (granted_col_r_reg_0),
        .\cmd_pipe_plus.mc_odt_reg[0] (\cmd_pipe_plus.mc_odt_reg[0] ),
        .\col_mux.col_periodic_rd_r (\col_mux.col_periodic_rd_r ),
        .\col_mux.col_periodic_rd_r_reg (\col_mux.col_periodic_rd_r_reg ),
        .col_rd_wr(col_rd_wr),
        .col_rd_wr_r(col_rd_wr_r),
        .col_wait_r(col_wait_r),
        .col_wait_r_0(col_wait_r_0),
        .col_wr_data_buf_addr(col_wr_data_buf_addr),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ),
        .\genblk3[1].rnk_config_strobe_r_reg (\genblk3[1].rnk_config_strobe_r_reg ),
        .\genblk3[1].rnk_config_strobe_r_reg[1] (\genblk3[1].rnk_config_strobe_r_reg[1]_0 ),
        .\genblk3[2].rnk_config_strobe_r_reg (\genblk3[2].rnk_config_strobe_r_reg ),
        .\grant_r[2]_i_3 (\grant_r[2]_i_3 ),
        .\grant_r[2]_i_3_0 (\grant_r[2]_i_3_0 ),
        .\grant_r[3]_i_2_0 (\rnk_config_r_reg[0] ),
        .\grant_r[3]_i_2_1 (\grant_r_reg[3]_7 ),
        .\grant_r_reg[0]_0 (\grant_r_reg[0]_4 ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1] ),
        .\grant_r_reg[1]_1 (\grant_r_reg[1]_1 ),
        .\grant_r_reg[2]_0 (\grant_r_reg[2] ),
        .\grant_r_reg[3]_0 (\grant_r_reg[3]_1 [24:14]),
        .\grant_r_reg[3]_1 (\grant_r_reg[3]_2 [5:3]),
        .\grant_r_reg[3]_2 (\grant_r_reg[3]_3 ),
        .\grant_r_reg[3]_3 (config_arb0_n_2),
        .\grant_r_reg[3]_4 (\grant_r_reg[3]_4 ),
        .\grant_r_reg[3]_5 (\grant_r_reg[3]_5 ),
        .\grant_r_reg[3]_6 (\grant_r_reg[3]_6 ),
        .granted_col_ns(granted_col_ns),
        .granted_col_r_reg(granted_col_r_reg_1),
        .granted_col_r_reg_0(granted_col_r_reg_2),
        .granted_col_r_reg_1(granted_col_r_reg_3),
        .granted_col_r_reg_2(granted_col_r_reg_4),
        .granted_col_r_reg_3(granted_col_r_reg_5),
        .granted_col_r_reg_4(granted_col_r_reg_6),
        .granted_col_r_reg_5(granted_col_r_reg_7),
        .granted_col_r_reg_6(config_arb0_n_4),
        .granted_col_r_reg_7(granted_col_r_reg_8),
        .\last_master_r_reg[0]_0 (\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .\last_master_r_reg[1]_0 (\last_master_r_reg[1] ),
        .ofs_rdy_r_3(ofs_rdy_r_3),
        .override_demand_r(override_demand_r),
        .\periodic_rd_generation.read_this_rank (\periodic_rd_generation.read_this_rank ),
        .\periodic_rd_generation.read_this_rank_r (\periodic_rd_generation.read_this_rank_r ),
        .\periodic_rd_generation.read_this_rank_r_reg (\periodic_rd_generation.read_this_rank_r_reg ),
        .rd_this_rank_r(rd_this_rank_r),
        .rd_wr_r(rd_wr_r),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),
        .req_data_buf_addr_r(req_data_buf_addr_r),
        .req_periodic_rd_r(req_periodic_rd_r),
        .rnk_config_strobe(rnk_config_strobe),
        .wr_this_rank_r(wr_this_rank_r),
        .\wr_this_rank_r_reg[0] (\wr_this_rank_r_reg[0] ),
        .\wr_this_rank_r_reg[0]_0 (\wr_this_rank_r_reg[0]_0 ),
        .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] ),
        .\wtr_timer.wtr_cnt_r_reg[1]_0 (\wtr_timer.wtr_cnt_r_reg[1]_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_round_robin_arb__parameterized1_3 config_arb0
       (.CLK(CLK),
        .Q({Q[3],Q[1:0]}),
        .\genblk3[1].rnk_config_strobe_r_reg (\genblk3[1].rnk_config_strobe_r_reg ),
        .\genblk3[2].rnk_config_strobe_r_reg (\genblk3[2].rnk_config_strobe_r_reg ),
        .\grant_r[2]_i_3 (\grant_r_reg[3]_5 ),
        .\grant_r[2]_i_3_0 (\grant_r[2]_i_3_1 ),
        .\grant_r[3]_i_4 (\grant_r[3]_i_4 ),
        .\grant_r[3]_i_4_0 (\grant_r[3]_i_4_0 ),
        .\grant_r[3]_i_6 (\genblk3[1].rnk_config_strobe_r_reg[1]_0 ),
        .\grant_r_reg[0]_0 (\grant_r_reg[0] ),
        .\grant_r_reg[0]_1 (\grant_r_reg[0]_1 ),
        .\grant_r_reg[0]_2 (\grant_r_reg[0]_3 ),
        .\grant_r_reg[0]_3 (\grant_r_reg[0]_2 ),
        .\grant_r_reg[0]_4 (\grant_r_reg[0]_5 ),
        .\grant_r_reg[1]_0 (config_arb0_n_2),
        .\grant_r_reg[1]_1 (\grant_r_reg[1]_0 ),
        .\grant_r_reg[1]_2 (\grant_r_reg[1]_2 ),
        .\grant_r_reg[2]_0 (\grant_r_reg[2]_0 ),
        .\grant_r_reg[3]_0 (\grant_r_reg[3]_7 ),
        .\last_master_r_reg[0]_0 (\last_master_r_reg[0] ),
        .\last_master_r_reg[3]_0 (\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r_3(ofs_rdy_r_3),
        .ofs_rdy_r_7(ofs_rdy_r_7),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_bank_rdy_ns_1(req_bank_rdy_ns_1),
        .req_bank_rdy_ns_2(req_bank_rdy_ns_2),
        .req_bank_rdy_ns_4(req_bank_rdy_ns_4),
        .rnk_config_0(rnk_config_0),
        .rnk_config_r(rnk_config_r),
        .\rnk_config_r_reg[0] (\rnk_config_r_reg[0] ),
        .rnk_config_strobe(rnk_config_strobe),
        .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0]_0 ),
        .rnk_config_valid_r(rnk_config_valid_r),
        .rnk_config_valid_r_lcl_reg(config_arb0_n_4));
  FDRE \genblk3[1].rnk_config_strobe_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rnk_config_strobe),
        .Q(\genblk3[1].rnk_config_strobe_r_reg ),
        .R(1'b0));
  FDRE \genblk3[2].rnk_config_strobe_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\genblk3[1].rnk_config_strobe_r_reg ),
        .Q(\genblk3[2].rnk_config_strobe_r_reg ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    granted_col_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(granted_col_ns),
        .Q(granted_col_r_reg_0),
        .R(1'b0));
  FDRE granted_row_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(granted_row_ns),
        .Q(sent_row),
        .R(1'b0));
  FDRE insert_maint_r1_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(insert_maint_r1_lcl_reg_1),
        .Q(insert_maint_r1_lcl_reg_0),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \pre_4_1_1T_arb.granted_pre_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\pre_4_1_1T_arb.granted_pre_ns ),
        .Q(cs_en2),
        .R(1'b0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_round_robin_arb__parameterized1_4 \pre_4_1_1T_arb.pre_arb0 
       (.CLK(CLK),
        .D(D[2]),
        .Q(\grant_r_reg[3]_0 ),
        .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] ),
        .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\cmd_pipe_plus.mc_bank_reg[8]_0 (\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .\cmd_pipe_plus.mc_bank_reg[8]_1 (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\cmd_pipe_plus.mc_bank_reg[8]_2 (\cmd_pipe_plus.mc_bank_reg[2]_1 ),
        .cs_en2(cs_en2),
        .\grant_r_reg[0]_0 (\grant_r_reg[0]_6 ),
        .\grant_r_reg[0]_1 (\grant_r_reg[0]_7 ),
        .\grant_r_reg[0]_2 (\grant_r_reg[0]_8 ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1]_3 ),
        .\grant_r_reg[3]_0 (\grant_r_reg[3]_1 [38:25]),
        .\grant_r_reg[3]_1 (\grant_r_reg[3]_2 [8:6]),
        .\last_master_r_reg[0]_0 (\last_master_r_reg[0] ),
        .mc_cas_n_ns(mc_cas_n_ns[2]),
        .req_row_r(req_row_r),
        .row_cmd_wr(row_cmd_wr));
  FDRE \rnk_config_strobe_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rnk_config_strobe_ns),
        .Q(rnk_config_strobe),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFEFFFFF)) 
    rnk_config_valid_r_lcl_i_1
       (.I0(rnk_config_valid_r),
        .I1(\grant_r_reg[0]_1 ),
        .I2(\grant_r_reg[0]_2 ),
        .I3(\grant_r_reg[1]_0 ),
        .I4(\grant_r_reg[0]_3 ),
        .O(rnk_config_valid_r_lcl_i_1_n_0));
  FDRE rnk_config_valid_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rnk_config_valid_r_lcl_i_1_n_0),
        .Q(rnk_config_valid_r),
        .R(in0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_round_robin_arb__parameterized1_5 row_arb0
       (.CLK(CLK),
        .D(D[0]),
        .I118(I118),
        .Q(\grant_r_reg[3] ),
        .act_this_rank(act_this_rank),
        .act_this_rank_r(act_this_rank_r),
        .\cmd_pipe_plus.mc_address_reg[10] (\cmd_pipe_plus.mc_address_reg[10] ),
        .\cmd_pipe_plus.mc_address_reg[13] (\cmd_pipe_plus.mc_address_reg[41] ),
        .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\cmd_pipe_plus.mc_bank_reg[2]_0 (\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .\cmd_pipe_plus.mc_bank_reg[2]_1 (\cmd_pipe_plus.mc_bank_reg[2]_1 ),
        .\cmd_pipe_plus.mc_bank_reg[2]_2 (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\cmd_pipe_plus.mc_cas_n_reg[0] (\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .\cmd_pipe_plus.mc_ras_n_reg[0] (insert_maint_r1_lcl_reg_0),
        .\cmd_pipe_plus.mc_we_n_reg[0] (\cmd_pipe_plus.mc_we_n[0]_i_5_n_0 ),
        .demand_act_priority_r(demand_act_priority_r),
        .demand_act_priority_r_5(demand_act_priority_r_5),
        .demand_act_priority_r_6(demand_act_priority_r_6),
        .demand_act_priority_r_8(demand_act_priority_r_8),
        .\grant_r[2]_i_3__0_0 (insert_maint_r1_lcl_reg_1),
        .\grant_r_reg[0]_0 (\grant_r_reg[0]_0 ),
        .\grant_r_reg[3]_0 (\grant_r_reg[3]_8 ),
        .\grant_r_reg[3]_1 (\grant_r_reg[3]_9 ),
        .\grant_r_reg[3]_2 (\grant_r_reg[3]_10 ),
        .\grant_r_reg[3]_3 (\grant_r_reg[3]_11 ),
        .\grant_r_reg[3]_4 (\grant_r_reg[3]_12 ),
        .\grant_r_reg[3]_5 (\grant_r_reg[3]_13 ),
        .granted_row_ns(granted_row_ns),
        .granted_row_r_reg(granted_row_r_reg_0),
        .granted_row_r_reg_0(granted_row_r_reg_1),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .\last_master_r_reg[0]_0 (\last_master_r_reg[0] ),
        .maint_rank_r(maint_rank_r),
        .maint_srx_r(maint_srx_r),
        .maint_zq_r(maint_zq_r),
        .mc_cas_n_ns(mc_cas_n_ns[0]),
        .mc_ras_n_ns(mc_ras_n_ns[0]),
        .\req_bank_r_lcl_reg[2] (\grant_r_reg[3]_2 [2:0]),
        .req_row_r({req_row_r[38],req_row_r[36:14],req_row_r[12:0]}),
        .\req_row_r_lcl_reg[13] (\grant_r_reg[3]_1 [13:0]),
        .row_cmd_wr(row_cmd_wr),
        .sent_row(sent_row));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_arb_select
   (\col_mux.col_periodic_rd_r ,
    col_rd_wr_r,
    cke_r,
    rnk_config_r,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ,
    O,
    DIC,
    CLK,
    col_rd_wr,
    SR,
    I120,
    rnk_config_0,
    \cmd_pipe_plus.mc_data_offset_reg[5] );
  output \col_mux.col_periodic_rd_r ;
  output col_rd_wr_r;
  output cke_r;
  output rnk_config_r;
  output [3:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  output [0:0]O;
  input [0:0]DIC;
  input CLK;
  input col_rd_wr;
  input [0:0]SR;
  input [0:0]I120;
  input rnk_config_0;
  input [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ;

  wire CLK;
  wire [0:0]DIC;
  wire [0:0]I120;
  wire [0:0]O;
  wire [0:0]SR;
  wire cke_r;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ;
  wire \col_mux.col_periodic_rd_r ;
  wire col_rd_wr;
  wire col_rd_wr_r;
  wire \mc_data_offset1_inferred__0/i__carry_n_0 ;
  wire \mc_data_offset1_inferred__0/i__carry_n_1 ;
  wire \mc_data_offset1_inferred__0/i__carry_n_2 ;
  wire \mc_data_offset1_inferred__0/i__carry_n_3 ;
  wire [3:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  wire rnk_config_0;
  wire rnk_config_r;
  wire [3:0]\NLW_mc_data_offset1_inferred__0/i__carry__0_CO_UNCONNECTED ;
  wire [3:1]\NLW_mc_data_offset1_inferred__0/i__carry__0_O_UNCONNECTED ;

  FDSE cke_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(I120),
        .Q(cke_r),
        .S(SR));
  FDRE \col_mux.col_periodic_rd_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(DIC),
        .Q(\col_mux.col_periodic_rd_r ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \col_mux.col_rd_wr_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(col_rd_wr),
        .Q(col_rd_wr_r),
        .R(1'b0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \mc_data_offset1_inferred__0/i__carry 
       (.CI(1'b0),
        .CO({\mc_data_offset1_inferred__0/i__carry_n_0 ,\mc_data_offset1_inferred__0/i__carry_n_1 ,\mc_data_offset1_inferred__0/i__carry_n_2 ,\mc_data_offset1_inferred__0/i__carry_n_3 }),
        .CYINIT(\cmd_pipe_plus.mc_data_offset_reg[5] [0]),
        .DI(\cmd_pipe_plus.mc_data_offset_reg[5] [4:1]),
        .O({\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [2],O,\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [1:0]}),
        .S(\cmd_pipe_plus.mc_data_offset_reg[5] [4:1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \mc_data_offset1_inferred__0/i__carry__0 
       (.CI(\mc_data_offset1_inferred__0/i__carry_n_0 ),
        .CO(\NLW_mc_data_offset1_inferred__0/i__carry__0_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_mc_data_offset1_inferred__0/i__carry__0_O_UNCONNECTED [3:1],\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [3]}),
        .S({1'b0,1'b0,1'b0,\cmd_pipe_plus.mc_data_offset_reg[5] [5]}));
  FDRE \rnk_config_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rnk_config_0),
        .Q(rnk_config_r),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_cntrl
   (idle_r,
    req_periodic_rd_r,
    rd_wr_r,
    rb_hit_busy_r,
    bm_end_r1,
    row_cmd_wr,
    col_wait_r,
    demand_act_priority_r,
    act_this_rank_r,
    req_bank_rdy_ns,
    demand_priority_r,
    demanded_prior_r,
    ofs_rdy_r,
    wr_this_rank_r,
    rd_this_rank_r,
    pass_open_bank_r_lcl_reg,
    wait_for_maint_r_lcl_reg,
    auto_pre_r,
    pre_bm_end_r_reg,
    idle_r_lcl_reg,
    idle_r_lcl_reg_0,
    idle_r_lcl_reg_1,
    D,
    head_r_lcl_reg,
    req_wr_r_lcl_reg,
    \grant_r_reg[0] ,
    bm_end_r1_reg,
    \ras_timer_r_reg[1] ,
    col_wait_r_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,
    pre_passing_open_bank_r_reg,
    idle_r_lcl_reg_2,
    idle_r_lcl_reg_3,
    idle_r_lcl_reg_4,
    p_9_in,
    idle_r_lcl_reg_5,
    q_entry_ns,
    ordered_r_lcl_reg,
    req_wr_r_lcl_reg_0,
    ordered_r_lcl_reg_0,
    \order_q_r_reg[1] ,
    \order_q_r_reg[1]_0 ,
    rb_hit_busy_r_reg,
    rb_hit_busy_r_reg_0,
    act_wait_r_lcl_reg,
    \pre_4_1_1T_arb.granted_pre_ns ,
    auto_pre_r_lcl_reg,
    \req_row_r_lcl_reg[13] ,
    act_wait_r_lcl_reg_0,
    demand_priority_r_reg,
    ofs_rdy_r0,
    ofs_rdy_r0_0,
    ofs_rdy_r0_1,
    \req_data_buf_addr_r_reg[3] ,
    \req_bank_r_lcl_reg[2] ,
    \req_col_r_reg[9] ,
    CLK,
    periodic_rd_insert,
    req_wr_r_lcl0,
    hi_priority,
    rb_hit_busy_r_reg_1,
    \q_entry_r[1]_i_5__1 ,
    SR,
    phy_mc_ctl_full,
    in0,
    phy_mc_cmd_full,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    S,
    row_hit_r_reg,
    pass_open_bank_r_lcl_reg_0,
    \compute_tail.tail_r_lcl_reg ,
    Q,
    head_r_lcl_reg_0,
    q_has_priority_r_reg,
    \rtp_timer_r_reg[1] ,
    \maint_controller.maint_hit_busies_r_reg[0] ,
    \maint_controller.maint_hit_busies_r_reg[0]_0 ,
    q_has_rd_r_reg,
    was_wr,
    col_wait_r_reg_0,
    granted_col_r_reg,
    granted_col_r_reg_0,
    granted_col_r_reg_1,
    rb_hit_busies_r,
    \q_entry_r_reg[1] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,
    accept_internal_r_reg,
    accept_internal_r_reg_0,
    accept_internal_r_reg_1,
    accept_internal_r_reg_2,
    rd_wr_r_lcl_reg,
    head_r_lcl_reg_1,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    \q_entry_r_reg[1]_0 ,
    ordered_r_lcl,
    \order_q_r_reg[0] ,
    \order_q_r_reg[0]_0 ,
    \rnk_config_strobe_r_reg[0] ,
    \rnk_config_strobe_r_reg[0]_0 ,
    req_bank_rdy_r_reg,
    req_bank_rdy_r_reg_0,
    req_bank_rdy_r_reg_1,
    accept_internal_r,
    app_en_r2,
    \q_entry_r_reg[0] ,
    \q_entry_r_reg[0]_0 ,
    act_wait_r_lcl_reg_1,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \q_entry_r_reg[0]_1 ,
    auto_pre_r_lcl_reg_0,
    was_priority,
    pass_open_bank_r_lcl_reg_1,
    maint_req_r,
    pass_open_bank_r_lcl_reg_2,
    pass_open_bank_r_lcl_reg_3,
    \pre_4_1_1T_arb.granted_pre_r_reg_0 ,
    \pre_4_1_1T_arb.granted_pre_r_reg_1 ,
    row,
    ras_timer_zero_r_reg,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_2 ,
    \ras_timer_r_reg[0]_3 ,
    \ras_timer_r_reg[0]_4 ,
    demand_priority_r_reg_0,
    demand_priority_r_2,
    demanded_prior_r_3,
    demanded_prior_r_reg,
    phy_mc_data_full,
    ofs_rdy_r_reg,
    \rtp_timer_r_reg[0] ,
    \req_data_buf_addr_r_reg[3]_0 ,
    bank,
    \req_col_r_reg[9]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ,
    \q_entry_r_reg[1]_1 ,
    \q_entry_r_reg[0]_2 );
  output [0:0]idle_r;
  output [0:0]req_periodic_rd_r;
  output [0:0]rd_wr_r;
  output [0:0]rb_hit_busy_r;
  output bm_end_r1;
  output [0:0]row_cmd_wr;
  output col_wait_r;
  output demand_act_priority_r;
  output [0:0]act_this_rank_r;
  output req_bank_rdy_ns;
  output demand_priority_r;
  output demanded_prior_r;
  output ofs_rdy_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output pass_open_bank_r_lcl_reg;
  output wait_for_maint_r_lcl_reg;
  output auto_pre_r;
  output pre_bm_end_r_reg;
  output idle_r_lcl_reg;
  output idle_r_lcl_reg_0;
  output idle_r_lcl_reg_1;
  output [0:0]D;
  output head_r_lcl_reg;
  output req_wr_r_lcl_reg;
  output \grant_r_reg[0] ;
  output bm_end_r1_reg;
  output \ras_timer_r_reg[1] ;
  output col_wait_r_reg;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  output pre_passing_open_bank_r_reg;
  output idle_r_lcl_reg_2;
  output idle_r_lcl_reg_3;
  output idle_r_lcl_reg_4;
  output p_9_in;
  output idle_r_lcl_reg_5;
  output [0:0]q_entry_ns;
  output ordered_r_lcl_reg;
  output req_wr_r_lcl_reg_0;
  output ordered_r_lcl_reg_0;
  output \order_q_r_reg[1] ;
  output \order_q_r_reg[1]_0 ;
  output rb_hit_busy_r_reg;
  output rb_hit_busy_r_reg_0;
  output act_wait_r_lcl_reg;
  output \pre_4_1_1T_arb.granted_pre_ns ;
  output auto_pre_r_lcl_reg;
  output [13:0]\req_row_r_lcl_reg[13] ;
  output act_wait_r_lcl_reg_0;
  output demand_priority_r_reg;
  output ofs_rdy_r0;
  output ofs_rdy_r0_0;
  output ofs_rdy_r0_1;
  output [3:0]\req_data_buf_addr_r_reg[3] ;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [9:0]\req_col_r_reg[9] ;
  input CLK;
  input periodic_rd_insert;
  input req_wr_r_lcl0;
  input hi_priority;
  input rb_hit_busy_r_reg_1;
  input [1:0]\q_entry_r[1]_i_5__1 ;
  input [0:0]SR;
  input phy_mc_ctl_full;
  input in0;
  input phy_mc_cmd_full;
  input wait_for_maint_r_lcl_reg_0;
  input wait_for_maint_r_lcl_reg_1;
  input [2:0]S;
  input [0:0]row_hit_r_reg;
  input pass_open_bank_r_lcl_reg_0;
  input \compute_tail.tail_r_lcl_reg ;
  input [1:0]Q;
  input [2:0]head_r_lcl_reg_0;
  input q_has_priority_r_reg;
  input \rtp_timer_r_reg[1] ;
  input [0:0]\maint_controller.maint_hit_busies_r_reg[0] ;
  input \maint_controller.maint_hit_busies_r_reg[0]_0 ;
  input q_has_rd_r_reg;
  input was_wr;
  input col_wait_r_reg_0;
  input granted_col_r_reg;
  input granted_col_r_reg_0;
  input granted_col_r_reg_1;
  input [0:0]rb_hit_busies_r;
  input \q_entry_r_reg[1] ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  input accept_internal_r_reg;
  input accept_internal_r_reg_0;
  input accept_internal_r_reg_1;
  input accept_internal_r_reg_2;
  input rd_wr_r_lcl_reg;
  input head_r_lcl_reg_1;
  input [0:0]\pre_4_1_1T_arb.granted_pre_r_reg ;
  input \q_entry_r_reg[1]_0 ;
  input ordered_r_lcl;
  input \order_q_r_reg[0] ;
  input \order_q_r_reg[0]_0 ;
  input \rnk_config_strobe_r_reg[0] ;
  input \rnk_config_strobe_r_reg[0]_0 ;
  input req_bank_rdy_r_reg;
  input req_bank_rdy_r_reg_0;
  input req_bank_rdy_r_reg_1;
  input accept_internal_r;
  input app_en_r2;
  input \q_entry_r_reg[0] ;
  input \q_entry_r_reg[0]_0 ;
  input [0:0]act_wait_r_lcl_reg_1;
  input \ras_timer_r_reg[0] ;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input [2:0]\q_entry_r_reg[0]_1 ;
  input auto_pre_r_lcl_reg_0;
  input was_priority;
  input pass_open_bank_r_lcl_reg_1;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg_2;
  input pass_open_bank_r_lcl_reg_3;
  input \pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  input \pre_4_1_1T_arb.granted_pre_r_reg_1 ;
  input [13:0]row;
  input ras_timer_zero_r_reg;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_2 ;
  input \ras_timer_r_reg[0]_3 ;
  input \ras_timer_r_reg[0]_4 ;
  input demand_priority_r_reg_0;
  input demand_priority_r_2;
  input demanded_prior_r_3;
  input demanded_prior_r_reg;
  input phy_mc_data_full;
  input [2:0]ofs_rdy_r_reg;
  input \rtp_timer_r_reg[0] ;
  input [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  input [2:0]bank;
  input [9:0]\req_col_r_reg[9]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;
  input \q_entry_r_reg[1]_1 ;
  input \q_entry_r_reg[0]_2 ;

  wire CLK;
  wire [0:0]D;
  wire [1:0]Q;
  wire [2:0]S;
  wire [0:0]SR;
  wire accept_internal_r;
  wire accept_internal_r_reg;
  wire accept_internal_r_reg_0;
  wire accept_internal_r_reg_1;
  wire accept_internal_r_reg_2;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire [0:0]act_wait_r_lcl_reg_1;
  wire app_en_r2;
  wire auto_pre_r;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire [2:0]bank;
  wire bank_compare0_n_10;
  wire bank_compare0_n_8;
  wire bank_queue0_n_31;
  wire [0:0]bm_end;
  wire bm_end_r1;
  wire bm_end_r1_reg;
  wire col_wait_r;
  wire col_wait_r_reg;
  wire col_wait_r_reg_0;
  wire \compute_tail.tail_r_lcl_reg ;
  wire demand_act_priority_r;
  wire demand_priority_r;
  wire demand_priority_r_2;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demanded_prior_r;
  wire demanded_prior_r_3;
  wire demanded_prior_r_reg;
  wire \grant_r_reg[0] ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire [0:0]head_r;
  wire head_r_lcl_reg;
  wire [2:0]head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire hi_priority;
  wire [0:0]idle_ns;
  wire [0:0]idle_r;
  wire idle_r_lcl_reg;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire idle_r_lcl_reg_3;
  wire idle_r_lcl_reg_4;
  wire idle_r_lcl_reg_5;
  wire in0;
  wire [0:0]\maint_controller.maint_hit_busies_r_reg[0] ;
  wire \maint_controller.maint_hit_busies_r_reg[0]_0 ;
  wire maint_req_r;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ofs_rdy_r0_0;
  wire ofs_rdy_r0_1;
  wire [2:0]ofs_rdy_r_reg;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[0]_0 ;
  wire \order_q_r_reg[1] ;
  wire \order_q_r_reg[1]_0 ;
  wire ordered_r;
  wire ordered_r_lcl;
  wire ordered_r_lcl_reg;
  wire ordered_r_lcl_reg_0;
  wire p_9_in;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire pass_open_bank_r_lcl_reg_3;
  wire periodic_rd_insert;
  wire phy_mc_cmd_full;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire \pre_4_1_1T_arb.granted_pre_ns ;
  wire [0:0]\pre_4_1_1T_arb.granted_pre_r_reg ;
  wire \pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  wire \pre_4_1_1T_arb.granted_pre_r_reg_1 ;
  wire pre_bm_end_ns;
  wire pre_bm_end_r_reg;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r_reg;
  wire pre_wait_r;
  wire [0:0]q_entry_ns;
  wire [1:0]\q_entry_r[1]_i_5__1 ;
  wire \q_entry_r_reg[0] ;
  wire \q_entry_r_reg[0]_0 ;
  wire [2:0]\q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire \q_entry_r_reg[1] ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire q_has_priority_r_reg;
  wire q_has_rd;
  wire q_has_rd_r_reg;
  wire [1:0]ras_timer_passed_ns;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  wire [0:0]rb_hit_busies_r;
  wire [0:0]rb_hit_busy_r;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire [0:0]rd_this_rank_r;
  wire [0:0]rd_wr_r;
  wire rd_wr_r_lcl_reg;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire req_bank_rdy_r_reg_0;
  wire req_bank_rdy_r_reg_1;
  wire [9:0]\req_col_r_reg[9] ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3] ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13] ;
  wire [0:0]req_wr_r;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg;
  wire req_wr_r_lcl_reg_0;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire [13:0]row;
  wire [0:0]row_cmd_wr;
  wire [0:0]row_hit_r_reg;
  wire \rtp_timer_r_reg[0] ;
  wire \rtp_timer_r_reg[1] ;
  wire start_wtp_timer0;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire was_priority;
  wire was_wr;
  wire [0:0]wr_this_rank_r;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_compare_2 bank_compare0
       (.CLK(CLK),
        .E(idle_ns),
        .Q(Q[0]),
        .S(S),
        .bank(bank),
        .\grant_r_reg[0] (bank_compare0_n_8),
        .hi_priority(hi_priority),
        .maint_req_r(maint_req_r),
        .\order_q_r_reg[1] (\order_q_r_reg[0] ),
        .\order_q_r_reg[1]_0 (\order_q_r_reg[0]_0 ),
        .ordered_r(ordered_r),
        .ordered_r_lcl(ordered_r_lcl),
        .ordered_r_lcl_reg(ordered_r_lcl_reg_0),
        .ordered_r_lcl_reg_0(idle_r_lcl_reg),
        .ordered_r_lcl_reg_1(\rtp_timer_r_reg[1] ),
        .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_1),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_2),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_3),
        .pass_open_bank_r_lcl_reg_2(wait_for_maint_r_lcl_reg),
        .periodic_rd_insert(periodic_rd_insert),
        .\q_entry_r[1]_i_4__2 (\q_entry_r_reg[0]_1 ),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r),
        .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_0),
        .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg),
        .rb_hit_busy_r_reg_3(rb_hit_busy_r_reg_1),
        .rd_wr_r_lcl_reg_0(rd_wr_r),
        .rd_wr_r_lcl_reg_1(head_r_lcl_reg),
        .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2] ),
        .req_bank_rdy_r_reg(req_bank_rdy_r_reg),
        .req_bank_rdy_r_reg_0(req_bank_rdy_r_reg_0),
        .req_bank_rdy_r_reg_1(req_bank_rdy_r_reg_1),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_col_r_reg[9]_1 (\req_col_r_reg[9]_0 ),
        .\req_data_buf_addr_r_reg[0]_0 (idle_r),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .\req_data_buf_addr_r_reg[3]_1 (\req_data_buf_addr_r_reg[3]_0 ),
        .req_periodic_rd_r(req_periodic_rd_r),
        .req_priority_r(req_priority_r),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13] ),
        .req_wr_r(req_wr_r),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg),
        .req_wr_r_lcl_reg_1(req_wr_r_lcl_reg_0),
        .row(row),
        .row_hit_r_reg_0(bank_compare0_n_10),
        .row_hit_r_reg_1(row_hit_r_reg),
        .start_wtp_timer0(start_wtp_timer0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_queue bank_queue0
       (.CLK(CLK),
        .D(D),
        .E(idle_ns),
        .Q(Q[0]),
        .SR(SR),
        .accept_internal_r(accept_internal_r),
        .accept_internal_r_reg(accept_internal_r_reg),
        .accept_internal_r_reg_0(accept_internal_r_reg_0),
        .accept_internal_r_reg_1(accept_internal_r_reg_1),
        .accept_internal_r_reg_2(accept_internal_r_reg_2),
        .act_wait_ns(act_wait_ns),
        .act_wait_r_lcl_reg(act_wait_r_lcl_reg),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_1),
        .app_en_r2(app_en_r2),
        .auto_pre_r_lcl_reg_0(auto_pre_r),
        .auto_pre_r_lcl_reg_1(col_wait_r),
        .auto_pre_r_lcl_reg_2(row_cmd_wr),
        .auto_pre_r_lcl_reg_3(auto_pre_r_lcl_reg_0),
        .bm_end(bm_end),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_reg(rd_wr_r),
        .col_wait_r_reg(col_wait_r_reg),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg ),
        .\grant_r[3]_i_2 (req_bank_rdy_r_reg),
        .\grant_r[3]_i_2_0 (req_wr_r_lcl_reg),
        .\grant_r[3]_i_2_1 (req_bank_rdy_r_reg_0),
        .\grant_r[3]_i_2_2 (req_bank_rdy_r_reg_1),
        .\grant_r_reg[0] (\grant_r_reg[0] ),
        .granted_col_r_reg(granted_col_r_reg),
        .granted_col_r_reg_0(granted_col_r_reg_0),
        .granted_col_r_reg_1(granted_col_r_reg_1),
        .head_r(head_r),
        .head_r_lcl_reg_0(head_r_lcl_reg),
        .head_r_lcl_reg_1(head_r_lcl_reg_0),
        .head_r_lcl_reg_2(head_r_lcl_reg_1),
        .head_r_lcl_reg_3(rb_hit_busy_r_reg),
        .head_r_lcl_reg_4(rb_hit_busy_r_reg_0),
        .idle_r_lcl_reg_0(idle_r),
        .idle_r_lcl_reg_1(idle_r_lcl_reg),
        .idle_r_lcl_reg_2(idle_r_lcl_reg_0),
        .idle_r_lcl_reg_3(idle_r_lcl_reg_1),
        .idle_r_lcl_reg_4(idle_r_lcl_reg_2),
        .idle_r_lcl_reg_5(idle_r_lcl_reg_3),
        .idle_r_lcl_reg_6(idle_r_lcl_reg_4),
        .idle_r_lcl_reg_7(idle_r_lcl_reg_5),
        .\maint_controller.maint_hit_busies_r_reg[0] (\maint_controller.maint_hit_busies_r_reg[0] ),
        .\maint_controller.maint_hit_busies_r_reg[0]_0 (\maint_controller.maint_hit_busies_r_reg[0]_0 ),
        .\order_q_r_reg[0]_0 (bank_queue0_n_31),
        .\order_q_r_reg[0]_1 (\order_q_r_reg[0] ),
        .\order_q_r_reg[0]_2 (\order_q_r_reg[0]_0 ),
        .\order_q_r_reg[1]_0 (\order_q_r_reg[1] ),
        .\order_q_r_reg[1]_1 (\order_q_r_reg[1]_0 ),
        .\order_q_r_reg[1]_2 (\rtp_timer_r_reg[1] ),
        .\order_q_r_reg[1]_3 (ordered_r_lcl_reg_0),
        .ordered_r(ordered_r),
        .ordered_r_lcl(ordered_r_lcl),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(bank_compare0_n_8),
        .p_9_in(p_9_in),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_0),
        .pass_open_bank_r_lcl_reg_2(bank_compare0_n_10),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),
        .pre_wait_r(pre_wait_r),
        .q_entry_ns(q_entry_ns),
        .\q_entry_r[1]_i_5__1_0 (\q_entry_r[1]_i_5__1 ),
        .\q_entry_r_reg[0]_0 (ras_timer_passed_ns),
        .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0] ),
        .\q_entry_r_reg[0]_2 (\q_entry_r_reg[0]_0 ),
        .\q_entry_r_reg[0]_3 (\q_entry_r_reg[0]_1 ),
        .\q_entry_r_reg[0]_4 (\q_entry_r_reg[0]_2 ),
        .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ),
        .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_0 ),
        .\q_entry_r_reg[1]_2 (\q_entry_r_reg[1]_1 ),
        .q_has_priority_r_reg_0(q_has_priority_r_reg),
        .q_has_priority_r_reg_1(rb_hit_busy_r),
        .q_has_rd(q_has_rd),
        .q_has_rd_r_reg_0(q_has_rd_r_reg),
        .\ras_timer_r_reg[0] (\ras_timer_r_reg[1] ),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_0 ),
        .\ras_timer_r_reg[0]_2 (\ras_timer_r_reg[0]_1 ),
        .\ras_timer_r_reg[0]_3 (\ras_timer_r_reg[0]_2 ),
        .\ras_timer_r_reg[0]_4 (\ras_timer_r_reg[0]_3 ),
        .\ras_timer_r_reg[0]_5 (\ras_timer_r_reg[0]_4 ),
        .\ras_timer_r_reg[1] (bm_end_r1_reg),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1]_0 ),
        .\ras_timer_r_reg[1]_1 (\ras_timer_r_reg[1]_1 ),
        .\ras_timer_r_reg[1]_2 (\ras_timer_r_reg[1]_2 ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),
        .rb_hit_busies_r(rb_hit_busies_r),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_bank_rdy_r_reg(req_wr_r_lcl_reg_0),
        .req_priority_r(req_priority_r),
        .req_wr_r(req_wr_r),
        .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ),
        .\rnk_config_strobe_r_reg[0]_0 (\rnk_config_strobe_r_reg[0]_0 ),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0),
        .wait_for_maint_r_lcl_reg_2(wait_for_maint_r_lcl_reg_1),
        .was_priority(was_priority),
        .was_wr(was_wr));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_state bank_state0
       (.CLK(CLK),
        .D(ras_timer_passed_ns),
        .Q(Q),
        .SR(SR),
        .act_this_rank_r(act_this_rank_r),
        .act_wait_ns(act_wait_ns),
        .act_wait_r_lcl_reg_0(row_cmd_wr),
        .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_0),
        .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),
        .bm_end(bm_end),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_reg_0(bm_end_r1_reg),
        .col_wait_r_reg_0(col_wait_r),
        .col_wait_r_reg_1(col_wait_r_reg_0),
        .col_wait_r_reg_2(\grant_r_reg[0] ),
        .demand_act_priority_r(demand_act_priority_r),
        .demand_act_priority_r_reg_0(wait_for_maint_r_lcl_reg),
        .demand_priority_r_2(demand_priority_r_2),
        .demand_priority_r_reg_0(demand_priority_r),
        .demand_priority_r_reg_1(demand_priority_r_reg),
        .demand_priority_r_reg_2(head_r_lcl_reg),
        .demand_priority_r_reg_3(bank_queue0_n_31),
        .demand_priority_r_reg_4(demand_priority_r_reg_0),
        .demanded_prior_r(demanded_prior_r),
        .demanded_prior_r_3(demanded_prior_r_3),
        .demanded_prior_r_reg_0(demanded_prior_r_reg),
        .\grant_r[3]_i_2__1 (act_wait_r_lcl_reg_1),
        .head_r(head_r),
        .idle_r(idle_r),
        .in0(in0),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r0(ofs_rdy_r0),
        .ofs_rdy_r0_0(ofs_rdy_r0_0),
        .ofs_rdy_r0_1(ofs_rdy_r0_1),
        .ofs_rdy_r_reg_0(ofs_rdy_r_reg),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .phy_mc_cmd_full(phy_mc_cmd_full),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .\pre_4_1_1T_arb.granted_pre_ns (\pre_4_1_1T_arb.granted_pre_ns ),
        .\pre_4_1_1T_arb.granted_pre_r_reg (\pre_4_1_1T_arb.granted_pre_r_reg ),
        .\pre_4_1_1T_arb.granted_pre_r_reg_0 (auto_pre_r),
        .\pre_4_1_1T_arb.granted_pre_r_reg_1 (\pre_4_1_1T_arb.granted_pre_r_reg_0 ),
        .\pre_4_1_1T_arb.granted_pre_r_reg_2 (\pre_4_1_1T_arb.granted_pre_r_reg_1 ),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_wait_r(pre_wait_r),
        .q_has_rd(q_has_rd),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),
        .rd_this_rank_r(rd_this_rank_r),
        .\rd_this_rank_r_reg[0]_0 (rd_wr_r),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_wr_r(req_wr_r),
        .\rtp_timer_r_reg[0]_0 (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1]_0 (\rtp_timer_r_reg[1] ),
        .start_wtp_timer0(start_wtp_timer0),
        .wr_this_rank_r(wr_this_rank_r));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_cntrl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_cntrl__parameterized0
   (idle_r_lcl_reg,
    req_periodic_rd_r,
    rd_wr_r_lcl_reg,
    rb_hit_busy_r_reg,
    row_cmd_wr,
    act_this_rank_r,
    wr_this_rank_r,
    rd_this_rank_r,
    bm_end_r1_0,
    col_wait_r,
    demand_act_priority_r,
    req_bank_rdy_ns,
    demand_priority_r,
    demanded_prior_r,
    ofs_rdy_r,
    pass_open_bank_r_lcl_reg,
    wait_for_maint_r_lcl_reg,
    ordered_r_lcl,
    auto_pre_r,
    pre_bm_end_r_reg,
    idle_r_lcl_reg_0,
    \grant_r_reg[1] ,
    idle_r_lcl_reg_1,
    D,
    head_r_lcl_reg,
    req_wr_r_lcl_reg,
    bm_end_r1_reg,
    \ras_timer_r_reg[1] ,
    \maint_controller.maint_rdy ,
    idle_r_lcl_reg_2,
    pass_open_bank_r_lcl_reg_0,
    \q_entry_r_reg[1] ,
    pre_bm_end_r_reg_0,
    \order_q_r_reg[1] ,
    \order_q_r_reg[1]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    pre_passing_open_bank_r_reg,
    act_wait_r_lcl_reg,
    auto_pre_r_lcl_reg,
    \grant_r_reg[2] ,
    act_wait_r_lcl_reg_0,
    \req_row_r_lcl_reg[13] ,
    demand_priority_r_reg,
    \req_data_buf_addr_r_reg[3] ,
    \req_bank_r_lcl_reg[2] ,
    \req_col_r_reg[9] ,
    CLK,
    periodic_rd_insert,
    req_wr_r_lcl0,
    rb_hit_busy_r_reg_0,
    hi_priority,
    \compute_tail.tail_r_lcl_reg ,
    SR,
    ofs_rdy_r0,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    row_hit_r_reg,
    head_r_lcl_reg_0,
    head_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_1,
    \compute_tail.tail_r_lcl_reg_0 ,
    Q,
    \rtp_timer_r_reg[1] ,
    idle_r,
    rb_hit_busy_r,
    \maint_controller.maint_hit_busies_r_reg[1] ,
    \maint_controller.maint_hit_busies_r_reg[1]_0 ,
    q_has_rd_r_reg,
    was_wr,
    pre_wait_r_reg,
    \cmd_pipe_plus.mc_address_reg[10] ,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \maint_controller.maint_rdy_r1_reg ,
    \maint_controller.maint_rdy_r1_reg_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,
    head_r_lcl_reg_2,
    head_r_lcl_reg_3,
    q_has_priority_r_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    req_bank_rdy_r_reg,
    \rnk_config_strobe_r_reg[0] ,
    \rnk_config_strobe_r_reg[0]_0 ,
    \grant_r[3]_i_12 ,
    \grant_r[3]_i_12_0 ,
    \grant_r[3]_i_12_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,
    rd_wr_r_lcl_reg_0,
    accept_internal_r,
    app_en_r2,
    \q_entry_r_reg[0] ,
    \q_entry_r_reg[0]_0 ,
    rb_hit_busies_r,
    pre_bm_end_r_reg_1,
    was_priority,
    auto_pre_r_lcl_reg_0,
    pass_open_bank_r_lcl_reg_2,
    maint_req_r,
    pass_open_bank_r_lcl_reg_3,
    pass_open_bank_r_lcl_reg_4,
    \cmd_pipe_plus.mc_address_reg[10]_0 ,
    \cmd_pipe_plus.mc_address_reg[10]_1 ,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_2 ,
    \ras_timer_r_reg[0]_3 ,
    \ras_timer_r_reg[0]_4 ,
    row,
    ras_timer_zero_r_reg,
    demand_priority_r_0,
    demanded_prior_r_reg,
    demanded_prior_r_1,
    demand_priority_r_reg_0,
    \rtp_timer_r_reg[0] ,
    \req_data_buf_addr_r_reg[3]_0 ,
    bank,
    \req_col_r_reg[9]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,
    q_entry_ns,
    \q_entry_r_reg[0]_1 ,
    \order_q_r_reg[1]_1 ,
    \order_q_r_reg[0] );
  output [0:0]idle_r_lcl_reg;
  output [0:0]req_periodic_rd_r;
  output [0:0]rd_wr_r_lcl_reg;
  output [0:0]rb_hit_busy_r_reg;
  output [0:0]row_cmd_wr;
  output [0:0]act_this_rank_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output bm_end_r1_0;
  output col_wait_r;
  output demand_act_priority_r;
  output req_bank_rdy_ns;
  output demand_priority_r;
  output demanded_prior_r;
  output ofs_rdy_r;
  output pass_open_bank_r_lcl_reg;
  output wait_for_maint_r_lcl_reg;
  output ordered_r_lcl;
  output auto_pre_r;
  output pre_bm_end_r_reg;
  output idle_r_lcl_reg_0;
  output \grant_r_reg[1] ;
  output idle_r_lcl_reg_1;
  output [0:0]D;
  output head_r_lcl_reg;
  output req_wr_r_lcl_reg;
  output bm_end_r1_reg;
  output \ras_timer_r_reg[1] ;
  output \maint_controller.maint_rdy ;
  output idle_r_lcl_reg_2;
  output pass_open_bank_r_lcl_reg_0;
  output \q_entry_r_reg[1] ;
  output pre_bm_end_r_reg_0;
  output \order_q_r_reg[1] ;
  output \order_q_r_reg[1]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  output pre_passing_open_bank_r_reg;
  output act_wait_r_lcl_reg;
  output auto_pre_r_lcl_reg;
  output \grant_r_reg[2] ;
  output act_wait_r_lcl_reg_0;
  output [13:0]\req_row_r_lcl_reg[13] ;
  output demand_priority_r_reg;
  output [3:0]\req_data_buf_addr_r_reg[3] ;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [9:0]\req_col_r_reg[9] ;
  input CLK;
  input periodic_rd_insert;
  input req_wr_r_lcl0;
  input rb_hit_busy_r_reg_0;
  input hi_priority;
  input [1:0]\compute_tail.tail_r_lcl_reg ;
  input [0:0]SR;
  input ofs_rdy_r0;
  input wait_for_maint_r_lcl_reg_0;
  input wait_for_maint_r_lcl_reg_1;
  input [0:0]row_hit_r_reg;
  input head_r_lcl_reg_0;
  input head_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_1;
  input \compute_tail.tail_r_lcl_reg_0 ;
  input [1:0]Q;
  input \rtp_timer_r_reg[1] ;
  input [2:0]idle_r;
  input [2:0]rb_hit_busy_r;
  input [0:0]\maint_controller.maint_hit_busies_r_reg[1] ;
  input \maint_controller.maint_hit_busies_r_reg[1]_0 ;
  input q_has_rd_r_reg;
  input was_wr;
  input pre_wait_r_reg;
  input [2:0]\cmd_pipe_plus.mc_address_reg[10] ;
  input \ras_timer_r_reg[0] ;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \maint_controller.maint_rdy_r1_reg ;
  input [2:0]\maint_controller.maint_rdy_r1_reg_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  input head_r_lcl_reg_2;
  input head_r_lcl_reg_3;
  input q_has_priority_r_reg;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  input req_bank_rdy_r_reg;
  input \rnk_config_strobe_r_reg[0] ;
  input \rnk_config_strobe_r_reg[0]_0 ;
  input \grant_r[3]_i_12 ;
  input \grant_r[3]_i_12_0 ;
  input \grant_r[3]_i_12_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  input rd_wr_r_lcl_reg_0;
  input accept_internal_r;
  input app_en_r2;
  input \q_entry_r_reg[0] ;
  input \q_entry_r_reg[0]_0 ;
  input [0:0]rb_hit_busies_r;
  input [0:0]pre_bm_end_r_reg_1;
  input was_priority;
  input auto_pre_r_lcl_reg_0;
  input pass_open_bank_r_lcl_reg_2;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg_3;
  input pass_open_bank_r_lcl_reg_4;
  input [0:0]\cmd_pipe_plus.mc_address_reg[10]_0 ;
  input [0:0]\cmd_pipe_plus.mc_address_reg[10]_1 ;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_2 ;
  input \ras_timer_r_reg[0]_3 ;
  input \ras_timer_r_reg[0]_4 ;
  input [13:0]row;
  input ras_timer_zero_r_reg;
  input demand_priority_r_0;
  input demanded_prior_r_reg;
  input demanded_prior_r_1;
  input demand_priority_r_reg_0;
  input \rtp_timer_r_reg[0] ;
  input [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  input [2:0]bank;
  input [9:0]\req_col_r_reg[9]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  input [0:0]q_entry_ns;
  input \q_entry_r_reg[0]_1 ;
  input \order_q_r_reg[1]_1 ;
  input \order_q_r_reg[0] ;

  wire CLK;
  wire [0:0]D;
  wire [1:0]Q;
  wire [0:0]SR;
  wire accept_internal_r;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire app_en_r2;
  wire auto_pre_r;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire [2:0]bank;
  wire bank_compare0_n_5;
  wire bank_compare0_n_7;
  wire bank_compare0_n_8;
  wire bank_queue0_n_23;
  wire bank_queue0_n_25;
  wire [1:1]bm_end;
  wire bm_end_r1_0;
  wire bm_end_r1_reg;
  wire [2:0]\cmd_pipe_plus.mc_address_reg[10] ;
  wire [0:0]\cmd_pipe_plus.mc_address_reg[10]_0 ;
  wire [0:0]\cmd_pipe_plus.mc_address_reg[10]_1 ;
  wire col_wait_r;
  wire [1:0]\compute_tail.tail_r_lcl_reg ;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire demand_act_priority_r;
  wire demand_priority_r;
  wire demand_priority_r_0;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demanded_prior_r;
  wire demanded_prior_r_1;
  wire demanded_prior_r_reg;
  wire \grant_r[3]_i_12 ;
  wire \grant_r[3]_i_12_0 ;
  wire \grant_r[3]_i_12_1 ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[2] ;
  wire [1:1]head_r;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire head_r_lcl_reg_3;
  wire hi_priority;
  wire [1:1]idle_ns;
  wire [2:0]idle_r;
  wire [0:0]idle_r_lcl_reg;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire [0:0]\maint_controller.maint_hit_busies_r_reg[1] ;
  wire \maint_controller.maint_hit_busies_r_reg[1]_0 ;
  wire \maint_controller.maint_rdy ;
  wire \maint_controller.maint_rdy_r1_reg ;
  wire [2:0]\maint_controller.maint_rdy_r1_reg_0 ;
  wire maint_req_r;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[1] ;
  wire \order_q_r_reg[1]_0 ;
  wire \order_q_r_reg[1]_1 ;
  wire ordered_r_lcl;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire pass_open_bank_r_lcl_reg_3;
  wire pass_open_bank_r_lcl_reg_4;
  wire periodic_rd_insert;
  wire pre_bm_end_ns;
  wire pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire [0:0]pre_bm_end_r_reg_1;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r_reg;
  wire pre_wait_r;
  wire pre_wait_r_reg;
  wire [0:0]q_entry_ns;
  wire \q_entry_r_reg[0] ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[1] ;
  wire q_has_priority_r_reg;
  wire q_has_rd;
  wire q_has_rd_r_reg;
  wire [1:0]ras_timer_passed_ns;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire [0:0]rb_hit_busies_r;
  wire [2:0]rb_hit_busy_r;
  wire [0:0]rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire [0:0]rd_this_rank_r;
  wire [0:0]rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire [9:0]\req_col_r_reg[9] ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3] ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13] ;
  wire [1:1]req_wr_r;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire [13:0]row;
  wire [0:0]row_cmd_wr;
  wire [0:0]row_hit_r_reg;
  wire \rtp_timer_r_reg[0] ;
  wire \rtp_timer_r_reg[1] ;
  wire start_wtp_timer0;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire was_priority;
  wire was_wr;
  wire [0:0]wr_this_rank_r;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_compare_1 bank_compare0
       (.CLK(CLK),
        .E(idle_ns),
        .Q(Q[0]),
        .bank(bank),
        .\grant_r_reg[1] (bank_compare0_n_7),
        .hi_priority(hi_priority),
        .maint_req_r(maint_req_r),
        .ordered_r_lcl(ordered_r_lcl),
        .ordered_r_lcl_reg(idle_r_lcl_reg_0),
        .ordered_r_lcl_reg_0(\rtp_timer_r_reg[1] ),
        .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_2),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_3),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_4),
        .pass_open_bank_r_lcl_reg_2(wait_for_maint_r_lcl_reg),
        .periodic_rd_insert(periodic_rd_insert),
        .\q_entry_r_reg[0] (bank_queue0_n_23),
        .rb_hit_busy_r(rb_hit_busy_r),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg),
        .rb_hit_busy_r_reg_1(bank_compare0_n_5),
        .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg_0),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),
        .rd_wr_r_lcl_reg_1(head_r_lcl_reg),
        .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_0),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2] ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_col_r_reg[9]_1 (\req_col_r_reg[9]_0 ),
        .\req_data_buf_addr_r_reg[0]_0 (idle_r_lcl_reg),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .\req_data_buf_addr_r_reg[3]_1 (\req_data_buf_addr_r_reg[3]_0 ),
        .req_periodic_rd_r(req_periodic_rd_r),
        .req_priority_r(req_priority_r),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13] ),
        .req_wr_r(req_wr_r),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg),
        .row(row),
        .row_hit_r_reg_0(bank_compare0_n_8),
        .row_hit_r_reg_1(row_hit_r_reg),
        .start_wtp_timer0(start_wtp_timer0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_queue__parameterized0 bank_queue0
       (.CLK(CLK),
        .D(D),
        .E(idle_ns),
        .Q(Q[0]),
        .SR(SR),
        .accept_internal_r(accept_internal_r),
        .act_wait_ns(act_wait_ns),
        .act_wait_r_lcl_reg(act_wait_r_lcl_reg),
        .act_wait_r_lcl_reg_0(\cmd_pipe_plus.mc_address_reg[10] [0]),
        .app_en_r2(app_en_r2),
        .auto_pre_r_lcl_reg_0(auto_pre_r),
        .auto_pre_r_lcl_reg_1(col_wait_r),
        .auto_pre_r_lcl_reg_2(row_cmd_wr),
        .auto_pre_r_lcl_reg_3(auto_pre_r_lcl_reg_0),
        .bm_end(bm_end),
        .bm_end_r1_0(bm_end_r1_0),
        .bm_end_r1_reg(rd_wr_r_lcl_reg),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg_0 ),
        .\compute_tail.tail_r_lcl_reg_1 (\compute_tail.tail_r_lcl_reg ),
        .\grant_r[3]_i_12 (req_wr_r_lcl_reg),
        .\grant_r[3]_i_12_0 (\grant_r[3]_i_12 ),
        .\grant_r[3]_i_12_1 (\grant_r[3]_i_12_0 ),
        .\grant_r[3]_i_12_2 (\grant_r[3]_i_12_1 ),
        .\grant_r_reg[1] (\grant_r_reg[1] ),
        .head_r(head_r),
        .head_r_lcl_reg_0(head_r_lcl_reg),
        .head_r_lcl_reg_1(head_r_lcl_reg_0),
        .head_r_lcl_reg_2(head_r_lcl_reg_1),
        .head_r_lcl_reg_3(head_r_lcl_reg_2),
        .head_r_lcl_reg_4(head_r_lcl_reg_3),
        .idle_r(idle_r),
        .idle_r_lcl_reg_0(idle_r_lcl_reg),
        .idle_r_lcl_reg_1(idle_r_lcl_reg_0),
        .idle_r_lcl_reg_2(idle_r_lcl_reg_1),
        .idle_r_lcl_reg_3(idle_r_lcl_reg_2),
        .\maint_controller.maint_hit_busies_r_reg[1] (\maint_controller.maint_hit_busies_r_reg[1] ),
        .\maint_controller.maint_hit_busies_r_reg[1]_0 (\maint_controller.maint_hit_busies_r_reg[1]_0 ),
        .\maint_controller.maint_rdy (\maint_controller.maint_rdy ),
        .\maint_controller.maint_rdy_r1_reg (\maint_controller.maint_rdy_r1_reg ),
        .\maint_controller.maint_rdy_r1_reg_0 (\maint_controller.maint_rdy_r1_reg_0 ),
        .\order_q_r_reg[0]_0 (bank_queue0_n_25),
        .\order_q_r_reg[0]_1 (\order_q_r_reg[0] ),
        .\order_q_r_reg[1]_0 (\order_q_r_reg[1] ),
        .\order_q_r_reg[1]_1 (\order_q_r_reg[1]_0 ),
        .\order_q_r_reg[1]_2 (\rtp_timer_r_reg[1] ),
        .\order_q_r_reg[1]_3 (\order_q_r_reg[1]_1 ),
        .ordered_r_lcl(ordered_r_lcl),
        .ordered_r_lcl_reg_0(bank_compare0_n_7),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_0),
        .pass_open_bank_r_lcl_reg_2(pass_open_bank_r_lcl_reg_1),
        .pass_open_bank_r_lcl_reg_3(bank_compare0_n_8),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg),
        .pre_bm_end_r_reg_1(pre_bm_end_r_reg_0),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),
        .pre_wait_r(pre_wait_r),
        .q_entry_ns(q_entry_ns),
        .\q_entry_r_reg[0]_0 (ras_timer_passed_ns),
        .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0] ),
        .\q_entry_r_reg[0]_2 (\q_entry_r_reg[0]_0 ),
        .\q_entry_r_reg[0]_3 (bank_compare0_n_5),
        .\q_entry_r_reg[0]_4 (\q_entry_r_reg[0]_1 ),
        .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ),
        .q_has_priority_r_reg_0(pre_wait_r_reg),
        .q_has_priority_r_reg_1(q_has_priority_r_reg),
        .q_has_priority_r_reg_2(rb_hit_busy_r_reg),
        .q_has_rd(q_has_rd),
        .q_has_rd_r_reg_0(q_has_rd_r_reg),
        .\ras_timer_r_reg[0] (\ras_timer_r_reg[1] ),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_0 ),
        .\ras_timer_r_reg[0]_2 (\ras_timer_r_reg[0]_1 ),
        .\ras_timer_r_reg[0]_3 (\ras_timer_r_reg[0]_2 ),
        .\ras_timer_r_reg[0]_4 (\ras_timer_r_reg[0]_3 ),
        .\ras_timer_r_reg[0]_5 (\ras_timer_r_reg[0]_4 ),
        .\ras_timer_r_reg[1] (bm_end_r1_reg),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1]_0 ),
        .\ras_timer_r_reg[1]_1 (\ras_timer_r_reg[1]_1 ),
        .\ras_timer_r_reg[1]_2 (\ras_timer_r_reg[1]_2 ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (bank_queue0_n_23),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .rb_hit_busies_r(rb_hit_busies_r),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_bank_rdy_r_reg(req_bank_rdy_r_reg),
        .req_priority_r(req_priority_r),
        .req_wr_r(req_wr_r),
        .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ),
        .\rnk_config_strobe_r_reg[0]_0 (\rnk_config_strobe_r_reg[0]_0 ),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0),
        .wait_for_maint_r_lcl_reg_2(wait_for_maint_r_lcl_reg_1),
        .was_priority(was_priority),
        .was_wr(was_wr));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_state__parameterized0 bank_state0
       (.CLK(CLK),
        .D(ras_timer_passed_ns),
        .Q(Q),
        .SR(SR),
        .act_this_rank_r(act_this_rank_r),
        .act_wait_ns(act_wait_ns),
        .act_wait_r_lcl_reg_0(row_cmd_wr),
        .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_0),
        .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),
        .bm_end(bm_end),
        .bm_end_r1_0(bm_end_r1_0),
        .bm_end_r1_reg_0(bm_end_r1_reg),
        .\cmd_pipe_plus.mc_address_reg[10] (\cmd_pipe_plus.mc_address_reg[10] ),
        .\cmd_pipe_plus.mc_address_reg[10]_0 (\req_row_r_lcl_reg[13] [10]),
        .\cmd_pipe_plus.mc_address_reg[10]_1 (\cmd_pipe_plus.mc_address_reg[10]_0 ),
        .\cmd_pipe_plus.mc_address_reg[10]_2 (\cmd_pipe_plus.mc_address_reg[10]_1 ),
        .col_wait_r_reg_0(col_wait_r),
        .col_wait_r_reg_1(\grant_r_reg[1] ),
        .demand_act_priority_r(demand_act_priority_r),
        .demand_act_priority_r_reg_0(wait_for_maint_r_lcl_reg),
        .demand_act_priority_r_reg_1(idle_r_lcl_reg),
        .demand_priority_r_0(demand_priority_r_0),
        .demand_priority_r_reg_0(demand_priority_r),
        .demand_priority_r_reg_1(demand_priority_r_reg),
        .demand_priority_r_reg_2(head_r_lcl_reg),
        .demand_priority_r_reg_3(bank_queue0_n_25),
        .demand_priority_r_reg_4(demand_priority_r_reg_0),
        .demanded_prior_r(demanded_prior_r),
        .demanded_prior_r_1(demanded_prior_r_1),
        .demanded_prior_r_reg_0(demanded_prior_r_reg),
        .\grant_r_reg[2] (\grant_r_reg[2] ),
        .head_r(head_r),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r0(ofs_rdy_r0),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg(pre_bm_end_r_reg_1),
        .pre_bm_end_r_reg_0(auto_pre_r),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_wait_r(pre_wait_r),
        .pre_wait_r_reg_0(pre_wait_r_reg),
        .q_has_rd(q_has_rd),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),
        .rd_this_rank_r(rd_this_rank_r),
        .\rd_this_rank_r_reg[0]_0 (rd_wr_r_lcl_reg),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_wr_r(req_wr_r),
        .\rtp_timer_r_reg[0]_0 (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1]_0 (\rtp_timer_r_reg[1] ),
        .start_wtp_timer0(start_wtp_timer0),
        .wr_this_rank_r(wr_this_rank_r));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_cntrl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_cntrl__parameterized1
   (idle_r,
    req_periodic_rd_r,
    rd_wr_r_lcl_reg,
    rb_hit_busy_r,
    row_cmd_wr,
    act_this_rank_r,
    wr_this_rank_r,
    rd_this_rank_r,
    bm_end_r1_1,
    pre_bm_end_r_reg,
    demand_act_priority_r,
    req_bank_rdy_ns,
    demand_priority_r,
    demanded_prior_r,
    override_demand_r,
    pass_open_bank_r_lcl_reg,
    wait_for_maint_r_lcl_reg,
    ordered_r_lcl_reg,
    auto_pre_r,
    idle_r_lcl_reg,
    pre_bm_end_r_reg_0,
    pre_bm_end_r_reg_1,
    D,
    head_r_lcl_reg,
    req_wr_r_lcl_reg,
    override_demand_r_reg,
    demanded_prior_r_reg,
    override_demand_r_reg_0,
    override_demand_r_reg_1,
    bm_end_r1_reg,
    \ras_timer_r_reg[1] ,
    col_wait_r_reg,
    col_wait_r_reg_0,
    col_wait_r_reg_1,
    rnk_config_strobe_ns,
    \order_q_r_reg[1] ,
    pre_bm_end_r_reg_2,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ,
    pre_passing_open_bank_r_reg,
    ras_timer_zero_r_reg,
    act_wait_r_lcl_reg,
    auto_pre_r_lcl_reg,
    \req_row_r_lcl_reg[13] ,
    act_wait_r_lcl_reg_0,
    demand_priority_r_reg,
    \req_data_buf_addr_r_reg[3] ,
    \req_bank_r_lcl_reg[2] ,
    \req_col_r_reg[9] ,
    CLK,
    periodic_rd_insert,
    req_wr_r_lcl0,
    rb_hit_busy_r_reg,
    hi_priority,
    override_demand_ns,
    SR,
    ofs_rdy_r0,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    row_hit_r_reg,
    head_r_lcl_reg_0,
    head_r_lcl_reg_1,
    \compute_tail.tail_r_lcl_reg ,
    pass_open_bank_r_lcl_reg_0,
    Q,
    \rtp_timer_r_reg[1] ,
    \compute_tail.tail_r_lcl_reg_0 ,
    \compute_tail.tail_r_lcl_reg_1 ,
    \q_entry_r_reg[0] ,
    \compute_tail.tail_r_lcl_reg_2 ,
    \maint_controller.maint_hit_busies_r_reg[2] ,
    \maint_controller.maint_hit_busies_r_reg[2]_0 ,
    q_has_rd_r_reg,
    was_wr,
    demanded_prior_r_0,
    demand_priority_r_1,
    demand_priority_r_2,
    demanded_prior_r_3,
    demand_priority_r_4,
    demanded_prior_r_reg_0,
    demanded_prior_r_5,
    \grant_r_reg[1] ,
    \grant_r_reg[0] ,
    \grant_r_reg[1]_0 ,
    granted_col_r_reg,
    granted_col_r_reg_0,
    act_wait_r_lcl_reg_1,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,
    \q_entry_r_reg[1] ,
    head_r_lcl_reg_2,
    head_r_lcl_reg_3,
    q_has_priority_r_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    \rnk_config_strobe_r_reg[0] ,
    \rnk_config_strobe_r_reg[0]_0 ,
    \rnk_config_strobe_r_reg[0]_1 ,
    \grant_r[0]_i_2 ,
    req_bank_rdy_r_reg,
    \rnk_config_strobe_r_reg[0]_2 ,
    \rnk_config_strobe_r_reg[0]_3 ,
    \grant_r[3]_i_13 ,
    \grant_r[3]_i_13_0 ,
    \grant_r[3]_i_13_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,
    rd_wr_r_lcl_reg_0,
    accept_internal_r,
    app_en_r2,
    \q_entry_r_reg[0]_0 ,
    \q_entry_r_reg[0]_1 ,
    rb_hit_busies_r,
    pre_bm_end_r_reg_3,
    pre_wait_r_reg,
    was_priority,
    auto_pre_r_lcl_reg_0,
    pass_open_bank_r_lcl_reg_1,
    maint_req_r,
    pass_open_bank_r_lcl_reg_2,
    pass_open_bank_r_lcl_reg_3,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_2 ,
    \ras_timer_r_reg[0]_3 ,
    \ras_timer_r_reg[0]_4 ,
    row,
    ras_timer_zero_r_reg_0,
    demand_priority_r_reg_0,
    \rtp_timer_r_reg[0] ,
    \req_data_buf_addr_r_reg[3]_0 ,
    bank,
    \req_col_r_reg[9]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,
    \q_entry_r_reg[1]_0 ,
    \q_entry_r_reg[0]_2 ,
    \order_q_r_reg[1]_0 ,
    \order_q_r_reg[0] );
  output [0:0]idle_r;
  output [0:0]req_periodic_rd_r;
  output [0:0]rd_wr_r_lcl_reg;
  output [0:0]rb_hit_busy_r;
  output [0:0]row_cmd_wr;
  output [0:0]act_this_rank_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output bm_end_r1_1;
  output [0:0]pre_bm_end_r_reg;
  output demand_act_priority_r;
  output req_bank_rdy_ns;
  output demand_priority_r;
  output demanded_prior_r;
  output override_demand_r;
  output pass_open_bank_r_lcl_reg;
  output wait_for_maint_r_lcl_reg;
  output ordered_r_lcl_reg;
  output auto_pre_r;
  output idle_r_lcl_reg;
  output pre_bm_end_r_reg_0;
  output pre_bm_end_r_reg_1;
  output [0:0]D;
  output head_r_lcl_reg;
  output req_wr_r_lcl_reg;
  output override_demand_r_reg;
  output demanded_prior_r_reg;
  output override_demand_r_reg_0;
  output override_demand_r_reg_1;
  output bm_end_r1_reg;
  output \ras_timer_r_reg[1] ;
  output col_wait_r_reg;
  output col_wait_r_reg_0;
  output col_wait_r_reg_1;
  output rnk_config_strobe_ns;
  output \order_q_r_reg[1] ;
  output pre_bm_end_r_reg_2;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  output pre_passing_open_bank_r_reg;
  output ras_timer_zero_r_reg;
  output act_wait_r_lcl_reg;
  output auto_pre_r_lcl_reg;
  output [13:0]\req_row_r_lcl_reg[13] ;
  output act_wait_r_lcl_reg_0;
  output demand_priority_r_reg;
  output [3:0]\req_data_buf_addr_r_reg[3] ;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [9:0]\req_col_r_reg[9] ;
  input CLK;
  input periodic_rd_insert;
  input req_wr_r_lcl0;
  input rb_hit_busy_r_reg;
  input hi_priority;
  input override_demand_ns;
  input [0:0]SR;
  input ofs_rdy_r0;
  input wait_for_maint_r_lcl_reg_0;
  input wait_for_maint_r_lcl_reg_1;
  input [0:0]row_hit_r_reg;
  input head_r_lcl_reg_0;
  input head_r_lcl_reg_1;
  input \compute_tail.tail_r_lcl_reg ;
  input pass_open_bank_r_lcl_reg_0;
  input [3:0]Q;
  input \rtp_timer_r_reg[1] ;
  input \compute_tail.tail_r_lcl_reg_0 ;
  input \compute_tail.tail_r_lcl_reg_1 ;
  input [2:0]\q_entry_r_reg[0] ;
  input [0:0]\compute_tail.tail_r_lcl_reg_2 ;
  input [0:0]\maint_controller.maint_hit_busies_r_reg[2] ;
  input \maint_controller.maint_hit_busies_r_reg[2]_0 ;
  input q_has_rd_r_reg;
  input was_wr;
  input demanded_prior_r_0;
  input demand_priority_r_1;
  input demand_priority_r_2;
  input demanded_prior_r_3;
  input demand_priority_r_4;
  input demanded_prior_r_reg_0;
  input demanded_prior_r_5;
  input \grant_r_reg[1] ;
  input \grant_r_reg[0] ;
  input \grant_r_reg[1]_0 ;
  input granted_col_r_reg;
  input granted_col_r_reg_0;
  input [0:0]act_wait_r_lcl_reg_1;
  input \ras_timer_r_reg[0] ;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  input \q_entry_r_reg[1] ;
  input head_r_lcl_reg_2;
  input head_r_lcl_reg_3;
  input q_has_priority_r_reg;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  input \rnk_config_strobe_r_reg[0] ;
  input \rnk_config_strobe_r_reg[0]_0 ;
  input \rnk_config_strobe_r_reg[0]_1 ;
  input \grant_r[0]_i_2 ;
  input req_bank_rdy_r_reg;
  input \rnk_config_strobe_r_reg[0]_2 ;
  input \rnk_config_strobe_r_reg[0]_3 ;
  input \grant_r[3]_i_13 ;
  input \grant_r[3]_i_13_0 ;
  input \grant_r[3]_i_13_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  input rd_wr_r_lcl_reg_0;
  input accept_internal_r;
  input app_en_r2;
  input \q_entry_r_reg[0]_0 ;
  input \q_entry_r_reg[0]_1 ;
  input [0:0]rb_hit_busies_r;
  input [0:0]pre_bm_end_r_reg_3;
  input pre_wait_r_reg;
  input was_priority;
  input auto_pre_r_lcl_reg_0;
  input pass_open_bank_r_lcl_reg_1;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg_2;
  input pass_open_bank_r_lcl_reg_3;
  input \pre_4_1_1T_arb.granted_pre_r_reg ;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_2 ;
  input \ras_timer_r_reg[0]_3 ;
  input \ras_timer_r_reg[0]_4 ;
  input [13:0]row;
  input ras_timer_zero_r_reg_0;
  input demand_priority_r_reg_0;
  input \rtp_timer_r_reg[0] ;
  input [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  input [2:0]bank;
  input [9:0]\req_col_r_reg[9]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  input \q_entry_r_reg[1]_0 ;
  input \q_entry_r_reg[0]_2 ;
  input \order_q_r_reg[1]_0 ;
  input \order_q_r_reg[0] ;

  wire CLK;
  wire [0:0]D;
  wire [3:0]Q;
  wire [0:0]SR;
  wire accept_internal_r;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire [0:0]act_wait_r_lcl_reg_1;
  wire app_en_r2;
  wire auto_pre_r;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire [2:0]bank;
  wire bank_compare0_n_5;
  wire bank_compare0_n_7;
  wire bank_compare0_n_8;
  wire bank_queue0_n_19;
  wire bank_queue0_n_20;
  wire bank_queue0_n_23;
  wire bank_queue0_n_25;
  wire bm_end_r1_1;
  wire bm_end_r1_reg;
  wire col_wait_r;
  wire col_wait_r_reg;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire \compute_tail.tail_r_lcl_reg ;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire \compute_tail.tail_r_lcl_reg_1 ;
  wire [0:0]\compute_tail.tail_r_lcl_reg_2 ;
  wire demand_act_priority_r;
  wire demand_priority_r;
  wire demand_priority_r_1;
  wire demand_priority_r_2;
  wire demand_priority_r_4;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demanded_prior_r;
  wire demanded_prior_r_0;
  wire demanded_prior_r_3;
  wire demanded_prior_r_5;
  wire demanded_prior_r_reg;
  wire demanded_prior_r_reg_0;
  wire \grant_r[0]_i_2 ;
  wire \grant_r[3]_i_13 ;
  wire \grant_r[3]_i_13_0 ;
  wire \grant_r[3]_i_13_1 ;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire [2:2]head_r;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire head_r_lcl_reg_3;
  wire hi_priority;
  wire [2:2]idle_ns;
  wire [0:0]idle_r;
  wire idle_r_lcl_reg;
  wire [0:0]\maint_controller.maint_hit_busies_r_reg[2] ;
  wire \maint_controller.maint_hit_busies_r_reg[2]_0 ;
  wire maint_req_r;
  wire ofs_rdy_r0;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[1] ;
  wire \order_q_r_reg[1]_0 ;
  wire ordered_r_lcl_reg;
  wire override_demand_ns;
  wire override_demand_r;
  wire override_demand_r_reg;
  wire override_demand_r_reg_0;
  wire override_demand_r_reg_1;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire pass_open_bank_r_lcl_reg_3;
  wire periodic_rd_insert;
  wire \pre_4_1_1T_arb.granted_pre_r_reg ;
  wire pre_bm_end_ns;
  wire [0:0]pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_bm_end_r_reg_1;
  wire pre_bm_end_r_reg_2;
  wire [0:0]pre_bm_end_r_reg_3;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r_reg;
  wire pre_wait_r;
  wire pre_wait_r_reg;
  wire [2:0]\q_entry_r_reg[0] ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire \q_entry_r_reg[1] ;
  wire \q_entry_r_reg[1]_0 ;
  wire q_has_priority_r_reg;
  wire q_has_rd;
  wire q_has_rd_r_reg;
  wire [1:0]ras_timer_passed_ns;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  wire [0:0]rb_hit_busies_r;
  wire [0:0]rb_hit_busy_r;
  wire rb_hit_busy_r_reg;
  wire [0:0]rd_this_rank_r;
  wire [0:0]rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire [9:0]\req_col_r_reg[9] ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3] ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13] ;
  wire [2:2]req_wr_r;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg;
  wire rnk_config_strobe_ns;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire \rnk_config_strobe_r_reg[0]_1 ;
  wire \rnk_config_strobe_r_reg[0]_2 ;
  wire \rnk_config_strobe_r_reg[0]_3 ;
  wire [13:0]row;
  wire [0:0]row_cmd_wr;
  wire [0:0]row_hit_r_reg;
  wire \rtp_timer_r_reg[0] ;
  wire \rtp_timer_r_reg[1] ;
  wire start_wtp_timer0;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire was_priority;
  wire was_wr;
  wire [0:0]wr_this_rank_r;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_compare_0 bank_compare0
       (.CLK(CLK),
        .E(idle_ns),
        .Q(Q[2]),
        .bank(bank),
        .\grant_r_reg[2] (bank_compare0_n_7),
        .hi_priority(hi_priority),
        .maint_req_r(maint_req_r),
        .ordered_r_lcl_reg(idle_r_lcl_reg),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(\rtp_timer_r_reg[1] ),
        .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_1),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_2),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_3),
        .pass_open_bank_r_lcl_reg_2(wait_for_maint_r_lcl_reg),
        .periodic_rd_insert(periodic_rd_insert),
        .\q_entry_r_reg[0] (\q_entry_r_reg[0] ),
        .\q_entry_r_reg[0]_0 (bank_queue0_n_20),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r),
        .rb_hit_busy_r_reg_1(bank_compare0_n_5),
        .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),
        .rd_wr_r_lcl_reg_1(head_r_lcl_reg),
        .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_0),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2] ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_col_r_reg[9]_1 (\req_col_r_reg[9]_0 ),
        .\req_data_buf_addr_r_reg[0]_0 (idle_r),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .\req_data_buf_addr_r_reg[3]_1 (\req_data_buf_addr_r_reg[3]_0 ),
        .req_periodic_rd_r(req_periodic_rd_r),
        .req_priority_r(req_priority_r),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13] ),
        .req_wr_r(req_wr_r),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg),
        .row(row),
        .row_hit_r_reg_0(bank_compare0_n_8),
        .row_hit_r_reg_1(row_hit_r_reg),
        .start_wtp_timer0(start_wtp_timer0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_queue__parameterized1 bank_queue0
       (.CLK(CLK),
        .D(D),
        .E(idle_ns),
        .Q(Q[2]),
        .SR(SR),
        .accept_internal_r(accept_internal_r),
        .act_wait_ns(act_wait_ns),
        .act_wait_r_lcl_reg(act_wait_r_lcl_reg),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_1),
        .app_en_r2(app_en_r2),
        .auto_pre_r_lcl_reg_0(auto_pre_r),
        .auto_pre_r_lcl_reg_1(row_cmd_wr),
        .auto_pre_r_lcl_reg_2(pre_wait_r_reg),
        .auto_pre_r_lcl_reg_3(auto_pre_r_lcl_reg_0),
        .bm_end_r1_1(bm_end_r1_1),
        .bm_end_r1_reg(rd_wr_r_lcl_reg),
        .col_wait_r(col_wait_r),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg ),
        .\compute_tail.tail_r_lcl_reg_1 (\compute_tail.tail_r_lcl_reg_0 ),
        .\compute_tail.tail_r_lcl_reg_2 (\compute_tail.tail_r_lcl_reg_1 ),
        .\compute_tail.tail_r_lcl_reg_3 (\compute_tail.tail_r_lcl_reg_2 ),
        .\grant_r[3]_i_13 (\grant_r[3]_i_13 ),
        .\grant_r[3]_i_13_0 (\grant_r[3]_i_13_0 ),
        .\grant_r[3]_i_13_1 (req_wr_r_lcl_reg),
        .\grant_r[3]_i_13_2 (\grant_r[3]_i_13_1 ),
        .\grant_r_reg[2] (bank_queue0_n_19),
        .head_r(head_r),
        .head_r_lcl_reg_0(head_r_lcl_reg),
        .head_r_lcl_reg_1(head_r_lcl_reg_0),
        .head_r_lcl_reg_2(head_r_lcl_reg_1),
        .head_r_lcl_reg_3(head_r_lcl_reg_2),
        .head_r_lcl_reg_4(head_r_lcl_reg_3),
        .idle_r_lcl_reg_0(idle_r),
        .idle_r_lcl_reg_1(idle_r_lcl_reg),
        .\maint_controller.maint_hit_busies_r_reg[2] (\maint_controller.maint_hit_busies_r_reg[2] ),
        .\maint_controller.maint_hit_busies_r_reg[2]_0 (\maint_controller.maint_hit_busies_r_reg[2]_0 ),
        .\order_q_r_reg[0]_0 (bank_queue0_n_23),
        .\order_q_r_reg[0]_1 (\order_q_r_reg[0] ),
        .\order_q_r_reg[1]_0 (\order_q_r_reg[1] ),
        .\order_q_r_reg[1]_1 (bank_queue0_n_25),
        .\order_q_r_reg[1]_2 (\rtp_timer_r_reg[1] ),
        .\order_q_r_reg[1]_3 (\order_q_r_reg[1]_0 ),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(bank_compare0_n_7),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_0),
        .pass_open_bank_r_lcl_reg_2(bank_compare0_n_8),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg),
        .pre_bm_end_r_reg_1(pre_bm_end_r_reg_0),
        .pre_bm_end_r_reg_2(pre_bm_end_r_reg_1),
        .pre_bm_end_r_reg_3(pre_bm_end_r_reg_2),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),
        .pre_wait_r(pre_wait_r),
        .\q_entry_r_reg[0]_0 (ras_timer_passed_ns),
        .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0]_0 ),
        .\q_entry_r_reg[0]_2 (\q_entry_r_reg[0]_1 ),
        .\q_entry_r_reg[0]_3 (\q_entry_r_reg[0]_2 ),
        .\q_entry_r_reg[0]_4 (bank_compare0_n_5),
        .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ),
        .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_0 ),
        .q_has_priority_r_reg_0(q_has_priority_r_reg),
        .q_has_rd(q_has_rd),
        .q_has_rd_r_reg_0(q_has_rd_r_reg),
        .\ras_timer_r_reg[0] (\ras_timer_r_reg[1] ),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_0 ),
        .\ras_timer_r_reg[0]_2 (\ras_timer_r_reg[0]_1 ),
        .\ras_timer_r_reg[0]_3 (\ras_timer_r_reg[0]_2 ),
        .\ras_timer_r_reg[0]_4 (\ras_timer_r_reg[0]_3 ),
        .\ras_timer_r_reg[0]_5 (\ras_timer_r_reg[0]_4 ),
        .\ras_timer_r_reg[1] (bm_end_r1_reg),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1]_0 ),
        .\ras_timer_r_reg[1]_1 (\ras_timer_r_reg[1]_1 ),
        .\ras_timer_r_reg[1]_2 (\ras_timer_r_reg[1]_2 ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (bank_queue0_n_20),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ),
        .rb_hit_busies_r(rb_hit_busies_r),
        .rb_hit_busy_r(rb_hit_busy_r),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_bank_rdy_r_reg(req_bank_rdy_r_reg),
        .req_priority_r(req_priority_r),
        .req_wr_r(req_wr_r),
        .rnk_config_strobe_ns(rnk_config_strobe_ns),
        .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ),
        .\rnk_config_strobe_r_reg[0]_0 (\rnk_config_strobe_r_reg[0]_0 ),
        .\rnk_config_strobe_r_reg[0]_1 (\rnk_config_strobe_r_reg[0]_1 ),
        .\rnk_config_strobe_r_reg[0]_2 (\rnk_config_strobe_r_reg[0]_2 ),
        .\rnk_config_strobe_r_reg[0]_3 (\rnk_config_strobe_r_reg[0]_3 ),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0),
        .wait_for_maint_r_lcl_reg_2(wait_for_maint_r_lcl_reg_1),
        .was_priority(was_priority),
        .was_wr(was_wr));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_state__parameterized1 bank_state0
       (.CLK(CLK),
        .D(ras_timer_passed_ns),
        .Q(Q),
        .SR(SR),
        .act_this_rank_r(act_this_rank_r),
        .act_wait_ns(act_wait_ns),
        .act_wait_r_lcl_reg_0(row_cmd_wr),
        .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_0),
        .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),
        .bm_end_r1_1(bm_end_r1_1),
        .bm_end_r1_reg_0(bm_end_r1_reg),
        .bm_end_r1_reg_1(pre_bm_end_r_reg),
        .col_wait_r(col_wait_r),
        .col_wait_r_reg_0(col_wait_r_reg),
        .col_wait_r_reg_1(col_wait_r_reg_0),
        .col_wait_r_reg_2(col_wait_r_reg_1),
        .col_wait_r_reg_3(bank_queue0_n_19),
        .demand_act_priority_r(demand_act_priority_r),
        .demand_act_priority_r_reg_0(wait_for_maint_r_lcl_reg),
        .demand_priority_r_1(demand_priority_r_1),
        .demand_priority_r_2(demand_priority_r_2),
        .demand_priority_r_4(demand_priority_r_4),
        .demand_priority_r_reg_0(demand_priority_r),
        .demand_priority_r_reg_1(demand_priority_r_reg),
        .demand_priority_r_reg_2(head_r_lcl_reg),
        .demand_priority_r_reg_3(bank_queue0_n_23),
        .demand_priority_r_reg_4(demand_priority_r_reg_0),
        .demanded_prior_r_0(demanded_prior_r_0),
        .demanded_prior_r_3(demanded_prior_r_3),
        .demanded_prior_r_5(demanded_prior_r_5),
        .demanded_prior_r_reg_0(demanded_prior_r),
        .demanded_prior_r_reg_1(demanded_prior_r_reg),
        .demanded_prior_r_reg_2(demanded_prior_r_reg_0),
        .\grant_r[0]_i_2_0 (\grant_r[0]_i_2 ),
        .\grant_r[0]_i_2_1 (bank_queue0_n_25),
        .\grant_r[3]_i_5__1 (act_wait_r_lcl_reg_1),
        .\grant_r_reg[0] (\grant_r_reg[0] ),
        .\grant_r_reg[1] (\grant_r_reg[1] ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1]_0 ),
        .granted_col_r_reg(granted_col_r_reg),
        .granted_col_r_reg_0(granted_col_r_reg_0),
        .head_r(head_r),
        .idle_r(idle_r),
        .ofs_rdy_r0(ofs_rdy_r0),
        .override_demand_ns(override_demand_ns),
        .override_demand_r_reg_0(override_demand_r),
        .override_demand_r_reg_1(override_demand_r_reg),
        .override_demand_r_reg_2(override_demand_r_reg_0),
        .override_demand_r_reg_3(override_demand_r_reg_1),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .\pre_4_1_1T_arb.granted_pre_r_reg (\pre_4_1_1T_arb.granted_pre_r_reg ),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg(pre_bm_end_r_reg_3),
        .pre_bm_end_r_reg_0(auto_pre_r),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_wait_r(pre_wait_r),
        .pre_wait_r_reg_0(pre_wait_r_reg),
        .q_has_rd(q_has_rd),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_0),
        .rd_this_rank_r(rd_this_rank_r),
        .\rd_this_rank_r_reg[0]_0 (rd_wr_r_lcl_reg),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_wr_r(req_wr_r),
        .\rtp_timer_r_reg[0]_0 (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1]_0 (\rtp_timer_r_reg[1] ),
        .start_wtp_timer0(start_wtp_timer0),
        .wr_this_rank_r(wr_this_rank_r));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_cntrl" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_cntrl__parameterized2
   (idle_r,
    req_periodic_rd_r,
    rd_wr_r_lcl_reg,
    rb_hit_busy_r_reg,
    act_wait_r_lcl_reg,
    act_this_rank_r,
    wr_this_rank_r,
    rd_this_rank_r,
    bm_end_r1_2,
    pre_bm_end_r_reg,
    demand_act_priority_r,
    req_bank_rdy_ns,
    demand_priority_r,
    demanded_prior_r,
    ofs_rdy_r,
    pass_open_bank_r_lcl_reg,
    wait_for_maint_r_lcl_reg,
    ordered_r_lcl_reg,
    auto_pre_r,
    idle_r_lcl_reg,
    D,
    head_r_lcl_reg,
    req_wr_r_lcl_reg,
    \ras_timer_r_reg[1] ,
    bm_end_r1_reg,
    col_wait_r_reg,
    act_wait_r_lcl_reg_0,
    \order_q_r_reg[1] ,
    rb_hit_busies_r,
    \order_q_r_reg[1]_0 ,
    pre_passing_open_bank_r_reg,
    act_wait_r_lcl_reg_1,
    auto_pre_r_lcl_reg,
    \req_row_r_lcl_reg[13] ,
    demand_priority_r_reg,
    demanded_prior_r_reg,
    idle_r_lcl_reg_0,
    \req_data_buf_addr_r_reg[3] ,
    \req_bank_r_lcl_reg[2] ,
    \req_col_r_reg[9] ,
    CLK,
    periodic_rd_insert,
    req_wr_r_lcl0,
    rb_hit_busy_r_reg_0,
    hi_priority,
    SR,
    ofs_rdy_r0,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    row_hit_r_reg,
    \compute_tail.tail_r_lcl_reg ,
    head_r_lcl_reg_0,
    pass_open_bank_r_lcl_reg_0,
    Q,
    \rtp_timer_r_reg[1] ,
    col_wait_r_reg_0,
    \maint_controller.maint_hit_busies_r_reg[3] ,
    \maint_controller.maint_hit_busies_r_reg[3]_0 ,
    q_has_rd_r_reg,
    was_wr,
    act_wait_r_lcl_reg_2,
    \ras_timer_r_reg[0] ,
    \grant_r[3]_i_6 ,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,
    \q_entry_r_reg[1] ,
    head_r_lcl_reg_1,
    \q_entry_r_reg[0] ,
    q_has_priority_r_reg,
    demand_priority_r_reg_0,
    rb_hit_busy_r,
    head_r_lcl_i_3,
    head_r_lcl_i_3_0,
    head_r_lcl_i_3_1,
    req_bank_rdy_r_reg,
    \rnk_config_strobe_r_reg[0] ,
    \rnk_config_strobe_r_reg[0]_0 ,
    demand_priority_r_reg_1,
    demand_priority_r_reg_2,
    demand_priority_r_reg_3,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ,
    rd_wr_r_lcl_reg_0,
    pre_wait_r_reg,
    accept_internal_r,
    app_en_r2,
    \order_q_r_reg[1]_1 ,
    \order_q_r_reg[1]_2 ,
    pre_bm_end_r_reg_0,
    auto_pre_r_lcl_reg_0,
    was_priority,
    pass_open_bank_r_lcl_reg_1,
    maint_req_r,
    pass_open_bank_r_lcl_reg_2,
    pass_open_bank_r_lcl_reg_3,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_2 ,
    \ras_timer_r_reg[0]_3 ,
    \ras_timer_r_reg[0]_4 ,
    row,
    ras_timer_zero_r_reg,
    demand_priority_r_0,
    demanded_prior_r_reg_0,
    demanded_prior_r_1,
    \q_entry_r_reg[1]_0 ,
    \starve_limit_cntr_r_reg[0] ,
    \rtp_timer_r_reg[0] ,
    \req_data_buf_addr_r_reg[3]_0 ,
    bank,
    \req_col_r_reg[9]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    \q_entry_r_reg[1]_1 ,
    \q_entry_r_reg[0]_0 ,
    \order_q_r_reg[1]_3 ,
    \order_q_r_reg[0] );
  output [0:0]idle_r;
  output [0:0]req_periodic_rd_r;
  output [0:0]rd_wr_r_lcl_reg;
  output [0:0]rb_hit_busy_r_reg;
  output [0:0]act_wait_r_lcl_reg;
  output [0:0]act_this_rank_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output bm_end_r1_2;
  output [0:0]pre_bm_end_r_reg;
  output demand_act_priority_r;
  output req_bank_rdy_ns;
  output demand_priority_r;
  output demanded_prior_r;
  output ofs_rdy_r;
  output pass_open_bank_r_lcl_reg;
  output wait_for_maint_r_lcl_reg;
  output ordered_r_lcl_reg;
  output auto_pre_r;
  output idle_r_lcl_reg;
  output [0:0]D;
  output head_r_lcl_reg;
  output req_wr_r_lcl_reg;
  output \ras_timer_r_reg[1] ;
  output bm_end_r1_reg;
  output col_wait_r_reg;
  output act_wait_r_lcl_reg_0;
  output \order_q_r_reg[1] ;
  output [2:0]rb_hit_busies_r;
  output \order_q_r_reg[1]_0 ;
  output pre_passing_open_bank_r_reg;
  output act_wait_r_lcl_reg_1;
  output auto_pre_r_lcl_reg;
  output [13:0]\req_row_r_lcl_reg[13] ;
  output demand_priority_r_reg;
  output demanded_prior_r_reg;
  output idle_r_lcl_reg_0;
  output [3:0]\req_data_buf_addr_r_reg[3] ;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [9:0]\req_col_r_reg[9] ;
  input CLK;
  input periodic_rd_insert;
  input req_wr_r_lcl0;
  input rb_hit_busy_r_reg_0;
  input hi_priority;
  input [0:0]SR;
  input ofs_rdy_r0;
  input wait_for_maint_r_lcl_reg_0;
  input wait_for_maint_r_lcl_reg_1;
  input [0:0]row_hit_r_reg;
  input \compute_tail.tail_r_lcl_reg ;
  input head_r_lcl_reg_0;
  input pass_open_bank_r_lcl_reg_0;
  input [1:0]Q;
  input \rtp_timer_r_reg[1] ;
  input [0:0]col_wait_r_reg_0;
  input [0:0]\maint_controller.maint_hit_busies_r_reg[3] ;
  input \maint_controller.maint_hit_busies_r_reg[3]_0 ;
  input q_has_rd_r_reg;
  input was_wr;
  input act_wait_r_lcl_reg_2;
  input \ras_timer_r_reg[0] ;
  input \grant_r[3]_i_6 ;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  input \q_entry_r_reg[1] ;
  input head_r_lcl_reg_1;
  input \q_entry_r_reg[0] ;
  input q_has_priority_r_reg;
  input demand_priority_r_reg_0;
  input [2:0]rb_hit_busy_r;
  input head_r_lcl_i_3;
  input [0:0]head_r_lcl_i_3_0;
  input head_r_lcl_i_3_1;
  input req_bank_rdy_r_reg;
  input \rnk_config_strobe_r_reg[0] ;
  input \rnk_config_strobe_r_reg[0]_0 ;
  input demand_priority_r_reg_1;
  input demand_priority_r_reg_2;
  input demand_priority_r_reg_3;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  input rd_wr_r_lcl_reg_0;
  input pre_wait_r_reg;
  input accept_internal_r;
  input app_en_r2;
  input \order_q_r_reg[1]_1 ;
  input \order_q_r_reg[1]_2 ;
  input [0:0]pre_bm_end_r_reg_0;
  input auto_pre_r_lcl_reg_0;
  input was_priority;
  input pass_open_bank_r_lcl_reg_1;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg_2;
  input pass_open_bank_r_lcl_reg_3;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_2 ;
  input \ras_timer_r_reg[0]_3 ;
  input \ras_timer_r_reg[0]_4 ;
  input [13:0]row;
  input ras_timer_zero_r_reg;
  input demand_priority_r_0;
  input demanded_prior_r_reg_0;
  input demanded_prior_r_1;
  input [2:0]\q_entry_r_reg[1]_0 ;
  input \starve_limit_cntr_r_reg[0] ;
  input \rtp_timer_r_reg[0] ;
  input [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  input [2:0]bank;
  input [9:0]\req_col_r_reg[9]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  input \q_entry_r_reg[1]_1 ;
  input \q_entry_r_reg[0]_0 ;
  input \order_q_r_reg[1]_3 ;
  input \order_q_r_reg[0] ;

  wire CLK;
  wire [0:0]D;
  wire [1:0]Q;
  wire [0:0]SR;
  wire accept_internal_r;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire [0:0]act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire act_wait_r_lcl_reg_2;
  wire app_en_r2;
  wire auto_pre_r;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire [2:0]bank;
  wire bank_compare0_n_6;
  wire bank_compare0_n_7;
  wire bank_queue0_n_14;
  wire bank_queue0_n_17;
  wire bank_state0_n_22;
  wire bank_state0_n_8;
  wire bm_end_r1_2;
  wire bm_end_r1_reg;
  wire col_wait_r;
  wire col_wait_r_reg;
  wire [0:0]col_wait_r_reg_0;
  wire \compute_tail.tail_r_lcl_reg ;
  wire demand_act_priority_r;
  wire demand_priority_ns;
  wire demand_priority_r;
  wire demand_priority_r_0;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire demand_priority_r_reg_3;
  wire demanded_prior_r;
  wire demanded_prior_r_1;
  wire demanded_prior_r_reg;
  wire demanded_prior_r_reg_0;
  wire \grant_r[3]_i_6 ;
  wire [3:3]head_r;
  wire head_r_lcl_i_3;
  wire [0:0]head_r_lcl_i_3_0;
  wire head_r_lcl_i_3_1;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire hi_priority;
  wire [3:3]idle_ns;
  wire [0:0]idle_r;
  wire idle_r_lcl_reg;
  wire idle_r_lcl_reg_0;
  wire [0:0]\maint_controller.maint_hit_busies_r_reg[3] ;
  wire \maint_controller.maint_hit_busies_r_reg[3]_0 ;
  wire maint_req_r;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[1] ;
  wire \order_q_r_reg[1]_0 ;
  wire \order_q_r_reg[1]_1 ;
  wire \order_q_r_reg[1]_2 ;
  wire \order_q_r_reg[1]_3 ;
  wire ordered_r_lcl_reg;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire pass_open_bank_r_lcl_reg_3;
  wire periodic_rd_insert;
  wire pre_bm_end_ns;
  wire [0:0]pre_bm_end_r_reg;
  wire [0:0]pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r_reg;
  wire pre_wait_r;
  wire pre_wait_r_reg;
  wire \q_entry_r_reg[0] ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[1] ;
  wire [2:0]\q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire q_has_priority_r_reg;
  wire q_has_rd;
  wire q_has_rd_r_reg;
  wire [1:0]ras_timer_passed_ns;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;
  wire [2:0]rb_hit_busies_r;
  wire [2:0]rb_hit_busy_r;
  wire [0:0]rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire [0:0]rd_this_rank_r;
  wire [0:0]rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire [9:0]\req_col_r_reg[9] ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3] ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13] ;
  wire [3:3]req_wr_r;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire [13:0]row;
  wire [0:0]row_hit_r_reg;
  wire \rtp_timer_r_reg[0] ;
  wire \rtp_timer_r_reg[1] ;
  wire start_wtp_timer0;
  wire \starve_limit_cntr_r_reg[0] ;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire was_priority;
  wire was_wr;
  wire [0:0]wr_this_rank_r;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_compare bank_compare0
       (.CLK(CLK),
        .E(idle_ns),
        .Q(Q[1]),
        .bank(bank),
        .\grant_r_reg[3] (bank_compare0_n_6),
        .hi_priority(hi_priority),
        .maint_req_r(maint_req_r),
        .ordered_r_lcl_reg(idle_r_lcl_reg),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(pre_wait_r_reg),
        .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_1),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_2),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_3),
        .pass_open_bank_r_lcl_reg_2(wait_for_maint_r_lcl_reg),
        .periodic_rd_insert(periodic_rd_insert),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg),
        .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_0),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),
        .rd_wr_r_lcl_reg_1(head_r_lcl_reg),
        .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_0),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2] ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_col_r_reg[9]_1 (\req_col_r_reg[9]_0 ),
        .\req_data_buf_addr_r_reg[0]_0 (idle_r),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .\req_data_buf_addr_r_reg[3]_1 (\req_data_buf_addr_r_reg[3]_0 ),
        .req_periodic_rd_r(req_periodic_rd_r),
        .req_priority_r(req_priority_r),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13] ),
        .req_wr_r(req_wr_r),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg),
        .row(row),
        .row_hit_r_reg_0(bank_compare0_n_7),
        .row_hit_r_reg_1(row_hit_r_reg),
        .start_wtp_timer0(start_wtp_timer0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_queue__parameterized2 bank_queue0
       (.CLK(CLK),
        .D(D),
        .E(idle_ns),
        .Q(Q[1]),
        .SR(SR),
        .accept_internal_r(accept_internal_r),
        .act_wait_ns(act_wait_ns),
        .act_wait_r_lcl_reg(act_wait_r_lcl_reg_1),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0),
        .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_2),
        .app_en_r2(app_en_r2),
        .auto_pre_r_lcl_reg_0(auto_pre_r),
        .auto_pre_r_lcl_reg_1(act_wait_r_lcl_reg),
        .auto_pre_r_lcl_reg_2(pre_wait_r_reg),
        .auto_pre_r_lcl_reg_3(auto_pre_r_lcl_reg_0),
        .bm_end_r1_2(bm_end_r1_2),
        .bm_end_r1_reg(rd_wr_r_lcl_reg),
        .col_wait_r(col_wait_r),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg ),
        .demand_priority_ns(demand_priority_ns),
        .demand_priority_r_reg(bank_state0_n_8),
        .demand_priority_r_reg_0(bank_state0_n_22),
        .demand_priority_r_reg_1(demand_priority_r_reg_0),
        .demand_priority_r_reg_2(demand_priority_r_reg_1),
        .demand_priority_r_reg_3(demand_priority_r_reg_2),
        .demand_priority_r_reg_4(demand_priority_r_reg_3),
        .demand_priority_r_reg_5(req_wr_r_lcl_reg),
        .head_r(head_r),
        .head_r_lcl_i_3_0(head_r_lcl_i_3),
        .head_r_lcl_i_3_1(head_r_lcl_i_3_0),
        .head_r_lcl_i_3_2(head_r_lcl_i_3_1),
        .head_r_lcl_reg_0(head_r_lcl_reg),
        .head_r_lcl_reg_1(head_r_lcl_reg_0),
        .head_r_lcl_reg_2(head_r_lcl_reg_1),
        .idle_r_lcl_reg_0(idle_r),
        .idle_r_lcl_reg_1(idle_r_lcl_reg),
        .idle_r_lcl_reg_2(bank_queue0_n_14),
        .idle_r_lcl_reg_3(idle_r_lcl_reg_0),
        .\maint_controller.maint_hit_busies_r_reg[3] (\maint_controller.maint_hit_busies_r_reg[3] ),
        .\maint_controller.maint_hit_busies_r_reg[3]_0 (\maint_controller.maint_hit_busies_r_reg[3]_0 ),
        .\order_q_r_reg[0]_0 (\order_q_r_reg[0] ),
        .\order_q_r_reg[1]_0 (\order_q_r_reg[1] ),
        .\order_q_r_reg[1]_1 (\order_q_r_reg[1]_0 ),
        .\order_q_r_reg[1]_2 (\rtp_timer_r_reg[1] ),
        .\order_q_r_reg[1]_3 (\order_q_r_reg[1]_1 ),
        .\order_q_r_reg[1]_4 (\order_q_r_reg[1]_2 ),
        .\order_q_r_reg[1]_5 (\order_q_r_reg[1]_3 ),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(bank_compare0_n_6),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_0),
        .pass_open_bank_r_lcl_reg_2(bank_compare0_n_7),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),
        .pre_wait_r(pre_wait_r),
        .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0] ),
        .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0]_0 ),
        .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ),
        .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_0 ),
        .\q_entry_r_reg[1]_2 (\q_entry_r_reg[1]_1 ),
        .q_has_priority_r_reg_0(q_has_priority_r_reg),
        .q_has_priority_r_reg_1(rb_hit_busy_r_reg),
        .q_has_rd(q_has_rd),
        .q_has_rd_r_reg_0(q_has_rd_r_reg),
        .\ras_timer_r_reg[0] (\ras_timer_r_reg[1] ),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_0 ),
        .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[0]_2 (\ras_timer_r_reg[0]_1 ),
        .\ras_timer_r_reg[0]_3 (\ras_timer_r_reg[0]_2 ),
        .\ras_timer_r_reg[0]_4 (\ras_timer_r_reg[0]_3 ),
        .\ras_timer_r_reg[0]_5 (\ras_timer_r_reg[0]_4 ),
        .\ras_timer_r_reg[1] (bm_end_r1_reg),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1]_0 ),
        .\ras_timer_r_reg[1]_1 (\ras_timer_r_reg[1]_1 ),
        .\ras_timer_r_reg[1]_2 (\ras_timer_r_reg[1]_2 ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (rb_hit_busies_r[0]),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (rb_hit_busies_r[1]),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 (ras_timer_passed_ns),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 (bank_queue0_n_17),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 (rb_hit_busies_r[2]),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_4 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ),
        .rb_hit_busy_r(rb_hit_busy_r),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_bank_rdy_r_reg(req_bank_rdy_r_reg),
        .req_priority_r(req_priority_r),
        .req_wr_r(req_wr_r),
        .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ),
        .\rnk_config_strobe_r_reg[0]_0 (\rnk_config_strobe_r_reg[0]_0 ),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0),
        .wait_for_maint_r_lcl_reg_2(wait_for_maint_r_lcl_reg_1),
        .was_priority(was_priority),
        .was_wr(was_wr));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_state__parameterized2 bank_state0
       (.CLK(CLK),
        .D(ras_timer_passed_ns),
        .Q(Q),
        .SR(SR),
        .act_this_rank_r(act_this_rank_r),
        .act_wait_ns(act_wait_ns),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg),
        .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_0),
        .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg),
        .bm_end_r1_2(bm_end_r1_2),
        .bm_end_r1_reg_0(bm_end_r1_reg),
        .bm_end_r1_reg_1(pre_bm_end_r_reg),
        .col_wait_r(col_wait_r),
        .col_wait_r_reg_0(bank_state0_n_8),
        .col_wait_r_reg_1(col_wait_r_reg),
        .col_wait_r_reg_2(col_wait_r_reg_0),
        .col_wait_r_reg_3(bank_queue0_n_17),
        .demand_act_priority_r(demand_act_priority_r),
        .demand_act_priority_r_reg_0(wait_for_maint_r_lcl_reg),
        .demand_priority_ns(demand_priority_ns),
        .demand_priority_r_0(demand_priority_r_0),
        .demand_priority_r_reg_0(demand_priority_r),
        .demand_priority_r_reg_1(demand_priority_r_reg),
        .demand_priority_r_reg_2(bank_state0_n_22),
        .demanded_prior_r_1(demanded_prior_r_1),
        .demanded_prior_r_reg_0(demanded_prior_r),
        .demanded_prior_r_reg_1(demanded_prior_r_reg),
        .demanded_prior_r_reg_2(demanded_prior_r_reg_0),
        .\grant_r[3]_i_6 (act_wait_r_lcl_reg_2),
        .\grant_r[3]_i_6_0 (\ras_timer_r_reg[0] ),
        .\grant_r[3]_i_6_1 (\grant_r[3]_i_6 ),
        .\grant_r[3]_i_6_2 (bank_queue0_n_14),
        .head_r(head_r),
        .idle_r(idle_r),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r0(ofs_rdy_r0),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg(pre_bm_end_r_reg_0),
        .pre_bm_end_r_reg_0(auto_pre_r),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_wait_r(pre_wait_r),
        .pre_wait_r_reg_0(pre_wait_r_reg),
        .q_has_rd(q_has_rd),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),
        .rd_this_rank_r(rd_this_rank_r),
        .\rd_this_rank_r_reg[0]_0 (rd_wr_r_lcl_reg),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_wr_r(req_wr_r),
        .\rtp_timer_r_reg[0]_0 (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1]_0 (\rtp_timer_r_reg[1] ),
        .start_wtp_timer0(start_wtp_timer0),
        .\starve_limit_cntr_r_reg[0]_0 (\starve_limit_cntr_r_reg[0] ),
        .wr_this_rank_r(wr_this_rank_r));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_common
   (accept_internal_r,
    periodic_rd_ack_r_lcl_reg_0,
    accept_r_reg_0,
    accept_ns,
    was_wr,
    \generate_maint_cmds.insert_maint_r_lcl_reg_0 ,
    \maint_controller.maint_wip_r_lcl_reg_0 ,
    \maintenance_request.maint_req_r_lcl_reg ,
    periodic_rd_cntr_r_reg_0,
    was_priority,
    hi_priority,
    app_rdy_r_reg,
    app_rdy_r_reg_0,
    \maint_controller.maint_wip_r_lcl_reg_1 ,
    Q,
    clear_periodic_rd_request,
    accept_internal_r_reg_0,
    periodic_rd_insert,
    idle_r_lcl_reg,
    periodic_rd_ack_r_lcl_reg_1,
    rb_hit_busy_r_reg,
    rb_hit_busy_r_reg_0,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ,
    \maint_controller.maint_hit_busies_r_reg[3]_0 ,
    p_9_in,
    CLK,
    was_wr0,
    maint_srx_r,
    \maint_controller.maint_rdy ,
    SR,
    periodic_rd_cntr_r_reg_1,
    was_priority_reg_0,
    app_en_r2,
    rb_hit_busy_r,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]_0 ,
    maint_req_r,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ,
    \periodic_read_request.periodic_rd_grant_r ,
    idle_r,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 ,
    maint_zq_r,
    D,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1 );
  output accept_internal_r;
  output periodic_rd_ack_r_lcl_reg_0;
  output accept_r_reg_0;
  output accept_ns;
  output was_wr;
  output \generate_maint_cmds.insert_maint_r_lcl_reg_0 ;
  output \maint_controller.maint_wip_r_lcl_reg_0 ;
  output \maintenance_request.maint_req_r_lcl_reg ;
  output periodic_rd_cntr_r_reg_0;
  output was_priority;
  output hi_priority;
  output app_rdy_r_reg;
  output app_rdy_r_reg_0;
  output \maint_controller.maint_wip_r_lcl_reg_1 ;
  output [0:0]Q;
  output clear_periodic_rd_request;
  output accept_internal_r_reg_0;
  output periodic_rd_insert;
  output idle_r_lcl_reg;
  output periodic_rd_ack_r_lcl_reg_1;
  output rb_hit_busy_r_reg;
  output rb_hit_busy_r_reg_0;
  output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ;
  output [3:0]\maint_controller.maint_hit_busies_r_reg[3]_0 ;
  input p_9_in;
  input CLK;
  input was_wr0;
  input maint_srx_r;
  input \maint_controller.maint_rdy ;
  input [0:0]SR;
  input periodic_rd_cntr_r_reg_1;
  input was_priority_reg_0;
  input app_en_r2;
  input [3:0]rb_hit_busy_r;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]_0 ;
  input maint_req_r;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ;
  input \periodic_read_request.periodic_rd_grant_r ;
  input [3:0]idle_r;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 ;
  input maint_zq_r;
  input [3:0]D;
  input [1:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1 ;

  wire CLK;
  wire [3:0]D;
  wire [0:0]Q;
  wire [0:0]SR;
  wire accept_internal_r;
  wire accept_internal_r_reg_0;
  wire accept_ns;
  wire accept_r_reg_0;
  wire app_en_r2;
  wire app_rdy_r_reg;
  wire app_rdy_r_reg_0;
  wire clear_periodic_rd_request;
  wire \generate_maint_cmds.insert_maint_ns ;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg_0 ;
  wire hi_priority;
  wire [3:0]idle_r;
  wire idle_r_lcl_reg;
  wire [3:0]\maint_controller.maint_hit_busies_r_reg[3]_0 ;
  wire \maint_controller.maint_rdy ;
  wire \maint_controller.maint_rdy_r1 ;
  wire \maint_controller.maint_srx_r1 ;
  wire \maint_controller.maint_wip_r_lcl_i_1_n_0 ;
  wire \maint_controller.maint_wip_r_lcl_reg_0 ;
  wire \maint_controller.maint_wip_r_lcl_reg_1 ;
  wire maint_req_r;
  wire maint_srx_r;
  wire maint_zq_r;
  wire \maintenance_request.maint_req_r_lcl_reg ;
  wire p_9_in;
  wire periodic_rd_ack_ns;
  wire periodic_rd_ack_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg_1;
  wire periodic_rd_cntr_r_i_1_n_0;
  wire periodic_rd_cntr_r_reg_0;
  wire periodic_rd_cntr_r_reg_1;
  wire periodic_rd_insert;
  wire \periodic_read_request.periodic_rd_grant_r ;
  wire [3:0]rb_hit_busy_r;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire [6:1]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns ;
  wire [7:1]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1_n_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ;
  wire [1:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1 ;
  wire was_priority;
  wire was_priority_reg_0;
  wire was_wr;
  wire was_wr0;

  FDRE accept_internal_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_9_in),
        .Q(accept_internal_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair607" *) 
  LUT4 #(
    .INIT(16'h80AA)) 
    accept_r_i_1
       (.I0(p_9_in),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(periodic_rd_cntr_r_reg_0),
        .I3(periodic_rd_cntr_r_reg_1),
        .O(accept_ns));
  FDRE accept_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(accept_ns),
        .Q(accept_r_reg_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4F44)) 
    \generate_maint_cmds.insert_maint_r_lcl_i_1 
       (.I0(\maint_controller.maint_srx_r1 ),
        .I1(maint_srx_r),
        .I2(\maint_controller.maint_rdy_r1 ),
        .I3(\maint_controller.maint_rdy ),
        .O(\generate_maint_cmds.insert_maint_ns ));
  FDRE \generate_maint_cmds.insert_maint_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\generate_maint_cmds.insert_maint_ns ),
        .Q(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair606" *) 
  LUT4 #(
    .INIT(16'h557F)) 
    idle_r_lcl_i_3
       (.I0(accept_internal_r),
        .I1(app_en_r2),
        .I2(was_priority_reg_0),
        .I3(periodic_rd_ack_r_lcl_reg_0),
        .O(accept_internal_r_reg_0));
  FDRE \maint_controller.maint_hit_busies_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\maint_controller.maint_hit_busies_r_reg[3]_0 [0]),
        .R(1'b0));
  FDRE \maint_controller.maint_hit_busies_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\maint_controller.maint_hit_busies_r_reg[3]_0 [1]),
        .R(1'b0));
  FDRE \maint_controller.maint_hit_busies_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(\maint_controller.maint_hit_busies_r_reg[3]_0 [2]),
        .R(1'b0));
  FDRE \maint_controller.maint_hit_busies_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(\maint_controller.maint_hit_busies_r_reg[3]_0 [3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair609" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \maint_controller.maint_rdy_r1_i_2 
       (.I0(\maint_controller.maint_wip_r_lcl_reg_0 ),
        .I1(periodic_rd_cntr_r_reg_0),
        .I2(maint_req_r),
        .O(\maint_controller.maint_wip_r_lcl_reg_1 ));
  FDRE \maint_controller.maint_rdy_r1_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\maint_controller.maint_rdy ),
        .Q(\maint_controller.maint_rdy_r1 ),
        .R(1'b0));
  FDRE \maint_controller.maint_srx_r1_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(maint_srx_r),
        .Q(\maint_controller.maint_srx_r1 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair608" *) 
  LUT4 #(
    .INIT(16'hF7FF)) 
    \maint_controller.maint_wip_r_lcl_i_1 
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [1]),
        .I1(Q),
        .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [2]),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ),
        .O(\maint_controller.maint_wip_r_lcl_i_1_n_0 ));
  FDRE \maint_controller.maint_wip_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\maint_controller.maint_wip_r_lcl_i_1_n_0 ),
        .Q(\maint_controller.maint_wip_r_lcl_reg_0 ),
        .R(\maintenance_request.maint_req_r_lcl_reg ));
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    pass_open_bank_r_lcl_i_2
       (.I0(rb_hit_busy_r[2]),
        .I1(was_priority_reg_0),
        .I2(app_en_r2),
        .I3(accept_r_reg_0),
        .I4(periodic_rd_ack_r_lcl_reg_0),
        .O(rb_hit_busy_r_reg));
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    pass_open_bank_r_lcl_i_2__0
       (.I0(rb_hit_busy_r[1]),
        .I1(was_priority_reg_0),
        .I2(app_en_r2),
        .I3(accept_r_reg_0),
        .I4(periodic_rd_ack_r_lcl_reg_0),
        .O(rb_hit_busy_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair605" *) 
  LUT5 #(
    .INIT(32'hFF800000)) 
    pass_open_bank_r_lcl_i_2__1
       (.I0(was_priority_reg_0),
        .I1(app_en_r2),
        .I2(accept_r_reg_0),
        .I3(periodic_rd_ack_r_lcl_reg_0),
        .I4(rb_hit_busy_r[3]),
        .O(app_rdy_r_reg));
  LUT5 #(
    .INIT(32'hFF800000)) 
    pass_open_bank_r_lcl_i_2__2
       (.I0(was_priority_reg_0),
        .I1(app_en_r2),
        .I2(accept_r_reg_0),
        .I3(periodic_rd_ack_r_lcl_reg_0),
        .I4(rb_hit_busy_r[0]),
        .O(app_rdy_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair607" *) 
  LUT4 #(
    .INIT(16'h7000)) 
    periodic_rd_ack_r_lcl_i_1
       (.I0(periodic_rd_ack_r_lcl_reg_0),
        .I1(periodic_rd_cntr_r_reg_0),
        .I2(periodic_rd_cntr_r_reg_1),
        .I3(p_9_in),
        .O(periodic_rd_ack_ns));
  FDRE periodic_rd_ack_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(periodic_rd_ack_ns),
        .Q(periodic_rd_ack_r_lcl_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair609" *) 
  LUT3 #(
    .INIT(8'h78)) 
    periodic_rd_cntr_r_i_1
       (.I0(periodic_rd_cntr_r_reg_1),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(periodic_rd_cntr_r_reg_0),
        .O(periodic_rd_cntr_r_i_1_n_0));
  FDRE periodic_rd_cntr_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(periodic_rd_cntr_r_i_1_n_0),
        .Q(periodic_rd_cntr_r_reg_0),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair610" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \periodic_rd_generation.periodic_rd_request_r_i_3 
       (.I0(periodic_rd_ack_r_lcl_reg_0),
        .I1(\periodic_read_request.periodic_rd_grant_r ),
        .O(clear_periodic_rd_request));
  LUT5 #(
    .INIT(32'h96696996)) 
    \q_entry_r[0]_i_4 
       (.I0(periodic_rd_ack_r_lcl_reg_1),
        .I1(idle_r[2]),
        .I2(idle_r[1]),
        .I3(idle_r[3]),
        .I4(idle_r[0]),
        .O(idle_r_lcl_reg));
  (* SOFT_HLUTNM = "soft_lutpair605" *) 
  LUT4 #(
    .INIT(16'hEAAA)) 
    \q_entry_r[1]_i_3__1 
       (.I0(periodic_rd_ack_r_lcl_reg_0),
        .I1(accept_r_reg_0),
        .I2(app_en_r2),
        .I3(was_priority_reg_0),
        .O(periodic_rd_ack_r_lcl_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair610" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    req_periodic_rd_r_lcl_i_1
       (.I0(periodic_rd_cntr_r_reg_1),
        .I1(periodic_rd_cntr_r_reg_0),
        .I2(periodic_rd_ack_r_lcl_reg_0),
        .O(periodic_rd_insert));
  (* SOFT_HLUTNM = "soft_lutpair606" *) 
  LUT2 #(
    .INIT(4'h2)) 
    req_priority_r_i_1
       (.I0(was_priority),
        .I1(was_priority_reg_0),
        .O(hi_priority));
  LUT4 #(
    .INIT(16'h1001)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1 
       (.I0(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ),
        .I2(Q),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [1]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [1]));
  LUT6 #(
    .INIT(64'hABAAABAAABAAAAAB)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1 
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]_0 ),
        .I2(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [2]),
        .I4(Q),
        .I5(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [1]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [2]));
  LUT6 #(
    .INIT(64'hEAEAEAEAEAEAEAAE)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1 
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 ),
        .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [3]),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [2]),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [1]),
        .I5(Q),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [3]));
  LUT5 #(
    .INIT(32'h20232320)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_1 
       (.I0(maint_zq_r),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ),
        .I2(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [4]),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0 ),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [4]));
  LUT5 #(
    .INIT(32'h000000D2)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1 
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0 ),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [4]),
        .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [5]),
        .I3(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1111110100000010)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1 
       (.I0(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ),
        .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0 ),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [4]),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [5]),
        .I5(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [6]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [6]));
  (* SOFT_HLUTNM = "soft_lutpair608" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2 
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [2]),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [1]),
        .I2(Q),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [3]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFD)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1 
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 ),
        .I2(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .I3(Q),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [1]),
        .I5(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [2]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3 
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [5]),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [4]),
        .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [6]),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [3]),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [7]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h55555559)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_4 
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [7]),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_2_n_0 ),
        .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [6]),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [4]),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [5]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] 
       (.C(CLK),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1 [0]),
        .Q(Q),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] 
       (.C(CLK),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [1]),
        .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [1]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] 
       (.C(CLK),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [2]),
        .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [2]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] 
       (.C(CLK),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [3]),
        .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [3]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] 
       (.C(CLK),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [4]),
        .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [4]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] 
       (.C(CLK),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1_n_0 ),
        .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [5]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] 
       (.C(CLK),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [6]),
        .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [6]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] 
       (.C(CLK),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1 [1]),
        .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [7]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hAAFB)) 
    wait_for_maint_r_lcl_i_1__2
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]_0 ),
        .I1(maint_req_r),
        .I2(periodic_rd_cntr_r_reg_0),
        .I3(\maint_controller.maint_wip_r_lcl_reg_0 ),
        .O(\maintenance_request.maint_req_r_lcl_reg ));
  FDRE was_priority_reg
       (.C(CLK),
        .CE(1'b1),
        .D(hi_priority),
        .Q(was_priority),
        .R(1'b0));
  FDRE was_wr_reg
       (.C(CLK),
        .CE(1'b1),
        .D(was_wr0),
        .Q(was_wr),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_compare
   (req_periodic_rd_r,
    rd_wr_r_lcl_reg_0,
    req_wr_r,
    rb_hit_busy_r_reg_0,
    req_priority_r,
    req_wr_r_lcl_reg_0,
    \grant_r_reg[3] ,
    row_hit_r_reg_0,
    start_wtp_timer0,
    \req_row_r_lcl_reg[13]_0 ,
    \req_data_buf_addr_r_reg[3]_0 ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_col_r_reg[9]_0 ,
    E,
    periodic_rd_insert,
    CLK,
    req_wr_r_lcl0,
    rb_hit_busy_r_reg_1,
    hi_priority,
    row_hit_r_reg_1,
    Q,
    rd_wr_r_lcl_reg_1,
    rd_wr_r_lcl_reg_2,
    ordered_r_lcl_reg,
    ordered_r_lcl_reg_0,
    ordered_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg,
    maint_req_r,
    pass_open_bank_r_lcl_reg_0,
    pass_open_bank_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_2,
    row,
    \req_data_buf_addr_r_reg[0]_0 ,
    \req_data_buf_addr_r_reg[3]_1 ,
    bank,
    \req_col_r_reg[9]_1 );
  output [0:0]req_periodic_rd_r;
  output rd_wr_r_lcl_reg_0;
  output [0:0]req_wr_r;
  output rb_hit_busy_r_reg_0;
  output req_priority_r;
  output req_wr_r_lcl_reg_0;
  output \grant_r_reg[3] ;
  output row_hit_r_reg_0;
  output start_wtp_timer0;
  output [13:0]\req_row_r_lcl_reg[13]_0 ;
  output [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  output [2:0]\req_bank_r_lcl_reg[2]_0 ;
  output [9:0]\req_col_r_reg[9]_0 ;
  input [0:0]E;
  input periodic_rd_insert;
  input CLK;
  input req_wr_r_lcl0;
  input rb_hit_busy_r_reg_1;
  input hi_priority;
  input [0:0]row_hit_r_reg_1;
  input [0:0]Q;
  input rd_wr_r_lcl_reg_1;
  input rd_wr_r_lcl_reg_2;
  input ordered_r_lcl_reg;
  input ordered_r_lcl_reg_0;
  input ordered_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg_0;
  input pass_open_bank_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_2;
  input [13:0]row;
  input [0:0]\req_data_buf_addr_r_reg[0]_0 ;
  input [3:0]\req_data_buf_addr_r_reg[3]_1 ;
  input [2:0]bank;
  input [9:0]\req_col_r_reg[9]_1 ;

  wire CLK;
  wire [0:0]E;
  wire [0:0]Q;
  wire [2:0]bank;
  wire \grant_r_reg[3] ;
  wire hi_priority;
  wire maint_req_r;
  wire ordered_r_lcl_reg;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire periodic_rd_insert;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rd_wr_ns;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire rd_wr_r_lcl_reg_2;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [9:0]\req_col_r_reg[9]_1 ;
  wire [0:0]\req_data_buf_addr_r_reg[0]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_1 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13]_0 ;
  wire [0:0]req_wr_r;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg_0;
  wire [13:0]row;
  wire row_hit_ns_carry__0_n_3;
  wire row_hit_ns_carry_i_1__2_n_0;
  wire row_hit_ns_carry_i_2__2_n_0;
  wire row_hit_ns_carry_i_3__2_n_0;
  wire row_hit_ns_carry_i_4__2_n_0;
  wire row_hit_ns_carry_n_0;
  wire row_hit_ns_carry_n_1;
  wire row_hit_ns_carry_n_2;
  wire row_hit_ns_carry_n_3;
  wire row_hit_r;
  wire row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire start_wtp_timer0;
  wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;
  wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;
  wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;

  LUT6 #(
    .INIT(64'h00000000D5D5D500)) 
    ordered_r_lcl_i_1__2
       (.I0(Q),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(req_wr_r),
        .I3(ordered_r_lcl_reg),
        .I4(ordered_r_lcl_reg_0),
        .I5(ordered_r_lcl_reg_1),
        .O(\grant_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAAAAAAAA8888AA8A)) 
    pass_open_bank_r_lcl_i_3
       (.I0(row_hit_r),
        .I1(pass_open_bank_r_lcl_reg),
        .I2(maint_req_r),
        .I3(pass_open_bank_r_lcl_reg_0),
        .I4(pass_open_bank_r_lcl_reg_1),
        .I5(pass_open_bank_r_lcl_reg_2),
        .O(row_hit_r_reg_0));
  FDRE rb_hit_busy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rb_hit_busy_r_reg_1),
        .Q(rb_hit_busy_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair601" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    rd_wr_r_lcl_i_1__2
       (.I0(rd_wr_r_lcl_reg_0),
        .I1(Q),
        .I2(rd_wr_r_lcl_reg_1),
        .I3(rd_wr_r_lcl_reg_2),
        .O(rd_wr_ns));
  FDRE rd_wr_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rd_wr_ns),
        .Q(rd_wr_r_lcl_reg_0),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(bank[0]),
        .Q(\req_bank_r_lcl_reg[2]_0 [0]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(bank[1]),
        .Q(\req_bank_r_lcl_reg[2]_0 [1]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(bank[2]),
        .Q(\req_bank_r_lcl_reg[2]_0 [2]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair601" *) 
  LUT3 #(
    .INIT(8'h8F)) 
    req_bank_rdy_r_i_5
       (.I0(req_wr_r),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(Q),
        .O(req_wr_r_lcl_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [0]),
        .Q(\req_col_r_reg[9]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [1]),
        .Q(\req_col_r_reg[9]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [2]),
        .Q(\req_col_r_reg[9]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [3]),
        .Q(\req_col_r_reg[9]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [4]),
        .Q(\req_col_r_reg[9]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [5]),
        .Q(\req_col_r_reg[9]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [6]),
        .Q(\req_col_r_reg[9]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [7]),
        .Q(\req_col_r_reg[9]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [8]),
        .Q(\req_col_r_reg[9]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [9]),
        .Q(\req_col_r_reg[9]_0 [9]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[0] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [0]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [0]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[1] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [1]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [1]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[2] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [2]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [2]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[3] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [3]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [3]),
        .R(1'b0));
  FDRE req_periodic_rd_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(periodic_rd_insert),
        .Q(req_periodic_rd_r),
        .R(1'b0));
  FDRE req_priority_r_reg
       (.C(CLK),
        .CE(E),
        .D(hi_priority),
        .Q(req_priority_r),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(row[0]),
        .Q(\req_row_r_lcl_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[10] 
       (.C(CLK),
        .CE(E),
        .D(row[10]),
        .Q(\req_row_r_lcl_reg[13]_0 [10]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[11] 
       (.C(CLK),
        .CE(E),
        .D(row[11]),
        .Q(\req_row_r_lcl_reg[13]_0 [11]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[12] 
       (.C(CLK),
        .CE(E),
        .D(row[12]),
        .Q(\req_row_r_lcl_reg[13]_0 [12]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[13] 
       (.C(CLK),
        .CE(E),
        .D(row[13]),
        .Q(\req_row_r_lcl_reg[13]_0 [13]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(row[1]),
        .Q(\req_row_r_lcl_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(row[2]),
        .Q(\req_row_r_lcl_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(row[3]),
        .Q(\req_row_r_lcl_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(row[4]),
        .Q(\req_row_r_lcl_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(row[5]),
        .Q(\req_row_r_lcl_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(row[6]),
        .Q(\req_row_r_lcl_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(row[7]),
        .Q(\req_row_r_lcl_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(row[8]),
        .Q(\req_row_r_lcl_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(row[9]),
        .Q(\req_row_r_lcl_reg[13]_0 [9]),
        .R(1'b0));
  FDRE req_wr_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(req_wr_r_lcl0),
        .Q(req_wr_r),
        .R(1'b0));
  CARRY4 row_hit_ns_carry
       (.CI(1'b0),
        .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),
        .S({row_hit_ns_carry_i_1__2_n_0,row_hit_ns_carry_i_2__2_n_0,row_hit_ns_carry_i_3__2_n_0,row_hit_ns_carry_i_4__2_n_0}));
  CARRY4 row_hit_ns_carry__0
       (.CI(row_hit_ns_carry_n_0),
        .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,row_hit_r_reg_1}));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_1__2
       (.I0(\req_row_r_lcl_reg[13]_0 [11]),
        .I1(row[11]),
        .I2(row[9]),
        .I3(\req_row_r_lcl_reg[13]_0 [9]),
        .I4(row[10]),
        .I5(\req_row_r_lcl_reg[13]_0 [10]),
        .O(row_hit_ns_carry_i_1__2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_2__2
       (.I0(\req_row_r_lcl_reg[13]_0 [8]),
        .I1(row[8]),
        .I2(row[7]),
        .I3(\req_row_r_lcl_reg[13]_0 [7]),
        .I4(row[6]),
        .I5(\req_row_r_lcl_reg[13]_0 [6]),
        .O(row_hit_ns_carry_i_2__2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_3__2
       (.I0(\req_row_r_lcl_reg[13]_0 [5]),
        .I1(row[5]),
        .I2(row[4]),
        .I3(\req_row_r_lcl_reg[13]_0 [4]),
        .I4(row[3]),
        .I5(\req_row_r_lcl_reg[13]_0 [3]),
        .O(row_hit_ns_carry_i_3__2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_4__2
       (.I0(\req_row_r_lcl_reg[13]_0 [2]),
        .I1(row[2]),
        .I2(row[0]),
        .I3(\req_row_r_lcl_reg[13]_0 [0]),
        .I4(row[1]),
        .I5(\req_row_r_lcl_reg[13]_0 [1]),
        .O(row_hit_ns_carry_i_4__2_n_0));
  FDRE row_hit_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(row_hit_ns_carry__0_n_3),
        .Q(row_hit_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_this_rank_r[0]_i_1__2 
       (.I0(rd_wr_r_lcl_reg_0),
        .O(start_wtp_timer0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_compare" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_compare_0
   (req_periodic_rd_r,
    rd_wr_r_lcl_reg_0,
    req_wr_r,
    rb_hit_busy_r_reg_0,
    req_priority_r,
    rb_hit_busy_r_reg_1,
    req_wr_r_lcl_reg_0,
    \grant_r_reg[2] ,
    row_hit_r_reg_0,
    start_wtp_timer0,
    \req_row_r_lcl_reg[13]_0 ,
    \req_data_buf_addr_r_reg[3]_0 ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_col_r_reg[9]_0 ,
    E,
    periodic_rd_insert,
    CLK,
    req_wr_r_lcl0,
    rb_hit_busy_r_reg_2,
    hi_priority,
    row_hit_r_reg_1,
    \q_entry_r_reg[0] ,
    \q_entry_r_reg[0]_0 ,
    Q,
    rd_wr_r_lcl_reg_1,
    rd_wr_r_lcl_reg_2,
    ordered_r_lcl_reg,
    ordered_r_lcl_reg_0,
    ordered_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg,
    maint_req_r,
    pass_open_bank_r_lcl_reg_0,
    pass_open_bank_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_2,
    row,
    \req_data_buf_addr_r_reg[0]_0 ,
    \req_data_buf_addr_r_reg[3]_1 ,
    bank,
    \req_col_r_reg[9]_1 );
  output [0:0]req_periodic_rd_r;
  output rd_wr_r_lcl_reg_0;
  output [0:0]req_wr_r;
  output rb_hit_busy_r_reg_0;
  output req_priority_r;
  output rb_hit_busy_r_reg_1;
  output req_wr_r_lcl_reg_0;
  output \grant_r_reg[2] ;
  output row_hit_r_reg_0;
  output start_wtp_timer0;
  output [13:0]\req_row_r_lcl_reg[13]_0 ;
  output [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  output [2:0]\req_bank_r_lcl_reg[2]_0 ;
  output [9:0]\req_col_r_reg[9]_0 ;
  input [0:0]E;
  input periodic_rd_insert;
  input CLK;
  input req_wr_r_lcl0;
  input rb_hit_busy_r_reg_2;
  input hi_priority;
  input [0:0]row_hit_r_reg_1;
  input [2:0]\q_entry_r_reg[0] ;
  input \q_entry_r_reg[0]_0 ;
  input [0:0]Q;
  input rd_wr_r_lcl_reg_1;
  input rd_wr_r_lcl_reg_2;
  input ordered_r_lcl_reg;
  input ordered_r_lcl_reg_0;
  input ordered_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg_0;
  input pass_open_bank_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_2;
  input [13:0]row;
  input [0:0]\req_data_buf_addr_r_reg[0]_0 ;
  input [3:0]\req_data_buf_addr_r_reg[3]_1 ;
  input [2:0]bank;
  input [9:0]\req_col_r_reg[9]_1 ;

  wire CLK;
  wire [0:0]E;
  wire [0:0]Q;
  wire [2:0]bank;
  wire \grant_r_reg[2] ;
  wire hi_priority;
  wire maint_req_r;
  wire ordered_r_lcl_reg;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire periodic_rd_insert;
  wire [2:0]\q_entry_r_reg[0] ;
  wire \q_entry_r_reg[0]_0 ;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rb_hit_busy_r_reg_2;
  wire rd_wr_ns;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire rd_wr_r_lcl_reg_2;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [9:0]\req_col_r_reg[9]_1 ;
  wire [0:0]\req_data_buf_addr_r_reg[0]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_1 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13]_0 ;
  wire [0:0]req_wr_r;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg_0;
  wire [13:0]row;
  wire row_hit_ns_carry__0_n_3;
  wire row_hit_ns_carry_i_1__1_n_0;
  wire row_hit_ns_carry_i_2__1_n_0;
  wire row_hit_ns_carry_i_3__1_n_0;
  wire row_hit_ns_carry_i_4__1_n_0;
  wire row_hit_ns_carry_n_0;
  wire row_hit_ns_carry_n_1;
  wire row_hit_ns_carry_n_2;
  wire row_hit_ns_carry_n_3;
  wire row_hit_r;
  wire row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire start_wtp_timer0;
  wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;
  wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;
  wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;

  LUT6 #(
    .INIT(64'h00000000D5D5D500)) 
    ordered_r_lcl_i_1__1
       (.I0(Q),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(req_wr_r),
        .I3(ordered_r_lcl_reg),
        .I4(ordered_r_lcl_reg_0),
        .I5(ordered_r_lcl_reg_1),
        .O(\grant_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAAAAAAAA8888AA8A)) 
    pass_open_bank_r_lcl_i_3__0
       (.I0(row_hit_r),
        .I1(pass_open_bank_r_lcl_reg),
        .I2(maint_req_r),
        .I3(pass_open_bank_r_lcl_reg_0),
        .I4(pass_open_bank_r_lcl_reg_1),
        .I5(pass_open_bank_r_lcl_reg_2),
        .O(row_hit_r_reg_0));
  LUT5 #(
    .INIT(32'h69969669)) 
    \q_entry_r[0]_i_4__2 
       (.I0(\q_entry_r_reg[0] [2]),
        .I1(rb_hit_busy_r_reg_0),
        .I2(\q_entry_r_reg[0] [1]),
        .I3(\q_entry_r_reg[0] [0]),
        .I4(\q_entry_r_reg[0]_0 ),
        .O(rb_hit_busy_r_reg_1));
  FDRE rb_hit_busy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rb_hit_busy_r_reg_2),
        .Q(rb_hit_busy_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair595" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    rd_wr_r_lcl_i_1__1
       (.I0(rd_wr_r_lcl_reg_0),
        .I1(Q),
        .I2(rd_wr_r_lcl_reg_1),
        .I3(rd_wr_r_lcl_reg_2),
        .O(rd_wr_ns));
  FDRE rd_wr_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rd_wr_ns),
        .Q(rd_wr_r_lcl_reg_0),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(bank[0]),
        .Q(\req_bank_r_lcl_reg[2]_0 [0]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(bank[1]),
        .Q(\req_bank_r_lcl_reg[2]_0 [1]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(bank[2]),
        .Q(\req_bank_r_lcl_reg[2]_0 [2]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair595" *) 
  LUT3 #(
    .INIT(8'h8F)) 
    req_bank_rdy_r_i_4
       (.I0(req_wr_r),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(Q),
        .O(req_wr_r_lcl_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [0]),
        .Q(\req_col_r_reg[9]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [1]),
        .Q(\req_col_r_reg[9]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [2]),
        .Q(\req_col_r_reg[9]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [3]),
        .Q(\req_col_r_reg[9]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [4]),
        .Q(\req_col_r_reg[9]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [5]),
        .Q(\req_col_r_reg[9]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [6]),
        .Q(\req_col_r_reg[9]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [7]),
        .Q(\req_col_r_reg[9]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [8]),
        .Q(\req_col_r_reg[9]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [9]),
        .Q(\req_col_r_reg[9]_0 [9]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[0] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [0]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [0]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[1] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [1]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [1]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[2] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [2]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [2]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[3] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [3]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [3]),
        .R(1'b0));
  FDRE req_periodic_rd_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(periodic_rd_insert),
        .Q(req_periodic_rd_r),
        .R(1'b0));
  FDRE req_priority_r_reg
       (.C(CLK),
        .CE(E),
        .D(hi_priority),
        .Q(req_priority_r),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(row[0]),
        .Q(\req_row_r_lcl_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[10] 
       (.C(CLK),
        .CE(E),
        .D(row[10]),
        .Q(\req_row_r_lcl_reg[13]_0 [10]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[11] 
       (.C(CLK),
        .CE(E),
        .D(row[11]),
        .Q(\req_row_r_lcl_reg[13]_0 [11]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[12] 
       (.C(CLK),
        .CE(E),
        .D(row[12]),
        .Q(\req_row_r_lcl_reg[13]_0 [12]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[13] 
       (.C(CLK),
        .CE(E),
        .D(row[13]),
        .Q(\req_row_r_lcl_reg[13]_0 [13]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(row[1]),
        .Q(\req_row_r_lcl_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(row[2]),
        .Q(\req_row_r_lcl_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(row[3]),
        .Q(\req_row_r_lcl_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(row[4]),
        .Q(\req_row_r_lcl_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(row[5]),
        .Q(\req_row_r_lcl_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(row[6]),
        .Q(\req_row_r_lcl_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(row[7]),
        .Q(\req_row_r_lcl_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(row[8]),
        .Q(\req_row_r_lcl_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(row[9]),
        .Q(\req_row_r_lcl_reg[13]_0 [9]),
        .R(1'b0));
  FDRE req_wr_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(req_wr_r_lcl0),
        .Q(req_wr_r),
        .R(1'b0));
  CARRY4 row_hit_ns_carry
       (.CI(1'b0),
        .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),
        .S({row_hit_ns_carry_i_1__1_n_0,row_hit_ns_carry_i_2__1_n_0,row_hit_ns_carry_i_3__1_n_0,row_hit_ns_carry_i_4__1_n_0}));
  CARRY4 row_hit_ns_carry__0
       (.CI(row_hit_ns_carry_n_0),
        .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,row_hit_r_reg_1}));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_1__1
       (.I0(\req_row_r_lcl_reg[13]_0 [11]),
        .I1(row[11]),
        .I2(row[10]),
        .I3(\req_row_r_lcl_reg[13]_0 [10]),
        .I4(row[9]),
        .I5(\req_row_r_lcl_reg[13]_0 [9]),
        .O(row_hit_ns_carry_i_1__1_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_2__1
       (.I0(\req_row_r_lcl_reg[13]_0 [8]),
        .I1(row[8]),
        .I2(row[7]),
        .I3(\req_row_r_lcl_reg[13]_0 [7]),
        .I4(row[6]),
        .I5(\req_row_r_lcl_reg[13]_0 [6]),
        .O(row_hit_ns_carry_i_2__1_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_3__1
       (.I0(\req_row_r_lcl_reg[13]_0 [5]),
        .I1(row[5]),
        .I2(row[3]),
        .I3(\req_row_r_lcl_reg[13]_0 [3]),
        .I4(row[4]),
        .I5(\req_row_r_lcl_reg[13]_0 [4]),
        .O(row_hit_ns_carry_i_3__1_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_4__1
       (.I0(\req_row_r_lcl_reg[13]_0 [2]),
        .I1(row[2]),
        .I2(row[0]),
        .I3(\req_row_r_lcl_reg[13]_0 [0]),
        .I4(row[1]),
        .I5(\req_row_r_lcl_reg[13]_0 [1]),
        .O(row_hit_ns_carry_i_4__1_n_0));
  FDRE row_hit_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(row_hit_ns_carry__0_n_3),
        .Q(row_hit_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_this_rank_r[0]_i_1__1 
       (.I0(rd_wr_r_lcl_reg_0),
        .O(start_wtp_timer0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_compare" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_compare_1
   (req_periodic_rd_r,
    rd_wr_r_lcl_reg_0,
    req_wr_r,
    rb_hit_busy_r_reg_0,
    req_priority_r,
    rb_hit_busy_r_reg_1,
    req_wr_r_lcl_reg_0,
    \grant_r_reg[1] ,
    row_hit_r_reg_0,
    start_wtp_timer0,
    \req_row_r_lcl_reg[13]_0 ,
    \req_data_buf_addr_r_reg[3]_0 ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_col_r_reg[9]_0 ,
    E,
    periodic_rd_insert,
    CLK,
    req_wr_r_lcl0,
    rb_hit_busy_r_reg_2,
    hi_priority,
    row_hit_r_reg_1,
    rb_hit_busy_r,
    \q_entry_r_reg[0] ,
    Q,
    rd_wr_r_lcl_reg_1,
    rd_wr_r_lcl_reg_2,
    ordered_r_lcl_reg,
    ordered_r_lcl,
    ordered_r_lcl_reg_0,
    pass_open_bank_r_lcl_reg,
    maint_req_r,
    pass_open_bank_r_lcl_reg_0,
    pass_open_bank_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_2,
    row,
    \req_data_buf_addr_r_reg[0]_0 ,
    \req_data_buf_addr_r_reg[3]_1 ,
    bank,
    \req_col_r_reg[9]_1 );
  output [0:0]req_periodic_rd_r;
  output rd_wr_r_lcl_reg_0;
  output [0:0]req_wr_r;
  output rb_hit_busy_r_reg_0;
  output req_priority_r;
  output rb_hit_busy_r_reg_1;
  output req_wr_r_lcl_reg_0;
  output \grant_r_reg[1] ;
  output row_hit_r_reg_0;
  output start_wtp_timer0;
  output [13:0]\req_row_r_lcl_reg[13]_0 ;
  output [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  output [2:0]\req_bank_r_lcl_reg[2]_0 ;
  output [9:0]\req_col_r_reg[9]_0 ;
  input [0:0]E;
  input periodic_rd_insert;
  input CLK;
  input req_wr_r_lcl0;
  input rb_hit_busy_r_reg_2;
  input hi_priority;
  input [0:0]row_hit_r_reg_1;
  input [2:0]rb_hit_busy_r;
  input \q_entry_r_reg[0] ;
  input [0:0]Q;
  input rd_wr_r_lcl_reg_1;
  input rd_wr_r_lcl_reg_2;
  input ordered_r_lcl_reg;
  input ordered_r_lcl;
  input ordered_r_lcl_reg_0;
  input pass_open_bank_r_lcl_reg;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg_0;
  input pass_open_bank_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_2;
  input [13:0]row;
  input [0:0]\req_data_buf_addr_r_reg[0]_0 ;
  input [3:0]\req_data_buf_addr_r_reg[3]_1 ;
  input [2:0]bank;
  input [9:0]\req_col_r_reg[9]_1 ;

  wire CLK;
  wire [0:0]E;
  wire [0:0]Q;
  wire [2:0]bank;
  wire \grant_r_reg[1] ;
  wire hi_priority;
  wire maint_req_r;
  wire ordered_r_lcl;
  wire ordered_r_lcl_reg;
  wire ordered_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire periodic_rd_insert;
  wire \q_entry_r_reg[0] ;
  wire [2:0]rb_hit_busy_r;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rb_hit_busy_r_reg_2;
  wire rd_wr_ns;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire rd_wr_r_lcl_reg_2;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [9:0]\req_col_r_reg[9]_1 ;
  wire [0:0]\req_data_buf_addr_r_reg[0]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_1 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13]_0 ;
  wire [0:0]req_wr_r;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg_0;
  wire [13:0]row;
  wire row_hit_ns_carry__0_n_3;
  wire row_hit_ns_carry_i_1__0_n_0;
  wire row_hit_ns_carry_i_2__0_n_0;
  wire row_hit_ns_carry_i_3__0_n_0;
  wire row_hit_ns_carry_i_4__0_n_0;
  wire row_hit_ns_carry_n_0;
  wire row_hit_ns_carry_n_1;
  wire row_hit_ns_carry_n_2;
  wire row_hit_ns_carry_n_3;
  wire row_hit_r;
  wire row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire start_wtp_timer0;
  wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;
  wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;
  wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;

  LUT6 #(
    .INIT(64'h00000000D5D5D500)) 
    ordered_r_lcl_i_1__0
       (.I0(Q),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(req_wr_r),
        .I3(ordered_r_lcl_reg),
        .I4(ordered_r_lcl),
        .I5(ordered_r_lcl_reg_0),
        .O(\grant_r_reg[1] ));
  LUT6 #(
    .INIT(64'hAAAAAAAA8888AA8A)) 
    pass_open_bank_r_lcl_i_3__1
       (.I0(row_hit_r),
        .I1(pass_open_bank_r_lcl_reg),
        .I2(maint_req_r),
        .I3(pass_open_bank_r_lcl_reg_0),
        .I4(pass_open_bank_r_lcl_reg_1),
        .I5(pass_open_bank_r_lcl_reg_2),
        .O(row_hit_r_reg_0));
  LUT5 #(
    .INIT(32'h69969669)) 
    \q_entry_r[0]_i_2__2 
       (.I0(rb_hit_busy_r[2]),
        .I1(rb_hit_busy_r[1]),
        .I2(rb_hit_busy_r_reg_0),
        .I3(rb_hit_busy_r[0]),
        .I4(\q_entry_r_reg[0] ),
        .O(rb_hit_busy_r_reg_1));
  FDRE rb_hit_busy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rb_hit_busy_r_reg_2),
        .Q(rb_hit_busy_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair589" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    rd_wr_r_lcl_i_1__0
       (.I0(rd_wr_r_lcl_reg_0),
        .I1(Q),
        .I2(rd_wr_r_lcl_reg_1),
        .I3(rd_wr_r_lcl_reg_2),
        .O(rd_wr_ns));
  FDRE rd_wr_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rd_wr_ns),
        .Q(rd_wr_r_lcl_reg_0),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(bank[0]),
        .Q(\req_bank_r_lcl_reg[2]_0 [0]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(bank[1]),
        .Q(\req_bank_r_lcl_reg[2]_0 [1]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(bank[2]),
        .Q(\req_bank_r_lcl_reg[2]_0 [2]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair589" *) 
  LUT3 #(
    .INIT(8'h8F)) 
    req_bank_rdy_r_i_3
       (.I0(req_wr_r),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(Q),
        .O(req_wr_r_lcl_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [0]),
        .Q(\req_col_r_reg[9]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [1]),
        .Q(\req_col_r_reg[9]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [2]),
        .Q(\req_col_r_reg[9]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [3]),
        .Q(\req_col_r_reg[9]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [4]),
        .Q(\req_col_r_reg[9]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [5]),
        .Q(\req_col_r_reg[9]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [6]),
        .Q(\req_col_r_reg[9]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [7]),
        .Q(\req_col_r_reg[9]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [8]),
        .Q(\req_col_r_reg[9]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [9]),
        .Q(\req_col_r_reg[9]_0 [9]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[0] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [0]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [0]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[1] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [1]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [1]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[2] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [2]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [2]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[3] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [3]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [3]),
        .R(1'b0));
  FDRE req_periodic_rd_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(periodic_rd_insert),
        .Q(req_periodic_rd_r),
        .R(1'b0));
  FDRE req_priority_r_reg
       (.C(CLK),
        .CE(E),
        .D(hi_priority),
        .Q(req_priority_r),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(row[0]),
        .Q(\req_row_r_lcl_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[10] 
       (.C(CLK),
        .CE(E),
        .D(row[10]),
        .Q(\req_row_r_lcl_reg[13]_0 [10]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[11] 
       (.C(CLK),
        .CE(E),
        .D(row[11]),
        .Q(\req_row_r_lcl_reg[13]_0 [11]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[12] 
       (.C(CLK),
        .CE(E),
        .D(row[12]),
        .Q(\req_row_r_lcl_reg[13]_0 [12]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[13] 
       (.C(CLK),
        .CE(E),
        .D(row[13]),
        .Q(\req_row_r_lcl_reg[13]_0 [13]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(row[1]),
        .Q(\req_row_r_lcl_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(row[2]),
        .Q(\req_row_r_lcl_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(row[3]),
        .Q(\req_row_r_lcl_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(row[4]),
        .Q(\req_row_r_lcl_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(row[5]),
        .Q(\req_row_r_lcl_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(row[6]),
        .Q(\req_row_r_lcl_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(row[7]),
        .Q(\req_row_r_lcl_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(row[8]),
        .Q(\req_row_r_lcl_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(row[9]),
        .Q(\req_row_r_lcl_reg[13]_0 [9]),
        .R(1'b0));
  FDRE req_wr_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(req_wr_r_lcl0),
        .Q(req_wr_r),
        .R(1'b0));
  CARRY4 row_hit_ns_carry
       (.CI(1'b0),
        .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),
        .S({row_hit_ns_carry_i_1__0_n_0,row_hit_ns_carry_i_2__0_n_0,row_hit_ns_carry_i_3__0_n_0,row_hit_ns_carry_i_4__0_n_0}));
  CARRY4 row_hit_ns_carry__0
       (.CI(row_hit_ns_carry_n_0),
        .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,row_hit_r_reg_1}));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_1__0
       (.I0(\req_row_r_lcl_reg[13]_0 [11]),
        .I1(row[11]),
        .I2(row[9]),
        .I3(\req_row_r_lcl_reg[13]_0 [9]),
        .I4(row[10]),
        .I5(\req_row_r_lcl_reg[13]_0 [10]),
        .O(row_hit_ns_carry_i_1__0_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_2__0
       (.I0(\req_row_r_lcl_reg[13]_0 [8]),
        .I1(row[8]),
        .I2(row[7]),
        .I3(\req_row_r_lcl_reg[13]_0 [7]),
        .I4(row[6]),
        .I5(\req_row_r_lcl_reg[13]_0 [6]),
        .O(row_hit_ns_carry_i_2__0_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_3__0
       (.I0(\req_row_r_lcl_reg[13]_0 [5]),
        .I1(row[5]),
        .I2(row[4]),
        .I3(\req_row_r_lcl_reg[13]_0 [4]),
        .I4(row[3]),
        .I5(\req_row_r_lcl_reg[13]_0 [3]),
        .O(row_hit_ns_carry_i_3__0_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_4__0
       (.I0(\req_row_r_lcl_reg[13]_0 [2]),
        .I1(row[2]),
        .I2(row[1]),
        .I3(\req_row_r_lcl_reg[13]_0 [1]),
        .I4(row[0]),
        .I5(\req_row_r_lcl_reg[13]_0 [0]),
        .O(row_hit_ns_carry_i_4__0_n_0));
  FDRE row_hit_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(row_hit_ns_carry__0_n_3),
        .Q(row_hit_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_this_rank_r[0]_i_1__0 
       (.I0(rd_wr_r_lcl_reg_0),
        .O(start_wtp_timer0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_compare" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_compare_2
   (req_periodic_rd_r,
    rd_wr_r_lcl_reg_0,
    req_wr_r,
    req_priority_r,
    rb_hit_busy_r_reg_0,
    req_wr_r_lcl_reg_0,
    ordered_r_lcl_reg,
    req_wr_r_lcl_reg_1,
    \grant_r_reg[0] ,
    start_wtp_timer0,
    row_hit_r_reg_0,
    \req_row_r_lcl_reg[13]_0 ,
    rb_hit_busy_r_reg_1,
    rb_hit_busy_r_reg_2,
    \req_data_buf_addr_r_reg[3]_0 ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_col_r_reg[9]_0 ,
    E,
    periodic_rd_insert,
    CLK,
    req_wr_r_lcl0,
    hi_priority,
    rb_hit_busy_r_reg_3,
    S,
    row_hit_r_reg_1,
    Q,
    rd_wr_r_lcl_reg_1,
    rd_wr_r_lcl_reg_2,
    ordered_r,
    ordered_r_lcl,
    \order_q_r_reg[1] ,
    \order_q_r_reg[1]_0 ,
    req_bank_rdy_r_reg,
    req_bank_rdy_r_reg_0,
    req_bank_rdy_r_reg_1,
    ordered_r_lcl_reg_0,
    ordered_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg,
    maint_req_r,
    pass_open_bank_r_lcl_reg_0,
    pass_open_bank_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_2,
    row,
    \q_entry_r[1]_i_4__2 ,
    \req_data_buf_addr_r_reg[0]_0 ,
    \req_data_buf_addr_r_reg[3]_1 ,
    bank,
    \req_col_r_reg[9]_1 );
  output [0:0]req_periodic_rd_r;
  output rd_wr_r_lcl_reg_0;
  output [0:0]req_wr_r;
  output req_priority_r;
  output rb_hit_busy_r_reg_0;
  output req_wr_r_lcl_reg_0;
  output ordered_r_lcl_reg;
  output req_wr_r_lcl_reg_1;
  output \grant_r_reg[0] ;
  output start_wtp_timer0;
  output row_hit_r_reg_0;
  output [13:0]\req_row_r_lcl_reg[13]_0 ;
  output rb_hit_busy_r_reg_1;
  output rb_hit_busy_r_reg_2;
  output [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  output [2:0]\req_bank_r_lcl_reg[2]_0 ;
  output [9:0]\req_col_r_reg[9]_0 ;
  input [0:0]E;
  input periodic_rd_insert;
  input CLK;
  input req_wr_r_lcl0;
  input hi_priority;
  input rb_hit_busy_r_reg_3;
  input [2:0]S;
  input [0:0]row_hit_r_reg_1;
  input [0:0]Q;
  input rd_wr_r_lcl_reg_1;
  input rd_wr_r_lcl_reg_2;
  input ordered_r;
  input ordered_r_lcl;
  input \order_q_r_reg[1] ;
  input \order_q_r_reg[1]_0 ;
  input req_bank_rdy_r_reg;
  input req_bank_rdy_r_reg_0;
  input req_bank_rdy_r_reg_1;
  input ordered_r_lcl_reg_0;
  input ordered_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg_0;
  input pass_open_bank_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_2;
  input [13:0]row;
  input [2:0]\q_entry_r[1]_i_4__2 ;
  input [0:0]\req_data_buf_addr_r_reg[0]_0 ;
  input [3:0]\req_data_buf_addr_r_reg[3]_1 ;
  input [2:0]bank;
  input [9:0]\req_col_r_reg[9]_1 ;

  wire CLK;
  wire [0:0]E;
  wire [0:0]Q;
  wire [2:0]S;
  wire [2:0]bank;
  wire \grant_r_reg[0] ;
  wire hi_priority;
  wire maint_req_r;
  wire \order_q_r_reg[1] ;
  wire \order_q_r_reg[1]_0 ;
  wire ordered_r;
  wire ordered_r_lcl;
  wire ordered_r_lcl_reg;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire periodic_rd_insert;
  wire [2:0]\q_entry_r[1]_i_4__2 ;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rb_hit_busy_r_reg_2;
  wire rb_hit_busy_r_reg_3;
  wire rd_wr_ns;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire rd_wr_r_lcl_reg_2;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire req_bank_rdy_r_reg;
  wire req_bank_rdy_r_reg_0;
  wire req_bank_rdy_r_reg_1;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [9:0]\req_col_r_reg[9]_1 ;
  wire [0:0]\req_data_buf_addr_r_reg[0]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_1 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13]_0 ;
  wire [0:0]req_wr_r;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg_0;
  wire req_wr_r_lcl_reg_1;
  wire [13:0]row;
  wire row_hit_ns;
  wire row_hit_ns_carry_i_1_n_0;
  wire row_hit_ns_carry_n_0;
  wire row_hit_ns_carry_n_1;
  wire row_hit_ns_carry_n_2;
  wire row_hit_ns_carry_n_3;
  wire row_hit_r;
  wire row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire start_wtp_timer0;
  wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;
  wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;
  wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair577" *) 
  LUT3 #(
    .INIT(8'h8F)) 
    demand_priority_r_i_4__2
       (.I0(req_wr_r),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(Q),
        .O(req_wr_r_lcl_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair576" *) 
  LUT4 #(
    .INIT(16'h7EE8)) 
    head_r_lcl_i_5
       (.I0(rb_hit_busy_r_reg_0),
        .I1(\q_entry_r[1]_i_4__2 [2]),
        .I2(\q_entry_r[1]_i_4__2 [1]),
        .I3(\q_entry_r[1]_i_4__2 [0]),
        .O(rb_hit_busy_r_reg_1));
  LUT5 #(
    .INIT(32'hBDD4D442)) 
    \order_q_r[1]_i_2 
       (.I0(req_wr_r_lcl_reg_1),
        .I1(ordered_r),
        .I2(ordered_r_lcl),
        .I3(\order_q_r_reg[1] ),
        .I4(\order_q_r_reg[1]_0 ),
        .O(ordered_r_lcl_reg));
  LUT6 #(
    .INIT(64'h00000000D5D5D500)) 
    ordered_r_lcl_i_1
       (.I0(Q),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(req_wr_r),
        .I3(ordered_r_lcl_reg_0),
        .I4(ordered_r),
        .I5(ordered_r_lcl_reg_1),
        .O(\grant_r_reg[0] ));
  LUT6 #(
    .INIT(64'hAAAAAAAA8888AA8A)) 
    pass_open_bank_r_lcl_i_3__2
       (.I0(row_hit_r),
        .I1(pass_open_bank_r_lcl_reg),
        .I2(maint_req_r),
        .I3(pass_open_bank_r_lcl_reg_0),
        .I4(pass_open_bank_r_lcl_reg_1),
        .I5(pass_open_bank_r_lcl_reg_2),
        .O(row_hit_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair576" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \q_entry_r[0]_i_4__0 
       (.I0(rb_hit_busy_r_reg_0),
        .I1(\q_entry_r[1]_i_4__2 [0]),
        .I2(\q_entry_r[1]_i_4__2 [1]),
        .I3(\q_entry_r[1]_i_4__2 [2]),
        .O(rb_hit_busy_r_reg_2));
  FDRE rb_hit_busy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rb_hit_busy_r_reg_3),
        .Q(rb_hit_busy_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair577" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    rd_wr_r_lcl_i_1
       (.I0(rd_wr_r_lcl_reg_0),
        .I1(Q),
        .I2(rd_wr_r_lcl_reg_1),
        .I3(rd_wr_r_lcl_reg_2),
        .O(rd_wr_ns));
  FDRE rd_wr_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rd_wr_ns),
        .Q(rd_wr_r_lcl_reg_0),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(bank[0]),
        .Q(\req_bank_r_lcl_reg[2]_0 [0]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(bank[1]),
        .Q(\req_bank_r_lcl_reg[2]_0 [1]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(bank[2]),
        .Q(\req_bank_r_lcl_reg[2]_0 [2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h7F55FFFFFFFFFFFF)) 
    req_bank_rdy_r_i_2
       (.I0(req_bank_rdy_r_reg),
        .I1(req_wr_r),
        .I2(rd_wr_r_lcl_reg_0),
        .I3(Q),
        .I4(req_bank_rdy_r_reg_0),
        .I5(req_bank_rdy_r_reg_1),
        .O(req_wr_r_lcl_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [0]),
        .Q(\req_col_r_reg[9]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [1]),
        .Q(\req_col_r_reg[9]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [2]),
        .Q(\req_col_r_reg[9]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [3]),
        .Q(\req_col_r_reg[9]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [4]),
        .Q(\req_col_r_reg[9]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [5]),
        .Q(\req_col_r_reg[9]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [6]),
        .Q(\req_col_r_reg[9]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [7]),
        .Q(\req_col_r_reg[9]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [8]),
        .Q(\req_col_r_reg[9]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [9]),
        .Q(\req_col_r_reg[9]_0 [9]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[0] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [0]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [0]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[1] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [1]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [1]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[2] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [2]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [2]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[3] 
       (.C(CLK),
        .CE(\req_data_buf_addr_r_reg[0]_0 ),
        .D(\req_data_buf_addr_r_reg[3]_1 [3]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [3]),
        .R(1'b0));
  FDRE req_periodic_rd_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(periodic_rd_insert),
        .Q(req_periodic_rd_r),
        .R(1'b0));
  FDRE req_priority_r_reg
       (.C(CLK),
        .CE(E),
        .D(hi_priority),
        .Q(req_priority_r),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(row[0]),
        .Q(\req_row_r_lcl_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[10] 
       (.C(CLK),
        .CE(E),
        .D(row[10]),
        .Q(\req_row_r_lcl_reg[13]_0 [10]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[11] 
       (.C(CLK),
        .CE(E),
        .D(row[11]),
        .Q(\req_row_r_lcl_reg[13]_0 [11]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[12] 
       (.C(CLK),
        .CE(E),
        .D(row[12]),
        .Q(\req_row_r_lcl_reg[13]_0 [12]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[13] 
       (.C(CLK),
        .CE(E),
        .D(row[13]),
        .Q(\req_row_r_lcl_reg[13]_0 [13]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(row[1]),
        .Q(\req_row_r_lcl_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(row[2]),
        .Q(\req_row_r_lcl_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(row[3]),
        .Q(\req_row_r_lcl_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(row[4]),
        .Q(\req_row_r_lcl_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(row[5]),
        .Q(\req_row_r_lcl_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(row[6]),
        .Q(\req_row_r_lcl_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(row[7]),
        .Q(\req_row_r_lcl_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(row[8]),
        .Q(\req_row_r_lcl_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(row[9]),
        .Q(\req_row_r_lcl_reg[13]_0 [9]),
        .R(1'b0));
  FDRE req_wr_r_lcl_reg
       (.C(CLK),
        .CE(E),
        .D(req_wr_r_lcl0),
        .Q(req_wr_r),
        .R(1'b0));
  CARRY4 row_hit_ns_carry
       (.CI(1'b0),
        .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),
        .S({row_hit_ns_carry_i_1_n_0,S}));
  CARRY4 row_hit_ns_carry__0
       (.CI(row_hit_ns_carry_n_0),
        .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,row_hit_r_reg_1}));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_1
       (.I0(\req_row_r_lcl_reg[13]_0 [11]),
        .I1(row[11]),
        .I2(\req_row_r_lcl_reg[13]_0 [9]),
        .I3(row[9]),
        .I4(\req_row_r_lcl_reg[13]_0 [10]),
        .I5(row[10]),
        .O(row_hit_ns_carry_i_1_n_0));
  FDRE row_hit_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(row_hit_ns),
        .Q(row_hit_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_this_rank_r[0]_i_1 
       (.I0(rd_wr_r_lcl_reg_0),
        .O(start_wtp_timer0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_mach
   (sent_col,
    insert_maint_r1,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    DIC,
    col_rd_wr,
    cke_r,
    bm_end_r1,
    bm_end_r1_0,
    bm_end_r1_1,
    bm_end_r1_2,
    periodic_rd_ack_r_lcl_reg,
    accept_ns,
    wait_for_maint_r,
    wait_for_maint_r_0,
    wait_for_maint_r_1,
    wait_for_maint_r_2,
    maint_wip_r,
    periodic_rd_cntr_r_reg,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ,
    set_order_q,
    set_order_q_3,
    set_order_q_4,
    set_order_q_5,
    \grant_r_reg[1] ,
    granted_col_r_reg,
    D,
    head_r_lcl_reg,
    head_r_lcl_reg_0,
    head_r_lcl_reg_1,
    head_r_lcl_reg_2,
    Q,
    \wr_this_rank_r_reg[0] ,
    \wr_this_rank_r_reg[0]_0 ,
    granted_col_r_reg_0,
    I119,
    granted_col_r_reg_1,
    \periodic_rd_generation.read_this_rank_r_reg ,
    \periodic_rd_generation.read_this_rank ,
    E,
    clear_periodic_rd_request,
    \grant_r_reg[3] ,
    \req_row_r_lcl_reg[13] ,
    \grant_r_reg[3]_0 ,
    \req_bank_r_lcl_reg[2] ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_bank_r_lcl_reg[2]_1 ,
    \req_bank_r_lcl_reg[2]_2 ,
    I118,
    mc_cas_n_ns,
    mc_ras_n_ns,
    col_wr_data_buf_addr,
    act_this_rank,
    \grant_r_reg[0] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ,
    CLK,
    SR,
    I120,
    req_wr_r_lcl0,
    rb_hit_busy_r_reg,
    rb_hit_busy_r_reg_0,
    rb_hit_busy_r_reg_1,
    rb_hit_busy_r_reg_2,
    phy_mc_ctl_full,
    in0,
    phy_mc_cmd_full,
    was_wr0,
    maint_srx_r,
    wait_for_maint_r_lcl_reg,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    wait_for_maint_r_lcl_reg_2,
    \cmd_pipe_plus.mc_data_offset_reg[5] ,
    S,
    row_hit_r_reg,
    row_hit_r_reg_0,
    row_hit_r_reg_1,
    row_hit_r_reg_2,
    periodic_rd_cntr_r_reg_0,
    \rtp_timer_r_reg[1] ,
    \maint_controller.maint_hit_busies_r_reg[3] ,
    q_has_rd_r_reg,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] ,
    was_priority_reg,
    app_en_r2,
    maint_req_r,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ,
    \rtp_timer_r_reg[0] ,
    \grant_r[2]_i_3 ,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    \periodic_rd_generation.read_this_rank_r ,
    \periodic_read_request.periodic_rd_grant_r ,
    accept_internal_r_reg,
    rd_wr_r_lcl_reg,
    pass_open_bank_r_lcl_reg,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ,
    maint_rank_r,
    maint_zq_r,
    row,
    ras_timer_zero_r_reg,
    inhbt_act_faw_r,
    ras_timer_zero_r_reg_0,
    ras_timer_zero_r_reg_1,
    ras_timer_zero_r_reg_2,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,
    phy_mc_data_full,
    \req_data_buf_addr_r_reg[3] ,
    bank,
    \req_col_r_reg[9] );
  output sent_col;
  output insert_maint_r1;
  output \generate_maint_cmds.insert_maint_r_lcl_reg ;
  output [0:0]DIC;
  output col_rd_wr;
  output cke_r;
  output bm_end_r1;
  output bm_end_r1_0;
  output bm_end_r1_1;
  output bm_end_r1_2;
  output periodic_rd_ack_r_lcl_reg;
  output accept_ns;
  output wait_for_maint_r;
  output wait_for_maint_r_0;
  output wait_for_maint_r_1;
  output wait_for_maint_r_2;
  output maint_wip_r;
  output periodic_rd_cntr_r_reg;
  output [3:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  output set_order_q;
  output set_order_q_3;
  output set_order_q_4;
  output set_order_q_5;
  output \grant_r_reg[1] ;
  output granted_col_r_reg;
  output [2:0]D;
  output head_r_lcl_reg;
  output head_r_lcl_reg_0;
  output head_r_lcl_reg_1;
  output head_r_lcl_reg_2;
  output [0:0]Q;
  output \wr_this_rank_r_reg[0] ;
  output \wr_this_rank_r_reg[0]_0 ;
  output granted_col_r_reg_0;
  output [0:0]I119;
  output [0:0]granted_col_r_reg_1;
  output \periodic_rd_generation.read_this_rank_r_reg ;
  output \periodic_rd_generation.read_this_rank ;
  output [0:0]E;
  output clear_periodic_rd_request;
  output [38:0]\grant_r_reg[3] ;
  output [16:0]\req_row_r_lcl_reg[13] ;
  output [8:0]\grant_r_reg[3]_0 ;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [2:0]\req_bank_r_lcl_reg[2]_0 ;
  output [2:0]\req_bank_r_lcl_reg[2]_1 ;
  output [2:0]\req_bank_r_lcl_reg[2]_2 ;
  output [0:0]I118;
  output [2:0]mc_cas_n_ns;
  output [1:0]mc_ras_n_ns;
  output [3:0]col_wr_data_buf_addr;
  output act_this_rank;
  output \grant_r_reg[0] ;
  output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  input CLK;
  input [0:0]SR;
  input [0:0]I120;
  input req_wr_r_lcl0;
  input rb_hit_busy_r_reg;
  input rb_hit_busy_r_reg_0;
  input rb_hit_busy_r_reg_1;
  input rb_hit_busy_r_reg_2;
  input phy_mc_ctl_full;
  input in0;
  input phy_mc_cmd_full;
  input was_wr0;
  input maint_srx_r;
  input wait_for_maint_r_lcl_reg;
  input wait_for_maint_r_lcl_reg_0;
  input wait_for_maint_r_lcl_reg_1;
  input wait_for_maint_r_lcl_reg_2;
  input [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ;
  input [2:0]S;
  input [0:0]row_hit_r_reg;
  input [0:0]row_hit_r_reg_0;
  input [0:0]row_hit_r_reg_1;
  input [0:0]row_hit_r_reg_2;
  input periodic_rd_cntr_r_reg_0;
  input \rtp_timer_r_reg[1] ;
  input \maint_controller.maint_hit_busies_r_reg[3] ;
  input q_has_rd_r_reg;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] ;
  input was_priority_reg;
  input app_en_r2;
  input maint_req_r;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ;
  input \rtp_timer_r_reg[0] ;
  input [0:0]\grant_r[2]_i_3 ;
  input \cmd_pipe_plus.mc_odt_reg[0] ;
  input \periodic_rd_generation.read_this_rank_r ;
  input \periodic_read_request.periodic_rd_grant_r ;
  input accept_internal_r_reg;
  input rd_wr_r_lcl_reg;
  input pass_open_bank_r_lcl_reg;
  input [1:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ;
  input maint_rank_r;
  input maint_zq_r;
  input [13:0]row;
  input ras_timer_zero_r_reg;
  input inhbt_act_faw_r;
  input ras_timer_zero_r_reg_0;
  input ras_timer_zero_r_reg_1;
  input ras_timer_zero_r_reg_2;
  input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  input phy_mc_data_full;
  input [3:0]\req_data_buf_addr_r_reg[3] ;
  input [2:0]bank;
  input [9:0]\req_col_r_reg[9] ;

  wire CLK;
  wire [2:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire [0:0]I118;
  wire [0:0]I119;
  wire [0:0]I120;
  wire [0:0]Q;
  wire [2:0]S;
  wire [0:0]SR;
  wire accept_internal_r;
  wire accept_internal_r_reg;
  wire accept_ns;
  wire act_this_rank;
  wire [3:0]act_this_rank_r;
  wire app_en_r2;
  wire arb_mux0_n_103;
  wire arb_mux0_n_22;
  wire arb_mux0_n_35;
  wire arb_mux0_n_36;
  wire arb_mux0_n_37;
  wire arb_mux0_n_38;
  wire arb_mux0_n_39;
  wire arb_mux0_n_40;
  wire arb_mux0_n_42;
  wire \arb_row_col0/pre_4_1_1T_arb.granted_pre_ns ;
  wire \arb_row_col0/rnk_config_strobe_ns ;
  wire auto_pre_r;
  wire auto_pre_r_11;
  wire auto_pre_r_17;
  wire auto_pre_r_3;
  wire [2:0]bank;
  wire \bank_cntrl[0].bank0_n_15 ;
  wire \bank_cntrl[0].bank0_n_18 ;
  wire \bank_cntrl[0].bank0_n_20 ;
  wire \bank_cntrl[0].bank0_n_21 ;
  wire \bank_cntrl[0].bank0_n_22 ;
  wire \bank_cntrl[0].bank0_n_24 ;
  wire \bank_cntrl[0].bank0_n_25 ;
  wire \bank_cntrl[0].bank0_n_26 ;
  wire \bank_cntrl[0].bank0_n_27 ;
  wire \bank_cntrl[0].bank0_n_28 ;
  wire \bank_cntrl[0].bank0_n_29 ;
  wire \bank_cntrl[0].bank0_n_30 ;
  wire \bank_cntrl[0].bank0_n_31 ;
  wire \bank_cntrl[0].bank0_n_32 ;
  wire \bank_cntrl[0].bank0_n_33 ;
  wire \bank_cntrl[0].bank0_n_35 ;
  wire \bank_cntrl[0].bank0_n_37 ;
  wire \bank_cntrl[0].bank0_n_38 ;
  wire \bank_cntrl[0].bank0_n_39 ;
  wire \bank_cntrl[0].bank0_n_40 ;
  wire \bank_cntrl[0].bank0_n_41 ;
  wire \bank_cntrl[0].bank0_n_42 ;
  wire \bank_cntrl[0].bank0_n_43 ;
  wire \bank_cntrl[0].bank0_n_44 ;
  wire \bank_cntrl[0].bank0_n_46 ;
  wire \bank_cntrl[0].bank0_n_61 ;
  wire \bank_cntrl[0].bank0_n_62 ;
  wire \bank_cntrl[1].bank0_n_15 ;
  wire \bank_cntrl[1].bank0_n_19 ;
  wire \bank_cntrl[1].bank0_n_21 ;
  wire \bank_cntrl[1].bank0_n_22 ;
  wire \bank_cntrl[1].bank0_n_23 ;
  wire \bank_cntrl[1].bank0_n_25 ;
  wire \bank_cntrl[1].bank0_n_26 ;
  wire \bank_cntrl[1].bank0_n_27 ;
  wire \bank_cntrl[1].bank0_n_29 ;
  wire \bank_cntrl[1].bank0_n_30 ;
  wire \bank_cntrl[1].bank0_n_31 ;
  wire \bank_cntrl[1].bank0_n_32 ;
  wire \bank_cntrl[1].bank0_n_33 ;
  wire \bank_cntrl[1].bank0_n_34 ;
  wire \bank_cntrl[1].bank0_n_35 ;
  wire \bank_cntrl[1].bank0_n_36 ;
  wire \bank_cntrl[1].bank0_n_37 ;
  wire \bank_cntrl[1].bank0_n_38 ;
  wire \bank_cntrl[1].bank0_n_39 ;
  wire \bank_cntrl[1].bank0_n_40 ;
  wire \bank_cntrl[1].bank0_n_55 ;
  wire \bank_cntrl[2].bank0_n_15 ;
  wire \bank_cntrl[2].bank0_n_17 ;
  wire \bank_cntrl[2].bank0_n_20 ;
  wire \bank_cntrl[2].bank0_n_21 ;
  wire \bank_cntrl[2].bank0_n_22 ;
  wire \bank_cntrl[2].bank0_n_24 ;
  wire \bank_cntrl[2].bank0_n_25 ;
  wire \bank_cntrl[2].bank0_n_26 ;
  wire \bank_cntrl[2].bank0_n_27 ;
  wire \bank_cntrl[2].bank0_n_28 ;
  wire \bank_cntrl[2].bank0_n_29 ;
  wire \bank_cntrl[2].bank0_n_30 ;
  wire \bank_cntrl[2].bank0_n_31 ;
  wire \bank_cntrl[2].bank0_n_32 ;
  wire \bank_cntrl[2].bank0_n_33 ;
  wire \bank_cntrl[2].bank0_n_35 ;
  wire \bank_cntrl[2].bank0_n_36 ;
  wire \bank_cntrl[2].bank0_n_37 ;
  wire \bank_cntrl[2].bank0_n_38 ;
  wire \bank_cntrl[2].bank0_n_39 ;
  wire \bank_cntrl[2].bank0_n_40 ;
  wire \bank_cntrl[2].bank0_n_41 ;
  wire \bank_cntrl[2].bank0_n_56 ;
  wire \bank_cntrl[2].bank0_n_57 ;
  wire \bank_cntrl[3].bank0_n_15 ;
  wire \bank_cntrl[3].bank0_n_17 ;
  wire \bank_cntrl[3].bank0_n_20 ;
  wire \bank_cntrl[3].bank0_n_22 ;
  wire \bank_cntrl[3].bank0_n_23 ;
  wire \bank_cntrl[3].bank0_n_24 ;
  wire \bank_cntrl[3].bank0_n_25 ;
  wire \bank_cntrl[3].bank0_n_26 ;
  wire \bank_cntrl[3].bank0_n_27 ;
  wire \bank_cntrl[3].bank0_n_31 ;
  wire \bank_cntrl[3].bank0_n_32 ;
  wire \bank_cntrl[3].bank0_n_33 ;
  wire \bank_cntrl[3].bank0_n_34 ;
  wire \bank_cntrl[3].bank0_n_49 ;
  wire \bank_cntrl[3].bank0_n_50 ;
  wire \bank_cntrl[3].bank0_n_51 ;
  wire bank_common0_n_11;
  wire bank_common0_n_12;
  wire bank_common0_n_13;
  wire bank_common0_n_16;
  wire bank_common0_n_18;
  wire bank_common0_n_19;
  wire bank_common0_n_2;
  wire bank_common0_n_20;
  wire bank_common0_n_21;
  wire bank_common0_n_7;
  wire [9:0]\bank_compare0/req_col_r ;
  wire [9:0]\bank_compare0/req_col_r_10 ;
  wire [9:0]\bank_compare0/req_col_r_16 ;
  wire [9:0]\bank_compare0/req_col_r_2 ;
  wire [1:1]\bank_queue0/q_entry_ns ;
  wire \bank_state0/col_wait_r ;
  wire \bank_state0/col_wait_r_9 ;
  wire \bank_state0/demand_act_priority_r ;
  wire \bank_state0/demand_act_priority_r_15 ;
  wire \bank_state0/demand_act_priority_r_22 ;
  wire \bank_state0/demand_act_priority_r_8 ;
  wire \bank_state0/demand_priority_r ;
  wire \bank_state0/demand_priority_r_13 ;
  wire \bank_state0/demand_priority_r_20 ;
  wire \bank_state0/demand_priority_r_6 ;
  wire \bank_state0/demanded_prior_r ;
  wire \bank_state0/demanded_prior_r_12 ;
  wire \bank_state0/demanded_prior_r_19 ;
  wire \bank_state0/demanded_prior_r_5 ;
  wire \bank_state0/ofs_rdy_r ;
  wire \bank_state0/ofs_rdy_r0 ;
  wire \bank_state0/ofs_rdy_r0_0 ;
  wire \bank_state0/ofs_rdy_r0_1 ;
  wire \bank_state0/ofs_rdy_r_18 ;
  wire \bank_state0/ofs_rdy_r_4 ;
  wire \bank_state0/override_demand_ns ;
  wire \bank_state0/override_demand_r ;
  wire \bank_state0/req_bank_rdy_ns ;
  wire \bank_state0/req_bank_rdy_ns_14 ;
  wire \bank_state0/req_bank_rdy_ns_21 ;
  wire \bank_state0/req_bank_rdy_ns_7 ;
  wire [3:2]bm_end;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire bm_end_r1_1;
  wire bm_end_r1_2;
  wire cke_r;
  wire clear_periodic_rd_request;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ;
  wire \cmd_pipe_plus.mc_odt_reg[0] ;
  wire col_rd_wr;
  wire [3:0]col_wr_data_buf_addr;
  wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire [0:0]\grant_r[2]_i_3 ;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[1] ;
  wire [38:0]\grant_r_reg[3] ;
  wire [8:0]\grant_r_reg[3]_0 ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire [0:0]granted_col_r_reg_1;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire hi_priority;
  wire [3:0]idle_r;
  wire in0;
  wire inhbt_act_faw_r;
  wire insert_maint_r1;
  wire [3:0]\maint_controller.maint_hit_busies_r ;
  wire \maint_controller.maint_hit_busies_r_reg[3] ;
  wire \maint_controller.maint_rdy ;
  wire maint_rank_r;
  wire maint_req_r;
  wire maint_srx_r;
  wire maint_wip_r;
  wire maint_zq_r;
  wire [2:0]mc_cas_n_ns;
  wire [1:0]mc_ras_n_ns;
  wire ordered_r_lcl;
  wire p_9_in;
  wire pass_open_bank_r_lcl_reg;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_cntr_r_reg;
  wire periodic_rd_cntr_r_reg_0;
  wire \periodic_rd_generation.read_this_rank ;
  wire \periodic_rd_generation.read_this_rank_r ;
  wire \periodic_rd_generation.read_this_rank_r_reg ;
  wire periodic_rd_insert;
  wire \periodic_read_request.periodic_rd_grant_r ;
  wire phy_mc_cmd_full;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire q_has_rd_r_reg;
  wire [3:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire ras_timer_zero_r_reg_2;
  wire [6:4]rb_hit_busies_r;
  wire [3:0]rb_hit_busy_r;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rb_hit_busy_r_reg_2;
  wire [3:0]rd_this_rank_r;
  wire [3:0]rd_wr_r;
  wire rd_wr_r_lcl_reg;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_2 ;
  wire [9:0]\req_col_r_reg[9] ;
  wire [18:0]req_data_buf_addr_r;
  wire [3:0]\req_data_buf_addr_r_reg[3] ;
  wire [3:0]req_periodic_rd_r;
  wire [53:9]req_row_r;
  wire [16:0]\req_row_r_lcl_reg[13] ;
  wire req_wr_r_lcl0;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  wire [1:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ;
  wire [13:0]row;
  wire [3:0]row_cmd_wr;
  wire [0:0]row_hit_r_reg;
  wire [0:0]row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire [0:0]row_hit_r_reg_2;
  wire \rtp_timer_r_reg[0] ;
  wire \rtp_timer_r_reg[1] ;
  wire [3:0]sending_col;
  wire [3:0]sending_pre;
  wire [3:0]sending_row;
  wire sent_col;
  wire set_order_q;
  wire set_order_q_3;
  wire set_order_q_4;
  wire set_order_q_5;
  wire wait_for_maint_r;
  wire wait_for_maint_r_0;
  wire wait_for_maint_r_1;
  wire wait_for_maint_r_2;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire wait_for_maint_r_lcl_reg_2;
  wire was_priority;
  wire was_priority_reg;
  wire was_wr;
  wire was_wr0;
  wire [3:0]wr_this_rank_r;
  wire \wr_this_rank_r_reg[0] ;
  wire \wr_this_rank_r_reg[0]_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_arb_mux arb_mux0
       (.CLK(CLK),
        .D(D),
        .DIC(DIC),
        .E(E),
        .I118(I118),
        .I119(I119),
        .I120(I120),
        .Q(sending_col),
        .SR(SR),
        .act_this_rank(act_this_rank),
        .act_this_rank_r(act_this_rank_r),
        .auto_pre_r(auto_pre_r_17),
        .auto_pre_r_10(auto_pre_r_3),
        .auto_pre_r_11(auto_pre_r_11),
        .auto_pre_r_9(auto_pre_r),
        .cke_r(cke_r),
        .\cmd_pipe_plus.mc_address_reg[10] (\bank_cntrl[1].bank0_n_39 ),
        .\cmd_pipe_plus.mc_address_reg[23] (\bank_compare0/req_col_r_16 ),
        .\cmd_pipe_plus.mc_address_reg[23]_0 (\bank_compare0/req_col_r ),
        .\cmd_pipe_plus.mc_address_reg[23]_1 (\bank_compare0/req_col_r_2 ),
        .\cmd_pipe_plus.mc_address_reg[23]_2 (\bank_compare0/req_col_r_10 ),
        .\cmd_pipe_plus.mc_address_reg[41] (\req_row_r_lcl_reg[13] ),
        .\cmd_pipe_plus.mc_bank_reg[2] (\req_bank_r_lcl_reg[2] ),
        .\cmd_pipe_plus.mc_bank_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ),
        .\cmd_pipe_plus.mc_bank_reg[2]_1 (\req_bank_r_lcl_reg[2]_1 ),
        .\cmd_pipe_plus.mc_bank_reg[8] (\req_bank_r_lcl_reg[2]_2 ),
        .\cmd_pipe_plus.mc_cas_n_reg[0] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] ),
        .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5] ),
        .\cmd_pipe_plus.mc_odt_reg[0] (\cmd_pipe_plus.mc_odt_reg[0] ),
        .\col_mux.col_periodic_rd_r_reg (\rtp_timer_r_reg[1] ),
        .col_rd_wr(col_rd_wr),
        .col_wait_r(\bank_state0/col_wait_r_9 ),
        .col_wait_r_0(\bank_state0/col_wait_r ),
        .col_wr_data_buf_addr(col_wr_data_buf_addr),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ),
        .demand_act_priority_r(\bank_state0/demand_act_priority_r ),
        .demand_act_priority_r_5(\bank_state0/demand_act_priority_r_8 ),
        .demand_act_priority_r_6(\bank_state0/demand_act_priority_r_15 ),
        .demand_act_priority_r_8(\bank_state0/demand_act_priority_r_22 ),
        .\grant_r[2]_i_3 (\rtp_timer_r_reg[0] ),
        .\grant_r[2]_i_3_0 (\grant_r[2]_i_3 ),
        .\grant_r[2]_i_3_1 (\bank_cntrl[2].bank0_n_25 ),
        .\grant_r[3]_i_4 (\bank_cntrl[1].bank0_n_34 ),
        .\grant_r[3]_i_4_0 (\bank_cntrl[2].bank0_n_27 ),
        .\grant_r_reg[0] (arb_mux0_n_42),
        .\grant_r_reg[0]_0 (\grant_r_reg[0] ),
        .\grant_r_reg[0]_1 (\bank_cntrl[3].bank0_n_31 ),
        .\grant_r_reg[0]_2 (\bank_cntrl[0].bank0_n_40 ),
        .\grant_r_reg[0]_3 (\bank_cntrl[2].bank0_n_35 ),
        .\grant_r_reg[0]_4 (\bank_cntrl[2].bank0_n_31 ),
        .\grant_r_reg[0]_5 (\bank_cntrl[2].bank0_n_57 ),
        .\grant_r_reg[0]_6 (\bank_cntrl[3].bank0_n_34 ),
        .\grant_r_reg[0]_7 (\bank_cntrl[2].bank0_n_41 ),
        .\grant_r_reg[0]_8 (\bank_cntrl[0].bank0_n_46 ),
        .\grant_r_reg[1] (\grant_r_reg[1] ),
        .\grant_r_reg[1]_0 (\bank_cntrl[1].bank0_n_33 ),
        .\grant_r_reg[1]_1 (\bank_cntrl[2].bank0_n_32 ),
        .\grant_r_reg[1]_2 (\bank_cntrl[1].bank0_n_55 ),
        .\grant_r_reg[1]_3 (\bank_cntrl[1].bank0_n_38 ),
        .\grant_r_reg[2] (arb_mux0_n_39),
        .\grant_r_reg[2]_0 (\bank_cntrl[0].bank0_n_62 ),
        .\grant_r_reg[3] (sending_row),
        .\grant_r_reg[3]_0 (sending_pre),
        .\grant_r_reg[3]_1 (\grant_r_reg[3] ),
        .\grant_r_reg[3]_10 (\bank_cntrl[3].bank0_n_26 ),
        .\grant_r_reg[3]_11 (\bank_cntrl[2].bank0_n_40 ),
        .\grant_r_reg[3]_12 (\bank_cntrl[3].bank0_n_33 ),
        .\grant_r_reg[3]_13 (\bank_cntrl[2].bank0_n_56 ),
        .\grant_r_reg[3]_2 (\grant_r_reg[3]_0 ),
        .\grant_r_reg[3]_3 (arb_mux0_n_103),
        .\grant_r_reg[3]_4 (\bank_cntrl[1].bank0_n_21 ),
        .\grant_r_reg[3]_5 (\bank_cntrl[0].bank0_n_41 ),
        .\grant_r_reg[3]_6 (\bank_cntrl[0].bank0_n_25 ),
        .\grant_r_reg[3]_7 (\bank_cntrl[3].bank0_n_49 ),
        .\grant_r_reg[3]_8 (\bank_cntrl[1].bank0_n_37 ),
        .\grant_r_reg[3]_9 (\bank_cntrl[0].bank0_n_61 ),
        .granted_col_r_reg(sent_col),
        .granted_col_r_reg_0(granted_col_r_reg),
        .granted_col_r_reg_1(granted_col_r_reg_0),
        .granted_col_r_reg_2(granted_col_r_reg_1),
        .granted_col_r_reg_3(\bank_cntrl[0].bank0_n_28 ),
        .granted_col_r_reg_4(\bank_cntrl[2].bank0_n_33 ),
        .granted_col_r_reg_5(\bank_cntrl[3].bank0_n_27 ),
        .granted_col_r_reg_6(\bank_cntrl[2].bank0_n_28 ),
        .granted_col_r_reg_7(\bank_cntrl[3].bank0_n_25 ),
        .granted_row_r_reg(\bank_cntrl[1].bank0_n_40 ),
        .granted_row_r_reg_0(\bank_cntrl[0].bank0_n_44 ),
        .in0(in0),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .insert_maint_r1_lcl_reg(insert_maint_r1),
        .insert_maint_r1_lcl_reg_0(\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .\last_master_r_reg[0] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ),
        .\last_master_r_reg[1] (arb_mux0_n_36),
        .maint_rank_r(maint_rank_r),
        .maint_srx_r(maint_srx_r),
        .maint_zq_r(maint_zq_r),
        .mc_cas_n_ns(mc_cas_n_ns),
        .mc_ras_n_ns(mc_ras_n_ns),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r_4 ),
        .ofs_rdy_r_3(\bank_state0/ofs_rdy_r ),
        .ofs_rdy_r_7(\bank_state0/ofs_rdy_r_18 ),
        .override_demand_ns(\bank_state0/override_demand_ns ),
        .override_demand_r(\bank_state0/override_demand_r ),
        .\periodic_rd_generation.read_this_rank (\periodic_rd_generation.read_this_rank ),
        .\periodic_rd_generation.read_this_rank_r (\periodic_rd_generation.read_this_rank_r ),
        .\periodic_rd_generation.read_this_rank_r_reg (\periodic_rd_generation.read_this_rank_r_reg ),
        .\pre_4_1_1T_arb.granted_pre_ns (\arb_row_col0/pre_4_1_1T_arb.granted_pre_ns ),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] (\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ),
        .rd_this_rank_r(rd_this_rank_r),
        .rd_wr_r(rd_wr_r),
        .rd_wr_r_lcl_reg(arb_mux0_n_37),
        .req_bank_rdy_ns(\bank_state0/req_bank_rdy_ns_21 ),
        .req_bank_rdy_ns_1(\bank_state0/req_bank_rdy_ns_14 ),
        .req_bank_rdy_ns_2(\bank_state0/req_bank_rdy_ns_7 ),
        .req_bank_rdy_ns_4(\bank_state0/req_bank_rdy_ns ),
        .req_data_buf_addr_r({req_data_buf_addr_r[18:15],req_data_buf_addr_r[13:10],req_data_buf_addr_r[8:5],req_data_buf_addr_r[3:0]}),
        .req_periodic_rd_r(req_periodic_rd_r),
        .req_row_r({req_row_r[53:42],req_row_r[39:28],req_row_r[25:14],req_row_r[11:9]}),
        .\rnk_config_r_reg[0] (arb_mux0_n_22),
        .rnk_config_strobe_ns(\arb_row_col0/rnk_config_strobe_ns ),
        .\rnk_config_strobe_r_reg[0] (arb_mux0_n_40),
        .row_cmd_wr(row_cmd_wr),
        .wr_this_rank_r(wr_this_rank_r),
        .\wr_this_rank_r_reg[0] (\wr_this_rank_r_reg[0] ),
        .\wr_this_rank_r_reg[0]_0 (\wr_this_rank_r_reg[0]_0 ),
        .\wtr_timer.wtr_cnt_r_reg[1] (arb_mux0_n_35),
        .\wtr_timer.wtr_cnt_r_reg[1]_0 (arb_mux0_n_38));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_cntrl \bank_cntrl[0].bank0 
       (.CLK(CLK),
        .D(\bank_cntrl[0].bank0_n_22 ),
        .Q({sending_col[3],sending_col[0]}),
        .S(S),
        .SR(SR),
        .accept_internal_r(accept_internal_r),
        .accept_internal_r_reg(accept_internal_r_reg),
        .accept_internal_r_reg_0(head_r_lcl_reg_2),
        .accept_internal_r_reg_1(head_r_lcl_reg_1),
        .accept_internal_r_reg_2(head_r_lcl_reg_0),
        .act_this_rank_r(act_this_rank_r[0]),
        .act_wait_r_lcl_reg(\bank_cntrl[0].bank0_n_44 ),
        .act_wait_r_lcl_reg_0(\bank_cntrl[0].bank0_n_61 ),
        .act_wait_r_lcl_reg_1(sending_row[0]),
        .app_en_r2(app_en_r2),
        .auto_pre_r(auto_pre_r),
        .auto_pre_r_lcl_reg(\bank_cntrl[0].bank0_n_46 ),
        .auto_pre_r_lcl_reg_0(bank_common0_n_2),
        .bank(bank),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_reg(\bank_cntrl[0].bank0_n_26 ),
        .col_wait_r(\bank_state0/col_wait_r ),
        .col_wait_r_reg(\bank_cntrl[0].bank0_n_28 ),
        .col_wait_r_reg_0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] ),
        .\compute_tail.tail_r_lcl_reg (\bank_cntrl[2].bank0_n_36 ),
        .demand_act_priority_r(\bank_state0/demand_act_priority_r ),
        .demand_priority_r(\bank_state0/demand_priority_r ),
        .demand_priority_r_2(\bank_state0/demand_priority_r_20 ),
        .demand_priority_r_reg(\bank_cntrl[0].bank0_n_62 ),
        .demand_priority_r_reg_0(sent_col),
        .demanded_prior_r(\bank_state0/demanded_prior_r ),
        .demanded_prior_r_3(\bank_state0/demanded_prior_r_19 ),
        .demanded_prior_r_reg(\bank_cntrl[2].bank0_n_26 ),
        .\grant_r_reg[0] (\bank_cntrl[0].bank0_n_25 ),
        .granted_col_r_reg(arb_mux0_n_38),
        .granted_col_r_reg_0(arb_mux0_n_39),
        .granted_col_r_reg_1(arb_mux0_n_42),
        .head_r_lcl_reg(head_r_lcl_reg),
        .head_r_lcl_reg_0(idle_r[3:1]),
        .head_r_lcl_reg_1(bank_common0_n_16),
        .hi_priority(hi_priority),
        .idle_r(idle_r[0]),
        .idle_r_lcl_reg(set_order_q),
        .idle_r_lcl_reg_0(\bank_cntrl[0].bank0_n_20 ),
        .idle_r_lcl_reg_1(\bank_cntrl[0].bank0_n_21 ),
        .idle_r_lcl_reg_2(\bank_cntrl[0].bank0_n_31 ),
        .idle_r_lcl_reg_3(\bank_cntrl[0].bank0_n_32 ),
        .idle_r_lcl_reg_4(\bank_cntrl[0].bank0_n_33 ),
        .idle_r_lcl_reg_5(\bank_cntrl[0].bank0_n_35 ),
        .in0(in0),
        .\maint_controller.maint_hit_busies_r_reg[0] (\maint_controller.maint_hit_busies_r [0]),
        .\maint_controller.maint_hit_busies_r_reg[0]_0 (\maint_controller.maint_hit_busies_r_reg[3] ),
        .maint_req_r(maint_req_r),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r ),
        .ofs_rdy_r0(\bank_state0/ofs_rdy_r0_1 ),
        .ofs_rdy_r0_0(\bank_state0/ofs_rdy_r0_0 ),
        .ofs_rdy_r0_1(\bank_state0/ofs_rdy_r0 ),
        .ofs_rdy_r_reg(rd_wr_r[3:1]),
        .\order_q_r_reg[0] (\bank_cntrl[2].bank0_n_17 ),
        .\order_q_r_reg[0]_0 (\bank_cntrl[3].bank0_n_17 ),
        .\order_q_r_reg[1] (\bank_cntrl[0].bank0_n_40 ),
        .\order_q_r_reg[1]_0 (\bank_cntrl[0].bank0_n_41 ),
        .ordered_r_lcl(ordered_r_lcl),
        .ordered_r_lcl_reg(\bank_cntrl[0].bank0_n_37 ),
        .ordered_r_lcl_reg_0(\bank_cntrl[0].bank0_n_39 ),
        .p_9_in(p_9_in),
        .pass_open_bank_r_lcl_reg(\bank_cntrl[0].bank0_n_15 ),
        .pass_open_bank_r_lcl_reg_0(bank_common0_n_12),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg),
        .pass_open_bank_r_lcl_reg_2(periodic_rd_cntr_r_reg),
        .pass_open_bank_r_lcl_reg_3(maint_wip_r),
        .periodic_rd_insert(periodic_rd_insert),
        .phy_mc_cmd_full(phy_mc_cmd_full),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .\pre_4_1_1T_arb.granted_pre_ns (\arb_row_col0/pre_4_1_1T_arb.granted_pre_ns ),
        .\pre_4_1_1T_arb.granted_pre_r_reg (sending_pre[0]),
        .\pre_4_1_1T_arb.granted_pre_r_reg_0 (\bank_cntrl[3].bank0_n_34 ),
        .\pre_4_1_1T_arb.granted_pre_r_reg_1 (\bank_cntrl[2].bank0_n_39 ),
        .pre_bm_end_r_reg(\bank_cntrl[0].bank0_n_18 ),
        .pre_passing_open_bank_r_reg(\bank_cntrl[0].bank0_n_30 ),
        .q_entry_ns(\bank_queue0/q_entry_ns ),
        .\q_entry_r[1]_i_5__1 (bm_end),
        .\q_entry_r_reg[0] (was_priority_reg),
        .\q_entry_r_reg[0]_0 (periodic_rd_ack_r_lcl_reg),
        .\q_entry_r_reg[0]_1 (rb_hit_busy_r[3:1]),
        .\q_entry_r_reg[0]_2 (bank_common0_n_18),
        .\q_entry_r_reg[1] (\bank_cntrl[1].bank0_n_19 ),
        .\q_entry_r_reg[1]_0 (\bank_cntrl[1].bank0_n_31 ),
        .\q_entry_r_reg[1]_1 (\bank_cntrl[3].bank0_n_51 ),
        .q_has_priority_r_reg(bank_common0_n_19),
        .q_has_rd_r_reg(q_has_rd_r_reg),
        .\ras_timer_r_reg[0] (\bank_cntrl[1].bank0_n_36 ),
        .\ras_timer_r_reg[0]_0 (\bank_cntrl[3].bank0_n_32 ),
        .\ras_timer_r_reg[0]_1 (\bank_cntrl[2].bank0_n_38 ),
        .\ras_timer_r_reg[0]_2 (\bank_cntrl[3].bank0_n_23 ),
        .\ras_timer_r_reg[0]_3 (\bank_cntrl[1].bank0_n_27 ),
        .\ras_timer_r_reg[0]_4 (\bank_cntrl[2].bank0_n_30 ),
        .\ras_timer_r_reg[1] (\bank_cntrl[0].bank0_n_27 ),
        .\ras_timer_r_reg[1]_0 (\bank_cntrl[3].bank0_n_24 ),
        .\ras_timer_r_reg[1]_1 (\bank_cntrl[1].bank0_n_26 ),
        .\ras_timer_r_reg[1]_2 (\bank_cntrl[2].bank0_n_29 ),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] (rb_hit_busy_r_reg_0),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 (\bank_cntrl[1].bank0_n_15 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (rb_hit_busy_r_reg_1),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\bank_cntrl[2].bank0_n_15 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (rb_hit_busy_r_reg_2),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\bank_cntrl[3].bank0_n_15 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\bank_cntrl[0].bank0_n_29 ),
        .rb_hit_busies_r(rb_hit_busies_r[4]),
        .rb_hit_busy_r(rb_hit_busy_r[0]),
        .rb_hit_busy_r_reg(\bank_cntrl[0].bank0_n_42 ),
        .rb_hit_busy_r_reg_0(\bank_cntrl[0].bank0_n_43 ),
        .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg),
        .rd_this_rank_r(rd_this_rank_r[0]),
        .rd_wr_r(rd_wr_r[0]),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2]_0 ),
        .req_bank_rdy_ns(\bank_state0/req_bank_rdy_ns ),
        .req_bank_rdy_r_reg(\bank_cntrl[1].bank0_n_25 ),
        .req_bank_rdy_r_reg_0(\bank_cntrl[2].bank0_n_24 ),
        .req_bank_rdy_r_reg_1(\bank_cntrl[3].bank0_n_22 ),
        .\req_col_r_reg[9] (\bank_compare0/req_col_r ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_data_buf_addr_r_reg[3] (req_data_buf_addr_r[3:0]),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .req_periodic_rd_r(req_periodic_rd_r[0]),
        .\req_row_r_lcl_reg[13] ({\req_row_r_lcl_reg[13] [10:9],req_row_r[11:9],\req_row_r_lcl_reg[13] [8:0]}),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .req_wr_r_lcl_reg(\bank_cntrl[0].bank0_n_24 ),
        .req_wr_r_lcl_reg_0(\bank_cntrl[0].bank0_n_38 ),
        .\rnk_config_strobe_r_reg[0] (\bank_cntrl[3].bank0_n_49 ),
        .\rnk_config_strobe_r_reg[0]_0 (arb_mux0_n_40),
        .row(row),
        .row_cmd_wr(row_cmd_wr[0]),
        .row_hit_r_reg(row_hit_r_reg),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1] (\rtp_timer_r_reg[1] ),
        .wait_for_maint_r_lcl_reg(wait_for_maint_r),
        .wait_for_maint_r_lcl_reg_0(bank_common0_n_7),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg),
        .was_priority(was_priority),
        .was_wr(was_wr),
        .wr_this_rank_r(wr_this_rank_r[0]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_cntrl__parameterized0 \bank_cntrl[1].bank0 
       (.CLK(CLK),
        .D(\bank_cntrl[1].bank0_n_23 ),
        .Q(sending_col[2:1]),
        .SR(SR),
        .accept_internal_r(accept_internal_r),
        .act_this_rank_r(act_this_rank_r[1]),
        .act_wait_r_lcl_reg(\bank_cntrl[1].bank0_n_37 ),
        .act_wait_r_lcl_reg_0(\bank_cntrl[1].bank0_n_40 ),
        .app_en_r2(app_en_r2),
        .auto_pre_r(auto_pre_r_3),
        .auto_pre_r_lcl_reg(\bank_cntrl[1].bank0_n_38 ),
        .auto_pre_r_lcl_reg_0(bank_common0_n_2),
        .bank(bank),
        .bm_end_r1_0(bm_end_r1_0),
        .bm_end_r1_reg(\bank_cntrl[1].bank0_n_26 ),
        .\cmd_pipe_plus.mc_address_reg[10] (sending_row[3:1]),
        .\cmd_pipe_plus.mc_address_reg[10]_0 (row_cmd_wr[3]),
        .\cmd_pipe_plus.mc_address_reg[10]_1 (req_row_r[52]),
        .col_wait_r(\bank_state0/col_wait_r_9 ),
        .\compute_tail.tail_r_lcl_reg (bm_end),
        .\compute_tail.tail_r_lcl_reg_0 (\bank_cntrl[2].bank0_n_21 ),
        .demand_act_priority_r(\bank_state0/demand_act_priority_r_8 ),
        .demand_priority_r(\bank_state0/demand_priority_r_6 ),
        .demand_priority_r_0(\bank_state0/demand_priority_r_13 ),
        .demand_priority_r_reg(\bank_cntrl[1].bank0_n_55 ),
        .demand_priority_r_reg_0(sent_col),
        .demanded_prior_r(\bank_state0/demanded_prior_r_5 ),
        .demanded_prior_r_1(\bank_state0/demanded_prior_r_12 ),
        .demanded_prior_r_reg(\bank_cntrl[3].bank0_n_50 ),
        .\grant_r[3]_i_12 (\bank_cntrl[0].bank0_n_24 ),
        .\grant_r[3]_i_12_0 (\bank_cntrl[2].bank0_n_24 ),
        .\grant_r[3]_i_12_1 (\bank_cntrl[3].bank0_n_22 ),
        .\grant_r_reg[1] (\bank_cntrl[1].bank0_n_21 ),
        .\grant_r_reg[2] (\bank_cntrl[1].bank0_n_39 ),
        .head_r_lcl_reg(head_r_lcl_reg_0),
        .head_r_lcl_reg_0(\bank_cntrl[0].bank0_n_20 ),
        .head_r_lcl_reg_1(\bank_cntrl[0].bank0_n_18 ),
        .head_r_lcl_reg_2(\bank_cntrl[0].bank0_n_43 ),
        .head_r_lcl_reg_3(\bank_cntrl[0].bank0_n_42 ),
        .hi_priority(hi_priority),
        .idle_r({idle_r[3:2],idle_r[0]}),
        .idle_r_lcl_reg(idle_r[1]),
        .idle_r_lcl_reg_0(set_order_q_3),
        .idle_r_lcl_reg_1(\bank_cntrl[1].bank0_n_22 ),
        .idle_r_lcl_reg_2(\bank_cntrl[1].bank0_n_29 ),
        .\maint_controller.maint_hit_busies_r_reg[1] (\maint_controller.maint_hit_busies_r [1]),
        .\maint_controller.maint_hit_busies_r_reg[1]_0 (\maint_controller.maint_hit_busies_r_reg[3] ),
        .\maint_controller.maint_rdy (\maint_controller.maint_rdy ),
        .\maint_controller.maint_rdy_r1_reg (bank_common0_n_13),
        .\maint_controller.maint_rdy_r1_reg_0 ({\bank_cntrl[3].bank0_n_20 ,\bank_cntrl[2].bank0_n_22 ,\bank_cntrl[0].bank0_n_22 }),
        .maint_req_r(maint_req_r),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r_4 ),
        .ofs_rdy_r0(\bank_state0/ofs_rdy_r0 ),
        .\order_q_r_reg[0] (\bank_cntrl[0].bank0_n_37 ),
        .\order_q_r_reg[1] (\bank_cntrl[1].bank0_n_33 ),
        .\order_q_r_reg[1]_0 (\bank_cntrl[1].bank0_n_34 ),
        .\order_q_r_reg[1]_1 (\bank_cntrl[0].bank0_n_39 ),
        .ordered_r_lcl(ordered_r_lcl),
        .pass_open_bank_r_lcl_reg(\bank_cntrl[1].bank0_n_15 ),
        .pass_open_bank_r_lcl_reg_0(\bank_cntrl[1].bank0_n_30 ),
        .pass_open_bank_r_lcl_reg_1(bank_common0_n_21),
        .pass_open_bank_r_lcl_reg_2(pass_open_bank_r_lcl_reg),
        .pass_open_bank_r_lcl_reg_3(periodic_rd_cntr_r_reg),
        .pass_open_bank_r_lcl_reg_4(maint_wip_r),
        .periodic_rd_insert(periodic_rd_insert),
        .pre_bm_end_r_reg(\bank_cntrl[1].bank0_n_19 ),
        .pre_bm_end_r_reg_0(\bank_cntrl[1].bank0_n_32 ),
        .pre_bm_end_r_reg_1(sending_pre[1]),
        .pre_passing_open_bank_r_reg(\bank_cntrl[1].bank0_n_36 ),
        .pre_wait_r_reg(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] ),
        .q_entry_ns(\bank_queue0/q_entry_ns ),
        .\q_entry_r_reg[0] (was_priority_reg),
        .\q_entry_r_reg[0]_0 (periodic_rd_ack_r_lcl_reg),
        .\q_entry_r_reg[0]_1 (\bank_cntrl[0].bank0_n_21 ),
        .\q_entry_r_reg[1] (\bank_cntrl[1].bank0_n_31 ),
        .q_has_priority_r_reg(bank_common0_n_19),
        .q_has_rd_r_reg(q_has_rd_r_reg),
        .\ras_timer_r_reg[0] (\bank_cntrl[0].bank0_n_30 ),
        .\ras_timer_r_reg[0]_0 (\bank_cntrl[3].bank0_n_32 ),
        .\ras_timer_r_reg[0]_1 (\bank_cntrl[2].bank0_n_38 ),
        .\ras_timer_r_reg[0]_2 (\bank_cntrl[0].bank0_n_27 ),
        .\ras_timer_r_reg[0]_3 (\bank_cntrl[3].bank0_n_23 ),
        .\ras_timer_r_reg[0]_4 (\bank_cntrl[2].bank0_n_30 ),
        .\ras_timer_r_reg[1] (\bank_cntrl[1].bank0_n_27 ),
        .\ras_timer_r_reg[1]_0 (\bank_cntrl[0].bank0_n_26 ),
        .\ras_timer_r_reg[1]_1 (\bank_cntrl[2].bank0_n_29 ),
        .\ras_timer_r_reg[1]_2 (\bank_cntrl[3].bank0_n_24 ),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg_0),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (rb_hit_busy_r_reg_1),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\bank_cntrl[2].bank0_n_15 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (rb_hit_busy_r_reg_2),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\bank_cntrl[3].bank0_n_15 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (rb_hit_busy_r_reg),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (bank_common0_n_16),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\bank_cntrl[0].bank0_n_15 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\bank_cntrl[1].bank0_n_35 ),
        .rb_hit_busies_r(rb_hit_busies_r[5]),
        .rb_hit_busy_r({rb_hit_busy_r[3:2],rb_hit_busy_r[0]}),
        .rb_hit_busy_r_reg(rb_hit_busy_r[1]),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0),
        .rd_this_rank_r(rd_this_rank_r[1]),
        .rd_wr_r_lcl_reg(rd_wr_r[1]),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ),
        .req_bank_rdy_ns(\bank_state0/req_bank_rdy_ns_7 ),
        .req_bank_rdy_r_reg(\bank_cntrl[0].bank0_n_38 ),
        .\req_col_r_reg[9] (\bank_compare0/req_col_r_2 ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_data_buf_addr_r_reg[3] (req_data_buf_addr_r[8:5]),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .req_periodic_rd_r(req_periodic_rd_r[1]),
        .\req_row_r_lcl_reg[13] ({\req_row_r_lcl_reg[13] [12:11],req_row_r[25:14]}),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .req_wr_r_lcl_reg(\bank_cntrl[1].bank0_n_25 ),
        .\rnk_config_strobe_r_reg[0] (\bank_cntrl[2].bank0_n_57 ),
        .\rnk_config_strobe_r_reg[0]_0 (arb_mux0_n_40),
        .row(row),
        .row_cmd_wr(row_cmd_wr[1]),
        .row_hit_r_reg(row_hit_r_reg_0),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1] (\rtp_timer_r_reg[1] ),
        .wait_for_maint_r_lcl_reg(wait_for_maint_r_0),
        .wait_for_maint_r_lcl_reg_0(bank_common0_n_7),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0),
        .was_priority(was_priority),
        .was_wr(was_wr),
        .wr_this_rank_r(wr_this_rank_r[1]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_cntrl__parameterized1 \bank_cntrl[2].bank0 
       (.CLK(CLK),
        .D(\bank_cntrl[2].bank0_n_22 ),
        .Q(sending_col),
        .SR(SR),
        .accept_internal_r(accept_internal_r),
        .act_this_rank_r(act_this_rank_r[2]),
        .act_wait_r_lcl_reg(\bank_cntrl[2].bank0_n_40 ),
        .act_wait_r_lcl_reg_0(\bank_cntrl[2].bank0_n_56 ),
        .act_wait_r_lcl_reg_1(sending_row[2]),
        .app_en_r2(app_en_r2),
        .auto_pre_r(auto_pre_r_11),
        .auto_pre_r_lcl_reg(\bank_cntrl[2].bank0_n_41 ),
        .auto_pre_r_lcl_reg_0(bank_common0_n_2),
        .bank(bank),
        .bm_end_r1_1(bm_end_r1_1),
        .bm_end_r1_reg(\bank_cntrl[2].bank0_n_29 ),
        .col_wait_r_reg(\bank_cntrl[2].bank0_n_31 ),
        .col_wait_r_reg_0(\bank_cntrl[2].bank0_n_32 ),
        .col_wait_r_reg_1(\bank_cntrl[2].bank0_n_33 ),
        .\compute_tail.tail_r_lcl_reg (\bank_cntrl[1].bank0_n_32 ),
        .\compute_tail.tail_r_lcl_reg_0 (\bank_cntrl[1].bank0_n_19 ),
        .\compute_tail.tail_r_lcl_reg_1 (\bank_cntrl[0].bank0_n_18 ),
        .\compute_tail.tail_r_lcl_reg_2 (bm_end[3]),
        .demand_act_priority_r(\bank_state0/demand_act_priority_r_15 ),
        .demand_priority_r(\bank_state0/demand_priority_r_13 ),
        .demand_priority_r_1(\bank_state0/demand_priority_r_20 ),
        .demand_priority_r_2(\bank_state0/demand_priority_r ),
        .demand_priority_r_4(\bank_state0/demand_priority_r_6 ),
        .demand_priority_r_reg(\bank_cntrl[2].bank0_n_57 ),
        .demand_priority_r_reg_0(sent_col),
        .demanded_prior_r(\bank_state0/demanded_prior_r_12 ),
        .demanded_prior_r_0(\bank_state0/demanded_prior_r_19 ),
        .demanded_prior_r_3(\bank_state0/demanded_prior_r_5 ),
        .demanded_prior_r_5(\bank_state0/demanded_prior_r ),
        .demanded_prior_r_reg(\bank_cntrl[2].bank0_n_26 ),
        .demanded_prior_r_reg_0(\bank_cntrl[3].bank0_n_50 ),
        .\grant_r[0]_i_2 (arb_mux0_n_22),
        .\grant_r[3]_i_13 (\bank_cntrl[1].bank0_n_25 ),
        .\grant_r[3]_i_13_0 (\bank_cntrl[0].bank0_n_24 ),
        .\grant_r[3]_i_13_1 (\bank_cntrl[3].bank0_n_22 ),
        .\grant_r_reg[0] (arb_mux0_n_35),
        .\grant_r_reg[1] (arb_mux0_n_37),
        .\grant_r_reg[1]_0 (arb_mux0_n_36),
        .granted_col_r_reg(arb_mux0_n_38),
        .granted_col_r_reg_0(arb_mux0_n_39),
        .head_r_lcl_reg(head_r_lcl_reg_1),
        .head_r_lcl_reg_0(\bank_cntrl[1].bank0_n_30 ),
        .head_r_lcl_reg_1(\bank_cntrl[0].bank0_n_20 ),
        .head_r_lcl_reg_2(\bank_cntrl[0].bank0_n_43 ),
        .head_r_lcl_reg_3(\bank_cntrl[0].bank0_n_42 ),
        .hi_priority(hi_priority),
        .idle_r(idle_r[2]),
        .idle_r_lcl_reg(set_order_q_4),
        .\maint_controller.maint_hit_busies_r_reg[2] (\maint_controller.maint_hit_busies_r [2]),
        .\maint_controller.maint_hit_busies_r_reg[2]_0 (\maint_controller.maint_hit_busies_r_reg[3] ),
        .maint_req_r(maint_req_r),
        .ofs_rdy_r0(\bank_state0/ofs_rdy_r0_0 ),
        .\order_q_r_reg[0] (\bank_cntrl[0].bank0_n_37 ),
        .\order_q_r_reg[1] (\bank_cntrl[2].bank0_n_35 ),
        .\order_q_r_reg[1]_0 (\bank_cntrl[0].bank0_n_39 ),
        .ordered_r_lcl_reg(\bank_cntrl[2].bank0_n_17 ),
        .override_demand_ns(\bank_state0/override_demand_ns ),
        .override_demand_r(\bank_state0/override_demand_r ),
        .override_demand_r_reg(\bank_cntrl[2].bank0_n_25 ),
        .override_demand_r_reg_0(\bank_cntrl[2].bank0_n_27 ),
        .override_demand_r_reg_1(\bank_cntrl[2].bank0_n_28 ),
        .pass_open_bank_r_lcl_reg(\bank_cntrl[2].bank0_n_15 ),
        .pass_open_bank_r_lcl_reg_0(bank_common0_n_20),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg),
        .pass_open_bank_r_lcl_reg_2(periodic_rd_cntr_r_reg),
        .pass_open_bank_r_lcl_reg_3(maint_wip_r),
        .periodic_rd_insert(periodic_rd_insert),
        .\pre_4_1_1T_arb.granted_pre_r_reg (\bank_cntrl[1].bank0_n_38 ),
        .pre_bm_end_r_reg(bm_end[2]),
        .pre_bm_end_r_reg_0(\bank_cntrl[2].bank0_n_20 ),
        .pre_bm_end_r_reg_1(\bank_cntrl[2].bank0_n_21 ),
        .pre_bm_end_r_reg_2(\bank_cntrl[2].bank0_n_36 ),
        .pre_bm_end_r_reg_3(sending_pre[2]),
        .pre_passing_open_bank_r_reg(\bank_cntrl[2].bank0_n_38 ),
        .pre_wait_r_reg(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] ),
        .\q_entry_r_reg[0] ({rb_hit_busy_r[3],rb_hit_busy_r[1:0]}),
        .\q_entry_r_reg[0]_0 (was_priority_reg),
        .\q_entry_r_reg[0]_1 (periodic_rd_ack_r_lcl_reg),
        .\q_entry_r_reg[0]_2 (\bank_cntrl[0].bank0_n_31 ),
        .\q_entry_r_reg[1] (\bank_cntrl[1].bank0_n_29 ),
        .\q_entry_r_reg[1]_0 (\bank_cntrl[1].bank0_n_22 ),
        .q_has_priority_r_reg(bank_common0_n_19),
        .q_has_rd_r_reg(q_has_rd_r_reg),
        .\ras_timer_r_reg[0] (\bank_cntrl[3].bank0_n_32 ),
        .\ras_timer_r_reg[0]_0 (\bank_cntrl[0].bank0_n_30 ),
        .\ras_timer_r_reg[0]_1 (\bank_cntrl[1].bank0_n_36 ),
        .\ras_timer_r_reg[0]_2 (\bank_cntrl[1].bank0_n_27 ),
        .\ras_timer_r_reg[0]_3 (\bank_cntrl[0].bank0_n_27 ),
        .\ras_timer_r_reg[0]_4 (\bank_cntrl[3].bank0_n_23 ),
        .\ras_timer_r_reg[1] (\bank_cntrl[2].bank0_n_30 ),
        .\ras_timer_r_reg[1]_0 (\bank_cntrl[1].bank0_n_26 ),
        .\ras_timer_r_reg[1]_1 (\bank_cntrl[3].bank0_n_24 ),
        .\ras_timer_r_reg[1]_2 (\bank_cntrl[0].bank0_n_26 ),
        .ras_timer_zero_r_reg(\bank_cntrl[2].bank0_n_39 ),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_1),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (rb_hit_busy_r_reg_2),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\bank_cntrl[3].bank0_n_15 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (rb_hit_busy_r_reg),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (bank_common0_n_16),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\bank_cntrl[0].bank0_n_15 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (rb_hit_busy_r_reg_0),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\bank_cntrl[1].bank0_n_15 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] (\bank_cntrl[2].bank0_n_37 ),
        .rb_hit_busies_r(rb_hit_busies_r[6]),
        .rb_hit_busy_r(rb_hit_busy_r[2]),
        .rb_hit_busy_r_reg(rb_hit_busy_r_reg_1),
        .rd_this_rank_r(rd_this_rank_r[2]),
        .rd_wr_r_lcl_reg(rd_wr_r[2]),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2]_1 ),
        .req_bank_rdy_ns(\bank_state0/req_bank_rdy_ns_14 ),
        .req_bank_rdy_r_reg(\bank_cntrl[0].bank0_n_38 ),
        .\req_col_r_reg[9] (\bank_compare0/req_col_r_10 ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_data_buf_addr_r_reg[3] (req_data_buf_addr_r[13:10]),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .req_periodic_rd_r(req_periodic_rd_r[2]),
        .\req_row_r_lcl_reg[13] ({\req_row_r_lcl_reg[13] [14:13],req_row_r[39:28]}),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .req_wr_r_lcl_reg(\bank_cntrl[2].bank0_n_24 ),
        .rnk_config_strobe_ns(\arb_row_col0/rnk_config_strobe_ns ),
        .\rnk_config_strobe_r_reg[0] (\bank_cntrl[1].bank0_n_33 ),
        .\rnk_config_strobe_r_reg[0]_0 (\bank_cntrl[0].bank0_n_40 ),
        .\rnk_config_strobe_r_reg[0]_1 (\bank_cntrl[3].bank0_n_31 ),
        .\rnk_config_strobe_r_reg[0]_2 (\bank_cntrl[1].bank0_n_55 ),
        .\rnk_config_strobe_r_reg[0]_3 (arb_mux0_n_40),
        .row(row),
        .row_cmd_wr(row_cmd_wr[2]),
        .row_hit_r_reg(row_hit_r_reg_1),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1] (\rtp_timer_r_reg[1] ),
        .wait_for_maint_r_lcl_reg(wait_for_maint_r_1),
        .wait_for_maint_r_lcl_reg_0(bank_common0_n_7),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_1),
        .was_priority(was_priority),
        .was_wr(was_wr),
        .wr_this_rank_r(wr_this_rank_r[2]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_cntrl__parameterized2 \bank_cntrl[3].bank0 
       (.CLK(CLK),
        .D(\bank_cntrl[3].bank0_n_20 ),
        .Q({sending_col[3],sending_col[0]}),
        .SR(SR),
        .accept_internal_r(accept_internal_r),
        .act_this_rank_r(act_this_rank_r[3]),
        .act_wait_r_lcl_reg(row_cmd_wr[3]),
        .act_wait_r_lcl_reg_0(\bank_cntrl[3].bank0_n_26 ),
        .act_wait_r_lcl_reg_1(\bank_cntrl[3].bank0_n_33 ),
        .act_wait_r_lcl_reg_2(\bank_cntrl[2].bank0_n_37 ),
        .app_en_r2(app_en_r2),
        .auto_pre_r(auto_pre_r_17),
        .auto_pre_r_lcl_reg(\bank_cntrl[3].bank0_n_34 ),
        .auto_pre_r_lcl_reg_0(bank_common0_n_2),
        .bank(bank),
        .bm_end_r1_2(bm_end_r1_2),
        .bm_end_r1_reg(\bank_cntrl[3].bank0_n_24 ),
        .col_wait_r_reg(\bank_cntrl[3].bank0_n_25 ),
        .col_wait_r_reg_0(sending_row[3]),
        .\compute_tail.tail_r_lcl_reg (\bank_cntrl[2].bank0_n_20 ),
        .demand_act_priority_r(\bank_state0/demand_act_priority_r_22 ),
        .demand_priority_r(\bank_state0/demand_priority_r_20 ),
        .demand_priority_r_0(\bank_state0/demand_priority_r ),
        .demand_priority_r_reg(\bank_cntrl[3].bank0_n_49 ),
        .demand_priority_r_reg_0(bank_common0_n_16),
        .demand_priority_r_reg_1(\bank_cntrl[1].bank0_n_25 ),
        .demand_priority_r_reg_2(\bank_cntrl[0].bank0_n_24 ),
        .demand_priority_r_reg_3(\bank_cntrl[2].bank0_n_24 ),
        .demanded_prior_r(\bank_state0/demanded_prior_r_19 ),
        .demanded_prior_r_1(\bank_state0/demanded_prior_r ),
        .demanded_prior_r_reg(\bank_cntrl[3].bank0_n_50 ),
        .demanded_prior_r_reg_0(\bank_cntrl[2].bank0_n_26 ),
        .\grant_r[3]_i_6 (\bank_cntrl[1].bank0_n_35 ),
        .head_r_lcl_i_3(\bank_cntrl[0].bank0_n_18 ),
        .head_r_lcl_i_3_0(bm_end[2]),
        .head_r_lcl_i_3_1(\bank_cntrl[1].bank0_n_19 ),
        .head_r_lcl_reg(head_r_lcl_reg_2),
        .head_r_lcl_reg_0(\bank_cntrl[0].bank0_n_20 ),
        .head_r_lcl_reg_1(\bank_cntrl[0].bank0_n_43 ),
        .hi_priority(hi_priority),
        .idle_r(idle_r[3]),
        .idle_r_lcl_reg(set_order_q_5),
        .idle_r_lcl_reg_0(\bank_cntrl[3].bank0_n_51 ),
        .\maint_controller.maint_hit_busies_r_reg[3] (\maint_controller.maint_hit_busies_r [3]),
        .\maint_controller.maint_hit_busies_r_reg[3]_0 (\maint_controller.maint_hit_busies_r_reg[3] ),
        .maint_req_r(maint_req_r),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r_18 ),
        .ofs_rdy_r0(\bank_state0/ofs_rdy_r0_1 ),
        .\order_q_r_reg[0] (\bank_cntrl[0].bank0_n_37 ),
        .\order_q_r_reg[1] (\bank_cntrl[3].bank0_n_27 ),
        .\order_q_r_reg[1]_0 (\bank_cntrl[3].bank0_n_31 ),
        .\order_q_r_reg[1]_1 (was_priority_reg),
        .\order_q_r_reg[1]_2 (periodic_rd_ack_r_lcl_reg),
        .\order_q_r_reg[1]_3 (\bank_cntrl[0].bank0_n_39 ),
        .ordered_r_lcl_reg(\bank_cntrl[3].bank0_n_17 ),
        .pass_open_bank_r_lcl_reg(\bank_cntrl[3].bank0_n_15 ),
        .pass_open_bank_r_lcl_reg_0(bank_common0_n_11),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg),
        .pass_open_bank_r_lcl_reg_2(periodic_rd_cntr_r_reg),
        .pass_open_bank_r_lcl_reg_3(maint_wip_r),
        .periodic_rd_insert(periodic_rd_insert),
        .pre_bm_end_r_reg(bm_end[3]),
        .pre_bm_end_r_reg_0(sending_pre[3]),
        .pre_passing_open_bank_r_reg(\bank_cntrl[3].bank0_n_32 ),
        .pre_wait_r_reg(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] ),
        .\q_entry_r_reg[0] (\bank_cntrl[0].bank0_n_42 ),
        .\q_entry_r_reg[0]_0 (\bank_cntrl[0].bank0_n_33 ),
        .\q_entry_r_reg[1] (\bank_cntrl[0].bank0_n_35 ),
        .\q_entry_r_reg[1]_0 (idle_r[2:0]),
        .\q_entry_r_reg[1]_1 (\bank_cntrl[0].bank0_n_32 ),
        .q_has_priority_r_reg(bank_common0_n_19),
        .q_has_rd_r_reg(q_has_rd_r_reg),
        .\ras_timer_r_reg[0] (\bank_cntrl[0].bank0_n_29 ),
        .\ras_timer_r_reg[0]_0 (\bank_cntrl[1].bank0_n_36 ),
        .\ras_timer_r_reg[0]_1 (\bank_cntrl[2].bank0_n_38 ),
        .\ras_timer_r_reg[0]_2 (\bank_cntrl[2].bank0_n_30 ),
        .\ras_timer_r_reg[0]_3 (\bank_cntrl[0].bank0_n_27 ),
        .\ras_timer_r_reg[0]_4 (\bank_cntrl[1].bank0_n_27 ),
        .\ras_timer_r_reg[1] (\bank_cntrl[3].bank0_n_23 ),
        .\ras_timer_r_reg[1]_0 (\bank_cntrl[2].bank0_n_29 ),
        .\ras_timer_r_reg[1]_1 (\bank_cntrl[0].bank0_n_26 ),
        .\ras_timer_r_reg[1]_2 (\bank_cntrl[1].bank0_n_26 ),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg_2),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (rb_hit_busy_r_reg),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\bank_cntrl[0].bank0_n_15 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (rb_hit_busy_r_reg_0),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\bank_cntrl[1].bank0_n_15 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] (rb_hit_busy_r_reg_1),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 (\bank_cntrl[2].bank0_n_15 ),
        .rb_hit_busies_r(rb_hit_busies_r),
        .rb_hit_busy_r(rb_hit_busy_r[2:0]),
        .rb_hit_busy_r_reg(rb_hit_busy_r[3]),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_2),
        .rd_this_rank_r(rd_this_rank_r[3]),
        .rd_wr_r_lcl_reg(rd_wr_r[3]),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2]_2 ),
        .req_bank_rdy_ns(\bank_state0/req_bank_rdy_ns_21 ),
        .req_bank_rdy_r_reg(\bank_cntrl[0].bank0_n_38 ),
        .\req_col_r_reg[9] (\bank_compare0/req_col_r_16 ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_data_buf_addr_r_reg[3] (req_data_buf_addr_r[18:15]),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .req_periodic_rd_r(req_periodic_rd_r[3]),
        .\req_row_r_lcl_reg[13] ({\req_row_r_lcl_reg[13] [16:15],req_row_r[53:42]}),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .req_wr_r_lcl_reg(\bank_cntrl[3].bank0_n_22 ),
        .\rnk_config_strobe_r_reg[0] (\bank_cntrl[0].bank0_n_62 ),
        .\rnk_config_strobe_r_reg[0]_0 (arb_mux0_n_40),
        .row(row),
        .row_hit_r_reg(row_hit_r_reg_2),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1] (\rtp_timer_r_reg[1] ),
        .\starve_limit_cntr_r_reg[0] (arb_mux0_n_103),
        .wait_for_maint_r_lcl_reg(wait_for_maint_r_2),
        .wait_for_maint_r_lcl_reg_0(bank_common0_n_7),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_2),
        .was_priority(was_priority),
        .was_wr(was_wr),
        .wr_this_rank_r(wr_this_rank_r[3]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_common bank_common0
       (.CLK(CLK),
        .D({\bank_cntrl[3].bank0_n_20 ,\bank_cntrl[2].bank0_n_22 ,\bank_cntrl[1].bank0_n_23 ,\bank_cntrl[0].bank0_n_22 }),
        .Q(Q),
        .SR(SR),
        .accept_internal_r(accept_internal_r),
        .accept_internal_r_reg_0(bank_common0_n_16),
        .accept_ns(accept_ns),
        .accept_r_reg_0(bank_common0_n_2),
        .app_en_r2(app_en_r2),
        .app_rdy_r_reg(bank_common0_n_11),
        .app_rdy_r_reg_0(bank_common0_n_12),
        .clear_periodic_rd_request(clear_periodic_rd_request),
        .\generate_maint_cmds.insert_maint_r_lcl_reg_0 (\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .hi_priority(hi_priority),
        .idle_r(idle_r),
        .idle_r_lcl_reg(bank_common0_n_18),
        .\maint_controller.maint_hit_busies_r_reg[3]_0 (\maint_controller.maint_hit_busies_r ),
        .\maint_controller.maint_rdy (\maint_controller.maint_rdy ),
        .\maint_controller.maint_wip_r_lcl_reg_0 (maint_wip_r),
        .\maint_controller.maint_wip_r_lcl_reg_1 (bank_common0_n_13),
        .maint_req_r(maint_req_r),
        .maint_srx_r(maint_srx_r),
        .maint_zq_r(maint_zq_r),
        .\maintenance_request.maint_req_r_lcl_reg (bank_common0_n_7),
        .p_9_in(p_9_in),
        .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r_lcl_reg),
        .periodic_rd_ack_r_lcl_reg_1(bank_common0_n_19),
        .periodic_rd_cntr_r_reg_0(periodic_rd_cntr_r_reg),
        .periodic_rd_cntr_r_reg_1(periodic_rd_cntr_r_reg_0),
        .periodic_rd_insert(periodic_rd_insert),
        .\periodic_read_request.periodic_rd_grant_r (\periodic_read_request.periodic_rd_grant_r ),
        .rb_hit_busy_r(rb_hit_busy_r),
        .rb_hit_busy_r_reg(bank_common0_n_20),
        .rb_hit_busy_r_reg_0(bank_common0_n_21),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ),
        .was_priority(was_priority),
        .was_priority_reg_0(was_priority_reg),
        .was_wr(was_wr),
        .was_wr0(was_wr0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_queue
   (idle_r_lcl_reg_0,
    E,
    pass_open_bank_r,
    pass_open_bank_ns,
    q_has_rd,
    pass_open_bank_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_0,
    head_r,
    ordered_r,
    auto_pre_r_lcl_reg_0,
    pre_bm_end_r_reg_0,
    idle_r_lcl_reg_1,
    idle_r_lcl_reg_2,
    idle_r_lcl_reg_3,
    D,
    head_r_lcl_reg_0,
    \q_entry_r_reg[0]_0 ,
    col_wait_r_reg,
    \grant_r_reg[0] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,
    pre_passing_open_bank_r_reg_0,
    idle_r_lcl_reg_4,
    idle_r_lcl_reg_5,
    idle_r_lcl_reg_6,
    p_9_in,
    idle_r_lcl_reg_7,
    q_entry_ns,
    act_wait_ns,
    bm_end,
    ordered_r_lcl_reg_0,
    \order_q_r_reg[0]_0 ,
    \order_q_r_reg[1]_0 ,
    req_bank_rdy_ns,
    \order_q_r_reg[1]_1 ,
    act_wait_r_lcl_reg,
    CLK,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    wait_for_maint_r_lcl_reg_1,
    wait_for_maint_r_lcl_reg_2,
    SR,
    ordered_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_1,
    \compute_tail.tail_r_lcl_reg_0 ,
    pass_open_bank_r_lcl_reg_2,
    auto_pre_r_lcl_reg_1,
    Q,
    auto_pre_r_lcl_reg_2,
    head_r_lcl_reg_1,
    q_has_priority_r_reg_0,
    \order_q_r_reg[1]_2 ,
    \maint_controller.maint_hit_busies_r_reg[0] ,
    \maint_controller.maint_hit_busies_r_reg[0]_0 ,
    q_has_rd_r_reg_0,
    was_wr,
    bm_end_r1_reg,
    req_wr_r,
    \ras_timer_r_reg[1] ,
    \ras_timer_r_reg[0] ,
    granted_col_r_reg,
    granted_col_r_reg_0,
    granted_col_r_reg_1,
    rb_hit_busies_r,
    \q_entry_r_reg[1]_0 ,
    \q_entry_r[1]_i_5__1_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    accept_internal_r_reg,
    accept_internal_r_reg_0,
    accept_internal_r_reg_1,
    accept_internal_r_reg_2,
    head_r_lcl_reg_2,
    pre_wait_r,
    \q_entry_r_reg[1]_1 ,
    bm_end_r1,
    ordered_r_lcl,
    \order_q_r_reg[0]_1 ,
    \order_q_r_reg[0]_2 ,
    req_bank_rdy_r_reg,
    req_priority_r,
    \rnk_config_strobe_r_reg[0] ,
    \rnk_config_strobe_r_reg[0]_0 ,
    \grant_r[3]_i_2 ,
    \grant_r[3]_i_2_0 ,
    \grant_r[3]_i_2_1 ,
    \grant_r[3]_i_2_2 ,
    head_r_lcl_reg_3,
    head_r_lcl_reg_4,
    accept_internal_r,
    app_en_r2,
    \q_entry_r_reg[0]_1 ,
    \q_entry_r_reg[0]_2 ,
    act_wait_r_lcl_reg_0,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \ras_timer_r_reg[0]_2 ,
    \q_entry_r_reg[0]_3 ,
    q_has_priority_r_reg_1,
    ras_timer_zero_r,
    auto_pre_r_lcl_reg_3,
    was_priority,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_3 ,
    \ras_timer_r_reg[0]_4 ,
    \ras_timer_r_reg[0]_5 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 ,
    \q_entry_r_reg[1]_2 ,
    \q_entry_r_reg[0]_4 ,
    \order_q_r_reg[1]_3 );
  output [0:0]idle_r_lcl_reg_0;
  output [0:0]E;
  output pass_open_bank_r;
  output pass_open_bank_ns;
  output q_has_rd;
  output pass_open_bank_r_lcl_reg_0;
  output wait_for_maint_r_lcl_reg_0;
  output [0:0]head_r;
  output ordered_r;
  output auto_pre_r_lcl_reg_0;
  output pre_bm_end_r_reg_0;
  output idle_r_lcl_reg_1;
  output idle_r_lcl_reg_2;
  output idle_r_lcl_reg_3;
  output [0:0]D;
  output head_r_lcl_reg_0;
  output [1:0]\q_entry_r_reg[0]_0 ;
  output col_wait_r_reg;
  output \grant_r_reg[0] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  output pre_passing_open_bank_r_reg_0;
  output idle_r_lcl_reg_4;
  output idle_r_lcl_reg_5;
  output idle_r_lcl_reg_6;
  output p_9_in;
  output idle_r_lcl_reg_7;
  output [0:0]q_entry_ns;
  output act_wait_ns;
  output [0:0]bm_end;
  output ordered_r_lcl_reg_0;
  output \order_q_r_reg[0]_0 ;
  output \order_q_r_reg[1]_0 ;
  output req_bank_rdy_ns;
  output \order_q_r_reg[1]_1 ;
  output act_wait_r_lcl_reg;
  input CLK;
  input pre_bm_end_ns;
  input pre_passing_open_bank_ns;
  input wait_for_maint_r_lcl_reg_1;
  input wait_for_maint_r_lcl_reg_2;
  input [0:0]SR;
  input ordered_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_1;
  input \compute_tail.tail_r_lcl_reg_0 ;
  input pass_open_bank_r_lcl_reg_2;
  input auto_pre_r_lcl_reg_1;
  input [0:0]Q;
  input auto_pre_r_lcl_reg_2;
  input [2:0]head_r_lcl_reg_1;
  input q_has_priority_r_reg_0;
  input \order_q_r_reg[1]_2 ;
  input [0:0]\maint_controller.maint_hit_busies_r_reg[0] ;
  input \maint_controller.maint_hit_busies_r_reg[0]_0 ;
  input q_has_rd_r_reg_0;
  input was_wr;
  input bm_end_r1_reg;
  input [0:0]req_wr_r;
  input \ras_timer_r_reg[1] ;
  input \ras_timer_r_reg[0] ;
  input granted_col_r_reg;
  input granted_col_r_reg_0;
  input granted_col_r_reg_1;
  input [0:0]rb_hit_busies_r;
  input \q_entry_r_reg[1]_0 ;
  input [1:0]\q_entry_r[1]_i_5__1_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  input accept_internal_r_reg;
  input accept_internal_r_reg_0;
  input accept_internal_r_reg_1;
  input accept_internal_r_reg_2;
  input head_r_lcl_reg_2;
  input pre_wait_r;
  input \q_entry_r_reg[1]_1 ;
  input bm_end_r1;
  input ordered_r_lcl;
  input \order_q_r_reg[0]_1 ;
  input \order_q_r_reg[0]_2 ;
  input req_bank_rdy_r_reg;
  input req_priority_r;
  input \rnk_config_strobe_r_reg[0] ;
  input \rnk_config_strobe_r_reg[0]_0 ;
  input \grant_r[3]_i_2 ;
  input \grant_r[3]_i_2_0 ;
  input \grant_r[3]_i_2_1 ;
  input \grant_r[3]_i_2_2 ;
  input head_r_lcl_reg_3;
  input head_r_lcl_reg_4;
  input accept_internal_r;
  input app_en_r2;
  input \q_entry_r_reg[0]_1 ;
  input \q_entry_r_reg[0]_2 ;
  input [0:0]act_wait_r_lcl_reg_0;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \ras_timer_r_reg[0]_2 ;
  input [2:0]\q_entry_r_reg[0]_3 ;
  input q_has_priority_r_reg_1;
  input ras_timer_zero_r;
  input auto_pre_r_lcl_reg_3;
  input was_priority;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_3 ;
  input \ras_timer_r_reg[0]_4 ;
  input \ras_timer_r_reg[0]_5 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 ;
  input \q_entry_r_reg[1]_2 ;
  input \q_entry_r_reg[0]_4 ;
  input \order_q_r_reg[1]_3 ;

  wire CLK;
  wire [0:0]D;
  wire [0:0]E;
  wire [0:0]Q;
  wire [0:0]SR;
  wire accept_internal_r;
  wire accept_internal_r_reg;
  wire accept_internal_r_reg_0;
  wire accept_internal_r_reg_1;
  wire accept_internal_r_reg_2;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg;
  wire [0:0]act_wait_r_lcl_reg_0;
  wire app_en_r2;
  wire auto_pre_r_lcl_i_1__0_n_0;
  wire auto_pre_r_lcl_i_2__0_n_0;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg_3;
  wire [0:0]bm_end;
  wire bm_end_r1;
  wire bm_end_r1_reg;
  wire col_wait_r_reg;
  wire \compute_tail.tail_r_lcl_i_1_n_0 ;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire \grant_r[3]_i_2 ;
  wire \grant_r[3]_i_2_0 ;
  wire \grant_r[3]_i_2_1 ;
  wire \grant_r[3]_i_2_2 ;
  wire \grant_r_reg[0] ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire [0:0]head_r;
  wire head_r_lcl_i_1_n_0;
  wire head_r_lcl_i_2__1_n_0;
  wire head_r_lcl_i_4__1_n_0;
  wire head_r_lcl_reg_0;
  wire [2:0]head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire head_r_lcl_reg_3;
  wire head_r_lcl_reg_4;
  wire [0:0]idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire idle_r_lcl_reg_3;
  wire idle_r_lcl_reg_4;
  wire idle_r_lcl_reg_5;
  wire idle_r_lcl_reg_6;
  wire idle_r_lcl_reg_7;
  wire [0:0]\maint_controller.maint_hit_busies_r_reg[0] ;
  wire \maint_controller.maint_hit_busies_r_reg[0]_0 ;
  wire [1:0]order_q_r;
  wire \order_q_r[0]_i_1_n_0 ;
  wire \order_q_r[1]_i_1_n_0 ;
  wire \order_q_r_reg[0]_0 ;
  wire \order_q_r_reg[0]_1 ;
  wire \order_q_r_reg[0]_2 ;
  wire \order_q_r_reg[1]_0 ;
  wire \order_q_r_reg[1]_1 ;
  wire \order_q_r_reg[1]_2 ;
  wire \order_q_r_reg[1]_3 ;
  wire ordered_r;
  wire ordered_r_lcl;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire p_9_in;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_wait_r;
  wire [0:0]q_entry_ns;
  wire [1:0]q_entry_r;
  wire \q_entry_r[0]_i_1_n_0 ;
  wire \q_entry_r[0]_i_2__1_n_0 ;
  wire \q_entry_r[1]_i_1_n_0 ;
  wire \q_entry_r[1]_i_4_n_0 ;
  wire [1:0]\q_entry_r[1]_i_5__1_0 ;
  wire \q_entry_r[1]_i_5__1_n_0 ;
  wire \q_entry_r[1]_i_5__2_n_0 ;
  wire \q_entry_r[1]_i_6__2_n_0 ;
  wire \q_entry_r[1]_i_7__1_n_0 ;
  wire \q_entry_r[1]_i_8_n_0 ;
  wire [1:0]\q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire [2:0]\q_entry_r_reg[0]_3 ;
  wire \q_entry_r_reg[0]_4 ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire \q_entry_r_reg[1]_2 ;
  wire q_has_priority;
  wire q_has_priority_r_i_1__0_n_0;
  wire q_has_priority_r_reg_0;
  wire q_has_priority_r_reg_1;
  wire q_has_rd;
  wire q_has_rd_r_i_1_n_0;
  wire q_has_rd_r_reg_0;
  wire \ras_timer_r[0]_i_2__2_n_0 ;
  wire \ras_timer_r[1]_i_2__1_n_0 ;
  wire \ras_timer_r[1]_i_3__2_n_0 ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[0]_5 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[1]_i_2_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_2_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  wire [0:0]rb_hit_busies_r;
  wire [3:1]rb_hit_busies_r_0;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire req_priority_r;
  wire [0:0]req_wr_r;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire wait_for_maint_r_lcl_reg_2;
  wire was_priority;
  wire was_wr;

  LUT5 #(
    .INIT(32'h2AAAAAAA)) 
    accept_internal_r_i_1
       (.I0(accept_internal_r_reg),
        .I1(head_r_lcl_reg_0),
        .I2(accept_internal_r_reg_0),
        .I3(accept_internal_r_reg_1),
        .I4(accept_internal_r_reg_2),
        .O(p_9_in));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF44F4)) 
    act_wait_r_lcl_i_1__2
       (.I0(\grant_r_reg[0] ),
        .I1(auto_pre_r_lcl_reg_2),
        .I2(pass_open_bank_r),
        .I3(pre_bm_end_r_reg_0),
        .I4(\order_q_r_reg[1]_2 ),
        .I5(bm_end_r1),
        .O(act_wait_ns));
  LUT6 #(
    .INIT(64'h888F888888888888)) 
    act_wait_r_lcl_i_2__2
       (.I0(act_wait_r_lcl_reg_0),
        .I1(auto_pre_r_lcl_reg_2),
        .I2(idle_r_lcl_reg_0),
        .I3(q_entry_r[1]),
        .I4(q_entry_r[0]),
        .I5(\ras_timer_r[1]_i_2__1_n_0 ),
        .O(\grant_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair578" *) 
  LUT5 #(
    .INIT(32'h40555555)) 
    act_wait_r_lcl_i_3
       (.I0(pre_bm_end_r),
        .I1(req_wr_r),
        .I2(bm_end_r1_reg),
        .I3(Q),
        .I4(pass_open_bank_r),
        .O(pre_bm_end_r_reg_0));
  LUT6 #(
    .INIT(64'hAAAAAAAA00808080)) 
    act_wait_r_lcl_i_5
       (.I0(rb_hit_busies_r),
        .I1(pass_open_bank_r),
        .I2(Q),
        .I3(bm_end_r1_reg),
        .I4(req_wr_r),
        .I5(pre_passing_open_bank_r),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ));
  LUT6 #(
    .INIT(64'hFFFFFFFF11110010)) 
    auto_pre_r_lcl_i_1__0
       (.I0(pass_open_bank_r_lcl_reg_2),
        .I1(auto_pre_r_lcl_i_2__0_n_0),
        .I2(auto_pre_r_lcl_reg_1),
        .I3(Q),
        .I4(auto_pre_r_lcl_reg_2),
        .I5(auto_pre_r_lcl_reg_0),
        .O(auto_pre_r_lcl_i_1__0_n_0));
  LUT6 #(
    .INIT(64'h777F7F7F7F7F7F7F)) 
    auto_pre_r_lcl_i_2__0
       (.I0(tail_r),
        .I1(q_has_priority_r_reg_1),
        .I2(\q_entry_r_reg[0]_2 ),
        .I3(auto_pre_r_lcl_reg_3),
        .I4(app_en_r2),
        .I5(\q_entry_r_reg[0]_1 ),
        .O(auto_pre_r_lcl_i_2__0_n_0));
  FDRE auto_pre_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(auto_pre_r_lcl_i_1__0_n_0),
        .Q(auto_pre_r_lcl_reg_0),
        .R(pass_open_bank_r_lcl_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair578" *) 
  LUT5 #(
    .INIT(32'hFFFF0888)) 
    bm_end_r1_i_1
       (.I0(pass_open_bank_r),
        .I1(Q),
        .I2(bm_end_r1_reg),
        .I3(req_wr_r),
        .I4(pre_bm_end_r),
        .O(bm_end));
  LUT6 #(
    .INIT(64'hDFDFCCCFDDDDCCCC)) 
    \compute_tail.tail_r_lcl_i_1 
       (.I0(pre_bm_end_r_reg_0),
        .I1(idle_r_lcl_reg_1),
        .I2(pass_open_bank_r_lcl_reg_1),
        .I3(idle_r_lcl_reg_0),
        .I4(\compute_tail.tail_r_lcl_reg_0 ),
        .I5(tail_r),
        .O(\compute_tail.tail_r_lcl_i_1_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \compute_tail.tail_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\compute_tail.tail_r_lcl_i_1_n_0 ),
        .Q(tail_r),
        .R(SR));
  LUT5 #(
    .INIT(32'hF2F2F2FF)) 
    demand_priority_r_i_2__2
       (.I0(order_q_r[0]),
        .I1(req_bank_rdy_r_reg),
        .I2(order_q_r[1]),
        .I3(q_has_priority),
        .I4(req_priority_r),
        .O(\order_q_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF1FFF111)) 
    \grant_r[2]_i_3 
       (.I0(\grant_r_reg[0] ),
        .I1(auto_pre_r_lcl_reg_1),
        .I2(granted_col_r_reg),
        .I3(bm_end_r1_reg),
        .I4(granted_col_r_reg_0),
        .I5(granted_col_r_reg_1),
        .O(col_wait_r_reg));
  LUT6 #(
    .INIT(64'hFDFFFDFDFFFFFFFF)) 
    \grant_r[2]_i_4 
       (.I0(\rnk_config_strobe_r_reg[0] ),
        .I1(\rnk_config_strobe_r_reg[0]_0 ),
        .I2(order_q_r[1]),
        .I3(req_bank_rdy_r_reg),
        .I4(order_q_r[0]),
        .I5(auto_pre_r_lcl_reg_1),
        .O(\order_q_r_reg[1]_0 ));
  LUT5 #(
    .INIT(32'hFFDFFFFF)) 
    \grant_r[2]_i_6 
       (.I0(auto_pre_r_lcl_reg_2),
        .I1(idle_r_lcl_reg_0),
        .I2(head_r),
        .I3(wait_for_maint_r_lcl_reg_0),
        .I4(ras_timer_zero_r),
        .O(act_wait_r_lcl_reg));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \grant_r[3]_i_8 
       (.I0(order_q_r[1]),
        .I1(\grant_r[3]_i_2 ),
        .I2(\grant_r[3]_i_2_0 ),
        .I3(\grant_r[3]_i_2_1 ),
        .I4(\grant_r[3]_i_2_2 ),
        .I5(order_q_r[0]),
        .O(\order_q_r_reg[1]_1 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    head_r_lcl_i_1
       (.I0(head_r_lcl_i_2__1_n_0),
        .I1(pre_bm_end_r_reg_0),
        .I2(idle_r_lcl_reg_2),
        .I3(\q_entry_r[1]_i_5__1_n_0 ),
        .I4(head_r),
        .O(head_r_lcl_i_1_n_0));
  LUT6 #(
    .INIT(64'h20202020202F2F20)) 
    head_r_lcl_i_2__1
       (.I0(q_entry_r[0]),
        .I1(q_entry_r[1]),
        .I2(head_r_lcl_i_4__1_n_0),
        .I3(head_r_lcl_reg_3),
        .I4(\q_entry_r[1]_i_8_n_0 ),
        .I5(head_r_lcl_reg_4),
        .O(head_r_lcl_i_2__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair582" *) 
  LUT5 #(
    .INIT(32'h01168001)) 
    head_r_lcl_i_3__2
       (.I0(idle_r_lcl_reg_0),
        .I1(head_r_lcl_reg_1[2]),
        .I2(head_r_lcl_reg_1[0]),
        .I3(head_r_lcl_reg_1[1]),
        .I4(q_has_priority_r_reg_0),
        .O(idle_r_lcl_reg_2));
  LUT5 #(
    .INIT(32'hDD1D1111)) 
    head_r_lcl_i_4__1
       (.I0(\q_entry_r[1]_i_8_n_0 ),
        .I1(idle_r_lcl_reg_0),
        .I2(head_r),
        .I3(head_r_lcl_reg_2),
        .I4(q_has_priority_r_reg_0),
        .O(head_r_lcl_i_4__1_n_0));
  FDSE head_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(head_r_lcl_i_1_n_0),
        .Q(head_r),
        .S(SR));
  (* SOFT_HLUTNM = "soft_lutpair579" *) 
  LUT1 #(
    .INIT(2'h1)) 
    idle_r_lcl_i_1
       (.I0(head_r_lcl_reg_0),
        .O(E));
  LUT5 #(
    .INIT(32'h00004F00)) 
    idle_r_lcl_i_2
       (.I0(head_r_lcl_reg_2),
        .I1(head_r),
        .I2(idle_r_lcl_reg_0),
        .I3(pre_bm_end_r_reg_0),
        .I4(\order_q_r_reg[1]_2 ),
        .O(head_r_lcl_reg_0));
  FDRE idle_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(E),
        .Q(idle_r_lcl_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair579" *) 
  LUT5 #(
    .INIT(32'h20222020)) 
    \maint_controller.maint_hit_busies_r[0]_i_1 
       (.I0(pre_bm_end_r_reg_0),
        .I1(\order_q_r_reg[1]_2 ),
        .I2(\maint_controller.maint_hit_busies_r_reg[0] ),
        .I3(\maint_controller.maint_hit_busies_r_reg[0]_0 ),
        .I4(head_r_lcl_reg_0),
        .O(D));
  LUT6 #(
    .INIT(64'h31553000315530CC)) 
    \order_q_r[0]_i_1 
       (.I0(ordered_r_lcl_reg_0),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_bank_rdy_r_reg),
        .I4(idle_r_lcl_reg_1),
        .I5(\order_q_r_reg[1]_2 ),
        .O(\order_q_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h69969669)) 
    \order_q_r[0]_i_2 
       (.I0(ordered_r),
        .I1(ordered_r_lcl),
        .I2(\order_q_r_reg[0]_1 ),
        .I3(\order_q_r_reg[0]_2 ),
        .I4(req_bank_rdy_r_reg),
        .O(ordered_r_lcl_reg_0));
  LUT6 #(
    .INIT(64'hC2AAC000C2AAC0F0)) 
    \order_q_r[1]_i_1 
       (.I0(\order_q_r_reg[1]_3 ),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_bank_rdy_r_reg),
        .I4(idle_r_lcl_reg_1),
        .I5(\order_q_r_reg[1]_2 ),
        .O(\order_q_r[1]_i_1_n_0 ));
  FDRE \order_q_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[0]_i_1_n_0 ),
        .Q(order_q_r[0]),
        .R(1'b0));
  FDRE \order_q_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[1]_i_1_n_0 ),
        .Q(order_q_r[1]),
        .R(1'b0));
  FDRE ordered_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ordered_r_lcl_reg_1),
        .Q(ordered_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4444544444444444)) 
    pass_open_bank_r_lcl_i_1
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(pass_open_bank_r),
        .I2(tail_r),
        .I3(pass_open_bank_r_lcl_reg_1),
        .I4(pre_wait_r),
        .I5(pass_open_bank_r_lcl_reg_2),
        .O(pass_open_bank_ns));
  FDRE pass_open_bank_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pass_open_bank_ns),
        .Q(pass_open_bank_r),
        .R(1'b0));
  FDRE pre_bm_end_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_bm_end_ns),
        .Q(pre_bm_end_r),
        .R(1'b0));
  FDRE pre_passing_open_bank_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_passing_open_bank_ns),
        .Q(pre_passing_open_bank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4F40FFFF7F700000)) 
    \q_entry_r[0]_i_1 
       (.I0(\q_entry_r[0]_i_2__1_n_0 ),
        .I1(idle_r_lcl_reg_1),
        .I2(pre_bm_end_r_reg_0),
        .I3(\q_entry_r_reg[0]_4 ),
        .I4(\q_entry_r[1]_i_5__1_n_0 ),
        .I5(q_entry_r[0]),
        .O(\q_entry_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair583" *) 
  LUT4 #(
    .INIT(16'h9669)) 
    \q_entry_r[0]_i_2 
       (.I0(\q_entry_r[1]_i_5__2_n_0 ),
        .I1(pre_bm_end_r_reg_0),
        .I2(q_has_priority_r_reg_0),
        .I3(\q_entry_r_reg[1]_0 ),
        .O(idle_r_lcl_reg_4));
  (* SOFT_HLUTNM = "soft_lutpair583" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \q_entry_r[0]_i_2__0 
       (.I0(\q_entry_r[1]_i_5__2_n_0 ),
        .I1(pre_bm_end_r_reg_0),
        .I2(\q_entry_r_reg[1]_0 ),
        .I3(\q_entry_r[1]_i_5__1_0 [0]),
        .O(idle_r_lcl_reg_6));
  (* SOFT_HLUTNM = "soft_lutpair580" *) 
  LUT5 #(
    .INIT(32'h96696996)) 
    \q_entry_r[0]_i_2__1 
       (.I0(\q_entry_r[1]_i_8_n_0 ),
        .I1(\q_entry_r_reg[0]_3 [2]),
        .I2(\q_entry_r_reg[0]_3 [1]),
        .I3(\q_entry_r_reg[0]_3 [0]),
        .I4(q_has_priority_r_reg_1),
        .O(\q_entry_r[0]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h8080808080000000)) 
    \q_entry_r[0]_i_3__2 
       (.I0(idle_r_lcl_reg_0),
        .I1(head_r),
        .I2(accept_internal_r),
        .I3(app_en_r2),
        .I4(\q_entry_r_reg[0]_1 ),
        .I5(\q_entry_r_reg[0]_2 ),
        .O(idle_r_lcl_reg_1));
  LUT6 #(
    .INIT(64'h9669699669969669)) 
    \q_entry_r[0]_i_4__1 
       (.I0(pre_bm_end_r_reg_0),
        .I1(idle_r_lcl_reg_0),
        .I2(head_r_lcl_reg_1[2]),
        .I3(head_r_lcl_reg_1[0]),
        .I4(head_r_lcl_reg_1[1]),
        .I5(q_has_priority_r_reg_0),
        .O(idle_r_lcl_reg_3));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \q_entry_r[1]_i_1 
       (.I0(\q_entry_r_reg[1]_2 ),
        .I1(q_has_priority_r_reg_0),
        .I2(pre_bm_end_r_reg_0),
        .I3(\q_entry_r[1]_i_4_n_0 ),
        .I4(\q_entry_r[1]_i_5__1_n_0 ),
        .I5(q_entry_r[1]),
        .O(\q_entry_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair581" *) 
  LUT5 #(
    .INIT(32'h599A6559)) 
    \q_entry_r[1]_i_2 
       (.I0(\q_entry_r[1]_i_6__2_n_0 ),
        .I1(\q_entry_r[1]_i_5__1_0 [0]),
        .I2(\q_entry_r_reg[1]_0 ),
        .I3(pre_bm_end_r_reg_0),
        .I4(\q_entry_r[1]_i_5__2_n_0 ),
        .O(idle_r_lcl_reg_5));
  LUT6 #(
    .INIT(64'hC0F3D1E2E2D1C0F3)) 
    \q_entry_r[1]_i_2__0 
       (.I0(q_has_priority_r_reg_0),
        .I1(\q_entry_r_reg[1]_0 ),
        .I2(\q_entry_r_reg[1]_1 ),
        .I3(\q_entry_r[1]_i_6__2_n_0 ),
        .I4(pre_bm_end_r_reg_0),
        .I5(\q_entry_r[1]_i_5__2_n_0 ),
        .O(q_entry_ns));
  LUT6 #(
    .INIT(64'h35050535F5C5C5F5)) 
    \q_entry_r[1]_i_4 
       (.I0(\q_entry_r[1]_i_6__2_n_0 ),
        .I1(idle_r_lcl_reg_1),
        .I2(pre_bm_end_r_reg_0),
        .I3(q_entry_r[0]),
        .I4(q_entry_r[1]),
        .I5(\q_entry_r[1]_i_7__1_n_0 ),
        .O(\q_entry_r[1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair581" *) 
  LUT5 #(
    .INIT(32'hBD2B42D4)) 
    \q_entry_r[1]_i_5 
       (.I0(\q_entry_r[1]_i_5__2_n_0 ),
        .I1(pre_bm_end_r_reg_0),
        .I2(\q_entry_r_reg[1]_0 ),
        .I3(\q_entry_r[1]_i_5__1_0 [0]),
        .I4(\q_entry_r[1]_i_6__2_n_0 ),
        .O(idle_r_lcl_reg_7));
  LUT6 #(
    .INIT(64'hA3A3F3A3FFFFFFFF)) 
    \q_entry_r[1]_i_5__1 
       (.I0(q_has_priority_r_reg_0),
        .I1(\q_entry_r[1]_i_8_n_0 ),
        .I2(idle_r_lcl_reg_0),
        .I3(head_r),
        .I4(head_r_lcl_reg_2),
        .I5(pre_bm_end_r_reg_0),
        .O(\q_entry_r[1]_i_5__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair582" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \q_entry_r[1]_i_5__2 
       (.I0(idle_r_lcl_reg_0),
        .I1(head_r_lcl_reg_1[2]),
        .I2(head_r_lcl_reg_1[0]),
        .I3(head_r_lcl_reg_1[1]),
        .O(\q_entry_r[1]_i_5__2_n_0 ));
  LUT4 #(
    .INIT(16'h8117)) 
    \q_entry_r[1]_i_6__2 
       (.I0(idle_r_lcl_reg_0),
        .I1(head_r_lcl_reg_1[1]),
        .I2(head_r_lcl_reg_1[0]),
        .I3(head_r_lcl_reg_1[2]),
        .O(\q_entry_r[1]_i_6__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair580" *) 
  LUT5 #(
    .INIT(32'h8117177E)) 
    \q_entry_r[1]_i_7__1 
       (.I0(\q_entry_r[1]_i_8_n_0 ),
        .I1(\q_entry_r_reg[0]_3 [0]),
        .I2(\q_entry_r_reg[0]_3 [1]),
        .I3(\q_entry_r_reg[0]_3 [2]),
        .I4(q_has_priority_r_reg_1),
        .O(\q_entry_r[1]_i_7__1_n_0 ));
  LUT6 #(
    .INIT(64'h0777077700000777)) 
    \q_entry_r[1]_i_8 
       (.I0(\q_entry_r[1]_i_5__1_0 [0]),
        .I1(rb_hit_busies_r_0[2]),
        .I2(rb_hit_busies_r_0[3]),
        .I3(\q_entry_r[1]_i_5__1_0 [1]),
        .I4(rb_hit_busies_r_0[1]),
        .I5(\q_entry_r_reg[1]_0 ),
        .O(\q_entry_r[1]_i_8_n_0 ));
  FDRE \q_entry_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[0]_i_1_n_0 ),
        .Q(q_entry_r[0]),
        .R(SR));
  FDRE \q_entry_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[1]_i_1_n_0 ),
        .Q(q_entry_r[1]),
        .R(SR));
  LUT4 #(
    .INIT(16'hEAAA)) 
    q_has_priority_r_i_1__0
       (.I0(q_has_priority),
        .I1(q_has_priority_r_reg_0),
        .I2(q_has_priority_r_reg_1),
        .I3(was_priority),
        .O(q_has_priority_r_i_1__0_n_0));
  FDRE q_has_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_priority_r_i_1__0_n_0),
        .Q(q_has_priority),
        .R(pass_open_bank_r_lcl_reg_0));
  LUT6 #(
    .INIT(64'h4445555544454445)) 
    q_has_rd_r_i_1
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(q_has_rd),
        .I2(q_has_rd_r_reg_0),
        .I3(idle_r_lcl_reg_0),
        .I4(was_wr),
        .I5(pass_open_bank_r_lcl_reg_1),
        .O(q_has_rd_r_i_1_n_0));
  FDRE q_has_rd_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_rd_r_i_1_n_0),
        .Q(q_has_rd),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFF700080000)) 
    \ras_timer_r[0]_i_1__2 
       (.I0(\ras_timer_r[1]_i_2__1_n_0 ),
        .I1(q_entry_r[0]),
        .I2(q_entry_r[1]),
        .I3(idle_r_lcl_reg_0),
        .I4(\ras_timer_r[0]_i_2__2_n_0 ),
        .I5(\ras_timer_r_reg[0] ),
        .O(\q_entry_r_reg[0]_0 [0]));
  LUT6 #(
    .INIT(64'hBBBBB8888888B888)) 
    \ras_timer_r[0]_i_2__2 
       (.I0(\ras_timer_r_reg[0]_3 ),
        .I1(rb_hit_busies_r_0[3]),
        .I2(rb_hit_busies_r_0[1]),
        .I3(\ras_timer_r_reg[0]_4 ),
        .I4(rb_hit_busies_r_0[2]),
        .I5(\ras_timer_r_reg[0]_5 ),
        .O(\ras_timer_r[0]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFF700080000)) 
    \ras_timer_r[1]_i_1__2 
       (.I0(\ras_timer_r[1]_i_2__1_n_0 ),
        .I1(q_entry_r[0]),
        .I2(q_entry_r[1]),
        .I3(idle_r_lcl_reg_0),
        .I4(\ras_timer_r[1]_i_3__2_n_0 ),
        .I5(\ras_timer_r_reg[1] ),
        .O(\q_entry_r_reg[0]_0 [1]));
  LUT6 #(
    .INIT(64'h44F444F4FFFF44F4)) 
    \ras_timer_r[1]_i_2__1 
       (.I0(\ras_timer_r_reg[0]_0 ),
        .I1(rb_hit_busies_r_0[1]),
        .I2(rb_hit_busies_r_0[3]),
        .I3(\ras_timer_r_reg[0]_1 ),
        .I4(rb_hit_busies_r_0[2]),
        .I5(\ras_timer_r_reg[0]_2 ),
        .O(\ras_timer_r[1]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBB8888888B888)) 
    \ras_timer_r[1]_i_3__2 
       (.I0(\ras_timer_r_reg[1]_0 ),
        .I1(rb_hit_busies_r_0[3]),
        .I2(rb_hit_busies_r_0[1]),
        .I3(\ras_timer_r_reg[1]_1 ),
        .I4(rb_hit_busies_r_0[2]),
        .I5(\ras_timer_r_reg[1]_2 ),
        .O(\ras_timer_r[1]_i_3__2_n_0 ));
  LUT5 #(
    .INIT(32'h40555555)) 
    \ras_timer_r[1]_i_5 
       (.I0(pre_passing_open_bank_r),
        .I1(req_wr_r),
        .I2(bm_end_r1_reg),
        .I3(Q),
        .I4(pass_open_bank_r),
        .O(pre_passing_open_bank_r_reg_0));
  LUT3 #(
    .INIT(8'hB8)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[1]_i_2 
       (.I0(rb_hit_busies_r_0[1]),
        .I1(head_r_lcl_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[1]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2 
       (.I0(rb_hit_busies_r_0[2]),
        .I1(head_r_lcl_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_2 
       (.I0(rb_hit_busies_r_0[3]),
        .I1(head_r_lcl_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAEAEAEA)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1 
       (.I0(\order_q_r_reg[1]_2 ),
        .I1(pass_open_bank_r),
        .I2(Q),
        .I3(bm_end_r1_reg),
        .I4(req_wr_r),
        .I5(pre_bm_end_r),
        .O(pass_open_bank_r_lcl_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[1]_i_2_n_0 ),
        .Q(rb_hit_busies_r_0[1]),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2_n_0 ),
        .Q(rb_hit_busies_r_0[2]),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_2_n_0 ),
        .Q(rb_hit_busies_r_0[3]),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ));
  LUT4 #(
    .INIT(16'h00A2)) 
    req_bank_rdy_r_i_1__2
       (.I0(auto_pre_r_lcl_reg_1),
        .I1(order_q_r[0]),
        .I2(req_bank_rdy_r_reg),
        .I3(order_q_r[1]),
        .O(req_bank_rdy_ns));
  FDRE wait_for_maint_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wait_for_maint_r_lcl_reg_2),
        .Q(wait_for_maint_r_lcl_reg_0),
        .R(wait_for_maint_r_lcl_reg_1));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_queue" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_queue__parameterized0
   (idle_r_lcl_reg_0,
    E,
    pass_open_bank_r,
    pass_open_bank_ns,
    q_has_rd,
    pass_open_bank_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_0,
    head_r,
    ordered_r_lcl,
    auto_pre_r_lcl_reg_0,
    pre_bm_end_r_reg_0,
    idle_r_lcl_reg_1,
    idle_r_lcl_reg_2,
    D,
    head_r_lcl_reg_0,
    \q_entry_r_reg[0]_0 ,
    act_wait_ns,
    \grant_r_reg[1] ,
    \maint_controller.maint_rdy ,
    idle_r_lcl_reg_3,
    pass_open_bank_r_lcl_reg_1,
    \q_entry_r_reg[1]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    pre_bm_end_r_reg_1,
    \order_q_r_reg[0]_0 ,
    \order_q_r_reg[1]_0 ,
    req_bank_rdy_ns,
    \order_q_r_reg[1]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    pre_passing_open_bank_r_reg_0,
    bm_end,
    act_wait_r_lcl_reg,
    CLK,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    wait_for_maint_r_lcl_reg_1,
    wait_for_maint_r_lcl_reg_2,
    SR,
    ordered_r_lcl_reg_0,
    head_r_lcl_reg_1,
    head_r_lcl_reg_2,
    pass_open_bank_r_lcl_reg_2,
    \compute_tail.tail_r_lcl_reg_0 ,
    pass_open_bank_r_lcl_reg_3,
    auto_pre_r_lcl_reg_1,
    Q,
    auto_pre_r_lcl_reg_2,
    idle_r,
    \order_q_r_reg[1]_2 ,
    \maint_controller.maint_hit_busies_r_reg[1] ,
    \maint_controller.maint_hit_busies_r_reg[1]_0 ,
    q_has_rd_r_reg_0,
    was_wr,
    q_has_priority_r_reg_0,
    bm_end_r1_reg,
    req_wr_r,
    \ras_timer_r_reg[1] ,
    \ras_timer_r_reg[0] ,
    bm_end_r1_0,
    act_wait_r_lcl_reg_0,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \ras_timer_r_reg[0]_2 ,
    \maint_controller.maint_rdy_r1_reg ,
    \maint_controller.maint_rdy_r1_reg_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,
    head_r_lcl_reg_3,
    head_r_lcl_reg_4,
    q_has_priority_r_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ,
    \compute_tail.tail_r_lcl_reg_1 ,
    req_bank_rdy_r_reg,
    req_priority_r,
    \rnk_config_strobe_r_reg[0] ,
    \rnk_config_strobe_r_reg[0]_0 ,
    \grant_r[3]_i_12 ,
    \grant_r[3]_i_12_0 ,
    \grant_r[3]_i_12_1 ,
    \grant_r[3]_i_12_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    accept_internal_r,
    app_en_r2,
    \q_entry_r_reg[0]_1 ,
    \q_entry_r_reg[0]_2 ,
    rb_hit_busies_r,
    pre_wait_r,
    q_has_priority_r_reg_2,
    was_priority,
    auto_pre_r_lcl_reg_3,
    ras_timer_zero_r,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_3 ,
    \ras_timer_r_reg[0]_4 ,
    \ras_timer_r_reg[0]_5 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 ,
    q_entry_ns,
    \q_entry_r_reg[0]_3 ,
    \q_entry_r_reg[0]_4 ,
    \order_q_r_reg[1]_3 ,
    \order_q_r_reg[0]_1 );
  output [0:0]idle_r_lcl_reg_0;
  output [0:0]E;
  output pass_open_bank_r;
  output pass_open_bank_ns;
  output q_has_rd;
  output pass_open_bank_r_lcl_reg_0;
  output wait_for_maint_r_lcl_reg_0;
  output [0:0]head_r;
  output ordered_r_lcl;
  output auto_pre_r_lcl_reg_0;
  output pre_bm_end_r_reg_0;
  output idle_r_lcl_reg_1;
  output idle_r_lcl_reg_2;
  output [0:0]D;
  output head_r_lcl_reg_0;
  output [1:0]\q_entry_r_reg[0]_0 ;
  output act_wait_ns;
  output \grant_r_reg[1] ;
  output \maint_controller.maint_rdy ;
  output idle_r_lcl_reg_3;
  output pass_open_bank_r_lcl_reg_1;
  output \q_entry_r_reg[1]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  output pre_bm_end_r_reg_1;
  output \order_q_r_reg[0]_0 ;
  output \order_q_r_reg[1]_0 ;
  output req_bank_rdy_ns;
  output \order_q_r_reg[1]_1 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  output pre_passing_open_bank_r_reg_0;
  output [0:0]bm_end;
  output act_wait_r_lcl_reg;
  input CLK;
  input pre_bm_end_ns;
  input pre_passing_open_bank_ns;
  input wait_for_maint_r_lcl_reg_1;
  input wait_for_maint_r_lcl_reg_2;
  input [0:0]SR;
  input ordered_r_lcl_reg_0;
  input head_r_lcl_reg_1;
  input head_r_lcl_reg_2;
  input pass_open_bank_r_lcl_reg_2;
  input \compute_tail.tail_r_lcl_reg_0 ;
  input pass_open_bank_r_lcl_reg_3;
  input auto_pre_r_lcl_reg_1;
  input [0:0]Q;
  input auto_pre_r_lcl_reg_2;
  input [2:0]idle_r;
  input \order_q_r_reg[1]_2 ;
  input [0:0]\maint_controller.maint_hit_busies_r_reg[1] ;
  input \maint_controller.maint_hit_busies_r_reg[1]_0 ;
  input q_has_rd_r_reg_0;
  input was_wr;
  input q_has_priority_r_reg_0;
  input bm_end_r1_reg;
  input [0:0]req_wr_r;
  input \ras_timer_r_reg[1] ;
  input \ras_timer_r_reg[0] ;
  input bm_end_r1_0;
  input [0:0]act_wait_r_lcl_reg_0;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \ras_timer_r_reg[0]_2 ;
  input \maint_controller.maint_rdy_r1_reg ;
  input [2:0]\maint_controller.maint_rdy_r1_reg_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  input head_r_lcl_reg_3;
  input head_r_lcl_reg_4;
  input q_has_priority_r_reg_1;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  input [1:0]\compute_tail.tail_r_lcl_reg_1 ;
  input req_bank_rdy_r_reg;
  input req_priority_r;
  input \rnk_config_strobe_r_reg[0] ;
  input \rnk_config_strobe_r_reg[0]_0 ;
  input \grant_r[3]_i_12 ;
  input \grant_r[3]_i_12_0 ;
  input \grant_r[3]_i_12_1 ;
  input \grant_r[3]_i_12_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  input accept_internal_r;
  input app_en_r2;
  input \q_entry_r_reg[0]_1 ;
  input \q_entry_r_reg[0]_2 ;
  input [0:0]rb_hit_busies_r;
  input pre_wait_r;
  input [0:0]q_has_priority_r_reg_2;
  input was_priority;
  input auto_pre_r_lcl_reg_3;
  input ras_timer_zero_r;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_3 ;
  input \ras_timer_r_reg[0]_4 ;
  input \ras_timer_r_reg[0]_5 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 ;
  input [0:0]q_entry_ns;
  input \q_entry_r_reg[0]_3 ;
  input \q_entry_r_reg[0]_4 ;
  input \order_q_r_reg[1]_3 ;
  input \order_q_r_reg[0]_1 ;

  wire CLK;
  wire [0:0]D;
  wire [0:0]E;
  wire [0:0]Q;
  wire [0:0]SR;
  wire accept_internal_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg;
  wire [0:0]act_wait_r_lcl_reg_0;
  wire app_en_r2;
  wire auto_pre_r_lcl_i_1__2_n_0;
  wire auto_pre_r_lcl_i_2__2_n_0;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg_3;
  wire [0:0]bm_end;
  wire bm_end_r1_0;
  wire bm_end_r1_reg;
  wire \compute_tail.tail_r_lcl_i_1__0_n_0 ;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire [1:0]\compute_tail.tail_r_lcl_reg_1 ;
  wire \grant_r[3]_i_12 ;
  wire \grant_r[3]_i_12_0 ;
  wire \grant_r[3]_i_12_1 ;
  wire \grant_r[3]_i_12_2 ;
  wire \grant_r_reg[1] ;
  wire [0:0]head_r;
  wire head_r_lcl_i_1__0_n_0;
  wire head_r_lcl_i_2__0_n_0;
  wire head_r_lcl_i_3__1_n_0;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire head_r_lcl_reg_3;
  wire head_r_lcl_reg_4;
  wire [2:0]idle_r;
  wire [0:0]idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire idle_r_lcl_reg_3;
  wire [0:0]\maint_controller.maint_hit_busies_r_reg[1] ;
  wire \maint_controller.maint_hit_busies_r_reg[1]_0 ;
  wire \maint_controller.maint_rdy ;
  wire \maint_controller.maint_rdy_r1_reg ;
  wire [2:0]\maint_controller.maint_rdy_r1_reg_0 ;
  wire [1:0]order_q_r;
  wire \order_q_r[0]_i_1_n_0 ;
  wire \order_q_r[1]_i_1_n_0 ;
  wire \order_q_r_reg[0]_0 ;
  wire \order_q_r_reg[0]_1 ;
  wire \order_q_r_reg[1]_0 ;
  wire \order_q_r_reg[1]_1 ;
  wire \order_q_r_reg[1]_2 ;
  wire \order_q_r_reg[1]_3 ;
  wire ordered_r_lcl;
  wire ordered_r_lcl_reg_0;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire pass_open_bank_r_lcl_reg_3;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg_0;
  wire pre_bm_end_r_reg_1;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_wait_r;
  wire [0:0]q_entry_ns;
  wire \q_entry_r[0]_i_1_n_0 ;
  wire \q_entry_r[1]_i_1_n_0 ;
  wire \q_entry_r[1]_i_3__0_n_0 ;
  wire [1:0]\q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire \q_entry_r_reg[0]_3 ;
  wire \q_entry_r_reg[0]_4 ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg_n_0_[0] ;
  wire \q_entry_r_reg_n_0_[1] ;
  wire q_has_priority;
  wire q_has_priority_r_i_1__2_n_0;
  wire q_has_priority_r_reg_0;
  wire q_has_priority_r_reg_1;
  wire [0:0]q_has_priority_r_reg_2;
  wire q_has_rd;
  wire q_has_rd_r_i_1__2_n_0;
  wire q_has_rd_r_reg_0;
  wire \ras_timer_r[0]_i_2__1_n_0 ;
  wire \ras_timer_r[1]_i_2__0_n_0 ;
  wire \ras_timer_r[1]_i_3__1_n_0 ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[0]_5 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_2_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire [0:0]rb_hit_busies_r;
  wire [4:2]rb_hit_busies_r_0;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire req_priority_r;
  wire [0:0]req_wr_r;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire wait_for_maint_r_lcl_reg_2;
  wire was_priority;
  wire was_wr;

  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF44F4)) 
    act_wait_r_lcl_i_1__1
       (.I0(\grant_r_reg[1] ),
        .I1(auto_pre_r_lcl_reg_2),
        .I2(pass_open_bank_r),
        .I3(pre_bm_end_r_reg_0),
        .I4(\order_q_r_reg[1]_2 ),
        .I5(bm_end_r1_0),
        .O(act_wait_ns));
  LUT6 #(
    .INIT(64'h888F888888888888)) 
    act_wait_r_lcl_i_2__1
       (.I0(act_wait_r_lcl_reg_0),
        .I1(auto_pre_r_lcl_reg_2),
        .I2(idle_r_lcl_reg_0),
        .I3(\q_entry_r_reg_n_0_[1] ),
        .I4(\q_entry_r_reg_n_0_[0] ),
        .I5(\ras_timer_r[1]_i_2__0_n_0 ),
        .O(\grant_r_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair590" *) 
  LUT5 #(
    .INIT(32'h40555555)) 
    act_wait_r_lcl_i_3__0
       (.I0(pre_bm_end_r),
        .I1(req_wr_r),
        .I2(bm_end_r1_reg),
        .I3(Q),
        .I4(pass_open_bank_r),
        .O(pre_bm_end_r_reg_0));
  LUT5 #(
    .INIT(32'h40555555)) 
    act_wait_r_lcl_i_4
       (.I0(pre_passing_open_bank_r),
        .I1(req_wr_r),
        .I2(bm_end_r1_reg),
        .I3(Q),
        .I4(pass_open_bank_r),
        .O(pre_passing_open_bank_r_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF11110010)) 
    auto_pre_r_lcl_i_1__2
       (.I0(pass_open_bank_r_lcl_reg_3),
        .I1(auto_pre_r_lcl_i_2__2_n_0),
        .I2(auto_pre_r_lcl_reg_1),
        .I3(Q),
        .I4(auto_pre_r_lcl_reg_2),
        .I5(auto_pre_r_lcl_reg_0),
        .O(auto_pre_r_lcl_i_1__2_n_0));
  LUT6 #(
    .INIT(64'h57777777FFFFFFFF)) 
    auto_pre_r_lcl_i_2__2
       (.I0(tail_r),
        .I1(\q_entry_r_reg[0]_2 ),
        .I2(auto_pre_r_lcl_reg_3),
        .I3(app_en_r2),
        .I4(\q_entry_r_reg[0]_1 ),
        .I5(q_has_priority_r_reg_2),
        .O(auto_pre_r_lcl_i_2__2_n_0));
  FDRE auto_pre_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(auto_pre_r_lcl_i_1__2_n_0),
        .Q(auto_pre_r_lcl_reg_0),
        .R(pass_open_bank_r_lcl_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair590" *) 
  LUT5 #(
    .INIT(32'hFFFF0888)) 
    bm_end_r1_i_1__2
       (.I0(pass_open_bank_r),
        .I1(Q),
        .I2(bm_end_r1_reg),
        .I3(req_wr_r),
        .I4(pre_bm_end_r),
        .O(bm_end));
  LUT6 #(
    .INIT(64'hDFDFCCCFDDDDCCCC)) 
    \compute_tail.tail_r_lcl_i_1__0 
       (.I0(pre_bm_end_r_reg_0),
        .I1(idle_r_lcl_reg_1),
        .I2(pass_open_bank_r_lcl_reg_2),
        .I3(idle_r_lcl_reg_0),
        .I4(\compute_tail.tail_r_lcl_reg_0 ),
        .I5(tail_r),
        .O(\compute_tail.tail_r_lcl_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h08)) 
    \compute_tail.tail_r_lcl_i_2 
       (.I0(pre_bm_end_r_reg_0),
        .I1(head_r_lcl_reg_2),
        .I2(\compute_tail.tail_r_lcl_reg_1 [1]),
        .O(pre_bm_end_r_reg_1));
  FDRE #(
    .INIT(1'b1)) 
    \compute_tail.tail_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\compute_tail.tail_r_lcl_i_1__0_n_0 ),
        .Q(tail_r),
        .R(SR));
  LUT5 #(
    .INIT(32'hF2F2F2FF)) 
    demand_priority_r_i_2__1
       (.I0(order_q_r[0]),
        .I1(req_bank_rdy_r_reg),
        .I2(order_q_r[1]),
        .I3(q_has_priority),
        .I4(req_priority_r),
        .O(\order_q_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \grant_r[3]_i_19 
       (.I0(order_q_r[1]),
        .I1(\grant_r[3]_i_12 ),
        .I2(\grant_r[3]_i_12_0 ),
        .I3(\grant_r[3]_i_12_1 ),
        .I4(\grant_r[3]_i_12_2 ),
        .I5(order_q_r[0]),
        .O(\order_q_r_reg[1]_1 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA00808080)) 
    \grant_r[3]_i_24 
       (.I0(rb_hit_busies_r),
        .I1(pass_open_bank_r),
        .I2(Q),
        .I3(bm_end_r1_reg),
        .I4(req_wr_r),
        .I5(pre_passing_open_bank_r),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ));
  LUT6 #(
    .INIT(64'h0000000045000000)) 
    \grant_r[3]_i_5__0 
       (.I0(order_q_r[1]),
        .I1(req_bank_rdy_r_reg),
        .I2(order_q_r[0]),
        .I3(auto_pre_r_lcl_reg_1),
        .I4(\rnk_config_strobe_r_reg[0] ),
        .I5(\rnk_config_strobe_r_reg[0]_0 ),
        .O(\order_q_r_reg[1]_0 ));
  LUT5 #(
    .INIT(32'hFFDFFFFF)) 
    \grant_r[3]_i_7 
       (.I0(auto_pre_r_lcl_reg_2),
        .I1(idle_r_lcl_reg_0),
        .I2(head_r),
        .I3(wait_for_maint_r_lcl_reg_0),
        .I4(ras_timer_zero_r),
        .O(act_wait_r_lcl_reg));
  LUT6 #(
    .INIT(64'hB888FFFFB8880000)) 
    head_r_lcl_i_1__0
       (.I0(head_r_lcl_i_2__0_n_0),
        .I1(pre_bm_end_r_reg_0),
        .I2(head_r_lcl_reg_1),
        .I3(head_r_lcl_reg_2),
        .I4(\q_entry_r[1]_i_3__0_n_0 ),
        .I5(head_r),
        .O(head_r_lcl_i_1__0_n_0));
  LUT6 #(
    .INIT(64'h00000000AA2A2A2A)) 
    head_r_lcl_i_2
       (.I0(head_r_lcl_reg_2),
        .I1(pass_open_bank_r),
        .I2(Q),
        .I3(bm_end_r1_reg),
        .I4(req_wr_r),
        .I5(pre_bm_end_r),
        .O(pass_open_bank_r_lcl_reg_1));
  LUT6 #(
    .INIT(64'h2020202F202F2020)) 
    head_r_lcl_i_2__0
       (.I0(\q_entry_r_reg_n_0_[0] ),
        .I1(\q_entry_r_reg_n_0_[1] ),
        .I2(head_r_lcl_i_3__1_n_0),
        .I3(head_r_lcl_reg_3),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I5(head_r_lcl_reg_4),
        .O(head_r_lcl_i_2__0_n_0));
  LUT5 #(
    .INIT(32'hDD1D1111)) 
    head_r_lcl_i_3__1
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I1(idle_r_lcl_reg_0),
        .I2(head_r),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ),
        .I4(q_has_priority_r_reg_1),
        .O(head_r_lcl_i_3__1_n_0));
  FDRE head_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(head_r_lcl_i_1__0_n_0),
        .Q(head_r),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair591" *) 
  LUT1 #(
    .INIT(2'h1)) 
    idle_r_lcl_i_1__0
       (.I0(head_r_lcl_reg_0),
        .O(E));
  LUT5 #(
    .INIT(32'h00004F00)) 
    idle_r_lcl_i_2__0
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ),
        .I1(head_r),
        .I2(idle_r_lcl_reg_0),
        .I3(pre_bm_end_r_reg_0),
        .I4(\order_q_r_reg[1]_2 ),
        .O(head_r_lcl_reg_0));
  FDRE idle_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(E),
        .Q(idle_r_lcl_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair591" *) 
  LUT5 #(
    .INIT(32'h20222020)) 
    \maint_controller.maint_hit_busies_r[1]_i_1 
       (.I0(pre_bm_end_r_reg_0),
        .I1(\order_q_r_reg[1]_2 ),
        .I2(\maint_controller.maint_hit_busies_r_reg[1] ),
        .I3(\maint_controller.maint_hit_busies_r_reg[1]_0 ),
        .I4(head_r_lcl_reg_0),
        .O(D));
  LUT5 #(
    .INIT(32'h00000001)) 
    \maint_controller.maint_rdy_r1_i_1 
       (.I0(D),
        .I1(\maint_controller.maint_rdy_r1_reg ),
        .I2(\maint_controller.maint_rdy_r1_reg_0 [1]),
        .I3(\maint_controller.maint_rdy_r1_reg_0 [2]),
        .I4(\maint_controller.maint_rdy_r1_reg_0 [0]),
        .O(\maint_controller.maint_rdy ));
  LUT6 #(
    .INIT(64'h31553000315530CC)) 
    \order_q_r[0]_i_1 
       (.I0(\order_q_r_reg[0]_1 ),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_bank_rdy_r_reg),
        .I4(idle_r_lcl_reg_1),
        .I5(\order_q_r_reg[1]_2 ),
        .O(\order_q_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hC2AAC000C2AAC0F0)) 
    \order_q_r[1]_i_1 
       (.I0(\order_q_r_reg[1]_3 ),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_bank_rdy_r_reg),
        .I4(idle_r_lcl_reg_1),
        .I5(\order_q_r_reg[1]_2 ),
        .O(\order_q_r[1]_i_1_n_0 ));
  FDRE \order_q_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[0]_i_1_n_0 ),
        .Q(order_q_r[0]),
        .R(1'b0));
  FDRE \order_q_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[1]_i_1_n_0 ),
        .Q(order_q_r[1]),
        .R(1'b0));
  FDRE ordered_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ordered_r_lcl_reg_0),
        .Q(ordered_r_lcl),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4444544444444444)) 
    pass_open_bank_r_lcl_i_1__2
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(pass_open_bank_r),
        .I2(tail_r),
        .I3(pass_open_bank_r_lcl_reg_2),
        .I4(pre_wait_r),
        .I5(pass_open_bank_r_lcl_reg_3),
        .O(pass_open_bank_ns));
  FDRE pass_open_bank_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pass_open_bank_ns),
        .Q(pass_open_bank_r),
        .R(1'b0));
  FDRE pre_bm_end_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_bm_end_ns),
        .Q(pre_bm_end_r),
        .R(1'b0));
  FDRE pre_passing_open_bank_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_passing_open_bank_ns),
        .Q(pre_passing_open_bank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8F80FFFFBFB00000)) 
    \q_entry_r[0]_i_1 
       (.I0(\q_entry_r_reg[0]_3 ),
        .I1(idle_r_lcl_reg_1),
        .I2(pre_bm_end_r_reg_0),
        .I3(\q_entry_r_reg[0]_4 ),
        .I4(\q_entry_r[1]_i_3__0_n_0 ),
        .I5(\q_entry_r_reg_n_0_[0] ),
        .O(\q_entry_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8080808080000000)) 
    \q_entry_r[0]_i_3__0 
       (.I0(idle_r_lcl_reg_0),
        .I1(head_r),
        .I2(accept_internal_r),
        .I3(app_en_r2),
        .I4(\q_entry_r_reg[0]_1 ),
        .I5(\q_entry_r_reg[0]_2 ),
        .O(idle_r_lcl_reg_1));
  LUT3 #(
    .INIT(8'hB8)) 
    \q_entry_r[1]_i_1 
       (.I0(q_entry_ns),
        .I1(\q_entry_r[1]_i_3__0_n_0 ),
        .I2(\q_entry_r_reg_n_0_[1] ),
        .O(\q_entry_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8EE7E771E7717118)) 
    \q_entry_r[1]_i_2__2 
       (.I0(pre_bm_end_r_reg_0),
        .I1(head_r_lcl_reg_2),
        .I2(idle_r[1]),
        .I3(idle_r_lcl_reg_0),
        .I4(idle_r[2]),
        .I5(idle_r[0]),
        .O(idle_r_lcl_reg_2));
  LUT6 #(
    .INIT(64'hAF3FAF3FFF3FAF3F)) 
    \q_entry_r[1]_i_3__0 
       (.I0(q_has_priority_r_reg_1),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I2(pre_bm_end_r_reg_0),
        .I3(idle_r_lcl_reg_0),
        .I4(head_r),
        .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ),
        .O(\q_entry_r[1]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hA9FFA900A900A9FF)) 
    \q_entry_r[1]_i_4__2 
       (.I0(head_r_lcl_reg_3),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I2(head_r_lcl_reg_4),
        .I3(idle_r_lcl_reg_1),
        .I4(\q_entry_r_reg_n_0_[1] ),
        .I5(\q_entry_r_reg_n_0_[0] ),
        .O(\q_entry_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h8117E881E8817EE8)) 
    \q_entry_r[1]_i_6__0 
       (.I0(idle_r[1]),
        .I1(idle_r_lcl_reg_0),
        .I2(idle_r[2]),
        .I3(idle_r[0]),
        .I4(pre_bm_end_r_reg_0),
        .I5(head_r_lcl_reg_2),
        .O(idle_r_lcl_reg_3));
  LUT6 #(
    .INIT(64'h00000DDD0DDD0DDD)) 
    \q_entry_r[1]_i_6__1 
       (.I0(rb_hit_busies_r_0[4]),
        .I1(head_r_lcl_reg_2),
        .I2(rb_hit_busies_r_0[3]),
        .I3(\compute_tail.tail_r_lcl_reg_1 [1]),
        .I4(rb_hit_busies_r_0[2]),
        .I5(\compute_tail.tail_r_lcl_reg_1 [0]),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ));
  FDSE \q_entry_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[0]_i_1_n_0 ),
        .Q(\q_entry_r_reg_n_0_[0] ),
        .S(SR));
  FDRE \q_entry_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[1]_i_1_n_0 ),
        .Q(\q_entry_r_reg_n_0_[1] ),
        .R(SR));
  LUT4 #(
    .INIT(16'hEAAA)) 
    q_has_priority_r_i_1__2
       (.I0(q_has_priority),
        .I1(q_has_priority_r_reg_2),
        .I2(q_has_priority_r_reg_1),
        .I3(was_priority),
        .O(q_has_priority_r_i_1__2_n_0));
  FDRE q_has_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_priority_r_i_1__2_n_0),
        .Q(q_has_priority),
        .R(pass_open_bank_r_lcl_reg_0));
  LUT6 #(
    .INIT(64'h4445555544454445)) 
    q_has_rd_r_i_1__2
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(q_has_rd),
        .I2(q_has_rd_r_reg_0),
        .I3(idle_r_lcl_reg_0),
        .I4(was_wr),
        .I5(pass_open_bank_r_lcl_reg_2),
        .O(q_has_rd_r_i_1__2_n_0));
  FDRE q_has_rd_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_rd_r_i_1__2_n_0),
        .Q(q_has_rd),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFF700080000)) 
    \ras_timer_r[0]_i_1__1 
       (.I0(\ras_timer_r[1]_i_2__0_n_0 ),
        .I1(\q_entry_r_reg_n_0_[0] ),
        .I2(\q_entry_r_reg_n_0_[1] ),
        .I3(idle_r_lcl_reg_0),
        .I4(\ras_timer_r[0]_i_2__1_n_0 ),
        .I5(\ras_timer_r_reg[0] ),
        .O(\q_entry_r_reg[0]_0 [0]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \ras_timer_r[0]_i_2__1 
       (.I0(\ras_timer_r_reg[0]_3 ),
        .I1(rb_hit_busies_r_0[4]),
        .I2(\ras_timer_r_reg[0]_4 ),
        .I3(rb_hit_busies_r_0[3]),
        .I4(rb_hit_busies_r_0[2]),
        .I5(\ras_timer_r_reg[0]_5 ),
        .O(\ras_timer_r[0]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFF700080000)) 
    \ras_timer_r[1]_i_1__1 
       (.I0(\ras_timer_r[1]_i_2__0_n_0 ),
        .I1(\q_entry_r_reg_n_0_[0] ),
        .I2(\q_entry_r_reg_n_0_[1] ),
        .I3(idle_r_lcl_reg_0),
        .I4(\ras_timer_r[1]_i_3__1_n_0 ),
        .I5(\ras_timer_r_reg[1] ),
        .O(\q_entry_r_reg[0]_0 [1]));
  LUT6 #(
    .INIT(64'h44F444F4FFFF44F4)) 
    \ras_timer_r[1]_i_2__0 
       (.I0(\ras_timer_r_reg[0]_0 ),
        .I1(rb_hit_busies_r_0[4]),
        .I2(rb_hit_busies_r_0[3]),
        .I3(\ras_timer_r_reg[0]_1 ),
        .I4(rb_hit_busies_r_0[2]),
        .I5(\ras_timer_r_reg[0]_2 ),
        .O(\ras_timer_r[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hBBBB8888B888B888)) 
    \ras_timer_r[1]_i_3__1 
       (.I0(\ras_timer_r_reg[1]_0 ),
        .I1(rb_hit_busies_r_0[4]),
        .I2(rb_hit_busies_r_0[2]),
        .I3(\ras_timer_r_reg[1]_1 ),
        .I4(\ras_timer_r_reg[1]_2 ),
        .I5(rb_hit_busies_r_0[3]),
        .O(\ras_timer_r[1]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAEAEAEA)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1 
       (.I0(q_has_priority_r_reg_0),
        .I1(pass_open_bank_r),
        .I2(Q),
        .I3(bm_end_r1_reg),
        .I4(req_wr_r),
        .I5(pre_bm_end_r),
        .O(pass_open_bank_r_lcl_reg_0));
  LUT3 #(
    .INIT(8'hB8)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1 
       (.I0(rb_hit_busies_r_0[2]),
        .I1(head_r_lcl_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1 
       (.I0(rb_hit_busies_r_0[3]),
        .I1(head_r_lcl_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_2 
       (.I0(rb_hit_busies_r_0[4]),
        .I1(head_r_lcl_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1_n_0 ),
        .Q(rb_hit_busies_r_0[2]),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1_n_0 ),
        .Q(rb_hit_busies_r_0[3]),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_2_n_0 ),
        .Q(rb_hit_busies_r_0[4]),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 ));
  LUT4 #(
    .INIT(16'h00A2)) 
    req_bank_rdy_r_i_1__1
       (.I0(auto_pre_r_lcl_reg_1),
        .I1(order_q_r[0]),
        .I2(req_bank_rdy_r_reg),
        .I3(order_q_r[1]),
        .O(req_bank_rdy_ns));
  FDRE wait_for_maint_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wait_for_maint_r_lcl_reg_2),
        .Q(wait_for_maint_r_lcl_reg_0),
        .R(wait_for_maint_r_lcl_reg_1));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_queue" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_queue__parameterized1
   (idle_r_lcl_reg_0,
    E,
    pass_open_bank_r,
    pass_open_bank_ns,
    q_has_rd,
    pass_open_bank_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_0,
    head_r,
    ordered_r_lcl_reg_0,
    auto_pre_r_lcl_reg_0,
    pre_bm_end_r_reg_0,
    idle_r_lcl_reg_1,
    pre_bm_end_r_reg_1,
    pre_bm_end_r_reg_2,
    D,
    head_r_lcl_reg_0,
    \q_entry_r_reg[0]_0 ,
    act_wait_ns,
    \grant_r_reg[2] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    rnk_config_strobe_ns,
    \order_q_r_reg[1]_0 ,
    \order_q_r_reg[0]_0 ,
    req_bank_rdy_ns,
    \order_q_r_reg[1]_1 ,
    pre_bm_end_r_reg_3,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ,
    pre_passing_open_bank_r_reg_0,
    act_wait_r_lcl_reg,
    CLK,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    wait_for_maint_r_lcl_reg_1,
    wait_for_maint_r_lcl_reg_2,
    SR,
    ordered_r_lcl_reg_1,
    head_r_lcl_reg_1,
    head_r_lcl_reg_2,
    \compute_tail.tail_r_lcl_reg_0 ,
    pass_open_bank_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_2,
    col_wait_r,
    Q,
    auto_pre_r_lcl_reg_1,
    \compute_tail.tail_r_lcl_reg_1 ,
    \compute_tail.tail_r_lcl_reg_2 ,
    \compute_tail.tail_r_lcl_reg_3 ,
    \order_q_r_reg[1]_2 ,
    \maint_controller.maint_hit_busies_r_reg[2] ,
    \maint_controller.maint_hit_busies_r_reg[2]_0 ,
    q_has_rd_r_reg_0,
    was_wr,
    \ras_timer_r_reg[1] ,
    \ras_timer_r_reg[0] ,
    bm_end_r1_1,
    act_wait_r_lcl_reg_0,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \ras_timer_r_reg[0]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    \q_entry_r_reg[1]_0 ,
    head_r_lcl_reg_3,
    head_r_lcl_reg_4,
    q_has_priority_r_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,
    \rnk_config_strobe_r_reg[0] ,
    \rnk_config_strobe_r_reg[0]_0 ,
    \rnk_config_strobe_r_reg[0]_1 ,
    req_bank_rdy_r_reg,
    req_priority_r,
    \rnk_config_strobe_r_reg[0]_2 ,
    \rnk_config_strobe_r_reg[0]_3 ,
    \grant_r[3]_i_13 ,
    \grant_r[3]_i_13_0 ,
    \grant_r[3]_i_13_1 ,
    \grant_r[3]_i_13_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,
    accept_internal_r,
    app_en_r2,
    \q_entry_r_reg[0]_1 ,
    \q_entry_r_reg[0]_2 ,
    rb_hit_busies_r,
    bm_end_r1_reg,
    req_wr_r,
    pre_wait_r,
    auto_pre_r_lcl_reg_2,
    rb_hit_busy_r,
    was_priority,
    auto_pre_r_lcl_reg_3,
    ras_timer_zero_r,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_3 ,
    \ras_timer_r_reg[0]_4 ,
    \ras_timer_r_reg[0]_5 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ,
    \q_entry_r_reg[1]_1 ,
    \q_entry_r_reg[0]_3 ,
    \q_entry_r_reg[0]_4 ,
    \order_q_r_reg[1]_3 ,
    \order_q_r_reg[0]_1 );
  output [0:0]idle_r_lcl_reg_0;
  output [0:0]E;
  output pass_open_bank_r;
  output pass_open_bank_ns;
  output q_has_rd;
  output pass_open_bank_r_lcl_reg_0;
  output wait_for_maint_r_lcl_reg_0;
  output [0:0]head_r;
  output ordered_r_lcl_reg_0;
  output auto_pre_r_lcl_reg_0;
  output pre_bm_end_r_reg_0;
  output idle_r_lcl_reg_1;
  output pre_bm_end_r_reg_1;
  output pre_bm_end_r_reg_2;
  output [0:0]D;
  output head_r_lcl_reg_0;
  output [1:0]\q_entry_r_reg[0]_0 ;
  output act_wait_ns;
  output \grant_r_reg[2] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  output rnk_config_strobe_ns;
  output \order_q_r_reg[1]_0 ;
  output \order_q_r_reg[0]_0 ;
  output req_bank_rdy_ns;
  output \order_q_r_reg[1]_1 ;
  output pre_bm_end_r_reg_3;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  output pre_passing_open_bank_r_reg_0;
  output act_wait_r_lcl_reg;
  input CLK;
  input pre_bm_end_ns;
  input pre_passing_open_bank_ns;
  input wait_for_maint_r_lcl_reg_1;
  input wait_for_maint_r_lcl_reg_2;
  input [0:0]SR;
  input ordered_r_lcl_reg_1;
  input head_r_lcl_reg_1;
  input head_r_lcl_reg_2;
  input \compute_tail.tail_r_lcl_reg_0 ;
  input pass_open_bank_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_2;
  input col_wait_r;
  input [0:0]Q;
  input auto_pre_r_lcl_reg_1;
  input \compute_tail.tail_r_lcl_reg_1 ;
  input \compute_tail.tail_r_lcl_reg_2 ;
  input [0:0]\compute_tail.tail_r_lcl_reg_3 ;
  input \order_q_r_reg[1]_2 ;
  input [0:0]\maint_controller.maint_hit_busies_r_reg[2] ;
  input \maint_controller.maint_hit_busies_r_reg[2]_0 ;
  input q_has_rd_r_reg_0;
  input was_wr;
  input \ras_timer_r_reg[1] ;
  input \ras_timer_r_reg[0] ;
  input bm_end_r1_1;
  input [0:0]act_wait_r_lcl_reg_0;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \ras_timer_r_reg[0]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  input \q_entry_r_reg[1]_0 ;
  input head_r_lcl_reg_3;
  input head_r_lcl_reg_4;
  input q_has_priority_r_reg_0;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  input \rnk_config_strobe_r_reg[0] ;
  input \rnk_config_strobe_r_reg[0]_0 ;
  input \rnk_config_strobe_r_reg[0]_1 ;
  input req_bank_rdy_r_reg;
  input req_priority_r;
  input \rnk_config_strobe_r_reg[0]_2 ;
  input \rnk_config_strobe_r_reg[0]_3 ;
  input \grant_r[3]_i_13 ;
  input \grant_r[3]_i_13_0 ;
  input \grant_r[3]_i_13_1 ;
  input \grant_r[3]_i_13_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  input accept_internal_r;
  input app_en_r2;
  input \q_entry_r_reg[0]_1 ;
  input \q_entry_r_reg[0]_2 ;
  input [0:0]rb_hit_busies_r;
  input bm_end_r1_reg;
  input [0:0]req_wr_r;
  input pre_wait_r;
  input auto_pre_r_lcl_reg_2;
  input [0:0]rb_hit_busy_r;
  input was_priority;
  input auto_pre_r_lcl_reg_3;
  input ras_timer_zero_r;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_3 ;
  input \ras_timer_r_reg[0]_4 ;
  input \ras_timer_r_reg[0]_5 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  input \q_entry_r_reg[1]_1 ;
  input \q_entry_r_reg[0]_3 ;
  input \q_entry_r_reg[0]_4 ;
  input \order_q_r_reg[1]_3 ;
  input \order_q_r_reg[0]_1 ;

  wire CLK;
  wire [0:0]D;
  wire [0:0]E;
  wire [0:0]Q;
  wire [0:0]SR;
  wire accept_internal_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg;
  wire [0:0]act_wait_r_lcl_reg_0;
  wire app_en_r2;
  wire auto_pre_r_lcl_i_1__1_n_0;
  wire auto_pre_r_lcl_i_2__1_n_0;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg_3;
  wire bm_end_r1_1;
  wire bm_end_r1_reg;
  wire col_wait_r;
  wire \compute_tail.tail_r_lcl_i_1__1_n_0 ;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire \compute_tail.tail_r_lcl_reg_1 ;
  wire \compute_tail.tail_r_lcl_reg_2 ;
  wire [0:0]\compute_tail.tail_r_lcl_reg_3 ;
  wire \grant_r[3]_i_13 ;
  wire \grant_r[3]_i_13_0 ;
  wire \grant_r[3]_i_13_1 ;
  wire \grant_r[3]_i_13_2 ;
  wire \grant_r_reg[2] ;
  wire [0:0]head_r;
  wire head_r_lcl_i_1__1_n_0;
  wire head_r_lcl_i_3__0_n_0;
  wire head_r_lcl_i_4__0_n_0;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire head_r_lcl_reg_3;
  wire head_r_lcl_reg_4;
  wire [0:0]idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire [0:0]\maint_controller.maint_hit_busies_r_reg[2] ;
  wire \maint_controller.maint_hit_busies_r_reg[2]_0 ;
  wire [1:0]order_q_r;
  wire \order_q_r[0]_i_1_n_0 ;
  wire \order_q_r[1]_i_1_n_0 ;
  wire \order_q_r_reg[0]_0 ;
  wire \order_q_r_reg[0]_1 ;
  wire \order_q_r_reg[1]_0 ;
  wire \order_q_r_reg[1]_1 ;
  wire \order_q_r_reg[1]_2 ;
  wire \order_q_r_reg[1]_3 ;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg_0;
  wire pre_bm_end_r_reg_1;
  wire pre_bm_end_r_reg_2;
  wire pre_bm_end_r_reg_3;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_wait_r;
  wire \q_entry_r[0]_i_1_n_0 ;
  wire \q_entry_r[1]_i_1_n_0 ;
  wire \q_entry_r[1]_i_4__1_n_0 ;
  wire \q_entry_r[1]_i_5__0_n_0 ;
  wire [1:0]\q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire \q_entry_r_reg[0]_3 ;
  wire \q_entry_r_reg[0]_4 ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire \q_entry_r_reg[1]_i_3_n_0 ;
  wire \q_entry_r_reg_n_0_[0] ;
  wire \q_entry_r_reg_n_0_[1] ;
  wire q_has_priority;
  wire q_has_priority_r_i_1__1_n_0;
  wire q_has_priority_r_reg_0;
  wire q_has_rd;
  wire q_has_rd_r_i_1__1_n_0;
  wire q_has_rd_r_reg_0;
  wire \ras_timer_r[0]_i_2__0_n_0 ;
  wire \ras_timer_r[1]_i_2_n_0 ;
  wire \ras_timer_r[1]_i_3__0_n_0 ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[0]_5 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  wire [0:0]rb_hit_busies_r;
  wire [5:3]rb_hit_busies_r_0;
  wire [0:0]rb_hit_busy_r;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire req_priority_r;
  wire [0:0]req_wr_r;
  wire rnk_config_strobe_ns;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire \rnk_config_strobe_r_reg[0]_1 ;
  wire \rnk_config_strobe_r_reg[0]_2 ;
  wire \rnk_config_strobe_r_reg[0]_3 ;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire wait_for_maint_r_lcl_reg_2;
  wire was_priority;
  wire was_wr;

  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF444)) 
    act_wait_r_lcl_i_1__0
       (.I0(\grant_r_reg[2] ),
        .I1(auto_pre_r_lcl_reg_1),
        .I2(pass_open_bank_r),
        .I3(pre_bm_end_r_reg_0),
        .I4(\order_q_r_reg[1]_2 ),
        .I5(bm_end_r1_1),
        .O(act_wait_ns));
  LUT6 #(
    .INIT(64'h888F888888888888)) 
    act_wait_r_lcl_i_2__0
       (.I0(act_wait_r_lcl_reg_0),
        .I1(auto_pre_r_lcl_reg_1),
        .I2(idle_r_lcl_reg_0),
        .I3(\q_entry_r_reg_n_0_[1] ),
        .I4(\q_entry_r_reg_n_0_[0] ),
        .I5(\ras_timer_r[1]_i_2_n_0 ),
        .O(\grant_r_reg[2] ));
  LUT6 #(
    .INIT(64'hAAAAAAAA00808080)) 
    act_wait_r_lcl_i_6
       (.I0(rb_hit_busies_r),
        .I1(pass_open_bank_r),
        .I2(Q),
        .I3(bm_end_r1_reg),
        .I4(req_wr_r),
        .I5(pre_passing_open_bank_r),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ));
  LUT6 #(
    .INIT(64'hFFFFFFFF11110010)) 
    auto_pre_r_lcl_i_1__1
       (.I0(pass_open_bank_r_lcl_reg_2),
        .I1(auto_pre_r_lcl_i_2__1_n_0),
        .I2(col_wait_r),
        .I3(Q),
        .I4(auto_pre_r_lcl_reg_1),
        .I5(auto_pre_r_lcl_reg_0),
        .O(auto_pre_r_lcl_i_1__1_n_0));
  LUT6 #(
    .INIT(64'h57777777FFFFFFFF)) 
    auto_pre_r_lcl_i_2__1
       (.I0(tail_r),
        .I1(\q_entry_r_reg[0]_2 ),
        .I2(auto_pre_r_lcl_reg_3),
        .I3(app_en_r2),
        .I4(\q_entry_r_reg[0]_1 ),
        .I5(rb_hit_busy_r),
        .O(auto_pre_r_lcl_i_2__1_n_0));
  FDRE auto_pre_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(auto_pre_r_lcl_i_1__1_n_0),
        .Q(auto_pre_r_lcl_reg_0),
        .R(pass_open_bank_r_lcl_reg_0));
  LUT5 #(
    .INIT(32'hBFAAAAAA)) 
    bm_end_r1_i_1__1
       (.I0(pre_bm_end_r),
        .I1(req_wr_r),
        .I2(bm_end_r1_reg),
        .I3(Q),
        .I4(pass_open_bank_r),
        .O(pre_bm_end_r_reg_0));
  LUT6 #(
    .INIT(64'hEECCFFCFEECCEECC)) 
    \compute_tail.tail_r_lcl_i_1__1 
       (.I0(pre_bm_end_r_reg_0),
        .I1(idle_r_lcl_reg_1),
        .I2(idle_r_lcl_reg_0),
        .I3(\compute_tail.tail_r_lcl_reg_0 ),
        .I4(pass_open_bank_r_lcl_reg_1),
        .I5(tail_r),
        .O(\compute_tail.tail_r_lcl_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair597" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \compute_tail.tail_r_lcl_i_2__0 
       (.I0(pre_bm_end_r_reg_0),
        .I1(\compute_tail.tail_r_lcl_reg_1 ),
        .I2(\compute_tail.tail_r_lcl_reg_3 ),
        .O(pre_bm_end_r_reg_3));
  LUT3 #(
    .INIT(8'h04)) 
    \compute_tail.tail_r_lcl_i_2__1 
       (.I0(pre_bm_end_r_reg_0),
        .I1(\compute_tail.tail_r_lcl_reg_2 ),
        .I2(\compute_tail.tail_r_lcl_reg_3 ),
        .O(pre_bm_end_r_reg_2));
  FDRE #(
    .INIT(1'b1)) 
    \compute_tail.tail_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\compute_tail.tail_r_lcl_i_1__1_n_0 ),
        .Q(tail_r),
        .R(SR));
  LUT5 #(
    .INIT(32'hF2F2F2FF)) 
    demand_priority_r_i_2__0
       (.I0(order_q_r[0]),
        .I1(req_bank_rdy_r_reg),
        .I2(order_q_r[1]),
        .I3(q_has_priority),
        .I4(req_priority_r),
        .O(\order_q_r_reg[0]_0 ));
  LUT5 #(
    .INIT(32'hFFDFFFFF)) 
    \grant_r[3]_i_12__0 
       (.I0(auto_pre_r_lcl_reg_1),
        .I1(idle_r_lcl_reg_0),
        .I2(head_r),
        .I3(wait_for_maint_r_lcl_reg_0),
        .I4(ras_timer_zero_r),
        .O(act_wait_r_lcl_reg));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \grant_r[3]_i_22 
       (.I0(order_q_r[1]),
        .I1(\grant_r[3]_i_13 ),
        .I2(\grant_r[3]_i_13_0 ),
        .I3(\grant_r[3]_i_13_1 ),
        .I4(\grant_r[3]_i_13_2 ),
        .I5(order_q_r[0]),
        .O(\order_q_r_reg[1]_1 ));
  LUT6 #(
    .INIT(64'hFDFFFDFDFFFFFFFF)) 
    \grant_r[3]_i_4__0 
       (.I0(\rnk_config_strobe_r_reg[0]_2 ),
        .I1(\rnk_config_strobe_r_reg[0]_3 ),
        .I2(order_q_r[1]),
        .I3(req_bank_rdy_r_reg),
        .I4(order_q_r[0]),
        .I5(col_wait_r),
        .O(\order_q_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h8F80FFFF8F800000)) 
    head_r_lcl_i_1__1
       (.I0(head_r_lcl_reg_1),
        .I1(head_r_lcl_reg_2),
        .I2(pre_bm_end_r_reg_0),
        .I3(head_r_lcl_i_3__0_n_0),
        .I4(\q_entry_r[1]_i_4__1_n_0 ),
        .I5(head_r),
        .O(head_r_lcl_i_1__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair597" *) 
  LUT3 #(
    .INIT(8'h40)) 
    head_r_lcl_i_2__2
       (.I0(pre_bm_end_r_reg_0),
        .I1(\compute_tail.tail_r_lcl_reg_1 ),
        .I2(\compute_tail.tail_r_lcl_reg_2 ),
        .O(pre_bm_end_r_reg_1));
  LUT6 #(
    .INIT(64'h2020202F202F2020)) 
    head_r_lcl_i_3__0
       (.I0(\q_entry_r_reg_n_0_[0] ),
        .I1(\q_entry_r_reg_n_0_[1] ),
        .I2(head_r_lcl_i_4__0_n_0),
        .I3(head_r_lcl_reg_3),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I5(head_r_lcl_reg_4),
        .O(head_r_lcl_i_3__0_n_0));
  LUT5 #(
    .INIT(32'hDD1D1111)) 
    head_r_lcl_i_4__0
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I1(idle_r_lcl_reg_0),
        .I2(head_r),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .I4(q_has_priority_r_reg_0),
        .O(head_r_lcl_i_4__0_n_0));
  FDRE head_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(head_r_lcl_i_1__1_n_0),
        .Q(head_r),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair596" *) 
  LUT1 #(
    .INIT(2'h1)) 
    idle_r_lcl_i_1__1
       (.I0(head_r_lcl_reg_0),
        .O(E));
  LUT5 #(
    .INIT(32'h0000004F)) 
    idle_r_lcl_i_2__1
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .I1(head_r),
        .I2(idle_r_lcl_reg_0),
        .I3(pre_bm_end_r_reg_0),
        .I4(\order_q_r_reg[1]_2 ),
        .O(head_r_lcl_reg_0));
  FDRE idle_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(E),
        .Q(idle_r_lcl_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair596" *) 
  LUT5 #(
    .INIT(32'h10111010)) 
    \maint_controller.maint_hit_busies_r[2]_i_1 
       (.I0(pre_bm_end_r_reg_0),
        .I1(\order_q_r_reg[1]_2 ),
        .I2(\maint_controller.maint_hit_busies_r_reg[2] ),
        .I3(\maint_controller.maint_hit_busies_r_reg[2]_0 ),
        .I4(head_r_lcl_reg_0),
        .O(D));
  LUT6 #(
    .INIT(64'h31553000315530CC)) 
    \order_q_r[0]_i_1 
       (.I0(\order_q_r_reg[0]_1 ),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_bank_rdy_r_reg),
        .I4(idle_r_lcl_reg_1),
        .I5(\order_q_r_reg[1]_2 ),
        .O(\order_q_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hC2AAC000C2AAC0F0)) 
    \order_q_r[1]_i_1 
       (.I0(\order_q_r_reg[1]_3 ),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_bank_rdy_r_reg),
        .I4(idle_r_lcl_reg_1),
        .I5(\order_q_r_reg[1]_2 ),
        .O(\order_q_r[1]_i_1_n_0 ));
  FDRE \order_q_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[0]_i_1_n_0 ),
        .Q(order_q_r[0]),
        .R(1'b0));
  FDRE \order_q_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[1]_i_1_n_0 ),
        .Q(order_q_r[1]),
        .R(1'b0));
  FDRE ordered_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ordered_r_lcl_reg_1),
        .Q(ordered_r_lcl_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4444544444444444)) 
    pass_open_bank_r_lcl_i_1__1
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(pass_open_bank_r),
        .I2(tail_r),
        .I3(pass_open_bank_r_lcl_reg_1),
        .I4(pre_wait_r),
        .I5(pass_open_bank_r_lcl_reg_2),
        .O(pass_open_bank_ns));
  FDRE pass_open_bank_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pass_open_bank_ns),
        .Q(pass_open_bank_r),
        .R(1'b0));
  FDRE pre_bm_end_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_bm_end_ns),
        .Q(pre_bm_end_r),
        .R(1'b0));
  FDRE pre_passing_open_bank_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_passing_open_bank_ns),
        .Q(pre_passing_open_bank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h5C50FFFF5F530000)) 
    \q_entry_r[0]_i_1 
       (.I0(\q_entry_r_reg[0]_3 ),
        .I1(idle_r_lcl_reg_1),
        .I2(pre_bm_end_r_reg_0),
        .I3(\q_entry_r_reg[0]_4 ),
        .I4(\q_entry_r[1]_i_4__1_n_0 ),
        .I5(\q_entry_r_reg_n_0_[0] ),
        .O(\q_entry_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8080808080000000)) 
    \q_entry_r[0]_i_3__1 
       (.I0(idle_r_lcl_reg_0),
        .I1(head_r),
        .I2(accept_internal_r),
        .I3(app_en_r2),
        .I4(\q_entry_r_reg[0]_1 ),
        .I5(\q_entry_r_reg[0]_2 ),
        .O(idle_r_lcl_reg_1));
  LUT6 #(
    .INIT(64'hA333FFFFA3330000)) 
    \q_entry_r[1]_i_1 
       (.I0(\q_entry_r_reg[1]_1 ),
        .I1(\q_entry_r_reg[1]_i_3_n_0 ),
        .I2(pre_bm_end_r_reg_0),
        .I3(q_has_priority_r_reg_0),
        .I4(\q_entry_r[1]_i_4__1_n_0 ),
        .I5(\q_entry_r_reg_n_0_[1] ),
        .O(\q_entry_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFAF3FAF3FFF3FAF3)) 
    \q_entry_r[1]_i_4__1 
       (.I0(q_has_priority_r_reg_0),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I2(pre_bm_end_r_reg_0),
        .I3(idle_r_lcl_reg_0),
        .I4(head_r),
        .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .O(\q_entry_r[1]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'h560056FF56FF5600)) 
    \q_entry_r[1]_i_5__0 
       (.I0(head_r_lcl_reg_3),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I2(head_r_lcl_reg_4),
        .I3(idle_r_lcl_reg_1),
        .I4(\q_entry_r_reg_n_0_[1] ),
        .I5(\q_entry_r_reg_n_0_[0] ),
        .O(\q_entry_r[1]_i_5__0_n_0 ));
  LUT6 #(
    .INIT(64'h7707770700007707)) 
    \q_entry_r[1]_i_7__0 
       (.I0(\compute_tail.tail_r_lcl_reg_3 ),
        .I1(rb_hit_busies_r_0[3]),
        .I2(rb_hit_busies_r_0[4]),
        .I3(\compute_tail.tail_r_lcl_reg_2 ),
        .I4(rb_hit_busies_r_0[5]),
        .I5(\compute_tail.tail_r_lcl_reg_1 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ));
  FDRE \q_entry_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[0]_i_1_n_0 ),
        .Q(\q_entry_r_reg_n_0_[0] ),
        .R(SR));
  FDSE \q_entry_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[1]_i_1_n_0 ),
        .Q(\q_entry_r_reg_n_0_[1] ),
        .S(SR));
  MUXF7 \q_entry_r_reg[1]_i_3 
       (.I0(\q_entry_r[1]_i_5__0_n_0 ),
        .I1(\q_entry_r_reg[1]_0 ),
        .O(\q_entry_r_reg[1]_i_3_n_0 ),
        .S(pre_bm_end_r_reg_0));
  LUT4 #(
    .INIT(16'hEAAA)) 
    q_has_priority_r_i_1__1
       (.I0(q_has_priority),
        .I1(rb_hit_busy_r),
        .I2(q_has_priority_r_reg_0),
        .I3(was_priority),
        .O(q_has_priority_r_i_1__1_n_0));
  FDRE q_has_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_priority_r_i_1__1_n_0),
        .Q(q_has_priority),
        .R(pass_open_bank_r_lcl_reg_0));
  LUT6 #(
    .INIT(64'h4445555544454445)) 
    q_has_rd_r_i_1__1
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(q_has_rd),
        .I2(q_has_rd_r_reg_0),
        .I3(idle_r_lcl_reg_0),
        .I4(was_wr),
        .I5(pass_open_bank_r_lcl_reg_1),
        .O(q_has_rd_r_i_1__1_n_0));
  FDRE q_has_rd_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_rd_r_i_1__1_n_0),
        .Q(q_has_rd),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFF700080000)) 
    \ras_timer_r[0]_i_1__0 
       (.I0(\ras_timer_r[1]_i_2_n_0 ),
        .I1(\q_entry_r_reg_n_0_[0] ),
        .I2(\q_entry_r_reg_n_0_[1] ),
        .I3(idle_r_lcl_reg_0),
        .I4(\ras_timer_r[0]_i_2__0_n_0 ),
        .I5(\ras_timer_r_reg[0] ),
        .O(\q_entry_r_reg[0]_0 [0]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \ras_timer_r[0]_i_2__0 
       (.I0(\ras_timer_r_reg[0]_3 ),
        .I1(rb_hit_busies_r_0[5]),
        .I2(\ras_timer_r_reg[0]_4 ),
        .I3(rb_hit_busies_r_0[4]),
        .I4(rb_hit_busies_r_0[3]),
        .I5(\ras_timer_r_reg[0]_5 ),
        .O(\ras_timer_r[0]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFF700080000)) 
    \ras_timer_r[1]_i_1__0 
       (.I0(\ras_timer_r[1]_i_2_n_0 ),
        .I1(\q_entry_r_reg_n_0_[0] ),
        .I2(\q_entry_r_reg_n_0_[1] ),
        .I3(idle_r_lcl_reg_0),
        .I4(\ras_timer_r[1]_i_3__0_n_0 ),
        .I5(\ras_timer_r_reg[1] ),
        .O(\q_entry_r_reg[0]_0 [1]));
  LUT6 #(
    .INIT(64'h44F444F4FFFF44F4)) 
    \ras_timer_r[1]_i_2 
       (.I0(\ras_timer_r_reg[0]_0 ),
        .I1(rb_hit_busies_r_0[3]),
        .I2(rb_hit_busies_r_0[4]),
        .I3(\ras_timer_r_reg[0]_1 ),
        .I4(rb_hit_busies_r_0[5]),
        .I5(\ras_timer_r_reg[0]_2 ),
        .O(\ras_timer_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBB8888B888B888)) 
    \ras_timer_r[1]_i_3__0 
       (.I0(\ras_timer_r_reg[1]_0 ),
        .I1(rb_hit_busies_r_0[5]),
        .I2(rb_hit_busies_r_0[3]),
        .I3(\ras_timer_r_reg[1]_1 ),
        .I4(\ras_timer_r_reg[1]_2 ),
        .I5(rb_hit_busies_r_0[4]),
        .O(\ras_timer_r[1]_i_3__0_n_0 ));
  LUT5 #(
    .INIT(32'h40555555)) 
    \ras_timer_r[1]_i_6 
       (.I0(pre_passing_open_bank_r),
        .I1(req_wr_r),
        .I2(bm_end_r1_reg),
        .I3(Q),
        .I4(pass_open_bank_r),
        .O(pre_passing_open_bank_r_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAEAEAEA)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0 
       (.I0(auto_pre_r_lcl_reg_2),
        .I1(pass_open_bank_r),
        .I2(Q),
        .I3(bm_end_r1_reg),
        .I4(req_wr_r),
        .I5(pre_bm_end_r),
        .O(pass_open_bank_r_lcl_reg_0));
  LUT3 #(
    .INIT(8'hB8)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0 
       (.I0(rb_hit_busies_r_0[3]),
        .I1(head_r_lcl_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1 
       (.I0(rb_hit_busies_r_0[4]),
        .I1(head_r_lcl_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1 
       (.I0(rb_hit_busies_r_0[5]),
        .I1(head_r_lcl_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0_n_0 ),
        .Q(rb_hit_busies_r_0[3]),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1_n_0 ),
        .Q(rb_hit_busies_r_0[4]),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1_n_0 ),
        .Q(rb_hit_busies_r_0[5]),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ));
  LUT4 #(
    .INIT(16'h00A2)) 
    req_bank_rdy_r_i_1__0
       (.I0(col_wait_r),
        .I1(order_q_r[0]),
        .I2(req_bank_rdy_r_reg),
        .I3(order_q_r[1]),
        .O(req_bank_rdy_ns));
  LUT4 #(
    .INIT(16'hFFDF)) 
    \rnk_config_strobe_r[0]_i_1 
       (.I0(\order_q_r_reg[1]_0 ),
        .I1(\rnk_config_strobe_r_reg[0] ),
        .I2(\rnk_config_strobe_r_reg[0]_0 ),
        .I3(\rnk_config_strobe_r_reg[0]_1 ),
        .O(rnk_config_strobe_ns));
  FDRE wait_for_maint_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wait_for_maint_r_lcl_reg_2),
        .Q(wait_for_maint_r_lcl_reg_0),
        .R(wait_for_maint_r_lcl_reg_1));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_queue" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_queue__parameterized2
   (idle_r_lcl_reg_0,
    E,
    pass_open_bank_r,
    pass_open_bank_ns,
    q_has_rd,
    pass_open_bank_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_0,
    head_r,
    ordered_r_lcl_reg_0,
    auto_pre_r_lcl_reg_0,
    pre_bm_end_r_reg_0,
    idle_r_lcl_reg_1,
    D,
    head_r_lcl_reg_0,
    idle_r_lcl_reg_2,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ,
    demand_priority_ns,
    \order_q_r_reg[1]_0 ,
    act_wait_ns,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    \order_q_r_reg[1]_1 ,
    req_bank_rdy_ns,
    pre_passing_open_bank_r_reg_0,
    act_wait_r_lcl_reg,
    idle_r_lcl_reg_3,
    CLK,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    wait_for_maint_r_lcl_reg_1,
    wait_for_maint_r_lcl_reg_2,
    SR,
    ordered_r_lcl_reg_1,
    \compute_tail.tail_r_lcl_reg_0 ,
    head_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_2,
    col_wait_r,
    Q,
    auto_pre_r_lcl_reg_1,
    \order_q_r_reg[1]_2 ,
    \maint_controller.maint_hit_busies_r_reg[3] ,
    \maint_controller.maint_hit_busies_r_reg[3]_0 ,
    q_has_rd_r_reg_0,
    was_wr,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[1] ,
    demand_priority_r_reg,
    req_priority_r,
    demand_priority_r_reg_0,
    bm_end_r1_2,
    act_wait_r_lcl_reg_0,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    act_wait_r_lcl_reg_1,
    \ras_timer_r_reg[0]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,
    \q_entry_r_reg[1]_0 ,
    head_r_lcl_reg_2,
    \q_entry_r_reg[0]_0 ,
    q_has_priority_r_reg_0,
    demand_priority_r_reg_1,
    rb_hit_busy_r,
    q_has_priority_r_reg_1,
    head_r_lcl_i_3_0,
    head_r_lcl_i_3_1,
    head_r_lcl_i_3_2,
    req_bank_rdy_r_reg,
    \rnk_config_strobe_r_reg[0] ,
    \rnk_config_strobe_r_reg[0]_0 ,
    demand_priority_r_reg_2,
    demand_priority_r_reg_3,
    demand_priority_r_reg_4,
    demand_priority_r_reg_5,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 ,
    auto_pre_r_lcl_reg_2,
    accept_internal_r,
    app_en_r2,
    \order_q_r_reg[1]_3 ,
    \order_q_r_reg[1]_4 ,
    req_wr_r,
    bm_end_r1_reg,
    pre_wait_r,
    auto_pre_r_lcl_reg_3,
    was_priority,
    ras_timer_zero_r,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_3 ,
    \ras_timer_r_reg[0]_4 ,
    \ras_timer_r_reg[0]_5 ,
    \q_entry_r_reg[1]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_4 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ,
    \q_entry_r_reg[1]_2 ,
    \q_entry_r_reg[0]_1 ,
    \order_q_r_reg[1]_5 ,
    \order_q_r_reg[0]_0 );
  output [0:0]idle_r_lcl_reg_0;
  output [0:0]E;
  output pass_open_bank_r;
  output pass_open_bank_ns;
  output q_has_rd;
  output pass_open_bank_r_lcl_reg_0;
  output wait_for_maint_r_lcl_reg_0;
  output [0:0]head_r;
  output ordered_r_lcl_reg_0;
  output auto_pre_r_lcl_reg_0;
  output pre_bm_end_r_reg_0;
  output idle_r_lcl_reg_1;
  output [0:0]D;
  output head_r_lcl_reg_0;
  output idle_r_lcl_reg_2;
  output [1:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ;
  output demand_priority_ns;
  output \order_q_r_reg[1]_0 ;
  output act_wait_ns;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  output \order_q_r_reg[1]_1 ;
  output req_bank_rdy_ns;
  output pre_passing_open_bank_r_reg_0;
  output act_wait_r_lcl_reg;
  output idle_r_lcl_reg_3;
  input CLK;
  input pre_bm_end_ns;
  input pre_passing_open_bank_ns;
  input wait_for_maint_r_lcl_reg_1;
  input wait_for_maint_r_lcl_reg_2;
  input [0:0]SR;
  input ordered_r_lcl_reg_1;
  input \compute_tail.tail_r_lcl_reg_0 ;
  input head_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_2;
  input col_wait_r;
  input [0:0]Q;
  input auto_pre_r_lcl_reg_1;
  input \order_q_r_reg[1]_2 ;
  input [0:0]\maint_controller.maint_hit_busies_r_reg[3] ;
  input \maint_controller.maint_hit_busies_r_reg[3]_0 ;
  input q_has_rd_r_reg_0;
  input was_wr;
  input \ras_timer_r_reg[0] ;
  input \ras_timer_r_reg[1] ;
  input demand_priority_r_reg;
  input req_priority_r;
  input demand_priority_r_reg_0;
  input bm_end_r1_2;
  input act_wait_r_lcl_reg_0;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input act_wait_r_lcl_reg_1;
  input \ras_timer_r_reg[0]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  input \q_entry_r_reg[1]_0 ;
  input head_r_lcl_reg_2;
  input \q_entry_r_reg[0]_0 ;
  input q_has_priority_r_reg_0;
  input demand_priority_r_reg_1;
  input [2:0]rb_hit_busy_r;
  input q_has_priority_r_reg_1;
  input head_r_lcl_i_3_0;
  input [0:0]head_r_lcl_i_3_1;
  input head_r_lcl_i_3_2;
  input req_bank_rdy_r_reg;
  input \rnk_config_strobe_r_reg[0] ;
  input \rnk_config_strobe_r_reg[0]_0 ;
  input demand_priority_r_reg_2;
  input demand_priority_r_reg_3;
  input demand_priority_r_reg_4;
  input demand_priority_r_reg_5;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 ;
  input auto_pre_r_lcl_reg_2;
  input accept_internal_r;
  input app_en_r2;
  input \order_q_r_reg[1]_3 ;
  input \order_q_r_reg[1]_4 ;
  input [0:0]req_wr_r;
  input bm_end_r1_reg;
  input pre_wait_r;
  input auto_pre_r_lcl_reg_3;
  input was_priority;
  input ras_timer_zero_r;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_3 ;
  input \ras_timer_r_reg[0]_4 ;
  input \ras_timer_r_reg[0]_5 ;
  input [2:0]\q_entry_r_reg[1]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_4 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  input \q_entry_r_reg[1]_2 ;
  input \q_entry_r_reg[0]_1 ;
  input \order_q_r_reg[1]_5 ;
  input \order_q_r_reg[0]_0 ;

  wire CLK;
  wire [0:0]D;
  wire [0:0]E;
  wire [0:0]Q;
  wire [0:0]SR;
  wire accept_internal_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_i_2_n_0;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire app_en_r2;
  wire auto_pre_r_lcl_i_1_n_0;
  wire auto_pre_r_lcl_i_2_n_0;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg_3;
  wire bm_end_r1_2;
  wire bm_end_r1_reg;
  wire col_wait_r;
  wire \compute_tail.tail_r_lcl_i_1__2_n_0 ;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire demand_priority_ns;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire demand_priority_r_reg_3;
  wire demand_priority_r_reg_4;
  wire demand_priority_r_reg_5;
  wire [0:0]head_r;
  wire head_r_lcl_i_1__2_n_0;
  wire head_r_lcl_i_3_0;
  wire [0:0]head_r_lcl_i_3_1;
  wire head_r_lcl_i_3_2;
  wire head_r_lcl_i_3_n_0;
  wire head_r_lcl_i_4_n_0;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire [0:0]idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire idle_r_lcl_reg_3;
  wire [0:0]\maint_controller.maint_hit_busies_r_reg[3] ;
  wire \maint_controller.maint_hit_busies_r_reg[3]_0 ;
  wire [1:0]order_q_r;
  wire \order_q_r[0]_i_1_n_0 ;
  wire \order_q_r[1]_i_1_n_0 ;
  wire \order_q_r_reg[0]_0 ;
  wire \order_q_r_reg[1]_0 ;
  wire \order_q_r_reg[1]_1 ;
  wire \order_q_r_reg[1]_2 ;
  wire \order_q_r_reg[1]_3 ;
  wire \order_q_r_reg[1]_4 ;
  wire \order_q_r_reg[1]_5 ;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_wait_r;
  wire \q_entry_r[0]_i_1_n_0 ;
  wire \q_entry_r[0]_i_3_n_0 ;
  wire \q_entry_r[1]_i_1_n_0 ;
  wire \q_entry_r[1]_i_3_n_0 ;
  wire \q_entry_r[1]_i_4__0_n_0 ;
  wire \q_entry_r[1]_i_6_n_0 ;
  wire \q_entry_r[1]_i_7_n_0 ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[1]_0 ;
  wire [2:0]\q_entry_r_reg[1]_1 ;
  wire \q_entry_r_reg[1]_2 ;
  wire \q_entry_r_reg_n_0_[0] ;
  wire \q_entry_r_reg_n_0_[1] ;
  wire q_has_priority;
  wire q_has_priority_r_i_1_n_0;
  wire q_has_priority_r_reg_0;
  wire q_has_priority_r_reg_1;
  wire q_has_rd;
  wire q_has_rd_r_i_1__0_n_0;
  wire q_has_rd_r_reg_0;
  wire \ras_timer_r[0]_i_2_n_0 ;
  wire \ras_timer_r[1]_i_2__2_n_0 ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[0]_5 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ;
  wire [1:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_4 ;
  wire [2:0]rb_hit_busy_r;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire req_priority_r;
  wire [0:0]req_wr_r;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire tail_r;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire wait_for_maint_r_lcl_reg_2;
  wire was_priority;
  wire was_wr;

  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF444)) 
    act_wait_r_lcl_i_1
       (.I0(act_wait_r_lcl_i_2_n_0),
        .I1(auto_pre_r_lcl_reg_1),
        .I2(pass_open_bank_r),
        .I3(pre_bm_end_r_reg_0),
        .I4(\order_q_r_reg[1]_2 ),
        .I5(bm_end_r1_2),
        .O(act_wait_ns));
  LUT6 #(
    .INIT(64'hBBBBBBBBBBBBABAA)) 
    act_wait_r_lcl_i_2
       (.I0(act_wait_r_lcl_reg_0),
        .I1(idle_r_lcl_reg_2),
        .I2(\ras_timer_r_reg[0]_0 ),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I4(\ras_timer_r_reg[0]_1 ),
        .I5(act_wait_r_lcl_reg_1),
        .O(act_wait_r_lcl_i_2_n_0));
  LUT3 #(
    .INIT(8'hEF)) 
    act_wait_r_lcl_i_3__1
       (.I0(idle_r_lcl_reg_0),
        .I1(\q_entry_r_reg_n_0_[1] ),
        .I2(\q_entry_r_reg_n_0_[0] ),
        .O(idle_r_lcl_reg_2));
  LUT6 #(
    .INIT(64'hFFFFFFFF11110010)) 
    auto_pre_r_lcl_i_1
       (.I0(pass_open_bank_r_lcl_reg_2),
        .I1(auto_pre_r_lcl_i_2_n_0),
        .I2(col_wait_r),
        .I3(Q),
        .I4(auto_pre_r_lcl_reg_1),
        .I5(auto_pre_r_lcl_reg_0),
        .O(auto_pre_r_lcl_i_1_n_0));
  LUT6 #(
    .INIT(64'h777F7F7F7F7F7F7F)) 
    auto_pre_r_lcl_i_2
       (.I0(tail_r),
        .I1(q_has_priority_r_reg_1),
        .I2(\order_q_r_reg[1]_4 ),
        .I3(auto_pre_r_lcl_reg_3),
        .I4(app_en_r2),
        .I5(\order_q_r_reg[1]_3 ),
        .O(auto_pre_r_lcl_i_2_n_0));
  FDRE auto_pre_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(auto_pre_r_lcl_i_1_n_0),
        .Q(auto_pre_r_lcl_reg_0),
        .R(pass_open_bank_r_lcl_reg_0));
  LUT5 #(
    .INIT(32'hBFAAAAAA)) 
    bm_end_r1_i_1__0
       (.I0(pre_bm_end_r),
        .I1(req_wr_r),
        .I2(bm_end_r1_reg),
        .I3(Q),
        .I4(pass_open_bank_r),
        .O(pre_bm_end_r_reg_0));
  LUT6 #(
    .INIT(64'hEECCFFCFEECCEECC)) 
    \compute_tail.tail_r_lcl_i_1__2 
       (.I0(pre_bm_end_r_reg_0),
        .I1(idle_r_lcl_reg_1),
        .I2(idle_r_lcl_reg_0),
        .I3(\compute_tail.tail_r_lcl_reg_0 ),
        .I4(pass_open_bank_r_lcl_reg_1),
        .I5(tail_r),
        .O(\compute_tail.tail_r_lcl_i_1__2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \compute_tail.tail_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\compute_tail.tail_r_lcl_i_1__2_n_0 ),
        .Q(tail_r),
        .R(SR));
  LUT6 #(
    .INIT(64'h8888888800008880)) 
    demand_priority_r_i_1
       (.I0(demand_priority_r_reg),
        .I1(head_r_lcl_reg_0),
        .I2(req_priority_r),
        .I3(q_has_priority),
        .I4(\order_q_r_reg[1]_0 ),
        .I5(demand_priority_r_reg_0),
        .O(demand_priority_ns));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    demand_priority_r_i_2
       (.I0(order_q_r[1]),
        .I1(demand_priority_r_reg_2),
        .I2(demand_priority_r_reg_3),
        .I3(demand_priority_r_reg_4),
        .I4(demand_priority_r_reg_5),
        .I5(order_q_r[0]),
        .O(\order_q_r_reg[1]_0 ));
  LUT5 #(
    .INIT(32'hFFDFFFFF)) 
    \grant_r[3]_i_14 
       (.I0(auto_pre_r_lcl_reg_1),
        .I1(idle_r_lcl_reg_0),
        .I2(head_r),
        .I3(wait_for_maint_r_lcl_reg_0),
        .I4(ras_timer_zero_r),
        .O(act_wait_r_lcl_reg));
  LUT6 #(
    .INIT(64'h0000000045000000)) 
    \grant_r[3]_i_3 
       (.I0(order_q_r[1]),
        .I1(req_bank_rdy_r_reg),
        .I2(order_q_r[0]),
        .I3(col_wait_r),
        .I4(\rnk_config_strobe_r_reg[0] ),
        .I5(\rnk_config_strobe_r_reg[0]_0 ),
        .O(\order_q_r_reg[1]_1 ));
  LUT6 #(
    .INIT(64'h8F80FFFF8F800000)) 
    head_r_lcl_i_1__2
       (.I0(\compute_tail.tail_r_lcl_reg_0 ),
        .I1(head_r_lcl_reg_1),
        .I2(pre_bm_end_r_reg_0),
        .I3(head_r_lcl_i_3_n_0),
        .I4(\q_entry_r[1]_i_4__0_n_0 ),
        .I5(head_r),
        .O(head_r_lcl_i_1__2_n_0));
  LUT6 #(
    .INIT(64'h2020202F202F2020)) 
    head_r_lcl_i_3
       (.I0(\q_entry_r_reg_n_0_[0] ),
        .I1(\q_entry_r_reg_n_0_[1] ),
        .I2(head_r_lcl_i_4_n_0),
        .I3(head_r_lcl_reg_2),
        .I4(\q_entry_r[1]_i_7_n_0 ),
        .I5(\q_entry_r_reg[0]_0 ),
        .O(head_r_lcl_i_3_n_0));
  LUT5 #(
    .INIT(32'hDD1D1111)) 
    head_r_lcl_i_4
       (.I0(\q_entry_r[1]_i_7_n_0 ),
        .I1(idle_r_lcl_reg_0),
        .I2(head_r),
        .I3(demand_priority_r_reg_1),
        .I4(q_has_priority_r_reg_0),
        .O(head_r_lcl_i_4_n_0));
  FDRE head_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(head_r_lcl_i_1__2_n_0),
        .Q(head_r),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair602" *) 
  LUT1 #(
    .INIT(2'h1)) 
    idle_r_lcl_i_1__2
       (.I0(head_r_lcl_reg_0),
        .O(E));
  LUT5 #(
    .INIT(32'h0000004F)) 
    idle_r_lcl_i_2__2
       (.I0(demand_priority_r_reg_1),
        .I1(head_r),
        .I2(idle_r_lcl_reg_0),
        .I3(pre_bm_end_r_reg_0),
        .I4(auto_pre_r_lcl_reg_2),
        .O(head_r_lcl_reg_0));
  FDRE idle_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(E),
        .Q(idle_r_lcl_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair602" *) 
  LUT5 #(
    .INIT(32'h10111010)) 
    \maint_controller.maint_hit_busies_r[3]_i_1 
       (.I0(pre_bm_end_r_reg_0),
        .I1(\order_q_r_reg[1]_2 ),
        .I2(\maint_controller.maint_hit_busies_r_reg[3] ),
        .I3(\maint_controller.maint_hit_busies_r_reg[3]_0 ),
        .I4(head_r_lcl_reg_0),
        .O(D));
  LUT6 #(
    .INIT(64'h31553000315530CC)) 
    \order_q_r[0]_i_1 
       (.I0(\order_q_r_reg[0]_0 ),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_bank_rdy_r_reg),
        .I4(idle_r_lcl_reg_1),
        .I5(\order_q_r_reg[1]_2 ),
        .O(\order_q_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hC2AAC000C2AAC0F0)) 
    \order_q_r[1]_i_1 
       (.I0(\order_q_r_reg[1]_5 ),
        .I1(order_q_r[0]),
        .I2(order_q_r[1]),
        .I3(req_bank_rdy_r_reg),
        .I4(idle_r_lcl_reg_1),
        .I5(\order_q_r_reg[1]_2 ),
        .O(\order_q_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8080808080000000)) 
    \order_q_r[1]_i_2__0 
       (.I0(idle_r_lcl_reg_0),
        .I1(head_r),
        .I2(accept_internal_r),
        .I3(app_en_r2),
        .I4(\order_q_r_reg[1]_3 ),
        .I5(\order_q_r_reg[1]_4 ),
        .O(idle_r_lcl_reg_1));
  FDRE \order_q_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[0]_i_1_n_0 ),
        .Q(order_q_r[0]),
        .R(1'b0));
  FDRE \order_q_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\order_q_r[1]_i_1_n_0 ),
        .Q(order_q_r[1]),
        .R(1'b0));
  FDRE ordered_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ordered_r_lcl_reg_1),
        .Q(ordered_r_lcl_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4444544444444444)) 
    pass_open_bank_r_lcl_i_1__0
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(pass_open_bank_r),
        .I2(tail_r),
        .I3(pass_open_bank_r_lcl_reg_1),
        .I4(pre_wait_r),
        .I5(pass_open_bank_r_lcl_reg_2),
        .O(pass_open_bank_ns));
  FDRE pass_open_bank_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pass_open_bank_ns),
        .Q(pass_open_bank_r),
        .R(1'b0));
  FDRE pre_bm_end_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_bm_end_ns),
        .Q(pre_bm_end_r),
        .R(1'b0));
  FDRE pre_passing_open_bank_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_passing_open_bank_ns),
        .Q(pre_passing_open_bank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h7F48FFFF7F480000)) 
    \q_entry_r[0]_i_1 
       (.I0(\q_entry_r_reg[0]_1 ),
        .I1(pre_bm_end_r_reg_0),
        .I2(q_has_priority_r_reg_0),
        .I3(\q_entry_r[0]_i_3_n_0 ),
        .I4(\q_entry_r[1]_i_4__0_n_0 ),
        .I5(\q_entry_r_reg_n_0_[0] ),
        .O(\q_entry_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0000990F)) 
    \q_entry_r[0]_i_3 
       (.I0(\q_entry_r_reg[0]_0 ),
        .I1(\q_entry_r[1]_i_7_n_0 ),
        .I2(\q_entry_r_reg_n_0_[0] ),
        .I3(idle_r_lcl_reg_1),
        .I4(pre_bm_end_r_reg_0),
        .O(\q_entry_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hBF80FFFFBF800000)) 
    \q_entry_r[1]_i_1 
       (.I0(\q_entry_r_reg[1]_2 ),
        .I1(pre_bm_end_r_reg_0),
        .I2(q_has_priority_r_reg_0),
        .I3(\q_entry_r[1]_i_3_n_0 ),
        .I4(\q_entry_r[1]_i_4__0_n_0 ),
        .I5(\q_entry_r_reg_n_0_[1] ),
        .O(\q_entry_r[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hE881)) 
    \q_entry_r[1]_i_2__1 
       (.I0(idle_r_lcl_reg_0),
        .I1(\q_entry_r_reg[1]_1 [1]),
        .I2(\q_entry_r_reg[1]_1 [2]),
        .I3(\q_entry_r_reg[1]_1 [0]),
        .O(idle_r_lcl_reg_3));
  LUT6 #(
    .INIT(64'hB8BBB888B888B8BB)) 
    \q_entry_r[1]_i_3 
       (.I0(\q_entry_r_reg[1]_0 ),
        .I1(pre_bm_end_r_reg_0),
        .I2(\q_entry_r[1]_i_6_n_0 ),
        .I3(idle_r_lcl_reg_1),
        .I4(\q_entry_r_reg_n_0_[1] ),
        .I5(\q_entry_r_reg_n_0_[0] ),
        .O(\q_entry_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFAF3FAF3FFF3FAF3)) 
    \q_entry_r[1]_i_4__0 
       (.I0(q_has_priority_r_reg_0),
        .I1(\q_entry_r[1]_i_7_n_0 ),
        .I2(pre_bm_end_r_reg_0),
        .I3(idle_r_lcl_reg_0),
        .I4(head_r),
        .I5(demand_priority_r_reg_1),
        .O(\q_entry_r[1]_i_4__0_n_0 ));
  LUT5 #(
    .INIT(32'h7EE8E881)) 
    \q_entry_r[1]_i_6 
       (.I0(\q_entry_r[1]_i_7_n_0 ),
        .I1(rb_hit_busy_r[0]),
        .I2(rb_hit_busy_r[1]),
        .I3(rb_hit_busy_r[2]),
        .I4(q_has_priority_r_reg_1),
        .O(\q_entry_r[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0DDD0DDD00000DDD)) 
    \q_entry_r[1]_i_7 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I1(head_r_lcl_i_3_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ),
        .I3(head_r_lcl_i_3_1),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I5(head_r_lcl_i_3_2),
        .O(\q_entry_r[1]_i_7_n_0 ));
  FDSE \q_entry_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[0]_i_1_n_0 ),
        .Q(\q_entry_r_reg_n_0_[0] ),
        .S(SR));
  FDSE \q_entry_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\q_entry_r[1]_i_1_n_0 ),
        .Q(\q_entry_r_reg_n_0_[1] ),
        .S(SR));
  LUT4 #(
    .INIT(16'hEAAA)) 
    q_has_priority_r_i_1
       (.I0(q_has_priority),
        .I1(q_has_priority_r_reg_0),
        .I2(q_has_priority_r_reg_1),
        .I3(was_priority),
        .O(q_has_priority_r_i_1_n_0));
  FDRE q_has_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_priority_r_i_1_n_0),
        .Q(q_has_priority),
        .R(pass_open_bank_r_lcl_reg_0));
  LUT6 #(
    .INIT(64'h4445555544454445)) 
    q_has_rd_r_i_1__0
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(q_has_rd),
        .I2(q_has_rd_r_reg_0),
        .I3(idle_r_lcl_reg_0),
        .I4(was_wr),
        .I5(pass_open_bank_r_lcl_reg_1),
        .O(q_has_rd_r_i_1__0_n_0));
  FDRE q_has_rd_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(q_has_rd_r_i_1__0_n_0),
        .Q(q_has_rd),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair603" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[0]_i_1 
       (.I0(\ras_timer_r[0]_i_2_n_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ),
        .I2(\ras_timer_r_reg[0] ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [0]));
  LUT6 #(
    .INIT(64'hBBBB8888B888B888)) 
    \ras_timer_r[0]_i_2 
       (.I0(\ras_timer_r_reg[0]_3 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I3(\ras_timer_r_reg[0]_4 ),
        .I4(\ras_timer_r_reg[0]_5 ),
        .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .O(\ras_timer_r[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair603" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[1]_i_1 
       (.I0(\ras_timer_r[1]_i_2__2_n_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ),
        .I2(\ras_timer_r_reg[1] ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 [1]));
  LUT6 #(
    .INIT(64'hBBBB8888B888B888)) 
    \ras_timer_r[1]_i_2__2 
       (.I0(\ras_timer_r_reg[1]_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I3(\ras_timer_r_reg[1]_1 ),
        .I4(\ras_timer_r_reg[1]_2 ),
        .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .O(\ras_timer_r[1]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000F4F4FFF4)) 
    \ras_timer_r[1]_i_3 
       (.I0(\ras_timer_r_reg[0]_2 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ),
        .I2(\ras_timer_r_reg[0]_1 ),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I4(\ras_timer_r_reg[0]_0 ),
        .I5(idle_r_lcl_reg_2),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ));
  LUT5 #(
    .INIT(32'h40555555)) 
    \ras_timer_r[1]_i_5__0 
       (.I0(pre_passing_open_bank_r),
        .I1(req_wr_r),
        .I2(bm_end_r1_reg),
        .I3(Q),
        .I4(pass_open_bank_r),
        .O(pre_passing_open_bank_r_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAEAEAEA)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1 
       (.I0(auto_pre_r_lcl_reg_2),
        .I1(pass_open_bank_r),
        .I2(Q),
        .I3(bm_end_r1_reg),
        .I4(req_wr_r),
        .I5(pre_bm_end_r),
        .O(pass_open_bank_r_lcl_reg_0));
  LUT3 #(
    .INIT(8'hB8)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I1(head_r_lcl_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I1(head_r_lcl_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ),
        .I1(head_r_lcl_reg_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0_n_0 ),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0_n_0 ),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1_n_0 ),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_4 ));
  LUT4 #(
    .INIT(16'h00A2)) 
    req_bank_rdy_r_i_1
       (.I0(col_wait_r),
        .I1(order_q_r[0]),
        .I2(req_bank_rdy_r_reg),
        .I3(order_q_r[1]),
        .O(req_bank_rdy_ns));
  FDRE wait_for_maint_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wait_for_maint_r_lcl_reg_2),
        .Q(wait_for_maint_r_lcl_reg_0),
        .R(wait_for_maint_r_lcl_reg_1));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_state
   (bm_end_r1,
    act_wait_r_lcl_reg_0,
    ras_timer_zero_r,
    pre_wait_r,
    col_wait_r_reg_0,
    demand_act_priority_r,
    act_this_rank_r,
    demand_priority_r_reg_0,
    demanded_prior_r,
    ofs_rdy_r,
    wr_this_rank_r,
    rd_this_rank_r,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    \pre_4_1_1T_arb.granted_pre_ns ,
    auto_pre_r_lcl_reg,
    \ras_timer_r_reg[1]_0 ,
    bm_end_r1_reg_0,
    act_wait_r_lcl_reg_1,
    demand_priority_r_reg_1,
    ofs_rdy_r0,
    ofs_rdy_r0_0,
    ofs_rdy_r0_1,
    bm_end,
    CLK,
    act_wait_ns,
    req_bank_rdy_ns,
    SR,
    phy_mc_ctl_full,
    in0,
    phy_mc_cmd_full,
    start_wtp_timer0,
    \rd_this_rank_r_reg[0]_0 ,
    col_wait_r_reg_1,
    Q,
    col_wait_r_reg_2,
    pass_open_bank_r,
    \rtp_timer_r_reg[1]_0 ,
    demand_priority_r_reg_2,
    demand_priority_r_reg_3,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    \pre_4_1_1T_arb.granted_pre_r_reg_0 ,
    pass_open_bank_ns,
    demand_act_priority_r_reg_0,
    head_r,
    idle_r,
    \pre_4_1_1T_arb.granted_pre_r_reg_1 ,
    \pre_4_1_1T_arb.granted_pre_r_reg_2 ,
    ras_timer_zero_r_reg_0,
    \grant_r[3]_i_2__1 ,
    demand_priority_r_reg_4,
    req_wr_r,
    q_has_rd,
    demand_priority_r_2,
    demanded_prior_r_3,
    demanded_prior_r_reg_0,
    phy_mc_data_full,
    ofs_rdy_r_reg_0,
    \rtp_timer_r_reg[0]_0 ,
    D);
  output bm_end_r1;
  output act_wait_r_lcl_reg_0;
  output ras_timer_zero_r;
  output pre_wait_r;
  output col_wait_r_reg_0;
  output demand_act_priority_r;
  output [0:0]act_this_rank_r;
  output demand_priority_r_reg_0;
  output demanded_prior_r;
  output ofs_rdy_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output pre_bm_end_ns;
  output pre_passing_open_bank_ns;
  output \pre_4_1_1T_arb.granted_pre_ns ;
  output auto_pre_r_lcl_reg;
  output \ras_timer_r_reg[1]_0 ;
  output bm_end_r1_reg_0;
  output act_wait_r_lcl_reg_1;
  output demand_priority_r_reg_1;
  output ofs_rdy_r0;
  output ofs_rdy_r0_0;
  output ofs_rdy_r0_1;
  input [0:0]bm_end;
  input CLK;
  input act_wait_ns;
  input req_bank_rdy_ns;
  input [0:0]SR;
  input phy_mc_ctl_full;
  input in0;
  input phy_mc_cmd_full;
  input start_wtp_timer0;
  input \rd_this_rank_r_reg[0]_0 ;
  input col_wait_r_reg_1;
  input [1:0]Q;
  input col_wait_r_reg_2;
  input pass_open_bank_r;
  input \rtp_timer_r_reg[1]_0 ;
  input demand_priority_r_reg_2;
  input demand_priority_r_reg_3;
  input [0:0]\pre_4_1_1T_arb.granted_pre_r_reg ;
  input \pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  input pass_open_bank_ns;
  input demand_act_priority_r_reg_0;
  input [0:0]head_r;
  input [0:0]idle_r;
  input \pre_4_1_1T_arb.granted_pre_r_reg_1 ;
  input \pre_4_1_1T_arb.granted_pre_r_reg_2 ;
  input ras_timer_zero_r_reg_0;
  input [0:0]\grant_r[3]_i_2__1 ;
  input demand_priority_r_reg_4;
  input [0:0]req_wr_r;
  input q_has_rd;
  input demand_priority_r_2;
  input demanded_prior_r_3;
  input demanded_prior_r_reg_0;
  input phy_mc_data_full;
  input [2:0]ofs_rdy_r_reg_0;
  input \rtp_timer_r_reg[0]_0 ;
  input [1:0]D;

  wire CLK;
  wire [1:0]D;
  wire [1:0]Q;
  wire [0:0]SR;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg;
  wire \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r ;
  wire \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r ;
  wire [0:0]bm_end;
  wire bm_end_r1;
  wire bm_end_r1_reg_0;
  wire col_wait_r_i_1__2_n_0;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire col_wait_r_reg_2;
  wire demand_act_priority_ns;
  wire demand_act_priority_r;
  wire demand_act_priority_r_reg_0;
  wire demand_priority_ns;
  wire demand_priority_r_2;
  wire demand_priority_r_i_3_n_0;
  wire demand_priority_r_i_4_n_0;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire demand_priority_r_reg_3;
  wire demand_priority_r_reg_4;
  wire demanded_prior_ns;
  wire demanded_prior_r;
  wire demanded_prior_r_3;
  wire demanded_prior_r_reg_0;
  wire [0:0]\grant_r[3]_i_2__1 ;
  wire [0:0]head_r;
  wire [0:0]idle_r;
  wire in0;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ofs_rdy_r0_0;
  wire ofs_rdy_r0_1;
  wire ofs_rdy_r0_2;
  wire [2:0]ofs_rdy_r_reg_0;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire phy_mc_cmd_full;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire \pre_4_1_1T_arb.granted_pre_ns ;
  wire [0:0]\pre_4_1_1T_arb.granted_pre_r_reg ;
  wire \pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  wire \pre_4_1_1T_arb.granted_pre_r_reg_1 ;
  wire \pre_4_1_1T_arb.granted_pre_r_reg_2 ;
  wire pre_bm_end_ns;
  wire pre_passing_open_bank_ns;
  wire pre_wait_ns;
  wire pre_wait_r;
  wire pre_wait_r_i_2_n_0;
  wire q_has_rd;
  wire [1:0]ras_timer_r;
  wire \ras_timer_r_reg[1]_0 ;
  wire ras_timer_zero_ns;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg_0;
  wire [0:0]rd_this_rank_r;
  wire \rd_this_rank_r_reg[0]_0 ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r;
  wire [0:0]req_wr_r;
  wire [1:0]rtp_timer_r;
  wire \rtp_timer_r[0]_i_1_n_0 ;
  wire \rtp_timer_r[1]_i_1_n_0 ;
  wire \rtp_timer_r_reg[0]_0 ;
  wire \rtp_timer_r_reg[1]_0 ;
  wire start_wtp_timer0;
  wire [2:0]starve_limit_cntr_r;
  wire starve_limit_cntr_r0;
  wire \starve_limit_cntr_r[0]_i_1_n_0 ;
  wire \starve_limit_cntr_r[1]_i_1_n_0 ;
  wire \starve_limit_cntr_r[2]_i_1_n_0 ;
  wire [0:0]wr_this_rank_r;

  FDRE \act_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(act_wait_r_lcl_reg_0),
        .Q(act_this_rank_r),
        .R(1'b0));
  FDRE act_wait_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(act_wait_ns),
        .Q(act_wait_r_lcl_reg_0),
        .R(1'b0));
  FDRE bm_end_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(bm_end),
        .Q(bm_end_r1),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h5504)) 
    col_wait_r_i_1__2
       (.I0(col_wait_r_reg_1),
        .I1(col_wait_r_reg_0),
        .I2(Q[0]),
        .I3(col_wait_r_reg_2),
        .O(col_wait_r_i_1__2_n_0));
  FDRE col_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(col_wait_r_i_1__2_n_0),
        .Q(col_wait_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    demand_act_priority_r_i_1
       (.I0(demand_act_priority_r),
        .I1(ras_timer_zero_r),
        .I2(demand_act_priority_r_reg_0),
        .I3(head_r),
        .I4(idle_r),
        .I5(act_wait_r_lcl_reg_0),
        .O(demand_act_priority_ns));
  FDRE demand_act_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_act_priority_ns),
        .Q(demand_act_priority_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h88888808)) 
    demand_priority_r_i_1__2
       (.I0(col_wait_r_i_1__2_n_0),
        .I1(demand_priority_r_reg_2),
        .I2(demand_priority_r_reg_3),
        .I3(demand_priority_r_i_3_n_0),
        .I4(demand_priority_r_reg_0),
        .O(demand_priority_ns));
  LUT6 #(
    .INIT(64'h0000000040400040)) 
    demand_priority_r_i_3
       (.I0(Q[0]),
        .I1(demand_priority_r_reg_4),
        .I2(req_bank_rdy_r),
        .I3(req_wr_r),
        .I4(q_has_rd),
        .I5(demand_priority_r_i_4_n_0),
        .O(demand_priority_r_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair588" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    demand_priority_r_i_4
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[0]),
        .O(demand_priority_r_i_4_n_0));
  FDRE demand_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_priority_ns),
        .Q(demand_priority_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000D00DDDDDDDD)) 
    demanded_prior_r_i_1
       (.I0(demand_priority_r_reg_0),
        .I1(demanded_prior_r),
        .I2(Q[1]),
        .I3(demand_priority_r_2),
        .I4(demanded_prior_r_3),
        .I5(demanded_prior_r_reg_0),
        .O(demanded_prior_ns));
  FDRE demanded_prior_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demanded_prior_ns),
        .Q(demanded_prior_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair584" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \grant_r[2]_i_3__1 
       (.I0(\pre_4_1_1T_arb.granted_pre_r_reg_0 ),
        .I1(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I2(pre_wait_r),
        .I3(ras_timer_zero_r),
        .O(auto_pre_r_lcl_reg));
  LUT2 #(
    .INIT(4'h8)) 
    \grant_r[3]_i_8__0 
       (.I0(act_wait_r_lcl_reg_0),
        .I1(\grant_r[3]_i_2__1 ),
        .O(act_wait_r_lcl_reg_1));
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    \grant_r[3]_i_9__1 
       (.I0(demand_priority_r_2),
        .I1(Q[0]),
        .I2(demand_priority_r_reg_0),
        .I3(demanded_prior_r),
        .I4(demanded_prior_r_reg_0),
        .O(demand_priority_r_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair586" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    ofs_rdy_r_i_1
       (.I0(\bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r ),
        .I1(\bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r ),
        .I2(\rd_this_rank_r_reg[0]_0 ),
        .I3(phy_mc_data_full),
        .O(ofs_rdy_r0_2));
  (* SOFT_HLUTNM = "soft_lutpair586" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    ofs_rdy_r_i_1__0
       (.I0(\bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r ),
        .I1(\bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r ),
        .I2(ofs_rdy_r_reg_0[2]),
        .I3(phy_mc_data_full),
        .O(ofs_rdy_r0));
  (* SOFT_HLUTNM = "soft_lutpair587" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    ofs_rdy_r_i_1__1
       (.I0(\bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r ),
        .I1(\bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r ),
        .I2(ofs_rdy_r_reg_0[1]),
        .I3(phy_mc_data_full),
        .O(ofs_rdy_r0_0));
  (* SOFT_HLUTNM = "soft_lutpair587" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    ofs_rdy_r_i_1__2
       (.I0(\bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r ),
        .I1(\bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r ),
        .I2(ofs_rdy_r_reg_0[0]),
        .I3(phy_mc_data_full),
        .O(ofs_rdy_r0_1));
  FDRE #(
    .INIT(1'b0)) 
    ofs_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ofs_rdy_r0_2),
        .Q(ofs_rdy_r),
        .R(SR));
  FDRE #(
    .INIT(1'b0)) 
    phy_mc_cmd_full_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_mc_cmd_full),
        .Q(\bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r ),
        .R(in0));
  FDRE #(
    .INIT(1'b0)) 
    phy_mc_ctl_full_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_mc_ctl_full),
        .Q(\bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r ),
        .R(SR));
  LUT6 #(
    .INIT(64'hABAAAAAAFFFFFFFF)) 
    \pre_4_1_1T_arb.granted_pre_r_i_1 
       (.I0(\pre_4_1_1T_arb.granted_pre_r_reg_1 ),
        .I1(\pre_4_1_1T_arb.granted_pre_r_reg_0 ),
        .I2(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I3(pre_wait_r),
        .I4(ras_timer_zero_r),
        .I5(\pre_4_1_1T_arb.granted_pre_r_reg_2 ),
        .O(\pre_4_1_1T_arb.granted_pre_ns ));
  (* SOFT_HLUTNM = "soft_lutpair584" *) 
  LUT5 #(
    .INIT(32'hEAEAEAAA)) 
    pre_bm_end_r_i_1
       (.I0(pre_passing_open_bank_ns),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\pre_4_1_1T_arb.granted_pre_r_reg_0 ),
        .O(pre_bm_end_ns));
  LUT6 #(
    .INIT(64'hAAA8AAAAAAA8AAA8)) 
    pre_passing_open_bank_r_i_1
       (.I0(pass_open_bank_ns),
        .I1(Q[0]),
        .I2(rtp_timer_r[0]),
        .I3(rtp_timer_r[1]),
        .I4(ras_timer_zero_r),
        .I5(pre_wait_r),
        .O(pre_passing_open_bank_ns));
  LUT6 #(
    .INIT(64'h4444444444454444)) 
    pre_wait_r_i_1
       (.I0(pass_open_bank_ns),
        .I1(pre_wait_r_i_2_n_0),
        .I2(pass_open_bank_r),
        .I3(\rtp_timer_r_reg[1]_0 ),
        .I4(rtp_timer_r[0]),
        .I5(rtp_timer_r[1]),
        .O(pre_wait_ns));
  LUT5 #(
    .INIT(32'h10101050)) 
    pre_wait_r_i_2
       (.I0(col_wait_r_reg_1),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I4(\pre_4_1_1T_arb.granted_pre_r_reg_0 ),
        .O(pre_wait_r_i_2_n_0));
  FDRE pre_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_wait_ns),
        .Q(pre_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000EFF0E0E)) 
    \ras_timer_r[0]_i_3 
       (.I0(act_wait_r_lcl_reg_1),
        .I1(ras_timer_r[1]),
        .I2(ras_timer_r[0]),
        .I3(\rd_this_rank_r_reg[0]_0 ),
        .I4(Q[0]),
        .I5(ras_timer_zero_r_reg_0),
        .O(\ras_timer_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h1000111110001000)) 
    \ras_timer_r[1]_i_4 
       (.I0(bm_end_r1),
        .I1(col_wait_r_reg_1),
        .I2(ras_timer_r[1]),
        .I3(ras_timer_r[0]),
        .I4(\rd_this_rank_r_reg[0]_0 ),
        .I5(Q[0]),
        .O(bm_end_r1_reg_0));
  FDRE \ras_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(ras_timer_r[0]),
        .R(1'b0));
  FDRE \ras_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(ras_timer_r[1]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h1)) 
    ras_timer_zero_r_i_1
       (.I0(\ras_timer_r_reg[1]_0 ),
        .I1(bm_end_r1_reg_0),
        .O(ras_timer_zero_ns));
  FDRE ras_timer_zero_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ras_timer_zero_ns),
        .Q(ras_timer_zero_r),
        .R(1'b0));
  FDRE \rd_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_this_rank_r_reg[0]_0 ),
        .Q(rd_this_rank_r),
        .R(1'b0));
  FDRE req_bank_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(req_bank_rdy_ns),
        .Q(req_bank_rdy_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0010)) 
    \rtp_timer_r[0]_i_1 
       (.I0(\rtp_timer_r_reg[0]_0 ),
        .I1(pass_open_bank_r),
        .I2(rtp_timer_r[1]),
        .I3(rtp_timer_r[0]),
        .O(\rtp_timer_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h000000C2)) 
    \rtp_timer_r[1]_i_1 
       (.I0(Q[0]),
        .I1(rtp_timer_r[0]),
        .I2(rtp_timer_r[1]),
        .I3(pass_open_bank_r),
        .I4(\rtp_timer_r_reg[1]_0 ),
        .O(\rtp_timer_r[1]_i_1_n_0 ));
  FDRE \rtp_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[0]_i_1_n_0 ),
        .Q(rtp_timer_r[0]),
        .R(1'b0));
  FDRE \rtp_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[1]_i_1_n_0 ),
        .Q(rtp_timer_r[1]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair588" *) 
  LUT3 #(
    .INIT(8'h60)) 
    \starve_limit_cntr_r[0]_i_1 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r0),
        .I2(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair585" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \starve_limit_cntr_r[1]_i_1 
       (.I0(starve_limit_cntr_r[1]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair585" *) 
  LUT5 #(
    .INIT(32'h6AAA0000)) 
    \starve_limit_cntr_r[2]_i_1 
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(starve_limit_cntr_r[1]),
        .I4(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h007F000000000000)) 
    \starve_limit_cntr_r[2]_i_2 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[2]),
        .I3(Q[0]),
        .I4(demand_priority_r_reg_4),
        .I5(req_bank_rdy_r),
        .O(starve_limit_cntr_r0));
  FDRE \starve_limit_cntr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[0]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[0]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[1]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[1]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[2]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[2]),
        .R(1'b0));
  FDRE \wr_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(start_wtp_timer0),
        .Q(wr_this_rank_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_state" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_state__parameterized0
   (act_wait_r_lcl_reg_0,
    act_this_rank_r,
    wr_this_rank_r,
    rd_this_rank_r,
    bm_end_r1_0,
    ras_timer_zero_r,
    pre_wait_r,
    col_wait_r_reg_0,
    demand_act_priority_r,
    demand_priority_r_reg_0,
    demanded_prior_r,
    ofs_rdy_r,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    auto_pre_r_lcl_reg,
    \grant_r_reg[2] ,
    act_wait_r_lcl_reg_1,
    \ras_timer_r_reg[1]_0 ,
    bm_end_r1_reg_0,
    demand_priority_r_reg_1,
    act_wait_ns,
    CLK,
    start_wtp_timer0,
    \rd_this_rank_r_reg[0]_0 ,
    bm_end,
    req_bank_rdy_ns,
    SR,
    ofs_rdy_r0,
    \rtp_timer_r_reg[1]_0 ,
    Q,
    col_wait_r_reg_1,
    pass_open_bank_r,
    demand_priority_r_reg_2,
    demand_priority_r_reg_3,
    pre_bm_end_r_reg,
    pre_bm_end_r_reg_0,
    pass_open_bank_ns,
    pre_wait_r_reg_0,
    demand_act_priority_r_reg_0,
    head_r,
    demand_act_priority_r_reg_1,
    \cmd_pipe_plus.mc_address_reg[10] ,
    \cmd_pipe_plus.mc_address_reg[10]_0 ,
    \cmd_pipe_plus.mc_address_reg[10]_1 ,
    \cmd_pipe_plus.mc_address_reg[10]_2 ,
    ras_timer_zero_r_reg_0,
    demand_priority_r_0,
    demanded_prior_r_reg_0,
    demanded_prior_r_1,
    demand_priority_r_reg_4,
    req_wr_r,
    q_has_rd,
    \rtp_timer_r_reg[0]_0 ,
    D);
  output act_wait_r_lcl_reg_0;
  output [0:0]act_this_rank_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output bm_end_r1_0;
  output ras_timer_zero_r;
  output pre_wait_r;
  output col_wait_r_reg_0;
  output demand_act_priority_r;
  output demand_priority_r_reg_0;
  output demanded_prior_r;
  output ofs_rdy_r;
  output pre_bm_end_ns;
  output pre_passing_open_bank_ns;
  output auto_pre_r_lcl_reg;
  output \grant_r_reg[2] ;
  output act_wait_r_lcl_reg_1;
  output \ras_timer_r_reg[1]_0 ;
  output bm_end_r1_reg_0;
  output demand_priority_r_reg_1;
  input act_wait_ns;
  input CLK;
  input start_wtp_timer0;
  input \rd_this_rank_r_reg[0]_0 ;
  input [0:0]bm_end;
  input req_bank_rdy_ns;
  input [0:0]SR;
  input ofs_rdy_r0;
  input \rtp_timer_r_reg[1]_0 ;
  input [1:0]Q;
  input col_wait_r_reg_1;
  input pass_open_bank_r;
  input demand_priority_r_reg_2;
  input demand_priority_r_reg_3;
  input [0:0]pre_bm_end_r_reg;
  input pre_bm_end_r_reg_0;
  input pass_open_bank_ns;
  input pre_wait_r_reg_0;
  input demand_act_priority_r_reg_0;
  input [0:0]head_r;
  input [0:0]demand_act_priority_r_reg_1;
  input [2:0]\cmd_pipe_plus.mc_address_reg[10] ;
  input [0:0]\cmd_pipe_plus.mc_address_reg[10]_0 ;
  input [0:0]\cmd_pipe_plus.mc_address_reg[10]_1 ;
  input [0:0]\cmd_pipe_plus.mc_address_reg[10]_2 ;
  input ras_timer_zero_r_reg_0;
  input demand_priority_r_0;
  input demanded_prior_r_reg_0;
  input demanded_prior_r_1;
  input demand_priority_r_reg_4;
  input [0:0]req_wr_r;
  input q_has_rd;
  input \rtp_timer_r_reg[0]_0 ;
  input [1:0]D;

  wire CLK;
  wire [1:0]D;
  wire [1:0]Q;
  wire [0:0]SR;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg;
  wire [0:0]bm_end;
  wire bm_end_r1_0;
  wire bm_end_r1_reg_0;
  wire [2:0]\cmd_pipe_plus.mc_address_reg[10] ;
  wire [0:0]\cmd_pipe_plus.mc_address_reg[10]_0 ;
  wire [0:0]\cmd_pipe_plus.mc_address_reg[10]_1 ;
  wire [0:0]\cmd_pipe_plus.mc_address_reg[10]_2 ;
  wire col_wait_r_i_1__1_n_0;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire demand_act_priority_ns;
  wire demand_act_priority_r;
  wire demand_act_priority_r_reg_0;
  wire [0:0]demand_act_priority_r_reg_1;
  wire demand_priority_ns;
  wire demand_priority_r_0;
  wire demand_priority_r_i_3__0_n_0;
  wire demand_priority_r_i_4__0_n_0;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire demand_priority_r_reg_3;
  wire demand_priority_r_reg_4;
  wire demanded_prior_ns;
  wire demanded_prior_r;
  wire demanded_prior_r_1;
  wire demanded_prior_r_reg_0;
  wire \grant_r_reg[2] ;
  wire [0:0]head_r;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pre_bm_end_ns;
  wire [0:0]pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_wait_ns;
  wire pre_wait_r;
  wire pre_wait_r_i_2__0_n_0;
  wire pre_wait_r_reg_0;
  wire q_has_rd;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg_n_0_[0] ;
  wire \ras_timer_r_reg_n_0_[1] ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_i_1__0_n_0;
  wire ras_timer_zero_r_reg_0;
  wire [0:0]rd_this_rank_r;
  wire \rd_this_rank_r_reg[0]_0 ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r;
  wire [0:0]req_wr_r;
  wire [1:0]rtp_timer_r;
  wire \rtp_timer_r[0]_i_1__0_n_0 ;
  wire \rtp_timer_r[1]_i_1__0_n_0 ;
  wire \rtp_timer_r_reg[0]_0 ;
  wire \rtp_timer_r_reg[1]_0 ;
  wire start_wtp_timer0;
  wire [2:0]starve_limit_cntr_r;
  wire starve_limit_cntr_r0;
  wire \starve_limit_cntr_r[0]_i_1_n_0 ;
  wire \starve_limit_cntr_r[1]_i_1_n_0 ;
  wire \starve_limit_cntr_r[2]_i_1_n_0 ;
  wire [0:0]wr_this_rank_r;

  FDRE \act_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(act_wait_r_lcl_reg_0),
        .Q(act_this_rank_r),
        .R(1'b0));
  FDRE act_wait_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(act_wait_ns),
        .Q(act_wait_r_lcl_reg_0),
        .R(1'b0));
  FDRE bm_end_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(bm_end),
        .Q(bm_end_r1_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFF00202000002020)) 
    \cmd_pipe_plus.mc_address[10]_i_2 
       (.I0(act_wait_r_lcl_reg_1),
        .I1(\cmd_pipe_plus.mc_address_reg[10] [1]),
        .I2(\cmd_pipe_plus.mc_address_reg[10]_0 ),
        .I3(\cmd_pipe_plus.mc_address_reg[10]_1 ),
        .I4(\cmd_pipe_plus.mc_address_reg[10] [2]),
        .I5(\cmd_pipe_plus.mc_address_reg[10]_2 ),
        .O(\grant_r_reg[2] ));
  LUT4 #(
    .INIT(16'h5504)) 
    col_wait_r_i_1__1
       (.I0(\rtp_timer_r_reg[1]_0 ),
        .I1(col_wait_r_reg_0),
        .I2(Q[0]),
        .I3(col_wait_r_reg_1),
        .O(col_wait_r_i_1__1_n_0));
  FDRE col_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(col_wait_r_i_1__1_n_0),
        .Q(col_wait_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    demand_act_priority_r_i_1__0
       (.I0(demand_act_priority_r),
        .I1(ras_timer_zero_r),
        .I2(demand_act_priority_r_reg_0),
        .I3(head_r),
        .I4(demand_act_priority_r_reg_1),
        .I5(act_wait_r_lcl_reg_0),
        .O(demand_act_priority_ns));
  FDRE demand_act_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_act_priority_ns),
        .Q(demand_act_priority_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h88888808)) 
    demand_priority_r_i_1__1
       (.I0(col_wait_r_i_1__1_n_0),
        .I1(demand_priority_r_reg_2),
        .I2(demand_priority_r_reg_3),
        .I3(demand_priority_r_i_3__0_n_0),
        .I4(demand_priority_r_reg_0),
        .O(demand_priority_ns));
  LUT6 #(
    .INIT(64'h0000000040400040)) 
    demand_priority_r_i_3__0
       (.I0(Q[0]),
        .I1(demand_priority_r_reg_4),
        .I2(req_bank_rdy_r),
        .I3(req_wr_r),
        .I4(q_has_rd),
        .I5(demand_priority_r_i_4__0_n_0),
        .O(demand_priority_r_i_3__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair594" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    demand_priority_r_i_4__0
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[0]),
        .O(demand_priority_r_i_4__0_n_0));
  FDRE demand_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_priority_ns),
        .Q(demand_priority_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0DDD0D0)) 
    demanded_prior_r_i_1__1
       (.I0(demand_priority_r_reg_0),
        .I1(demanded_prior_r),
        .I2(demanded_prior_r_reg_0),
        .I3(Q[1]),
        .I4(demand_priority_r_0),
        .I5(demanded_prior_r_1),
        .O(demanded_prior_ns));
  FDRE demanded_prior_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demanded_prior_ns),
        .Q(demanded_prior_r),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    \grant_r[2]_i_5__0 
       (.I0(act_wait_r_lcl_reg_0),
        .I1(\cmd_pipe_plus.mc_address_reg[10] [0]),
        .O(act_wait_r_lcl_reg_1));
  LUT5 #(
    .INIT(32'hBBBBBABB)) 
    \grant_r[3]_i_10 
       (.I0(demand_priority_r_0),
        .I1(demanded_prior_r_reg_0),
        .I2(Q[0]),
        .I3(demand_priority_r_reg_0),
        .I4(demanded_prior_r),
        .O(demand_priority_r_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair592" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \grant_r[3]_i_3__0 
       (.I0(pre_bm_end_r_reg_0),
        .I1(pre_bm_end_r_reg),
        .I2(pre_wait_r),
        .I3(ras_timer_zero_r),
        .O(auto_pre_r_lcl_reg));
  FDRE #(
    .INIT(1'b0)) 
    ofs_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ofs_rdy_r0),
        .Q(ofs_rdy_r),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair592" *) 
  LUT5 #(
    .INIT(32'hEAEAEAAA)) 
    pre_bm_end_r_i_1__2
       (.I0(pre_passing_open_bank_ns),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_bm_end_ns));
  LUT6 #(
    .INIT(64'hAAA8AAAAAAA8AAA8)) 
    pre_passing_open_bank_r_i_1__2
       (.I0(pass_open_bank_ns),
        .I1(Q[0]),
        .I2(rtp_timer_r[0]),
        .I3(rtp_timer_r[1]),
        .I4(ras_timer_zero_r),
        .I5(pre_wait_r),
        .O(pre_passing_open_bank_ns));
  LUT6 #(
    .INIT(64'h4444444444454444)) 
    pre_wait_r_i_1__2
       (.I0(pass_open_bank_ns),
        .I1(pre_wait_r_i_2__0_n_0),
        .I2(pass_open_bank_r),
        .I3(pre_wait_r_reg_0),
        .I4(rtp_timer_r[0]),
        .I5(rtp_timer_r[1]),
        .O(pre_wait_ns));
  LUT5 #(
    .INIT(32'h10101050)) 
    pre_wait_r_i_2__0
       (.I0(pre_wait_r_reg_0),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_wait_r_i_2__0_n_0));
  FDRE pre_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_wait_ns),
        .Q(pre_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000EFF0E0E)) 
    \ras_timer_r[0]_i_3__0 
       (.I0(act_wait_r_lcl_reg_1),
        .I1(\ras_timer_r_reg_n_0_[1] ),
        .I2(\ras_timer_r_reg_n_0_[0] ),
        .I3(\rd_this_rank_r_reg[0]_0 ),
        .I4(Q[0]),
        .I5(ras_timer_zero_r_reg_0),
        .O(\ras_timer_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h1000111110001000)) 
    \ras_timer_r[1]_i_4__0 
       (.I0(bm_end_r1_0),
        .I1(pre_wait_r_reg_0),
        .I2(\ras_timer_r_reg_n_0_[1] ),
        .I3(\ras_timer_r_reg_n_0_[0] ),
        .I4(\rd_this_rank_r_reg[0]_0 ),
        .I5(Q[0]),
        .O(bm_end_r1_reg_0));
  FDRE \ras_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\ras_timer_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \ras_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\ras_timer_r_reg_n_0_[1] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h1)) 
    ras_timer_zero_r_i_1__0
       (.I0(\ras_timer_r_reg[1]_0 ),
        .I1(bm_end_r1_reg_0),
        .O(ras_timer_zero_r_i_1__0_n_0));
  FDRE ras_timer_zero_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ras_timer_zero_r_i_1__0_n_0),
        .Q(ras_timer_zero_r),
        .R(1'b0));
  FDRE \rd_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_this_rank_r_reg[0]_0 ),
        .Q(rd_this_rank_r),
        .R(1'b0));
  FDRE req_bank_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(req_bank_rdy_ns),
        .Q(req_bank_rdy_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0010)) 
    \rtp_timer_r[0]_i_1__0 
       (.I0(\rtp_timer_r_reg[0]_0 ),
        .I1(pass_open_bank_r),
        .I2(rtp_timer_r[1]),
        .I3(rtp_timer_r[0]),
        .O(\rtp_timer_r[0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h000000C2)) 
    \rtp_timer_r[1]_i_1__0 
       (.I0(Q[0]),
        .I1(rtp_timer_r[0]),
        .I2(rtp_timer_r[1]),
        .I3(pass_open_bank_r),
        .I4(\rtp_timer_r_reg[1]_0 ),
        .O(\rtp_timer_r[1]_i_1__0_n_0 ));
  FDRE \rtp_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[0]_i_1__0_n_0 ),
        .Q(rtp_timer_r[0]),
        .R(1'b0));
  FDRE \rtp_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[1]_i_1__0_n_0 ),
        .Q(rtp_timer_r[1]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair594" *) 
  LUT3 #(
    .INIT(8'h60)) 
    \starve_limit_cntr_r[0]_i_1 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r0),
        .I2(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair593" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \starve_limit_cntr_r[1]_i_1 
       (.I0(starve_limit_cntr_r[1]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair593" *) 
  LUT5 #(
    .INIT(32'h6AAA0000)) 
    \starve_limit_cntr_r[2]_i_1 
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(starve_limit_cntr_r[1]),
        .I4(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h007F000000000000)) 
    \starve_limit_cntr_r[2]_i_2__0 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[2]),
        .I3(Q[0]),
        .I4(demand_priority_r_reg_4),
        .I5(req_bank_rdy_r),
        .O(starve_limit_cntr_r0));
  FDRE \starve_limit_cntr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[0]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[0]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[1]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[1]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[2]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[2]),
        .R(1'b0));
  FDRE \wr_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(start_wtp_timer0),
        .Q(wr_this_rank_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_state" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_state__parameterized1
   (act_wait_r_lcl_reg_0,
    act_this_rank_r,
    wr_this_rank_r,
    rd_this_rank_r,
    bm_end_r1_1,
    ras_timer_zero_r,
    pre_wait_r,
    col_wait_r,
    demand_act_priority_r,
    demand_priority_r_reg_0,
    demanded_prior_r_reg_0,
    override_demand_r_reg_0,
    override_demand_r_reg_1,
    demanded_prior_r_reg_1,
    override_demand_r_reg_2,
    override_demand_r_reg_3,
    col_wait_r_reg_0,
    col_wait_r_reg_1,
    col_wait_r_reg_2,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    ras_timer_zero_r_reg_0,
    auto_pre_r_lcl_reg,
    \ras_timer_r_reg[1]_0 ,
    bm_end_r1_reg_0,
    act_wait_r_lcl_reg_1,
    demand_priority_r_reg_1,
    act_wait_ns,
    CLK,
    start_wtp_timer0,
    \rd_this_rank_r_reg[0]_0 ,
    bm_end_r1_reg_1,
    req_bank_rdy_ns,
    override_demand_ns,
    SR,
    ofs_rdy_r0,
    \rtp_timer_r_reg[1]_0 ,
    Q,
    col_wait_r_reg_3,
    demanded_prior_r_0,
    demand_priority_r_1,
    demand_priority_r_2,
    demanded_prior_r_3,
    demand_priority_r_4,
    demanded_prior_r_reg_2,
    demanded_prior_r_5,
    pass_open_bank_r,
    \grant_r_reg[1] ,
    \grant_r_reg[0] ,
    \grant_r_reg[1]_0 ,
    granted_col_r_reg,
    granted_col_r_reg_0,
    demand_priority_r_reg_2,
    demand_priority_r_reg_3,
    \grant_r[0]_i_2_0 ,
    \grant_r[0]_i_2_1 ,
    pre_bm_end_r_reg,
    pre_bm_end_r_reg_0,
    pass_open_bank_ns,
    pre_wait_r_reg_0,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    demand_act_priority_r_reg_0,
    head_r,
    idle_r,
    ras_timer_zero_r_reg_1,
    \grant_r[3]_i_5__1 ,
    demand_priority_r_reg_4,
    req_wr_r,
    q_has_rd,
    \rtp_timer_r_reg[0]_0 ,
    D);
  output act_wait_r_lcl_reg_0;
  output [0:0]act_this_rank_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output bm_end_r1_1;
  output ras_timer_zero_r;
  output pre_wait_r;
  output col_wait_r;
  output demand_act_priority_r;
  output demand_priority_r_reg_0;
  output demanded_prior_r_reg_0;
  output override_demand_r_reg_0;
  output override_demand_r_reg_1;
  output demanded_prior_r_reg_1;
  output override_demand_r_reg_2;
  output override_demand_r_reg_3;
  output col_wait_r_reg_0;
  output col_wait_r_reg_1;
  output col_wait_r_reg_2;
  output pre_bm_end_ns;
  output pre_passing_open_bank_ns;
  output ras_timer_zero_r_reg_0;
  output auto_pre_r_lcl_reg;
  output \ras_timer_r_reg[1]_0 ;
  output bm_end_r1_reg_0;
  output act_wait_r_lcl_reg_1;
  output demand_priority_r_reg_1;
  input act_wait_ns;
  input CLK;
  input start_wtp_timer0;
  input \rd_this_rank_r_reg[0]_0 ;
  input [0:0]bm_end_r1_reg_1;
  input req_bank_rdy_ns;
  input override_demand_ns;
  input [0:0]SR;
  input ofs_rdy_r0;
  input \rtp_timer_r_reg[1]_0 ;
  input [3:0]Q;
  input col_wait_r_reg_3;
  input demanded_prior_r_0;
  input demand_priority_r_1;
  input demand_priority_r_2;
  input demanded_prior_r_3;
  input demand_priority_r_4;
  input demanded_prior_r_reg_2;
  input demanded_prior_r_5;
  input pass_open_bank_r;
  input \grant_r_reg[1] ;
  input \grant_r_reg[0] ;
  input \grant_r_reg[1]_0 ;
  input granted_col_r_reg;
  input granted_col_r_reg_0;
  input demand_priority_r_reg_2;
  input demand_priority_r_reg_3;
  input \grant_r[0]_i_2_0 ;
  input \grant_r[0]_i_2_1 ;
  input [0:0]pre_bm_end_r_reg;
  input pre_bm_end_r_reg_0;
  input pass_open_bank_ns;
  input pre_wait_r_reg_0;
  input \pre_4_1_1T_arb.granted_pre_r_reg ;
  input demand_act_priority_r_reg_0;
  input [0:0]head_r;
  input [0:0]idle_r;
  input ras_timer_zero_r_reg_1;
  input [0:0]\grant_r[3]_i_5__1 ;
  input demand_priority_r_reg_4;
  input [0:0]req_wr_r;
  input q_has_rd;
  input \rtp_timer_r_reg[0]_0 ;
  input [1:0]D;

  wire CLK;
  wire [1:0]D;
  wire [3:0]Q;
  wire [0:0]SR;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg;
  wire bm_end_r1_1;
  wire bm_end_r1_reg_0;
  wire [0:0]bm_end_r1_reg_1;
  wire col_wait_r;
  wire col_wait_r_i_1__0_n_0;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire col_wait_r_reg_2;
  wire col_wait_r_reg_3;
  wire demand_act_priority_ns;
  wire demand_act_priority_r;
  wire demand_act_priority_r_reg_0;
  wire demand_priority_ns;
  wire demand_priority_r_1;
  wire demand_priority_r_2;
  wire demand_priority_r_4;
  wire demand_priority_r_i_3__1_n_0;
  wire demand_priority_r_i_4__1_n_0;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire demand_priority_r_reg_3;
  wire demand_priority_r_reg_4;
  wire demanded_prior_ns;
  wire demanded_prior_r_0;
  wire demanded_prior_r_3;
  wire demanded_prior_r_5;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire demanded_prior_r_reg_2;
  wire \grant_r[0]_i_2_0 ;
  wire \grant_r[0]_i_2_1 ;
  wire \grant_r[3]_i_13_n_0 ;
  wire \grant_r[3]_i_21_n_0 ;
  wire [0:0]\grant_r[3]_i_5__1 ;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire [0:0]head_r;
  wire [0:0]idle_r;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire override_demand_ns;
  wire override_demand_r_reg_0;
  wire override_demand_r_reg_1;
  wire override_demand_r_reg_2;
  wire override_demand_r_reg_3;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire \pre_4_1_1T_arb.granted_pre_r_reg ;
  wire pre_bm_end_ns;
  wire [0:0]pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_wait_ns;
  wire pre_wait_r;
  wire pre_wait_r_i_2__1_n_0;
  wire pre_wait_r_reg_0;
  wire q_has_rd;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg_n_0_[0] ;
  wire \ras_timer_r_reg_n_0_[1] ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_i_1__1_n_0;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire [0:0]rd_this_rank_r;
  wire \rd_this_rank_r_reg[0]_0 ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r;
  wire [0:0]req_wr_r;
  wire [1:0]rtp_timer_r;
  wire \rtp_timer_r[0]_i_1__1_n_0 ;
  wire \rtp_timer_r[1]_i_1__1_n_0 ;
  wire \rtp_timer_r_reg[0]_0 ;
  wire \rtp_timer_r_reg[1]_0 ;
  wire start_wtp_timer0;
  wire [2:0]starve_limit_cntr_r;
  wire starve_limit_cntr_r0;
  wire \starve_limit_cntr_r[0]_i_1_n_0 ;
  wire \starve_limit_cntr_r[1]_i_1_n_0 ;
  wire \starve_limit_cntr_r[2]_i_1_n_0 ;
  wire [0:0]wr_this_rank_r;

  FDRE \act_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(act_wait_r_lcl_reg_0),
        .Q(act_this_rank_r),
        .R(1'b0));
  FDRE act_wait_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(act_wait_ns),
        .Q(act_wait_r_lcl_reg_0),
        .R(1'b0));
  FDRE bm_end_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(bm_end_r1_reg_1),
        .Q(bm_end_r1_1),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h5504)) 
    col_wait_r_i_1__0
       (.I0(\rtp_timer_r_reg[1]_0 ),
        .I1(col_wait_r),
        .I2(Q[2]),
        .I3(col_wait_r_reg_3),
        .O(col_wait_r_i_1__0_n_0));
  FDRE col_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(col_wait_r_i_1__0_n_0),
        .Q(col_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    demand_act_priority_r_i_1__1
       (.I0(demand_act_priority_r),
        .I1(ras_timer_zero_r),
        .I2(demand_act_priority_r_reg_0),
        .I3(head_r),
        .I4(idle_r),
        .I5(act_wait_r_lcl_reg_0),
        .O(demand_act_priority_ns));
  FDRE demand_act_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_act_priority_ns),
        .Q(demand_act_priority_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h88888808)) 
    demand_priority_r_i_1__0
       (.I0(col_wait_r_i_1__0_n_0),
        .I1(demand_priority_r_reg_2),
        .I2(demand_priority_r_reg_3),
        .I3(demand_priority_r_i_3__1_n_0),
        .I4(demand_priority_r_reg_0),
        .O(demand_priority_ns));
  LUT6 #(
    .INIT(64'h0000000040400040)) 
    demand_priority_r_i_3__1
       (.I0(Q[2]),
        .I1(demand_priority_r_reg_4),
        .I2(req_bank_rdy_r),
        .I3(req_wr_r),
        .I4(q_has_rd),
        .I5(demand_priority_r_i_4__1_n_0),
        .O(demand_priority_r_i_3__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair600" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    demand_priority_r_i_4__1
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[0]),
        .O(demand_priority_r_i_4__1_n_0));
  FDRE demand_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_priority_ns),
        .Q(demand_priority_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0DDD0D0)) 
    demanded_prior_r_i_1__0
       (.I0(demand_priority_r_reg_0),
        .I1(demanded_prior_r_reg_0),
        .I2(demanded_prior_r_reg_2),
        .I3(Q[1]),
        .I4(demand_priority_r_4),
        .I5(demanded_prior_r_3),
        .O(demanded_prior_ns));
  LUT6 #(
    .INIT(64'hFBFBFBFBFB00FBFB)) 
    demanded_prior_r_i_2__0
       (.I0(demanded_prior_r_reg_0),
        .I1(demand_priority_r_reg_0),
        .I2(Q[2]),
        .I3(demanded_prior_r_3),
        .I4(demand_priority_r_4),
        .I5(Q[1]),
        .O(demanded_prior_r_reg_1));
  FDRE demanded_prior_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demanded_prior_ns),
        .Q(demanded_prior_r_reg_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h1110FFFF)) 
    \grant_r[0]_i_2 
       (.I0(\grant_r_reg[1] ),
        .I1(\grant_r[3]_i_13_n_0 ),
        .I2(col_wait_r),
        .I3(col_wait_r_reg_3),
        .I4(\grant_r_reg[0] ),
        .O(col_wait_r_reg_0));
  LUT5 #(
    .INIT(32'h02020200)) 
    \grant_r[1]_i_2 
       (.I0(\grant_r_reg[1]_0 ),
        .I1(\grant_r_reg[1] ),
        .I2(\grant_r[3]_i_13_n_0 ),
        .I3(col_wait_r),
        .I4(col_wait_r_reg_3),
        .O(col_wait_r_reg_1));
  LUT6 #(
    .INIT(64'h0000000011111511)) 
    \grant_r[2]_i_6__0 
       (.I0(override_demand_r_reg_0),
        .I1(demanded_prior_r_reg_1),
        .I2(demanded_prior_r_0),
        .I3(demand_priority_r_1),
        .I4(Q[3]),
        .I5(demand_priority_r_2),
        .O(override_demand_r_reg_1));
  LUT5 #(
    .INIT(32'hBBBBBABB)) 
    \grant_r[3]_i_11__1 
       (.I0(demand_priority_r_4),
        .I1(demanded_prior_r_reg_2),
        .I2(Q[2]),
        .I3(demand_priority_r_reg_0),
        .I4(demanded_prior_r_reg_0),
        .O(demand_priority_r_reg_1));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \grant_r[3]_i_13 
       (.I0(\grant_r[3]_i_21_n_0 ),
        .I1(\grant_r[0]_i_2_0 ),
        .I2(Q[2]),
        .I3(ofs_rdy_r),
        .I4(override_demand_ns),
        .I5(\grant_r[0]_i_2_1 ),
        .O(\grant_r[3]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \grant_r[3]_i_15 
       (.I0(act_wait_r_lcl_reg_0),
        .I1(\grant_r[3]_i_5__1 ),
        .O(act_wait_r_lcl_reg_1));
  LUT6 #(
    .INIT(64'h0000000011111511)) 
    \grant_r[3]_i_16 
       (.I0(override_demand_r_reg_0),
        .I1(demanded_prior_r_reg_1),
        .I2(demanded_prior_r_5),
        .I3(demand_priority_r_2),
        .I4(Q[0]),
        .I5(demand_priority_r_1),
        .O(override_demand_r_reg_3));
  LUT6 #(
    .INIT(64'h0000000055550010)) 
    \grant_r[3]_i_20 
       (.I0(override_demand_r_reg_0),
        .I1(demanded_prior_r_reg_0),
        .I2(demand_priority_r_reg_0),
        .I3(Q[2]),
        .I4(demanded_prior_r_reg_2),
        .I5(demand_priority_r_4),
        .O(override_demand_r_reg_2));
  LUT6 #(
    .INIT(64'h0000000055550010)) 
    \grant_r[3]_i_21 
       (.I0(override_demand_r_reg_0),
        .I1(demanded_prior_r_3),
        .I2(demand_priority_r_4),
        .I3(Q[1]),
        .I4(demanded_prior_r_reg_2),
        .I5(demand_priority_r_reg_0),
        .O(\grant_r[3]_i_21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair598" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \grant_r[3]_i_2__2 
       (.I0(pre_bm_end_r_reg_0),
        .I1(pre_bm_end_r_reg),
        .I2(pre_wait_r),
        .I3(ras_timer_zero_r),
        .O(auto_pre_r_lcl_reg));
  LUT6 #(
    .INIT(64'hFFF1FFFFFFF1F1F1)) 
    \grant_r[3]_i_5 
       (.I0(col_wait_r_reg_3),
        .I1(col_wait_r),
        .I2(\grant_r[3]_i_13_n_0 ),
        .I3(granted_col_r_reg),
        .I4(\rd_this_rank_r_reg[0]_0 ),
        .I5(granted_col_r_reg_0),
        .O(col_wait_r_reg_2));
  FDRE #(
    .INIT(1'b0)) 
    ofs_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ofs_rdy_r0),
        .Q(ofs_rdy_r),
        .R(SR));
  FDRE override_demand_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(override_demand_ns),
        .Q(override_demand_r_reg_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000FFF7)) 
    \pre_4_1_1T_arb.granted_pre_r_i_2 
       (.I0(ras_timer_zero_r),
        .I1(pre_wait_r),
        .I2(pre_bm_end_r_reg),
        .I3(pre_bm_end_r_reg_0),
        .I4(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .O(ras_timer_zero_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair598" *) 
  LUT5 #(
    .INIT(32'hEAEAEAAA)) 
    pre_bm_end_r_i_1__1
       (.I0(pre_passing_open_bank_ns),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_bm_end_ns));
  LUT6 #(
    .INIT(64'hAAA8AAAAAAA8AAA8)) 
    pre_passing_open_bank_r_i_1__1
       (.I0(pass_open_bank_ns),
        .I1(Q[2]),
        .I2(rtp_timer_r[0]),
        .I3(rtp_timer_r[1]),
        .I4(ras_timer_zero_r),
        .I5(pre_wait_r),
        .O(pre_passing_open_bank_ns));
  LUT6 #(
    .INIT(64'h4444444444454444)) 
    pre_wait_r_i_1__1
       (.I0(pass_open_bank_ns),
        .I1(pre_wait_r_i_2__1_n_0),
        .I2(pass_open_bank_r),
        .I3(pre_wait_r_reg_0),
        .I4(rtp_timer_r[0]),
        .I5(rtp_timer_r[1]),
        .O(pre_wait_ns));
  LUT5 #(
    .INIT(32'h10101050)) 
    pre_wait_r_i_2__1
       (.I0(pre_wait_r_reg_0),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_wait_r_i_2__1_n_0));
  FDRE pre_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_wait_ns),
        .Q(pre_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000EFF0E0E)) 
    \ras_timer_r[0]_i_3__1 
       (.I0(act_wait_r_lcl_reg_1),
        .I1(\ras_timer_r_reg_n_0_[1] ),
        .I2(\ras_timer_r_reg_n_0_[0] ),
        .I3(\rd_this_rank_r_reg[0]_0 ),
        .I4(Q[2]),
        .I5(ras_timer_zero_r_reg_1),
        .O(\ras_timer_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h1000111110001000)) 
    \ras_timer_r[1]_i_4__1 
       (.I0(bm_end_r1_1),
        .I1(pre_wait_r_reg_0),
        .I2(\ras_timer_r_reg_n_0_[1] ),
        .I3(\ras_timer_r_reg_n_0_[0] ),
        .I4(\rd_this_rank_r_reg[0]_0 ),
        .I5(Q[2]),
        .O(bm_end_r1_reg_0));
  FDRE \ras_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\ras_timer_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \ras_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\ras_timer_r_reg_n_0_[1] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h1)) 
    ras_timer_zero_r_i_1__1
       (.I0(\ras_timer_r_reg[1]_0 ),
        .I1(bm_end_r1_reg_0),
        .O(ras_timer_zero_r_i_1__1_n_0));
  FDRE ras_timer_zero_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ras_timer_zero_r_i_1__1_n_0),
        .Q(ras_timer_zero_r),
        .R(1'b0));
  FDRE \rd_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_this_rank_r_reg[0]_0 ),
        .Q(rd_this_rank_r),
        .R(1'b0));
  FDRE req_bank_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(req_bank_rdy_ns),
        .Q(req_bank_rdy_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0010)) 
    \rtp_timer_r[0]_i_1__1 
       (.I0(\rtp_timer_r_reg[0]_0 ),
        .I1(pass_open_bank_r),
        .I2(rtp_timer_r[1]),
        .I3(rtp_timer_r[0]),
        .O(\rtp_timer_r[0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h000000C2)) 
    \rtp_timer_r[1]_i_1__1 
       (.I0(Q[2]),
        .I1(rtp_timer_r[0]),
        .I2(rtp_timer_r[1]),
        .I3(pass_open_bank_r),
        .I4(\rtp_timer_r_reg[1]_0 ),
        .O(\rtp_timer_r[1]_i_1__1_n_0 ));
  FDRE \rtp_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[0]_i_1__1_n_0 ),
        .Q(rtp_timer_r[0]),
        .R(1'b0));
  FDRE \rtp_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[1]_i_1__1_n_0 ),
        .Q(rtp_timer_r[1]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair600" *) 
  LUT3 #(
    .INIT(8'h60)) 
    \starve_limit_cntr_r[0]_i_1 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r0),
        .I2(col_wait_r),
        .O(\starve_limit_cntr_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair599" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \starve_limit_cntr_r[1]_i_1 
       (.I0(starve_limit_cntr_r[1]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(col_wait_r),
        .O(\starve_limit_cntr_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair599" *) 
  LUT5 #(
    .INIT(32'h6AAA0000)) 
    \starve_limit_cntr_r[2]_i_1 
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(starve_limit_cntr_r[1]),
        .I4(col_wait_r),
        .O(\starve_limit_cntr_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h007F000000000000)) 
    \starve_limit_cntr_r[2]_i_2__1 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[2]),
        .I3(Q[2]),
        .I4(demand_priority_r_reg_4),
        .I5(req_bank_rdy_r),
        .O(starve_limit_cntr_r0));
  FDRE \starve_limit_cntr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[0]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[0]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[1]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[1]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[2]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[2]),
        .R(1'b0));
  FDRE \wr_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(start_wtp_timer0),
        .Q(wr_this_rank_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_state" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_state__parameterized2
   (act_wait_r_lcl_reg_0,
    act_this_rank_r,
    wr_this_rank_r,
    rd_this_rank_r,
    bm_end_r1_2,
    ras_timer_zero_r,
    pre_wait_r,
    col_wait_r,
    col_wait_r_reg_0,
    demand_act_priority_r,
    demand_priority_r_reg_0,
    demanded_prior_r_reg_0,
    ofs_rdy_r,
    col_wait_r_reg_1,
    act_wait_r_lcl_reg_1,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    auto_pre_r_lcl_reg,
    bm_end_r1_reg_0,
    \ras_timer_r_reg[1]_0 ,
    demand_priority_r_reg_1,
    demanded_prior_r_reg_1,
    demand_priority_r_reg_2,
    act_wait_ns,
    CLK,
    start_wtp_timer0,
    \rd_this_rank_r_reg[0]_0 ,
    bm_end_r1_reg_1,
    req_bank_rdy_ns,
    demand_priority_ns,
    SR,
    ofs_rdy_r0,
    \rtp_timer_r_reg[1]_0 ,
    Q,
    col_wait_r_reg_2,
    col_wait_r_reg_3,
    pass_open_bank_r,
    \grant_r[3]_i_6 ,
    \grant_r[3]_i_6_0 ,
    \grant_r[3]_i_6_1 ,
    \grant_r[3]_i_6_2 ,
    pre_bm_end_r_reg,
    pre_bm_end_r_reg_0,
    pass_open_bank_ns,
    pre_wait_r_reg_0,
    demand_act_priority_r_reg_0,
    head_r,
    idle_r,
    ras_timer_zero_r_reg_0,
    demand_priority_r_0,
    demanded_prior_r_reg_2,
    demanded_prior_r_1,
    \starve_limit_cntr_r_reg[0]_0 ,
    q_has_rd,
    req_wr_r,
    \rtp_timer_r_reg[0]_0 ,
    D);
  output act_wait_r_lcl_reg_0;
  output [0:0]act_this_rank_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output bm_end_r1_2;
  output ras_timer_zero_r;
  output pre_wait_r;
  output col_wait_r;
  output col_wait_r_reg_0;
  output demand_act_priority_r;
  output demand_priority_r_reg_0;
  output demanded_prior_r_reg_0;
  output ofs_rdy_r;
  output col_wait_r_reg_1;
  output act_wait_r_lcl_reg_1;
  output pre_bm_end_ns;
  output pre_passing_open_bank_ns;
  output auto_pre_r_lcl_reg;
  output bm_end_r1_reg_0;
  output \ras_timer_r_reg[1]_0 ;
  output demand_priority_r_reg_1;
  output demanded_prior_r_reg_1;
  output demand_priority_r_reg_2;
  input act_wait_ns;
  input CLK;
  input start_wtp_timer0;
  input \rd_this_rank_r_reg[0]_0 ;
  input [0:0]bm_end_r1_reg_1;
  input req_bank_rdy_ns;
  input demand_priority_ns;
  input [0:0]SR;
  input ofs_rdy_r0;
  input \rtp_timer_r_reg[1]_0 ;
  input [1:0]Q;
  input [0:0]col_wait_r_reg_2;
  input col_wait_r_reg_3;
  input pass_open_bank_r;
  input \grant_r[3]_i_6 ;
  input \grant_r[3]_i_6_0 ;
  input \grant_r[3]_i_6_1 ;
  input \grant_r[3]_i_6_2 ;
  input [0:0]pre_bm_end_r_reg;
  input pre_bm_end_r_reg_0;
  input pass_open_bank_ns;
  input pre_wait_r_reg_0;
  input demand_act_priority_r_reg_0;
  input [0:0]head_r;
  input [0:0]idle_r;
  input ras_timer_zero_r_reg_0;
  input demand_priority_r_0;
  input demanded_prior_r_reg_2;
  input demanded_prior_r_1;
  input \starve_limit_cntr_r_reg[0]_0 ;
  input q_has_rd;
  input [0:0]req_wr_r;
  input \rtp_timer_r_reg[0]_0 ;
  input [1:0]D;

  wire CLK;
  wire [1:0]D;
  wire [1:0]Q;
  wire [0:0]SR;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg;
  wire bm_end_r1_2;
  wire bm_end_r1_reg_0;
  wire [0:0]bm_end_r1_reg_1;
  wire col_wait_r;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire [0:0]col_wait_r_reg_2;
  wire col_wait_r_reg_3;
  wire demand_act_priority_ns;
  wire demand_act_priority_r;
  wire demand_act_priority_r_reg_0;
  wire demand_priority_ns;
  wire demand_priority_r_0;
  wire demand_priority_r_i_5_n_0;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire demanded_prior_ns;
  wire demanded_prior_r_1;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire demanded_prior_r_reg_2;
  wire \grant_r[3]_i_6 ;
  wire \grant_r[3]_i_6_0 ;
  wire \grant_r[3]_i_6_1 ;
  wire \grant_r[3]_i_6_2 ;
  wire [0:0]head_r;
  wire [0:0]idle_r;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pre_bm_end_ns;
  wire [0:0]pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_wait_ns;
  wire pre_wait_r;
  wire pre_wait_r_i_2__2_n_0;
  wire pre_wait_r_reg_0;
  wire q_has_rd;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg_n_0_[0] ;
  wire \ras_timer_r_reg_n_0_[1] ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_i_1__2_n_0;
  wire ras_timer_zero_r_reg_0;
  wire [0:0]rd_this_rank_r;
  wire \rd_this_rank_r_reg[0]_0 ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r;
  wire [0:0]req_wr_r;
  wire [1:0]rtp_timer_r;
  wire \rtp_timer_r[0]_i_1__2_n_0 ;
  wire \rtp_timer_r[1]_i_1__2_n_0 ;
  wire \rtp_timer_r_reg[0]_0 ;
  wire \rtp_timer_r_reg[1]_0 ;
  wire start_wtp_timer0;
  wire [2:0]starve_limit_cntr_r;
  wire \starve_limit_cntr_r[0]_i_1_n_0 ;
  wire \starve_limit_cntr_r[1]_i_1_n_0 ;
  wire \starve_limit_cntr_r[2]_i_1_n_0 ;
  wire \starve_limit_cntr_r_reg[0]_0 ;
  wire [0:0]wr_this_rank_r;

  FDRE \act_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(act_wait_r_lcl_reg_0),
        .Q(act_this_rank_r),
        .R(1'b0));
  FDRE act_wait_r_lcl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(act_wait_ns),
        .Q(act_wait_r_lcl_reg_0),
        .R(1'b0));
  FDRE bm_end_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(bm_end_r1_reg_1),
        .Q(bm_end_r1_2),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h5555555555040404)) 
    col_wait_r_i_1
       (.I0(\rtp_timer_r_reg[1]_0 ),
        .I1(col_wait_r),
        .I2(Q[1]),
        .I3(col_wait_r_reg_2),
        .I4(act_wait_r_lcl_reg_0),
        .I5(col_wait_r_reg_3),
        .O(col_wait_r_reg_0));
  FDRE col_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(col_wait_r_reg_0),
        .Q(col_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    demand_act_priority_r_i_1__2
       (.I0(demand_act_priority_r),
        .I1(ras_timer_zero_r),
        .I2(demand_act_priority_r_reg_0),
        .I3(head_r),
        .I4(idle_r),
        .I5(act_wait_r_lcl_reg_0),
        .O(demand_act_priority_ns));
  FDRE demand_act_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_act_priority_ns),
        .Q(demand_act_priority_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAEAAAEAEAAAAAAAA)) 
    demand_priority_r_i_3__2
       (.I0(demand_priority_r_reg_0),
        .I1(req_bank_rdy_r),
        .I2(\starve_limit_cntr_r_reg[0]_0 ),
        .I3(q_has_rd),
        .I4(req_wr_r),
        .I5(demand_priority_r_i_5_n_0),
        .O(demand_priority_r_reg_2));
  LUT3 #(
    .INIT(8'h80)) 
    demand_priority_r_i_5
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[0]),
        .O(demand_priority_r_i_5_n_0));
  FDRE demand_priority_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demand_priority_ns),
        .Q(demand_priority_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000D00DDDDDDDD)) 
    demanded_prior_r_i_1__2
       (.I0(demand_priority_r_reg_0),
        .I1(demanded_prior_r_reg_0),
        .I2(Q[0]),
        .I3(demand_priority_r_0),
        .I4(demanded_prior_r_1),
        .I5(demanded_prior_r_reg_2),
        .O(demanded_prior_ns));
  LUT6 #(
    .INIT(64'h0404040404FF0404)) 
    demanded_prior_r_i_2
       (.I0(demanded_prior_r_reg_0),
        .I1(demand_priority_r_reg_0),
        .I2(Q[1]),
        .I3(demanded_prior_r_1),
        .I4(demand_priority_r_0),
        .I5(Q[0]),
        .O(demanded_prior_r_reg_1));
  FDRE demanded_prior_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(demanded_prior_ns),
        .Q(demanded_prior_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAFFFE)) 
    \grant_r[3]_i_18 
       (.I0(col_wait_r),
        .I1(\grant_r[3]_i_6 ),
        .I2(\grant_r[3]_i_6_0 ),
        .I3(\grant_r[3]_i_6_1 ),
        .I4(\grant_r[3]_i_6_2 ),
        .I5(act_wait_r_lcl_reg_1),
        .O(col_wait_r_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair604" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \grant_r[3]_i_5__2 
       (.I0(pre_bm_end_r_reg_0),
        .I1(pre_bm_end_r_reg),
        .I2(pre_wait_r),
        .I3(ras_timer_zero_r),
        .O(auto_pre_r_lcl_reg));
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    \grant_r[3]_i_8__1 
       (.I0(demand_priority_r_0),
        .I1(Q[1]),
        .I2(demand_priority_r_reg_0),
        .I3(demanded_prior_r_reg_0),
        .I4(demanded_prior_r_reg_2),
        .O(demand_priority_r_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    ofs_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ofs_rdy_r0),
        .Q(ofs_rdy_r),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair604" *) 
  LUT5 #(
    .INIT(32'hEAEAEAAA)) 
    pre_bm_end_r_i_1__0
       (.I0(pre_passing_open_bank_ns),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_bm_end_ns));
  LUT6 #(
    .INIT(64'hAAA8AAAAAAA8AAA8)) 
    pre_passing_open_bank_r_i_1__0
       (.I0(pass_open_bank_ns),
        .I1(Q[1]),
        .I2(rtp_timer_r[0]),
        .I3(rtp_timer_r[1]),
        .I4(ras_timer_zero_r),
        .I5(pre_wait_r),
        .O(pre_passing_open_bank_ns));
  LUT6 #(
    .INIT(64'h4444444444454444)) 
    pre_wait_r_i_1__0
       (.I0(pass_open_bank_ns),
        .I1(pre_wait_r_i_2__2_n_0),
        .I2(pass_open_bank_r),
        .I3(pre_wait_r_reg_0),
        .I4(rtp_timer_r[0]),
        .I5(rtp_timer_r[1]),
        .O(pre_wait_ns));
  LUT5 #(
    .INIT(32'h10101050)) 
    pre_wait_r_i_2__2
       (.I0(pre_wait_r_reg_0),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_wait_r_i_2__2_n_0));
  FDRE pre_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pre_wait_ns),
        .Q(pre_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000EFF0E0E)) 
    \ras_timer_r[0]_i_3__2 
       (.I0(act_wait_r_lcl_reg_1),
        .I1(\ras_timer_r_reg_n_0_[1] ),
        .I2(\ras_timer_r_reg_n_0_[0] ),
        .I3(\rd_this_rank_r_reg[0]_0 ),
        .I4(Q[1]),
        .I5(ras_timer_zero_r_reg_0),
        .O(\ras_timer_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h1000111110001000)) 
    \ras_timer_r[1]_i_4__2 
       (.I0(bm_end_r1_2),
        .I1(pre_wait_r_reg_0),
        .I2(\ras_timer_r_reg_n_0_[1] ),
        .I3(\ras_timer_r_reg_n_0_[0] ),
        .I4(\rd_this_rank_r_reg[0]_0 ),
        .I5(Q[1]),
        .O(bm_end_r1_reg_0));
  FDRE \ras_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(\ras_timer_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \ras_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(\ras_timer_r_reg_n_0_[1] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000F351)) 
    ras_timer_zero_r_i_1__2
       (.I0(act_wait_r_lcl_reg_1),
        .I1(Q[1]),
        .I2(\rd_this_rank_r_reg[0]_0 ),
        .I3(\ras_timer_r_reg_n_0_[0] ),
        .I4(\ras_timer_r_reg_n_0_[1] ),
        .I5(ras_timer_zero_r_reg_0),
        .O(ras_timer_zero_r_i_1__2_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    ras_timer_zero_r_i_2
       (.I0(act_wait_r_lcl_reg_0),
        .I1(col_wait_r_reg_2),
        .O(act_wait_r_lcl_reg_1));
  FDRE ras_timer_zero_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ras_timer_zero_r_i_1__2_n_0),
        .Q(ras_timer_zero_r),
        .R(1'b0));
  FDRE \rd_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_this_rank_r_reg[0]_0 ),
        .Q(rd_this_rank_r),
        .R(1'b0));
  FDRE req_bank_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(req_bank_rdy_ns),
        .Q(req_bank_rdy_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0010)) 
    \rtp_timer_r[0]_i_1__2 
       (.I0(\rtp_timer_r_reg[0]_0 ),
        .I1(pass_open_bank_r),
        .I2(rtp_timer_r[1]),
        .I3(rtp_timer_r[0]),
        .O(\rtp_timer_r[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h000000C2)) 
    \rtp_timer_r[1]_i_1__2 
       (.I0(Q[1]),
        .I1(rtp_timer_r[0]),
        .I2(rtp_timer_r[1]),
        .I3(pass_open_bank_r),
        .I4(\rtp_timer_r_reg[1]_0 ),
        .O(\rtp_timer_r[1]_i_1__2_n_0 ));
  FDRE \rtp_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[0]_i_1__2_n_0 ),
        .Q(rtp_timer_r[0]),
        .R(1'b0));
  FDRE \rtp_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rtp_timer_r[1]_i_1__2_n_0 ),
        .Q(rtp_timer_r[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAD5AA00000000)) 
    \starve_limit_cntr_r[0]_i_1 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[2]),
        .I3(req_bank_rdy_r),
        .I4(\starve_limit_cntr_r_reg[0]_0 ),
        .I5(col_wait_r),
        .O(\starve_limit_cntr_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB44FF0000000000)) 
    \starve_limit_cntr_r[1]_i_1 
       (.I0(\starve_limit_cntr_r_reg[0]_0 ),
        .I1(req_bank_rdy_r),
        .I2(starve_limit_cntr_r[2]),
        .I3(starve_limit_cntr_r[1]),
        .I4(starve_limit_cntr_r[0]),
        .I5(col_wait_r),
        .O(\starve_limit_cntr_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF4F0F0F000000000)) 
    \starve_limit_cntr_r[2]_i_1 
       (.I0(\starve_limit_cntr_r_reg[0]_0 ),
        .I1(req_bank_rdy_r),
        .I2(starve_limit_cntr_r[2]),
        .I3(starve_limit_cntr_r[1]),
        .I4(starve_limit_cntr_r[0]),
        .I5(col_wait_r),
        .O(\starve_limit_cntr_r[2]_i_1_n_0 ));
  FDRE \starve_limit_cntr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[0]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[0]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[1]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[1]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[2]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[2]),
        .R(1'b0));
  FDRE \wr_this_rank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(start_wtp_timer0),
        .Q(wr_this_rank_r),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_clk_ibuf
   (mmcm_clk,
    sys_clk_i);
  output mmcm_clk;
  input sys_clk_i;

  (* RTL_KEEP = "true" *) (* syn_keep = "true" *) wire sys_clk_ibufg;

  assign mmcm_clk = sys_clk_ibufg;
  assign sys_clk_ibufg = sys_clk_i;
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_col_mach
   (D,
    mc_wrdata_en_ns,
    wr_data_en_ns,
    \read_fifo.tail_r_reg[0]_0 ,
    mc_ref_zq_wip_ns,
    \read_fifo.fifo_out_data_r_reg[7]_0 ,
    CLK,
    DIC,
    col_rd_wr,
    mc_cmd,
    col_wr_data_buf_addr,
    \read_fifo.fifo_out_data_r_reg[7]_1 ,
    \read_fifo.tail_r_reg[1]_0 ,
    \read_fifo.fifo_out_data_r_reg[7]_2 ,
    maint_ref_zq_wip,
    in0,
    E,
    \read_fifo.tail_r_reg[0]_1 );
  output [3:0]D;
  output mc_wrdata_en_ns;
  output wr_data_en_ns;
  output \read_fifo.tail_r_reg[0]_0 ;
  output mc_ref_zq_wip_ns;
  output [1:0]\read_fifo.fifo_out_data_r_reg[7]_0 ;
  input CLK;
  input [0:0]DIC;
  input col_rd_wr;
  input [0:0]mc_cmd;
  input [3:0]col_wr_data_buf_addr;
  input \read_fifo.fifo_out_data_r_reg[7]_1 ;
  input \read_fifo.tail_r_reg[1]_0 ;
  input \read_fifo.fifo_out_data_r_reg[7]_2 ;
  input maint_ref_zq_wip;
  input in0;
  input [0:0]E;
  input \read_fifo.tail_r_reg[0]_1 ;

  wire CLK;
  wire [3:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire col_rd_wr;
  wire col_rd_wr_r1;
  wire col_rd_wr_r2;
  wire [3:0]col_wr_data_buf_addr;
  wire in0;
  wire maint_ref_zq_wip;
  wire [0:0]mc_cmd;
  wire mc_ref_zq_wip_ns;
  wire mc_ref_zq_wip_r_i_2_n_0;
  wire mc_wrdata_en_ns;
  wire [4:0]p_0_in;
  wire [7:6]\read_fifo.fifo_out_data_ns ;
  wire [1:0]\read_fifo.fifo_out_data_r_reg[7]_0 ;
  wire \read_fifo.fifo_out_data_r_reg[7]_1 ;
  wire \read_fifo.fifo_out_data_r_reg[7]_2 ;
  wire \read_fifo.fifo_ram[1].RAM32M0_i_1_n_0 ;
  wire \read_fifo.fifo_ram[1].RAM32M0_i_3_n_0 ;
  wire \read_fifo.fifo_ram[1].RAM32M0_i_4_n_0 ;
  wire [4:0]\read_fifo.head_r_reg ;
  wire [3:0]\read_fifo.tail_ns ;
  wire \read_fifo.tail_r[1]_i_1_n_0 ;
  wire \read_fifo.tail_r[2]_i_1_n_0 ;
  wire \read_fifo.tail_r[3]_i_1_n_0 ;
  wire \read_fifo.tail_r[4]_i_1_n_0 ;
  wire [4:1]\read_fifo.tail_r_reg ;
  wire \read_fifo.tail_r_reg[0]_0 ;
  wire \read_fifo.tail_r_reg[0]_1 ;
  wire \read_fifo.tail_r_reg[1]_0 ;
  wire sent_col_r2;
  wire wr_data_en_ns;
  wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED ;
  wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED ;
  wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED ;

  LUT2 #(
    .INIT(4'h2)) 
    \cmd_pipe_plus.mc_wrdata_en_i_1 
       (.I0(sent_col_r2),
        .I1(col_rd_wr_r2),
        .O(mc_wrdata_en_ns));
  LUT2 #(
    .INIT(4'h2)) 
    \cmd_pipe_plus.wr_data_en_i_1 
       (.I0(mc_cmd),
        .I1(col_rd_wr_r1),
        .O(wr_data_en_ns));
  FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr[0]),
        .Q(D[0]),
        .R(1'b0));
  FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr[1]),
        .Q(D[1]),
        .R(1'b0));
  FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr[2]),
        .Q(D[2]),
        .R(1'b0));
  FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(col_wr_data_buf_addr[3]),
        .Q(D[3]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0082000000000082)) 
    mc_ref_zq_wip_r_i_1
       (.I0(maint_ref_zq_wip),
        .I1(\read_fifo.tail_r_reg [4]),
        .I2(\read_fifo.head_r_reg [4]),
        .I3(mc_ref_zq_wip_r_i_2_n_0),
        .I4(\read_fifo.head_r_reg [3]),
        .I5(\read_fifo.tail_r_reg [3]),
        .O(mc_ref_zq_wip_ns));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    mc_ref_zq_wip_r_i_2
       (.I0(\read_fifo.tail_r_reg[0]_0 ),
        .I1(\read_fifo.head_r_reg [0]),
        .I2(\read_fifo.head_r_reg [1]),
        .I3(\read_fifo.tail_r_reg [1]),
        .I4(\read_fifo.head_r_reg [2]),
        .I5(\read_fifo.tail_r_reg [2]),
        .O(mc_ref_zq_wip_r_i_2_n_0));
  FDRE \offset_pipe_0.col_rd_wr_r1_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(col_rd_wr),
        .Q(col_rd_wr_r1),
        .R(1'b0));
  FDRE \offset_pipe_1.col_rd_wr_r2_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(col_rd_wr_r1),
        .Q(col_rd_wr_r2),
        .R(1'b0));
  FDRE \read_fifo.fifo_out_data_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\read_fifo.fifo_out_data_ns [6]),
        .Q(\read_fifo.fifo_out_data_r_reg[7]_0 [0]),
        .R(1'b0));
  FDRE \read_fifo.fifo_out_data_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\read_fifo.fifo_out_data_ns [7]),
        .Q(\read_fifo.fifo_out_data_r_reg[7]_0 [1]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \read_fifo.fifo_ram[1].RAM32M0 
       (.ADDRA({\read_fifo.fifo_ram[1].RAM32M0_i_1_n_0 ,\read_fifo.tail_ns [3],\read_fifo.fifo_ram[1].RAM32M0_i_3_n_0 ,\read_fifo.fifo_ram[1].RAM32M0_i_4_n_0 ,\read_fifo.tail_ns [0]}),
        .ADDRB({\read_fifo.fifo_ram[1].RAM32M0_i_1_n_0 ,\read_fifo.tail_ns [3],\read_fifo.fifo_ram[1].RAM32M0_i_3_n_0 ,\read_fifo.fifo_ram[1].RAM32M0_i_4_n_0 ,\read_fifo.tail_ns [0]}),
        .ADDRC({\read_fifo.fifo_ram[1].RAM32M0_i_1_n_0 ,\read_fifo.tail_ns [3],\read_fifo.fifo_ram[1].RAM32M0_i_3_n_0 ,\read_fifo.fifo_ram[1].RAM32M0_i_4_n_0 ,\read_fifo.tail_ns [0]}),
        .ADDRD(\read_fifo.head_r_reg ),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b1,DIC}),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED [1:0]),
        .DOB(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED [1:0]),
        .DOC(\read_fifo.fifo_out_data_ns ),
        .DOD(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(1'b1));
  LUT6 #(
    .INIT(64'h1555555540000000)) 
    \read_fifo.fifo_ram[1].RAM32M0_i_1 
       (.I0(\read_fifo.fifo_out_data_r_reg[7]_1 ),
        .I1(\read_fifo.tail_r_reg [3]),
        .I2(\read_fifo.tail_r_reg [2]),
        .I3(\read_fifo.fifo_out_data_r_reg[7]_2 ),
        .I4(\read_fifo.tail_r_reg [1]),
        .I5(\read_fifo.tail_r_reg [4]),
        .O(\read_fifo.fifo_ram[1].RAM32M0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000007FFF8000)) 
    \read_fifo.fifo_ram[1].RAM32M0_i_2 
       (.I0(\read_fifo.tail_r_reg [1]),
        .I1(\read_fifo.tail_r_reg[1]_0 ),
        .I2(\read_fifo.tail_r_reg[0]_0 ),
        .I3(\read_fifo.tail_r_reg [2]),
        .I4(\read_fifo.tail_r_reg [3]),
        .I5(\read_fifo.fifo_out_data_r_reg[7]_1 ),
        .O(\read_fifo.tail_ns [3]));
  LUT5 #(
    .INIT(32'h15554000)) 
    \read_fifo.fifo_ram[1].RAM32M0_i_3 
       (.I0(\read_fifo.fifo_out_data_r_reg[7]_1 ),
        .I1(\read_fifo.tail_r_reg[0]_0 ),
        .I2(\read_fifo.tail_r_reg[1]_0 ),
        .I3(\read_fifo.tail_r_reg [1]),
        .I4(\read_fifo.tail_r_reg [2]),
        .O(\read_fifo.fifo_ram[1].RAM32M0_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h1540)) 
    \read_fifo.fifo_ram[1].RAM32M0_i_4 
       (.I0(\read_fifo.fifo_out_data_r_reg[7]_1 ),
        .I1(\read_fifo.tail_r_reg[1]_0 ),
        .I2(\read_fifo.tail_r_reg[0]_0 ),
        .I3(\read_fifo.tail_r_reg [1]),
        .O(\read_fifo.fifo_ram[1].RAM32M0_i_4_n_0 ));
  LUT3 #(
    .INIT(8'h06)) 
    \read_fifo.fifo_ram[1].RAM32M0_i_5 
       (.I0(\read_fifo.tail_r_reg[0]_0 ),
        .I1(\read_fifo.tail_r_reg[1]_0 ),
        .I2(\read_fifo.fifo_out_data_r_reg[7]_1 ),
        .O(\read_fifo.tail_ns [0]));
  LUT1 #(
    .INIT(2'h1)) 
    \read_fifo.head_r[0]_i_1 
       (.I0(\read_fifo.head_r_reg [0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair613" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \read_fifo.head_r[1]_i_1 
       (.I0(\read_fifo.head_r_reg [0]),
        .I1(\read_fifo.head_r_reg [1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair613" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \read_fifo.head_r[2]_i_1 
       (.I0(\read_fifo.head_r_reg [2]),
        .I1(\read_fifo.head_r_reg [1]),
        .I2(\read_fifo.head_r_reg [0]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair612" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \read_fifo.head_r[3]_i_1 
       (.I0(\read_fifo.head_r_reg [3]),
        .I1(\read_fifo.head_r_reg [0]),
        .I2(\read_fifo.head_r_reg [1]),
        .I3(\read_fifo.head_r_reg [2]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair612" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \read_fifo.head_r[4]_i_1 
       (.I0(\read_fifo.head_r_reg [4]),
        .I1(\read_fifo.head_r_reg [2]),
        .I2(\read_fifo.head_r_reg [1]),
        .I3(\read_fifo.head_r_reg [0]),
        .I4(\read_fifo.head_r_reg [3]),
        .O(p_0_in[4]));
  FDRE \read_fifo.head_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in[0]),
        .Q(\read_fifo.head_r_reg [0]),
        .R(in0));
  FDRE \read_fifo.head_r_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in[1]),
        .Q(\read_fifo.head_r_reg [1]),
        .R(in0));
  FDRE \read_fifo.head_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in[2]),
        .Q(\read_fifo.head_r_reg [2]),
        .R(in0));
  FDRE \read_fifo.head_r_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in[3]),
        .Q(\read_fifo.head_r_reg [3]),
        .R(in0));
  FDRE \read_fifo.head_r_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in[4]),
        .Q(\read_fifo.head_r_reg [4]),
        .R(in0));
  LUT3 #(
    .INIT(8'h78)) 
    \read_fifo.tail_r[1]_i_1 
       (.I0(\read_fifo.tail_r_reg[1]_0 ),
        .I1(\read_fifo.tail_r_reg[0]_0 ),
        .I2(\read_fifo.tail_r_reg [1]),
        .O(\read_fifo.tail_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair611" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \read_fifo.tail_r[2]_i_1 
       (.I0(\read_fifo.tail_r_reg[0]_0 ),
        .I1(\read_fifo.tail_r_reg[1]_0 ),
        .I2(\read_fifo.tail_r_reg [1]),
        .I3(\read_fifo.tail_r_reg [2]),
        .O(\read_fifo.tail_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair611" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \read_fifo.tail_r[3]_i_1 
       (.I0(\read_fifo.tail_r_reg [3]),
        .I1(\read_fifo.tail_r_reg [2]),
        .I2(\read_fifo.tail_r_reg[0]_0 ),
        .I3(\read_fifo.tail_r_reg[1]_0 ),
        .I4(\read_fifo.tail_r_reg [1]),
        .O(\read_fifo.tail_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \read_fifo.tail_r[4]_i_1 
       (.I0(\read_fifo.tail_r_reg [3]),
        .I1(\read_fifo.tail_r_reg [2]),
        .I2(\read_fifo.tail_r_reg[0]_0 ),
        .I3(\read_fifo.tail_r_reg[1]_0 ),
        .I4(\read_fifo.tail_r_reg [1]),
        .I5(\read_fifo.tail_r_reg [4]),
        .O(\read_fifo.tail_r[4]_i_1_n_0 ));
  FDRE \read_fifo.tail_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\read_fifo.tail_r_reg[0]_1 ),
        .Q(\read_fifo.tail_r_reg[0]_0 ),
        .R(in0));
  FDRE \read_fifo.tail_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\read_fifo.tail_r[1]_i_1_n_0 ),
        .Q(\read_fifo.tail_r_reg [1]),
        .R(in0));
  FDRE \read_fifo.tail_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\read_fifo.tail_r[2]_i_1_n_0 ),
        .Q(\read_fifo.tail_r_reg [2]),
        .R(in0));
  FDRE \read_fifo.tail_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\read_fifo.tail_r[3]_i_1_n_0 ),
        .Q(\read_fifo.tail_r_reg [3]),
        .R(in0));
  FDRE \read_fifo.tail_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\read_fifo.tail_r[4]_i_1_n_0 ),
        .Q(\read_fifo.tail_r_reg [4]),
        .R(in0));
  FDRE sent_col_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mc_cmd),
        .Q(sent_col_r2),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_group_io
   (mem_dq_out,
    oserdes_clk,
    oserdes_clkdiv,
    oserdes_dq,
    po_oserdes_rst);
  output [10:0]mem_dq_out;
  input oserdes_clk;
  input oserdes_clkdiv;
  input [43:0]oserdes_dq;
  input po_oserdes_rst;

  wire [10:0]mem_dq_out;
  wire oserdes_clk;
  wire oserdes_clkdiv;
  wire [43:0]oserdes_dq;
  wire po_oserdes_rst;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[0].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[0]),
        .D2(oserdes_dq[1]),
        .D3(oserdes_dq[2]),
        .D4(oserdes_dq[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[11].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[40]),
        .D2(oserdes_dq[41]),
        .D3(oserdes_dq[42]),
        .D4(oserdes_dq[43]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[10]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[1].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[4]),
        .D2(oserdes_dq[5]),
        .D3(oserdes_dq[6]),
        .D4(oserdes_dq[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[2].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[8]),
        .D2(oserdes_dq[9]),
        .D3(oserdes_dq[10]),
        .D4(oserdes_dq[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[3].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[12]),
        .D2(oserdes_dq[13]),
        .D3(oserdes_dq[14]),
        .D4(oserdes_dq[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[4].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[16]),
        .D2(oserdes_dq[17]),
        .D3(oserdes_dq[18]),
        .D4(oserdes_dq[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[5].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[20]),
        .D2(oserdes_dq[21]),
        .D3(oserdes_dq[22]),
        .D4(oserdes_dq[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[6].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[24]),
        .D2(oserdes_dq[25]),
        .D3(oserdes_dq[26]),
        .D4(oserdes_dq[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[7].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[28]),
        .D2(oserdes_dq[29]),
        .D3(oserdes_dq[30]),
        .D4(oserdes_dq[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[8].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[32]),
        .D2(oserdes_dq[33]),
        .D3(oserdes_dq[34]),
        .D4(oserdes_dq[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[9].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[36]),
        .D2(oserdes_dq[37]),
        .D3(oserdes_dq[38]),
        .D4(oserdes_dq[39]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[9]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_group_io__parameterized0
   (mem_dq_out,
    oserdes_clk,
    oserdes_clkdiv,
    oserdes_dq,
    po_oserdes_rst);
  output [11:0]mem_dq_out;
  input oserdes_clk;
  input oserdes_clkdiv;
  input [47:0]oserdes_dq;
  input po_oserdes_rst;

  wire [11:0]mem_dq_out;
  wire oserdes_clk;
  wire oserdes_clkdiv;
  wire [47:0]oserdes_dq;
  wire po_oserdes_rst;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[0].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[0]),
        .D2(oserdes_dq[1]),
        .D3(oserdes_dq[2]),
        .D4(oserdes_dq[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[0].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[10].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[40]),
        .D2(oserdes_dq[41]),
        .D3(oserdes_dq[42]),
        .D4(oserdes_dq[43]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[10]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[11].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[44]),
        .D2(oserdes_dq[45]),
        .D3(oserdes_dq[46]),
        .D4(oserdes_dq[47]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[11]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[1].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[4]),
        .D2(oserdes_dq[5]),
        .D3(oserdes_dq[6]),
        .D4(oserdes_dq[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[2].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[8]),
        .D2(oserdes_dq[9]),
        .D3(oserdes_dq[10]),
        .D4(oserdes_dq[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[3].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[12]),
        .D2(oserdes_dq[13]),
        .D3(oserdes_dq[14]),
        .D4(oserdes_dq[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[4].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[16]),
        .D2(oserdes_dq[17]),
        .D3(oserdes_dq[18]),
        .D4(oserdes_dq[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[5].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[20]),
        .D2(oserdes_dq[21]),
        .D3(oserdes_dq[22]),
        .D4(oserdes_dq[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[6].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[24]),
        .D2(oserdes_dq[25]),
        .D3(oserdes_dq[26]),
        .D4(oserdes_dq[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[7].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[28]),
        .D2(oserdes_dq[29]),
        .D3(oserdes_dq[30]),
        .D4(oserdes_dq[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[8].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[32]),
        .D2(oserdes_dq[33]),
        .D3(oserdes_dq[34]),
        .D4(oserdes_dq[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[9].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[36]),
        .D2(oserdes_dq[37]),
        .D3(oserdes_dq[38]),
        .D4(oserdes_dq[39]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[9]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_group_io__parameterized1
   (D0,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D9,
    mem_dq_out,
    mem_dq_ts,
    out_dqs_0,
    ts_dqs_0,
    idelay_ld_rst,
    CLK,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    mem_dq_in,
    idelay_inc,
    LD0,
    idelay_ld_rst_reg_0,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    CLKB0,
    iserdes_clkdiv,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    of_dqbus,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS);
  output [3:0]D0;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D9;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output out_dqs_0;
  output ts_dqs_0;
  output idelay_ld_rst;
  input CLK;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0;
  input idelay_ld_rst_reg_0;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input CLKB0;
  input iserdes_clkdiv;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input [35:0]of_dqbus;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;

  wire CLK;
  wire CLKB0;
  wire [0:0]CTSBUS;
  wire [3:0]D0;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D9;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire LD0;
  wire data_in_dly_0;
  wire data_in_dly_2;
  wire data_in_dly_3;
  wire data_in_dly_4;
  wire data_in_dly_5;
  wire data_in_dly_6;
  wire data_in_dly_7;
  wire data_in_dly_9;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire idelay_ld_rst_i_1_n_0;
  wire idelay_ld_rst_reg_0;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [35:0]of_dqbus;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire out_dqs_0;
  wire po_oserdes_rst;
  wire rst_r3_reg_srl3_n_0;
  wire rst_r4;
  wire tbyte_out;
  wire ts_dqs_0;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(out_dqs_0),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(ts_dqs_0),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT3 #(
    .INIT(8'hF4)) 
    idelay_ld_rst_i_1
       (.I0(rst_r4),
        .I1(idelay_ld_rst),
        .I2(idelay_ld_rst_reg_0),
        .O(idelay_ld_rst_i_1_n_0));
  FDRE idelay_ld_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1_n_0),
        .Q(idelay_ld_rst),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[0].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[0].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_0),
        .IDATAIN(mem_dq_in[0]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(idelay_ld_rst_reg_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[0].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[0].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[0]),
        .DDLY(data_in_dly_0),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[0].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[0].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[0].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D0[3]),
        .Q2(D0[2]),
        .Q3(D0[1]),
        .Q4(D0[0]),
        .Q5(\NLW_input_[0].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[0].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[0].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[0].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[0].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_2),
        .IDATAIN(mem_dq_in[1]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(idelay_ld_rst_reg_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[1]),
        .DDLY(data_in_dly_2),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_3),
        .IDATAIN(mem_dq_in[2]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(idelay_ld_rst_reg_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[2]),
        .DDLY(data_in_dly_3),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_4),
        .IDATAIN(mem_dq_in[3]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(idelay_ld_rst_reg_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[3]),
        .DDLY(data_in_dly_4),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_5),
        .IDATAIN(mem_dq_in[4]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(idelay_ld_rst_reg_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[4]),
        .DDLY(data_in_dly_5),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_6),
        .IDATAIN(mem_dq_in[5]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(idelay_ld_rst_reg_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[5]),
        .DDLY(data_in_dly_6),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_7),
        .IDATAIN(mem_dq_in[6]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(idelay_ld_rst_reg_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[6]),
        .DDLY(data_in_dly_7),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_9),
        .IDATAIN(mem_dq_in[7]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(idelay_ld_rst_reg_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[9].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[7]),
        .DDLY(data_in_dly_9),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D9[3]),
        .Q2(D9[2]),
        .Q3(D9[1]),
        .Q4(D9[0]),
        .Q5(\NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[0].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[0]),
        .D2(of_dqbus[1]),
        .D3(of_dqbus[2]),
        .D4(of_dqbus[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[4]),
        .D2(of_dqbus[5]),
        .D3(of_dqbus[6]),
        .D4(of_dqbus[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[8]),
        .D2(of_dqbus[9]),
        .D3(of_dqbus[10]),
        .D4(of_dqbus[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[12]),
        .D2(of_dqbus[13]),
        .D3(of_dqbus[14]),
        .D4(of_dqbus[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[16]),
        .D2(of_dqbus[17]),
        .D3(of_dqbus[18]),
        .D4(of_dqbus[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[20]),
        .D2(of_dqbus[21]),
        .D3(of_dqbus[22]),
        .D4(of_dqbus[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[24]),
        .D2(of_dqbus[25]),
        .D3(of_dqbus[26]),
        .D4(of_dqbus[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[8].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[28]),
        .D2(of_dqbus[29]),
        .D3(of_dqbus[30]),
        .D4(of_dqbus[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[32]),
        .D2(of_dqbus[33]),
        .D3(of_dqbus[34]),
        .D4(of_dqbus[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[8]));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/rst_r3_reg_srl3 " *) 
  SRL16E rst_r3_reg_srl3
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(idelay_ld_rst_reg_0),
        .Q(rst_r3_reg_srl3_n_0));
  FDRE rst_r4_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_r3_reg_srl3_n_0),
        .Q(rst_r4),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_group_io__parameterized2
   (D1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D9,
    mem_dq_out,
    mem_dq_ts,
    out_dqs_1,
    ts_dqs_1,
    CLK,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    mem_dq_in,
    idelay_inc,
    LD0_0,
    \input_[9].iserdes_dq_.iserdesdq_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    CLKB0_4,
    iserdes_clkdiv,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    of_dqbus,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS);
  output [3:0]D1;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D9;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output out_dqs_1;
  output ts_dqs_1;
  input CLK;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_0;
  input \input_[9].iserdes_dq_.iserdesdq_1 ;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input CLKB0_4;
  input iserdes_clkdiv;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input [35:0]of_dqbus;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;

  wire CLK;
  wire CLKB0_4;
  wire [0:0]CTSBUS;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D9;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire LD0_0;
  wire data_in_dly_1;
  wire data_in_dly_2;
  wire data_in_dly_3;
  wire data_in_dly_4;
  wire data_in_dly_5;
  wire data_in_dly_6;
  wire data_in_dly_7;
  wire data_in_dly_9;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire idelay_inc;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire \input_[9].iserdes_dq_.iserdesdq_1 ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [35:0]of_dqbus;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire out_dqs_1;
  wire po_oserdes_rst;
  wire tbyte_out;
  wire ts_dqs_1;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(out_dqs_1),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(ts_dqs_1),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_1),
        .IDATAIN(mem_dq_in[0]),
        .INC(idelay_inc),
        .LD(LD0_0),
        .LDPIPEEN(1'b0),
        .REGRST(\input_[9].iserdes_dq_.iserdesdq_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[1].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_4),
        .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[0]),
        .DDLY(data_in_dly_1),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D1[3]),
        .Q2(D1[2]),
        .Q3(D1[1]),
        .Q4(D1[0]),
        .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_2),
        .IDATAIN(mem_dq_in[1]),
        .INC(idelay_inc),
        .LD(LD0_0),
        .LDPIPEEN(1'b0),
        .REGRST(\input_[9].iserdes_dq_.iserdesdq_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_4),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[1]),
        .DDLY(data_in_dly_2),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_3),
        .IDATAIN(mem_dq_in[2]),
        .INC(idelay_inc),
        .LD(LD0_0),
        .LDPIPEEN(1'b0),
        .REGRST(\input_[9].iserdes_dq_.iserdesdq_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_4),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[2]),
        .DDLY(data_in_dly_3),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_4),
        .IDATAIN(mem_dq_in[3]),
        .INC(idelay_inc),
        .LD(LD0_0),
        .LDPIPEEN(1'b0),
        .REGRST(\input_[9].iserdes_dq_.iserdesdq_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_4),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[3]),
        .DDLY(data_in_dly_4),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_5),
        .IDATAIN(mem_dq_in[4]),
        .INC(idelay_inc),
        .LD(LD0_0),
        .LDPIPEEN(1'b0),
        .REGRST(\input_[9].iserdes_dq_.iserdesdq_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_4),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[4]),
        .DDLY(data_in_dly_5),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_6),
        .IDATAIN(mem_dq_in[5]),
        .INC(idelay_inc),
        .LD(LD0_0),
        .LDPIPEEN(1'b0),
        .REGRST(\input_[9].iserdes_dq_.iserdesdq_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_4),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[5]),
        .DDLY(data_in_dly_6),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_7),
        .IDATAIN(mem_dq_in[6]),
        .INC(idelay_inc),
        .LD(LD0_0),
        .LDPIPEEN(1'b0),
        .REGRST(\input_[9].iserdes_dq_.iserdesdq_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_4),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[6]),
        .DDLY(data_in_dly_7),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 
       (.C(CLK),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_9),
        .IDATAIN(mem_dq_in[7]),
        .INC(idelay_inc),
        .LD(LD0_0),
        .LDPIPEEN(1'b0),
        .REGRST(\input_[9].iserdes_dq_.iserdesdq_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[9].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_4),
        .CLKDIV(\NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[7]),
        .DDLY(data_in_dly_9),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D9[3]),
        .Q2(D9[2]),
        .Q3(D9[1]),
        .Q4(D9[0]),
        .Q5(\NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[0]),
        .D2(of_dqbus[1]),
        .D3(of_dqbus[2]),
        .D4(of_dqbus[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[4]),
        .D2(of_dqbus[5]),
        .D3(of_dqbus[6]),
        .D4(of_dqbus[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[8]),
        .D2(of_dqbus[9]),
        .D3(of_dqbus[10]),
        .D4(of_dqbus[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[12]),
        .D2(of_dqbus[13]),
        .D3(of_dqbus[14]),
        .D4(of_dqbus[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[16]),
        .D2(of_dqbus[17]),
        .D3(of_dqbus[18]),
        .D4(of_dqbus[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[20]),
        .D2(of_dqbus[21]),
        .D3(of_dqbus[22]),
        .D4(of_dqbus[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[24]),
        .D2(of_dqbus[25]),
        .D3(of_dqbus[26]),
        .D4(of_dqbus[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[8].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[28]),
        .D2(of_dqbus[29]),
        .D3(of_dqbus[30]),
        .D4(of_dqbus[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[32]),
        .D2(of_dqbus[33]),
        .D3(of_dqbus[34]),
        .D4(of_dqbus[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[8]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_lane
   (ofifo_rst,
    ddr_ck_out,
    COUNTERREADVAL,
    \my_empty_reg[1] ,
    phy_mc_cmd_full,
    mem_dq_out,
    \rd_ptr_reg[3] ,
    ofifo_rst_reg_0,
    CLK,
    OUTBURSTPENDING,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \po_counter_read_val_reg[8]_2 ,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    PCENABLECALIB,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    \wr_ptr_timing_reg[0] ,
    calib_cmd_wren,
    B_of_full,
    mux_cmd_wren,
    mc_address,
    mc_cas_n,
    phy_dout);
  output ofifo_rst;
  output [1:0]ddr_ck_out;
  output [8:0]COUNTERREADVAL;
  output \my_empty_reg[1] ;
  output phy_mc_cmd_full;
  output [10:0]mem_dq_out;
  output [35:0]\rd_ptr_reg[3] ;
  input ofifo_rst_reg_0;
  input CLK;
  input [0:0]OUTBURSTPENDING;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input \po_counter_read_val_reg[8]_2 ;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input [1:0]PCENABLECALIB;
  input [3:0]\my_empty_reg[7] ;
  input [3:0]\my_empty_reg[7]_0 ;
  input [3:0]\my_empty_reg[7]_1 ;
  input [3:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [3:0]\my_empty_reg[7]_4 ;
  input [3:0]\my_empty_reg[7]_5 ;
  input [3:0]\my_empty_reg[7]_6 ;
  input \wr_ptr_timing_reg[0] ;
  input calib_cmd_wren;
  input B_of_full;
  input mux_cmd_wren;
  input [3:0]mc_address;
  input [0:0]mc_cas_n;
  input [38:0]phy_dout;

  wire A_of_full;
  wire B_of_full;
  wire CLK;
  wire [8:0]COUNTERREADVAL;
  wire [0:0]OUTBURSTPENDING;
  wire [1:0]PCENABLECALIB;
  wire calib_cmd_wren;
  wire [1:0]ddr_ck_out;
  wire [0:0]ddr_ck_out_q;
  wire freq_refclk;
  wire [3:0]mc_address;
  wire [0:0]mc_cas_n;
  wire [10:0]mem_dq_out;
  wire mem_refclk;
  wire mux_cmd_wren;
  wire \my_empty_reg[1] ;
  wire [3:0]\my_empty_reg[7] ;
  wire [3:0]\my_empty_reg[7]_0 ;
  wire [3:0]\my_empty_reg[7]_1 ;
  wire [3:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [3:0]\my_empty_reg[7]_4 ;
  wire [3:0]\my_empty_reg[7]_5 ;
  wire [3:0]\my_empty_reg[7]_6 ;
  wire [3:0]of_d1;
  wire [3:0]of_d3;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [7:0]of_q5;
  wire [7:0]of_q6;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire ofifo_rst;
  wire ofifo_rst_reg_0;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire [38:0]phy_dout;
  wire phy_mc_cmd_full;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire \po_counter_read_val_reg[8]_2 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [35:0]\rd_ptr_reg[3] ;
  wire sync_pulse;
  wire \wr_ptr_timing_reg[0] ;
  wire \NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED ;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_group_io ddr_byte_group_io
       (.mem_dq_out(mem_dq_out),
        .oserdes_clk(oserdes_clk),
        .oserdes_clkdiv(oserdes_clkdiv),
        .oserdes_dq({of_q6[7:4],of_q9,of_q8,of_q7,of_q6[3:0],of_q5[3:0],of_q4,of_q3,of_q2,of_q1,of_q0}),
        .po_oserdes_rst(po_oserdes_rst));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck 
       (.C(oserdes_clk),
        .CE(1'b1),
        .D1(1'b0),
        .D2(1'b1),
        .Q(ddr_ck_out_q),
        .R(1'b0),
        .S(\NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  (* XILINX_LEGACY_PRIM = "OBUFDS" *) 
  OBUFDS #(
    .IOSTANDARD("DEFAULT")) 
    \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf 
       (.I(ddr_ck_out_q),
        .O(ddr_ck_out[0]),
        .OB(ddr_ck_out[1]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_10 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.A_of_full(A_of_full),
        .CLK(CLK),
        .D1(of_d1),
        .D3(of_d3),
        .SR(ofifo_rst),
        .calib_cmd_wren(calib_cmd_wren),
        .mc_address(mc_address),
        .mc_cas_n(mc_cas_n),
        .mux_cmd_wren(mux_cmd_wren),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .\my_empty_reg[1]_1 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ),
        .phy_dout(phy_dout),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0] ));
  FDRE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ofifo_rst_reg_0),
        .Q(ofifo_rst),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0({1'b0,1'b0,1'b0,1'b0,\my_empty_reg[7] }),
        .D1({1'b0,1'b0,1'b0,1'b0,of_d1}),
        .D2({1'b0,1'b0,1'b0,1'b0,\my_empty_reg[7]_0 }),
        .D3({1'b0,1'b0,1'b0,1'b0,of_d3}),
        .D4({1'b0,1'b0,1'b0,1'b0,\my_empty_reg[7]_1 }),
        .D5({1'b0,1'b0,1'b0,1'b0,\my_empty_reg[7]_2 }),
        .D6(\my_empty_reg[7]_3 ),
        .D7({1'b0,1'b0,1'b0,1'b0,\my_empty_reg[7]_4 }),
        .D8({1'b0,1'b0,1'b0,1'b0,\my_empty_reg[7]_5 }),
        .D9({1'b0,1'b0,1'b0,1'b0,\my_empty_reg[7]_6 }),
        .EMPTY(out_fifo_n_2),
        .FULL(A_of_full),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5(of_q5),
        .Q6(of_q6),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(4),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("FALSE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.077000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.538500),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(OUTBURSTPENDING),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\po_counter_read_val_reg[8]_0 ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_1 ),
        .FINEINC(\po_counter_read_val_reg[8]_2 ),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(ofifo_rst_reg_0),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
  LUT2 #(
    .INIT(4'hE)) 
    phy_mc_cmd_full_r_i_1
       (.I0(A_of_full),
        .I1(B_of_full),
        .O(phy_mc_cmd_full));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_lane__parameterized0
   (B_of_full,
    \rd_ptr_reg[0] ,
    \rd_ptr_reg[1] ,
    \rd_ptr_reg[2] ,
    \rd_ptr_reg[3] ,
    wr_en_3,
    \my_empty_reg[1] ,
    Q,
    mem_dq_out,
    D,
    OUTBURSTPENDING,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \po_counter_read_val_reg[8]_2 ,
    freq_refclk,
    mem_refclk,
    \po_counter_read_val_reg[8]_3 ,
    sync_pulse,
    CLK,
    PCENABLECALIB,
    ofifo_rst,
    \rd_ptr_reg[3]_0 ,
    \rd_ptr_reg[3]_1 ,
    \rd_ptr_reg[3]_2 ,
    \rd_ptr_reg[3]_3 ,
    \rd_ptr_reg[3]_4 ,
    \rd_ptr_reg[3]_5 ,
    \rd_ptr_reg[3]_6 ,
    \rd_ptr_reg[3]_7 ,
    \rd_ptr_reg[3]_8 ,
    \rd_ptr_reg[3]_9 ,
    calib_cmd_wren,
    \wr_ptr_timing_reg[0] ,
    mem_out,
    mux_cmd_wren,
    COUNTERREADVAL,
    \po_counter_read_val_reg[8]_4 ,
    calib_sel,
    \po_counter_read_val_reg[8]_5 );
  output B_of_full;
  output \rd_ptr_reg[0] ;
  output \rd_ptr_reg[1] ;
  output \rd_ptr_reg[2] ;
  output \rd_ptr_reg[3] ;
  output wr_en_3;
  output \my_empty_reg[1] ;
  output [3:0]Q;
  output [11:0]mem_dq_out;
  output [8:0]D;
  input [0:0]OUTBURSTPENDING;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input \po_counter_read_val_reg[8]_2 ;
  input freq_refclk;
  input mem_refclk;
  input \po_counter_read_val_reg[8]_3 ;
  input sync_pulse;
  input CLK;
  input [1:0]PCENABLECALIB;
  input ofifo_rst;
  input [3:0]\rd_ptr_reg[3]_0 ;
  input [3:0]\rd_ptr_reg[3]_1 ;
  input [2:0]\rd_ptr_reg[3]_2 ;
  input [3:0]\rd_ptr_reg[3]_3 ;
  input [3:0]\rd_ptr_reg[3]_4 ;
  input [7:0]\rd_ptr_reg[3]_5 ;
  input [5:0]\rd_ptr_reg[3]_6 ;
  input [2:0]\rd_ptr_reg[3]_7 ;
  input [3:0]\rd_ptr_reg[3]_8 ;
  input [3:0]\rd_ptr_reg[3]_9 ;
  input calib_cmd_wren;
  input \wr_ptr_timing_reg[0] ;
  input [3:0]mem_out;
  input mux_cmd_wren;
  input [8:0]COUNTERREADVAL;
  input [8:0]\po_counter_read_val_reg[8]_4 ;
  input [1:0]calib_sel;
  input [8:0]\po_counter_read_val_reg[8]_5 ;

  wire B_of_a_full;
  wire B_of_full;
  wire B_po_coarse_overflow;
  wire [8:0]B_po_counter_read_val;
  wire B_po_fine_overflow;
  wire CLK;
  wire [8:0]COUNTERREADVAL;
  wire [8:0]D;
  wire [0:0]OUTBURSTPENDING;
  wire [1:0]PCENABLECALIB;
  wire [3:0]Q;
  wire calib_cmd_wren;
  wire [1:0]calib_sel;
  wire freq_refclk;
  wire [11:0]mem_dq_out;
  wire [3:0]mem_out;
  wire mem_refclk;
  wire mux_cmd_wren;
  wire \my_empty_reg[1] ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [7:0]of_q5;
  wire [7:0]of_q6;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_n_0;
  wire out_fifo_n_2;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire \po_counter_read_val_reg[8]_2 ;
  wire \po_counter_read_val_reg[8]_3 ;
  wire [8:0]\po_counter_read_val_reg[8]_4 ;
  wire [8:0]\po_counter_read_val_reg[8]_5 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire \rd_ptr_reg[0] ;
  wire \rd_ptr_reg[1] ;
  wire \rd_ptr_reg[2] ;
  wire \rd_ptr_reg[3] ;
  wire [3:0]\rd_ptr_reg[3]_0 ;
  wire [3:0]\rd_ptr_reg[3]_1 ;
  wire [2:0]\rd_ptr_reg[3]_2 ;
  wire [3:0]\rd_ptr_reg[3]_3 ;
  wire [3:0]\rd_ptr_reg[3]_4 ;
  wire [7:0]\rd_ptr_reg[3]_5 ;
  wire [5:0]\rd_ptr_reg[3]_6 ;
  wire [2:0]\rd_ptr_reg[3]_7 ;
  wire [3:0]\rd_ptr_reg[3]_8 ;
  wire [3:0]\rd_ptr_reg[3]_9 ;
  wire sync_pulse;
  wire wr_en_3;
  wire \wr_ptr_timing_reg[0] ;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_group_io__parameterized0 ddr_byte_group_io
       (.mem_dq_out(mem_dq_out),
        .oserdes_clk(oserdes_clk),
        .oserdes_clkdiv(oserdes_clkdiv),
        .oserdes_dq({of_q6[7:4],of_q5[7:4],of_q9,of_q8,of_q7,of_q6[3:0],of_q5[3:0],of_q4,of_q3,of_q2,of_q1,of_q0}),
        .po_oserdes_rst(po_oserdes_rst));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_9 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.CLK(CLK),
        .D2(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ),
        .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D7(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ),
        .Q(Q),
        .calib_cmd_wren(calib_cmd_wren),
        .mem_out(mem_out),
        .mux_cmd_wren(mux_cmd_wren),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .\my_empty_reg[1]_1 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ),
        .ofifo_rst(ofifo_rst),
        .\rd_ptr_reg[0]_0 (\rd_ptr_reg[0] ),
        .\rd_ptr_reg[1]_0 (\rd_ptr_reg[1] ),
        .\rd_ptr_reg[2]_0 (\rd_ptr_reg[2] ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ),
        .\rd_ptr_reg[3]_1 (B_of_full),
        .wr_en_3(wr_en_3),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0] ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(B_of_a_full),
        .D0({1'b0,1'b0,1'b0,1'b0,\rd_ptr_reg[3]_0 }),
        .D1({1'b0,1'b0,1'b0,1'b0,\rd_ptr_reg[3]_1 }),
        .D2({1'b0,1'b0,1'b0,1'b0,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\rd_ptr_reg[3]_2 }),
        .D3({1'b0,1'b0,1'b0,1'b0,\rd_ptr_reg[3]_3 }),
        .D4({1'b0,1'b0,1'b0,1'b0,\rd_ptr_reg[3]_4 }),
        .D5(\rd_ptr_reg[3]_5 ),
        .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\rd_ptr_reg[3]_6 [5:3],\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\rd_ptr_reg[3]_6 [2:0]}),
        .D7({1'b0,1'b0,1'b0,1'b0,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\rd_ptr_reg[3]_7 }),
        .D8({1'b0,1'b0,1'b0,1'b0,\rd_ptr_reg[3]_8 }),
        .D9({1'b0,1'b0,1'b0,1'b0,\rd_ptr_reg[3]_9 }),
        .EMPTY(out_fifo_n_2),
        .FULL(B_of_full),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5(of_q5),
        .Q6(of_q6),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(4),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("FALSE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.077000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.538500),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(OUTBURSTPENDING),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(B_po_coarse_overflow),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\po_counter_read_val_reg[8]_0 ),
        .COUNTERREADVAL(B_po_counter_read_val),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_1 ),
        .FINEINC(\po_counter_read_val_reg[8]_2 ),
        .FINEOVERFLOW(B_po_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(\po_counter_read_val_reg[8]_3 ),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[0]_i_1 
       (.I0(B_po_counter_read_val[0]),
        .I1(COUNTERREADVAL[0]),
        .I2(\po_counter_read_val_reg[8]_4 [0]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_5 [0]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[1]_i_1 
       (.I0(B_po_counter_read_val[1]),
        .I1(COUNTERREADVAL[1]),
        .I2(\po_counter_read_val_reg[8]_4 [1]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_5 [1]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[2]_i_1 
       (.I0(B_po_counter_read_val[2]),
        .I1(COUNTERREADVAL[2]),
        .I2(\po_counter_read_val_reg[8]_4 [2]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_5 [2]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[3]_i_1 
       (.I0(B_po_counter_read_val[3]),
        .I1(COUNTERREADVAL[3]),
        .I2(\po_counter_read_val_reg[8]_4 [3]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_5 [3]),
        .O(D[3]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[4]_i_1 
       (.I0(B_po_counter_read_val[4]),
        .I1(COUNTERREADVAL[4]),
        .I2(\po_counter_read_val_reg[8]_4 [4]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_5 [4]),
        .O(D[4]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[5]_i_1 
       (.I0(B_po_counter_read_val[5]),
        .I1(COUNTERREADVAL[5]),
        .I2(\po_counter_read_val_reg[8]_4 [5]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_5 [5]),
        .O(D[5]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[6]_i_1 
       (.I0(B_po_counter_read_val[6]),
        .I1(COUNTERREADVAL[6]),
        .I2(\po_counter_read_val_reg[8]_4 [6]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_5 [6]),
        .O(D[6]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[7]_i_1 
       (.I0(B_po_counter_read_val[7]),
        .I1(COUNTERREADVAL[7]),
        .I2(\po_counter_read_val_reg[8]_4 [7]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_5 [7]),
        .O(D[7]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[8]_i_1 
       (.I0(B_po_counter_read_val[8]),
        .I1(COUNTERREADVAL[8]),
        .I2(\po_counter_read_val_reg[8]_4 [8]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_5 [8]),
        .O(D[8]));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_lane__parameterized1
   (out,
    A_rst_primitives_reg,
    mem_dq_out,
    mem_dq_ts,
    out_dqs_0,
    ts_dqs_0,
    pi_dqs_found_lanes,
    A_rst_primitives_reg_0,
    if_empty_r,
    \rd_ptr_reg[0] ,
    \rd_ptr_reg[1] ,
    \rd_ptr_reg[2] ,
    \rd_ptr_reg[3] ,
    idelay_ld_rst,
    init_complete_r1_timing_reg,
    \my_empty_reg[3] ,
    \my_empty_reg[1] ,
    phy_rddata_en,
    A_rst_primitives_reg_1,
    phy_mc_data_full,
    wr_en_2,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[0] ,
    \my_empty_reg[4] ,
    app_rd_data,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \wr_ptr_reg[3] ,
    D,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    CLK,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0,
    idelay_ld_rst_reg,
    CLKB0,
    INBURSTPENDING,
    \pi_dqs_found_lanes_r1_reg[2] ,
    \pi_dqs_found_lanes_r1_reg[2]_0 ,
    \pi_dqs_found_lanes_r1_reg[2]_1 ,
    \pi_dqs_found_lanes_r1_reg[2]_2 ,
    freq_refclk,
    mem_refclk,
    mem_dqs_in,
    \pi_dqs_found_lanes_r1_reg[2]_3 ,
    sync_pulse,
    PCENABLECALIB,
    INRANKC,
    COUNTERLOADVAL,
    OUTBURSTPENDING,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    D0,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    D9,
    ififo_rst_reg0,
    ofifo_rst_reg0,
    \read_fifo.tail_r_reg[1] ,
    if_empty_r_0,
    my_empty,
    mux_wrdata_en,
    mc_wrdata_en,
    \wr_ptr_timing_reg[0] ,
    calib_wrdata_en,
    pi_phase_locked_all_r1_reg,
    Q,
    \app_rd_data[112] ,
    calib_sel,
    COUNTERREADVAL,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] );
  output [1:0]out;
  output A_rst_primitives_reg;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output out_dqs_0;
  output ts_dqs_0;
  output [0:0]pi_dqs_found_lanes;
  output [8:0]A_rst_primitives_reg_0;
  output [0:0]if_empty_r;
  output \rd_ptr_reg[0] ;
  output \rd_ptr_reg[1] ;
  output \rd_ptr_reg[2] ;
  output \rd_ptr_reg[3] ;
  output idelay_ld_rst;
  output init_complete_r1_timing_reg;
  output [1:0]\my_empty_reg[3] ;
  output \my_empty_reg[1] ;
  output phy_rddata_en;
  output A_rst_primitives_reg_1;
  output phy_mc_data_full;
  output wr_en_2;
  output \wr_ptr_reg[1] ;
  output \wr_ptr_reg[0] ;
  output \my_empty_reg[4] ;
  output [63:0]app_rd_data;
  output [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output [3:0]\wr_ptr_reg[3] ;
  output [5:0]D;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  input CLK;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0;
  input idelay_ld_rst_reg;
  input CLKB0;
  input [0:0]INBURSTPENDING;
  input \pi_dqs_found_lanes_r1_reg[2] ;
  input \pi_dqs_found_lanes_r1_reg[2]_0 ;
  input \pi_dqs_found_lanes_r1_reg[2]_1 ;
  input \pi_dqs_found_lanes_r1_reg[2]_2 ;
  input freq_refclk;
  input mem_refclk;
  input [0:0]mem_dqs_in;
  input \pi_dqs_found_lanes_r1_reg[2]_3 ;
  input sync_pulse;
  input [1:0]PCENABLECALIB;
  input [1:0]INRANKC;
  input [5:0]COUNTERLOADVAL;
  input [0:0]OUTBURSTPENDING;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input [7:0]D0;
  input [7:0]D2;
  input [7:0]D3;
  input [7:0]D4;
  input [7:0]D5;
  input [7:0]D6;
  input [7:0]D7;
  input [7:0]D8;
  input [7:0]D9;
  input ififo_rst_reg0;
  input ofifo_rst_reg0;
  input \read_fifo.tail_r_reg[1] ;
  input [0:0]if_empty_r_0;
  input [1:0]my_empty;
  input mux_wrdata_en;
  input mc_wrdata_en;
  input \wr_ptr_timing_reg[0] ;
  input calib_wrdata_en;
  input pi_phase_locked_all_r1_reg;
  input [2:0]Q;
  input [63:0]\app_rd_data[112] ;
  input [1:0]calib_sel;
  input [5:0]COUNTERREADVAL;
  input [63:0]\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input [0:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;

  wire A_rst_primitives_reg;
  wire [8:0]A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire CLK;
  wire CLKB0;
  wire [5:0]COUNTERLOADVAL;
  wire [5:0]COUNTERREADVAL;
  wire C_if_a_empty;
  wire C_of_a_full;
  wire C_of_full;
  wire [5:0]C_pi_counter_read_val;
  wire C_pi_dqs_out_of_range;
  wire C_pi_fine_overflow;
  wire C_po_coarse_overflow;
  wire C_po_fine_overflow;
  wire [5:0]D;
  wire [7:0]D0;
  wire [7:0]D2;
  wire [7:0]D3;
  wire [7:0]D4;
  wire [7:0]D5;
  wire [7:0]D6;
  wire [7:0]D7;
  wire [7:0]D8;
  wire [7:0]D9;
  wire [0:0]INBURSTPENDING;
  wire [1:0]INRANKC;
  wire LD0;
  wire [0:0]OUTBURSTPENDING;
  wire [1:0]PCENABLECALIB;
  wire [2:0]Q;
  wire [63:0]app_rd_data;
  wire [63:0]\app_rd_data[112] ;
  wire [1:0]calib_sel;
  wire calib_wrdata_en;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire freq_refclk;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire [0:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire [63:0]\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire idelay_ld_rst_reg;
  wire [3:0]if_d0;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d9;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire ififo_rst;
  wire ififo_rst_reg0;
  wire ififo_wr_enable;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire init_complete_r1_timing_reg;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire iserdes_clkdiv;
  wire mc_wrdata_en;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [0:0]mem_dqs_in;
  wire mem_refclk;
  wire mux_wrdata_en;
  wire [1:0]my_empty;
  wire \my_empty_reg[1] ;
  wire [1:0]\my_empty_reg[3] ;
  wire \my_empty_reg[4] ;
  wire [39:0]of_dqbus;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire ofifo_rst;
  wire ofifo_rst_reg0;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire [1:0]out;
  wire out_dqs_0;
  wire out_fifo_n_0;
  wire out_fifo_n_2;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_6 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire phy_mc_data_full;
  wire phy_rddata_en;
  wire [0:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[2] ;
  wire \pi_dqs_found_lanes_r1_reg[2]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_2 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_3 ;
  wire pi_phase_locked_all_r1_reg;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [79:0]rd_data;
  wire \rd_ptr_reg[0] ;
  wire \rd_ptr_reg[1] ;
  wire \rd_ptr_reg[2] ;
  wire \rd_ptr_reg[3] ;
  wire \read_fifo.tail_r_reg[1] ;
  wire sync_pulse;
  wire ts_dqs_0;
  wire wr_en_2;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[1] ;
  wire [3:0]\wr_ptr_reg[3] ;
  wire \wr_ptr_timing_reg[0] ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_group_io__parameterized1 ddr_byte_group_io
       (.CLK(CLK),
        .CLKB0(CLKB0),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D0(if_d0),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .D9(if_d9),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .LD0(LD0),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (A_rst_primitives_reg),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(idelay_ld_rst),
        .idelay_ld_rst_reg_0(idelay_ld_rst_reg),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq ),
        .iserdes_clkdiv(iserdes_clkdiv),
        .mem_dq_in(mem_dq_in),
        .mem_dq_out(mem_dq_out),
        .mem_dq_ts(mem_dq_ts),
        .of_dqbus({of_dqbus[39:8],of_dqbus[3:0]}),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .out_dqs_0(out_dqs_0),
        .po_oserdes_rst(po_oserdes_rst),
        .ts_dqs_0(ts_dqs_0));
  (* syn_maxfan = "3" *) 
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_empty_),
        .Q(if_empty_r),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[0]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [0]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[10]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [10]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[11]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [11]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[12]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[13]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[14]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[15]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[16]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[17]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[18]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[19]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[1]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [1]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[20]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[21]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[22]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[23]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[24]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[25]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[26]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[27]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[28]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[29]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[2]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [2]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[30]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[31]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[32]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[33]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[34]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[35]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[36]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[37]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[38]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[39]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[3]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [3]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[40]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[41]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[42]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[43]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[44]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[45]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[46]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[47]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[48]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[49]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[4]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [4]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[50]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[51]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[52]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[53]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[54]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[55]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[56]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[57]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[58]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[59]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[5]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [5]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[60]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[61]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[62]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[63]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[64]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[65]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[6]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [6]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[72]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [66]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[73]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [67]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[74]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [68]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[75]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [69]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[76]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [70]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[77]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [71]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[78]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [72]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[79]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [73]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[7]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [7]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[8]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [8]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[9]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [9]),
        .R(1'b0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_if_post_fifo_7 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.CLK(CLK),
        .app_rd_data(app_rd_data),
        .\app_rd_data[112] ({\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [73:66],\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [63:16],\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [7:0]}),
        .\app_rd_data[112]_0 (\app_rd_data[112] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .if_empty_r_0(if_empty_r_0),
        .ififo_rst(ififo_rst),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .my_empty(my_empty),
        .\my_empty_reg[0]_0 (\my_empty_reg[3] [0]),
        .\my_empty_reg[3]_0 (\my_empty_reg[3] [1]),
        .\my_empty_reg[4]_0 (\my_empty_reg[4] ),
        .\my_empty_reg[4]_rep__1_0 (if_empty_r),
        .out(out),
        .phy_rddata_en(phy_rddata_en),
        .\read_fifo.tail_r_reg[1] (\read_fifo.tail_r_reg[1] ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1] ));
  FDRE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ififo_rst_reg0),
        .Q(ififo_rst),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(C_if_a_empty),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0(if_d0),
        .D1({1'b0,1'b0,1'b0,1'b0}),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8({1'b0,1'b0,1'b0,1'b0}),
        .D9(if_d9),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(rd_data[7:0]),
        .Q1(rd_data[15:8]),
        .Q2(rd_data[23:16]),
        .Q3(rd_data[31:24]),
        .Q4(rd_data[39:32]),
        .Q5(rd_data[47:40]),
        .Q6(rd_data[55:48]),
        .Q7(rd_data[63:56]),
        .Q8(rd_data[71:64]),
        .Q9(rd_data[79:72]),
        .RDCLK(CLK),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_8 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.CLK(CLK),
        .C_of_full(C_of_full),
        .Q(Q),
        .calib_wrdata_en(calib_wrdata_en),
        .mc_wrdata_en(mc_wrdata_en),
        .mux_wrdata_en(mux_wrdata_en),
        .\my_empty_reg[1]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1] ),
        .ofifo_rst(ofifo_rst),
        .phy_mc_data_full(phy_mc_data_full),
        .\rd_ptr_reg[0]_0 (\rd_ptr_reg[0] ),
        .\rd_ptr_reg[1]_0 (\rd_ptr_reg[1] ),
        .\rd_ptr_reg[2]_0 (\rd_ptr_reg[2] ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ),
        .wr_en_2(wr_en_2),
        .\wr_ptr_reg[3]_0 (\wr_ptr_reg[3] ),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0] ));
  FDRE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ofifo_rst_reg0),
        .Q(ofifo_rst),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(C_of_a_full),
        .D0(D0),
        .D1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .D2(D2),
        .D3(D3),
        .D4(D4),
        .D5(D5),
        .D6(D6),
        .D7(D7),
        .D8(D8),
        .D9(D9),
        .EMPTY(out_fifo_n_2),
        .FULL(C_of_full),
        .Q0(of_dqbus[3:0]),
        .Q1(of_dqbus[7:4]),
        .Q2(of_dqbus[11:8]),
        .Q3(of_dqbus[15:12]),
        .Q4(of_dqbus[19:16]),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),
        .Q7(of_dqbus[31:28]),
        .Q8(of_dqbus[35:32]),
        .Q9(of_dqbus[39:36]),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b001),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.077000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(3.077000),
    .REFCLK_PERIOD(1.538500),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(INBURSTPENDING),
        .COUNTERLOADEN(\pi_dqs_found_lanes_r1_reg[2] ),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[2]_0 ),
        .COUNTERREADVAL(C_pi_counter_read_val),
        .DQSFOUND(pi_dqs_found_lanes),
        .DQSOUTOFRANGE(C_pi_dqs_out_of_range),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\pi_dqs_found_lanes_r1_reg[2]_1 ),
        .FINEINC(\pi_dqs_found_lanes_r1_reg[2]_2 ),
        .FINEOVERFLOW(C_pi_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .ICLK(A_rst_primitives_reg),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(\phaser_in_gen.phaser_in_n_6 ),
        .PHASEREFCLK(mem_dqs_in),
        .RANKSELPHY(INRANKC),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(idelay_ld_rst_reg),
        .RSTDQSFIND(\pi_dqs_found_lanes_r1_reg[2]_3 ),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.077000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.538500),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(OUTBURSTPENDING),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(C_po_coarse_overflow),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[2]_0 ),
        .COUNTERREADVAL(A_rst_primitives_reg_0),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_0 ),
        .FINEINC(\po_counter_read_val_reg[8]_1 ),
        .FINEOVERFLOW(C_po_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(idelay_ld_rst_reg),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
  LUT4 #(
    .INIT(16'hE020)) 
    \pi_counter_read_val[0]_i_1 
       (.I0(C_pi_counter_read_val[0]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(COUNTERREADVAL[0]),
        .O(D[0]));
  LUT4 #(
    .INIT(16'hE020)) 
    \pi_counter_read_val[1]_i_1 
       (.I0(C_pi_counter_read_val[1]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(COUNTERREADVAL[1]),
        .O(D[1]));
  LUT4 #(
    .INIT(16'hE020)) 
    \pi_counter_read_val[2]_i_1 
       (.I0(C_pi_counter_read_val[2]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(COUNTERREADVAL[2]),
        .O(D[2]));
  LUT4 #(
    .INIT(16'hE020)) 
    \pi_counter_read_val[3]_i_1 
       (.I0(C_pi_counter_read_val[3]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(COUNTERREADVAL[3]),
        .O(D[3]));
  LUT4 #(
    .INIT(16'hE020)) 
    \pi_counter_read_val[4]_i_1 
       (.I0(C_pi_counter_read_val[4]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(COUNTERREADVAL[4]),
        .O(D[4]));
  LUT4 #(
    .INIT(16'hE020)) 
    \pi_counter_read_val[5]_i_1 
       (.I0(C_pi_counter_read_val[5]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(COUNTERREADVAL[5]),
        .O(D[5]));
  LUT2 #(
    .INIT(4'h8)) 
    pi_phase_locked_all_inferred_i_1
       (.I0(\phaser_in_gen.phaser_in_n_6 ),
        .I1(pi_phase_locked_all_r1_reg),
        .O(A_rst_primitives_reg_1));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_lane__parameterized2
   (\rd_ptr_timing_reg[1] ,
    A_rst_primitives_reg,
    mem_dq_out,
    mem_dq_ts,
    out_dqs_1,
    ts_dqs_1,
    pi_dqs_found_lanes,
    A_rst_primitives_reg_0,
    COUNTERREADVAL,
    A_rst_primitives_reg_1,
    if_empty_r,
    \rd_ptr_reg[0] ,
    \rd_ptr_reg[1] ,
    \rd_ptr_reg[2] ,
    \rd_ptr_reg[3] ,
    \my_empty_reg[1] ,
    app_rd_data_valid,
    \my_empty_reg[3] ,
    \my_empty_reg[0] ,
    \my_empty_reg[0]_0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    Q,
    wr_en,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \my_empty_reg[4]_rep__0 ,
    p_1_in,
    \wr_ptr_reg[3] ,
    CLK,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0_0,
    \pi_dqs_found_lanes_r1_reg[3] ,
    CLKB0_4,
    INBURSTPENDING,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    \pi_dqs_found_lanes_r1_reg[3]_1 ,
    \pi_dqs_found_lanes_r1_reg[3]_2 ,
    \pi_dqs_found_lanes_r1_reg[3]_3 ,
    freq_refclk,
    mem_refclk,
    mem_dqs_in,
    \pi_dqs_found_lanes_r1_reg[3]_4 ,
    sync_pulse,
    PCENABLECALIB,
    INRANKD,
    \pi_dqs_found_lanes_r1_reg[3]_5 ,
    OUTBURSTPENDING,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    D1,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    ififo_rst_reg0_1,
    ofifo_rst_reg0_2,
    mux_wrdata_en,
    mc_wrdata_en,
    out_fifo_0,
    calib_wrdata_en,
    \my_empty_reg[4]_rep__1 ,
    if_empty_r_0,
    app_rd_data_valid_0,
    app_rd_data_valid_1,
    \read_fifo.tail_r_reg ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    app_rd_data,
    \wr_ptr_timing_reg[0] );
  output [1:0]\rd_ptr_timing_reg[1] ;
  output A_rst_primitives_reg;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output out_dqs_1;
  output ts_dqs_1;
  output [0:0]pi_dqs_found_lanes;
  output A_rst_primitives_reg_0;
  output [5:0]COUNTERREADVAL;
  output [8:0]A_rst_primitives_reg_1;
  output [0:0]if_empty_r;
  output \rd_ptr_reg[0] ;
  output \rd_ptr_reg[1] ;
  output \rd_ptr_reg[2] ;
  output \rd_ptr_reg[3] ;
  output \my_empty_reg[1] ;
  output app_rd_data_valid;
  output [1:0]\my_empty_reg[3] ;
  output \my_empty_reg[0] ;
  output \my_empty_reg[0]_0 ;
  output \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  output [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  output [2:0]Q;
  output wr_en;
  output \wr_ptr_reg[1] ;
  output \wr_ptr_reg[0] ;
  output [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \my_empty_reg[4]_rep__0 ;
  output p_1_in;
  output [3:0]\wr_ptr_reg[3] ;
  input CLK;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_0;
  input \pi_dqs_found_lanes_r1_reg[3] ;
  input CLKB0_4;
  input [0:0]INBURSTPENDING;
  input \pi_dqs_found_lanes_r1_reg[3]_0 ;
  input \pi_dqs_found_lanes_r1_reg[3]_1 ;
  input \pi_dqs_found_lanes_r1_reg[3]_2 ;
  input \pi_dqs_found_lanes_r1_reg[3]_3 ;
  input freq_refclk;
  input mem_refclk;
  input [0:0]mem_dqs_in;
  input \pi_dqs_found_lanes_r1_reg[3]_4 ;
  input sync_pulse;
  input [1:0]PCENABLECALIB;
  input [1:0]INRANKD;
  input [5:0]\pi_dqs_found_lanes_r1_reg[3]_5 ;
  input [0:0]OUTBURSTPENDING;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input [7:0]D1;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input ififo_rst_reg0_1;
  input ofifo_rst_reg0_2;
  input mux_wrdata_en;
  input mc_wrdata_en;
  input out_fifo_0;
  input calib_wrdata_en;
  input [1:0]\my_empty_reg[4]_rep__1 ;
  input [0:0]if_empty_r_0;
  input app_rd_data_valid_0;
  input [0:0]app_rd_data_valid_1;
  input [0:0]\read_fifo.tail_r_reg ;
  input [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input [63:0]app_rd_data;
  input \wr_ptr_timing_reg[0] ;

  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire [8:0]A_rst_primitives_reg_1;
  wire CLK;
  wire CLKB0_4;
  wire [5:0]COUNTERREADVAL;
  wire [7:0]D1;
  wire D_if_a_empty;
  wire D_of_a_full;
  wire D_of_full;
  wire D_pi_dqs_out_of_range;
  wire D_pi_fine_overflow;
  wire D_po_coarse_overflow;
  wire D_po_fine_overflow;
  wire [0:0]INBURSTPENDING;
  wire [1:0]INRANKD;
  wire LD0_0;
  wire [0:0]OUTBURSTPENDING;
  wire [1:0]PCENABLECALIB;
  wire [2:0]Q;
  wire [63:0]app_rd_data;
  wire app_rd_data_valid;
  wire app_rd_data_valid_0;
  wire [0:0]app_rd_data_valid_1;
  wire calib_wrdata_en;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire freq_refclk;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire idelay_inc;
  wire [3:0]if_d1;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d9;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire ififo_rst;
  wire ififo_rst_reg0_1;
  wire ififo_wr_enable;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire iserdes_clkdiv;
  wire mc_wrdata_en;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [0:0]mem_dqs_in;
  wire mem_refclk;
  wire mux_wrdata_en;
  wire \my_empty_reg[0] ;
  wire \my_empty_reg[0]_0 ;
  wire \my_empty_reg[1] ;
  wire [1:0]\my_empty_reg[3] ;
  wire \my_empty_reg[4]_rep__0 ;
  wire [1:0]\my_empty_reg[4]_rep__1 ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire [39:0]of_dqbus;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire ofifo_rst;
  wire ofifo_rst_reg0_2;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_dqs_1;
  wire out_fifo_0;
  wire out_fifo_n_0;
  wire out_fifo_n_2;
  wire p_1_in;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire [0:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire \pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_2 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_4 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[3]_5 ;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [79:0]rd_data;
  wire \rd_ptr_reg[0] ;
  wire \rd_ptr_reg[1] ;
  wire \rd_ptr_reg[2] ;
  wire \rd_ptr_reg[3] ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire [0:0]\read_fifo.tail_r_reg ;
  wire sync_pulse;
  wire ts_dqs_1;
  wire wr_en;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[1] ;
  wire [3:0]\wr_ptr_reg[3] ;
  wire \wr_ptr_timing_reg[0] ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_group_io__parameterized2 ddr_byte_group_io
       (.CLK(CLK),
        .CLKB0_4(CLKB0_4),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .D9(if_d9),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .LD0_0(LD0_0),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (A_rst_primitives_reg),
        .idelay_inc(idelay_inc),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq ),
        .\input_[9].iserdes_dq_.iserdesdq_1 (\pi_dqs_found_lanes_r1_reg[3] ),
        .iserdes_clkdiv(iserdes_clkdiv),
        .mem_dq_in(mem_dq_in),
        .mem_dq_out(mem_dq_out),
        .mem_dq_ts(mem_dq_ts),
        .of_dqbus(of_dqbus[39:4]),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .out_dqs_1(out_dqs_1),
        .po_oserdes_rst(po_oserdes_rst),
        .ts_dqs_1(ts_dqs_1));
  (* syn_maxfan = "3" *) 
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(if_empty_),
        .Q(if_empty_r),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[10]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [4]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[11]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [5]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[12]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [6]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[13]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [7]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[14]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [8]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[15]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [9]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[16]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [10]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[17]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [11]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[18]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[19]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[20]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[21]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[22]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[23]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[24]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[25]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[26]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[27]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[28]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[29]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[30]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[31]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[32]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[33]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[34]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[35]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[36]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[37]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[38]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[39]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[40]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[41]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[42]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[43]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[44]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[45]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[46]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[47]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[48]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[49]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[50]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[51]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[52]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[53]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[54]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[55]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[56]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[57]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[58]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[59]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[60]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[61]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[62]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[63]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[64]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[65]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[6]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [0]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[72]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[73]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[74]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[75]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[76]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[77]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[78]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [66]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[79]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [67]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[7]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [1]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[8]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [2]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data[9]),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [3]),
        .R(1'b0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_if_post_fifo \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.CLK(CLK),
        .app_rd_data(app_rd_data),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rd_data_valid_0(app_rd_data_valid_0),
        .app_rd_data_valid_1(app_rd_data_valid_1),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg0 (\gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg0 (\gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg0 (\gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg0 (\gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg0 (\gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg0 (\gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg0 (\gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg0 (\gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg0 (\gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg0 (\gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg0 (\gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg0 (\gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg0 (\gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg0 (\gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg0 (\gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg0 (\gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg0 (\gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg0 (\gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg0 (\gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg0 (\gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ({\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [67:60],\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [57:2]}),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg0 (\gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg0 (\gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg0 (\gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg0 (\gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg0 (\gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg0 (\gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg0 (\gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg0 (\gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg0 (\gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg0 (\gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg0 (\gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg0 (\gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg0 (\gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg0 (\gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg0 (\gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg0 (\gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg0 (\gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg0 (\gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg0 (\gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg0 (\gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg0 (\gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg0 (\gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg0 (\gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg0 (\gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg0 (\gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg0 (\gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg0 (\gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg0 (\gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg0 (\gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg0 (\gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg0 (\gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg0 (\gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg0 (\gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg0 (\gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg0 (\gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg0 (\gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg0 (\gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg0 (\gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg0 (\gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg0 (\gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg0 (\gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg0 (\gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg0 (\gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg0 (\gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .if_empty_r_0(if_empty_r_0),
        .ififo_rst(ififo_rst),
        .\my_empty_reg[0]_0 (\my_empty_reg[3] [0]),
        .\my_empty_reg[0]_1 (\my_empty_reg[0] ),
        .\my_empty_reg[0]_2 (\my_empty_reg[0]_0 ),
        .\my_empty_reg[3]_0 (\my_empty_reg[3] [1]),
        .\my_empty_reg[4]_rep__0_0 (\my_empty_reg[4]_rep__0 ),
        .\my_empty_reg[4]_rep__1_0 (if_empty_r),
        .\my_empty_reg[4]_rep__1_1 (\my_empty_reg[4]_rep__1 ),
        .p_1_in(p_1_in),
        .\rd_ptr_timing_reg[1]_0 (\rd_ptr_timing_reg[1] ),
        .\read_fifo.tail_r_reg (\read_fifo.tail_r_reg ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1] ));
  FDRE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ififo_rst_reg0_1),
        .Q(ififo_rst),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(D_if_a_empty),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8({1'b0,1'b0,1'b0,1'b0}),
        .D9(if_d9),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(rd_data[7:0]),
        .Q1(rd_data[15:8]),
        .Q2(rd_data[23:16]),
        .Q3(rd_data[31:24]),
        .Q4(rd_data[39:32]),
        .Q5(rd_data[47:40]),
        .Q6(rd_data[55:48]),
        .Q7(rd_data[63:56]),
        .Q8(rd_data[71:64]),
        .Q9(rd_data[79:72]),
        .RDCLK(CLK),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.CLK(CLK),
        .D_of_full(D_of_full),
        .Q(Q),
        .calib_wrdata_en(calib_wrdata_en),
        .mc_wrdata_en(mc_wrdata_en),
        .mux_wrdata_en(mux_wrdata_en),
        .\my_empty_reg[1]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1] ),
        .ofifo_rst(ofifo_rst),
        .out_fifo(out_fifo_0),
        .\rd_ptr_reg[0]_0 (\rd_ptr_reg[0] ),
        .\rd_ptr_reg[1]_0 (\rd_ptr_reg[1] ),
        .\rd_ptr_reg[2]_0 (\rd_ptr_reg[2] ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ),
        .wr_en(wr_en),
        .\wr_ptr_reg[3]_0 (\wr_ptr_reg[3] ),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0] ));
  FDRE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ofifo_rst_reg0_2),
        .Q(ofifo_rst),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(D_of_a_full),
        .D0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .D1(D1),
        .D2(\my_empty_reg[7] ),
        .D3(\my_empty_reg[7]_0 ),
        .D4(\my_empty_reg[7]_1 ),
        .D5(\my_empty_reg[7]_2 ),
        .D6(\my_empty_reg[7]_3 ),
        .D7(\my_empty_reg[7]_4 ),
        .D8(\my_empty_reg[7]_5 ),
        .D9(\my_empty_reg[7]_6 ),
        .EMPTY(out_fifo_n_2),
        .FULL(D_of_full),
        .Q0(of_dqbus[3:0]),
        .Q1(of_dqbus[7:4]),
        .Q2(of_dqbus[11:8]),
        .Q3(of_dqbus[15:12]),
        .Q4(of_dqbus[19:16]),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),
        .Q7(of_dqbus[31:28]),
        .Q8(of_dqbus[35:32]),
        .Q9(of_dqbus[39:36]),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(CLK),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b001),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.077000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(3.077000),
    .REFCLK_PERIOD(1.538500),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(INBURSTPENDING),
        .COUNTERLOADEN(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .COUNTERLOADVAL(\pi_dqs_found_lanes_r1_reg[3]_5 ),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .DQSFOUND(pi_dqs_found_lanes),
        .DQSOUTOFRANGE(D_pi_dqs_out_of_range),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\pi_dqs_found_lanes_r1_reg[3]_2 ),
        .FINEINC(\pi_dqs_found_lanes_r1_reg[3]_3 ),
        .FINEOVERFLOW(D_pi_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .ICLK(A_rst_primitives_reg),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(A_rst_primitives_reg_0),
        .PHASEREFCLK(mem_dqs_in),
        .RANKSELPHY(INRANKD),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(\pi_dqs_found_lanes_r1_reg[3] ),
        .RSTDQSFIND(\pi_dqs_found_lanes_r1_reg[3]_4 ),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(3.077000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.538500),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(OUTBURSTPENDING),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(D_po_coarse_overflow),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .COUNTERREADVAL(A_rst_primitives_reg_1),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_0 ),
        .FINEINC(\po_counter_read_val_reg[8]_1 ),
        .FINEOVERFLOW(D_po_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(\pi_dqs_found_lanes_r1_reg[3] ),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(CLK));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_calib_top
   (dqs_po_dec_done,
    po_cnt_dec_reg,
    po_cnt_dec_3,
    \rd_mux_sel_r_reg[0] ,
    new_cnt_cpt_r_reg,
    rdlvl_stg1_start_reg,
    samp_edge_cnt0_en_r,
    pi_fine_dly_dec_done,
    pi_cnt_dec_reg,
    rdlvl_stg1_done_int_reg,
    out,
    prbs_rdlvl_done_pulse_reg,
    calib_cmd_wren,
    calib_wrdata_en,
    phy_write_calib,
    phy_read_calib,
    tempmon_pi_f_inc,
    tempmon_pi_f_dec,
    idelay_inc,
    phy_dout,
    rdlvl_stg1_done_r1,
    calib_in_common,
    init_calib_complete_reg_rep_0,
    init_calib_complete_reg_rep__0_0,
    init_calib_complete_reg_rep__1_0,
    init_calib_complete_reg_rep__2_0,
    init_calib_complete_reg_rep__5_0,
    init_calib_complete_reg_rep__7_0,
    init_calib_complete_reg_rep__8_0,
    init_calib_complete_reg_rep__9_0,
    wrcal_done_reg,
    calib_ctl_wren_reg,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    calib_sel,
    \gen_byte_sel_div2.calib_in_common_reg_1 ,
    \gen_byte_sel_div2.calib_in_common_reg_2 ,
    \gen_byte_sel_div2.calib_in_common_reg_3 ,
    \gen_byte_sel_div2.calib_in_common_reg_4 ,
    dqs_wl_po_stg2_c_incdec_reg,
    \calib_sel_reg[1]_0 ,
    \calib_sel_reg[1]_1 ,
    \calib_sel_reg[1]_2 ,
    \calib_sel_reg[1]_3 ,
    \calib_sel_reg[1]_4 ,
    \calib_sel_reg[1]_5 ,
    \calib_sel_reg[1]_6 ,
    \calib_sel_reg[1]_7 ,
    \calib_sel_reg[1]_8 ,
    \calib_sel_reg[1]_9 ,
    idelay_ce_r2_reg_0,
    \gen_byte_sel_div2.calib_in_common_reg_5 ,
    \calib_sel_reg[0]_0 ,
    \gen_byte_sel_div2.calib_in_common_reg_6 ,
    ck_po_stg2_f_indec_reg,
    \pi_rst_stg1_cal_reg[0] ,
    pi_en_stg2_f_reg,
    pi_stg2_f_incdec_reg,
    pi_stg2_load_reg,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ,
    \gen_byte_sel_div2.calib_in_common_reg_7 ,
    init_calib_complete_reg_rep__0_1,
    \write_buffer.wr_buf_out_data_reg[122] ,
    E,
    \my_empty_reg[3] ,
    \my_empty_reg[5] ,
    \my_empty_reg[3]_0 ,
    \my_empty_reg[5]_0 ,
    \my_empty_reg[3]_1 ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ,
    \po_stg2_wrcal_cnt_reg[0] ,
    \init_state_r_reg[2] ,
    mux_wrdata_en,
    mux_cmd_wren,
    mux_reset_n,
    LD0,
    ififo_rst_reg0,
    ofifo_rst_reg0,
    LD0_0,
    ififo_rst_reg0_1,
    ofifo_rst_reg0_2,
    D0,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    D9,
    D1,
    \write_buffer.wr_buf_out_data_reg[124] ,
    \write_buffer.wr_buf_out_data_reg[126] ,
    \write_buffer.wr_buf_out_data_reg[121] ,
    \write_buffer.wr_buf_out_data_reg[123] ,
    \write_buffer.wr_buf_out_data_reg[127] ,
    \write_buffer.wr_buf_out_data_reg[125] ,
    init_calib_complete_reg_rep__4_0,
    \write_buffer.wr_buf_out_data_reg[122]_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[2] ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[8] ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[1] ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[4] ,
    D,
    COUNTERLOADVAL,
    \pi_stg2_reg_l_reg[5] ,
    calib_in_common4_out,
    dqs_found_done_r_reg,
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ,
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] ,
    \cmd_pipe_plus.mc_ras_n_reg[2] ,
    \cmd_pipe_plus.mc_cas_n_reg[2] ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[3] ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ,
    \cmd_pipe_plus.mc_cke_reg[3] ,
    \cmd_pipe_plus.mc_we_n_reg[2] ,
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ,
    Q,
    CLK,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    \smallest_reg[1][0] ,
    \rdlvl_dqs_tap_cnt_r_reg[0][1][4] ,
    in0,
    \gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[2] ,
    \samp_edge_cnt1_r_reg[0] ,
    pi_phase_locked_all_r1_reg,
    init_calib_complete_reg_0,
    prbs_rdlvl_done_pulse0,
    pi_f_dec_reg,
    mc_ref_zq_wip,
    \cnt_pwron_ce_r_reg[9] ,
    tempmon_sel_pi_incdec,
    phy_rddata_en,
    \gen_byte_sel_div2.calib_in_common_reg_8 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    wrcal_sanity_chk_done_reg,
    idelay_ld_reg,
    SR,
    \idelay_tap_cnt_r_reg[0][1][4] ,
    wrcal_done_reg_0,
    complex_row0_rd_done_reg,
    \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 ,
    \wr_ptr_timing_reg[0] ,
    wr_en_inferred__0_i_1,
    \wr_ptr_timing_reg[0]_0 ,
    wr_en_inferred__0_i_1__0,
    \wr_ptr_timing_reg[0]_1 ,
    wr_en_inferred__0_i_1__1,
    dqs_po_stg2_f_incdec_reg,
    \po_rdval_cnt_reg[8] ,
    \pi_rdval_cnt_reg[5] ,
    store_sr_req_r_reg,
    mc_wrdata_en,
    mc_cas_n,
    mc_ras_n,
    mc_odt,
    mc_cke,
    mc_we_n,
    idelay_ld_rst,
    A_rst_primitives,
    out_fifo,
    out_fifo_0,
    out_fifo_1,
    out_fifo_2,
    mc_address,
    mem_out,
    out_fifo_3,
    app_rd_data,
    \gen_rd[0].rd_data_rise_wl_r_reg[0] ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ,
    my_empty,
    \gen_rd[1].rd_data_rise_wl_r_reg[1] ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ,
    SS,
    \wait_cnt_r_reg[0] ,
    \tap_cnt_cpt_r_reg[5] ,
    \cnt_shift_r_reg[0] ,
    \wait_cnt_r_reg[0]_0 ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[4] ,
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126] ,
    \device_temp_101_reg[11] ,
    mc_cmd,
    \phy_ctl_wd_i1_reg[17] ,
    \phy_ctl_wd_i1_reg[18] ,
    \phy_ctl_wd_i1_reg[19] ,
    mc_data_offset,
    \phy_ctl_wd_i1_reg[21] ,
    \phy_ctl_wd_i1_reg[22] ,
    mc_bank,
    out_fifo_4,
    out_fifo_5,
    mc_cs_n,
    pi_dqs_found_lanes);
  output dqs_po_dec_done;
  output po_cnt_dec_reg;
  output po_cnt_dec_3;
  output \rd_mux_sel_r_reg[0] ;
  output new_cnt_cpt_r_reg;
  output rdlvl_stg1_start_reg;
  output samp_edge_cnt0_en_r;
  output pi_fine_dly_dec_done;
  output pi_cnt_dec_reg;
  output rdlvl_stg1_done_int_reg;
  output out;
  output prbs_rdlvl_done_pulse_reg;
  output calib_cmd_wren;
  output calib_wrdata_en;
  output phy_write_calib;
  output phy_read_calib;
  output tempmon_pi_f_inc;
  output tempmon_pi_f_dec;
  output idelay_inc;
  output [38:0]phy_dout;
  output rdlvl_stg1_done_r1;
  output calib_in_common;
  output init_calib_complete_reg_rep_0;
  output init_calib_complete_reg_rep__0_0;
  output init_calib_complete_reg_rep__1_0;
  output init_calib_complete_reg_rep__2_0;
  output init_calib_complete_reg_rep__5_0;
  output init_calib_complete_reg_rep__7_0;
  output init_calib_complete_reg_rep__8_0;
  output init_calib_complete_reg_rep__9_0;
  output wrcal_done_reg;
  output calib_ctl_wren_reg;
  output \gen_byte_sel_div2.calib_in_common_reg_0 ;
  output [1:0]calib_sel;
  output \gen_byte_sel_div2.calib_in_common_reg_1 ;
  output \gen_byte_sel_div2.calib_in_common_reg_2 ;
  output \gen_byte_sel_div2.calib_in_common_reg_3 ;
  output \gen_byte_sel_div2.calib_in_common_reg_4 ;
  output dqs_wl_po_stg2_c_incdec_reg;
  output \calib_sel_reg[1]_0 ;
  output \calib_sel_reg[1]_1 ;
  output \calib_sel_reg[1]_2 ;
  output \calib_sel_reg[1]_3 ;
  output \calib_sel_reg[1]_4 ;
  output \calib_sel_reg[1]_5 ;
  output \calib_sel_reg[1]_6 ;
  output \calib_sel_reg[1]_7 ;
  output \calib_sel_reg[1]_8 ;
  output \calib_sel_reg[1]_9 ;
  output idelay_ce_r2_reg_0;
  output \gen_byte_sel_div2.calib_in_common_reg_5 ;
  output \calib_sel_reg[0]_0 ;
  output \gen_byte_sel_div2.calib_in_common_reg_6 ;
  output ck_po_stg2_f_indec_reg;
  output \pi_rst_stg1_cal_reg[0] ;
  output pi_en_stg2_f_reg;
  output pi_stg2_f_incdec_reg;
  output pi_stg2_load_reg;
  output [32:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;
  output \gen_byte_sel_div2.calib_in_common_reg_7 ;
  output [59:0]init_calib_complete_reg_rep__0_1;
  output [59:0]\write_buffer.wr_buf_out_data_reg[122] ;
  output [0:0]E;
  output \my_empty_reg[3] ;
  output [0:0]\my_empty_reg[5] ;
  output \my_empty_reg[3]_0 ;
  output [0:0]\my_empty_reg[5]_0 ;
  output \my_empty_reg[3]_1 ;
  output \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;
  output [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  output [0:0]\po_stg2_wrcal_cnt_reg[0] ;
  output \init_state_r_reg[2] ;
  output mux_wrdata_en;
  output mux_cmd_wren;
  output mux_reset_n;
  output LD0;
  output ififo_rst_reg0;
  output ofifo_rst_reg0;
  output LD0_0;
  output ififo_rst_reg0_1;
  output ofifo_rst_reg0_2;
  output [7:0]D0;
  output [7:0]D2;
  output [7:0]D3;
  output [7:0]D4;
  output [7:0]D5;
  output [7:0]D6;
  output [7:0]D7;
  output [7:0]D8;
  output [7:0]D9;
  output [7:0]D1;
  output [7:0]\write_buffer.wr_buf_out_data_reg[124] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[126] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[121] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[123] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[127] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[125] ;
  output [7:0]init_calib_complete_reg_rep__4_0;
  output [7:0]\write_buffer.wr_buf_out_data_reg[122]_0 ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[2] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[8] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[1] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;
  output [7:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[4] ;
  output [10:0]D;
  output [5:0]COUNTERLOADVAL;
  output [5:0]\pi_stg2_reg_l_reg[5] ;
  output calib_in_common4_out;
  output dqs_found_done_r_reg;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] ;
  output [2:0]\cmd_pipe_plus.mc_ras_n_reg[2] ;
  output [5:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[3] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;
  output [7:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  output [2:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ;
  input [0:0]Q;
  input CLK;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  input [1:0]\smallest_reg[1][0] ;
  input [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][1][4] ;
  input in0;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  input \samp_edge_cnt1_r_reg[0] ;
  input pi_phase_locked_all_r1_reg;
  input init_calib_complete_reg_0;
  input prbs_rdlvl_done_pulse0;
  input pi_f_dec_reg;
  input mc_ref_zq_wip;
  input [3:0]\cnt_pwron_ce_r_reg[9] ;
  input tempmon_sel_pi_incdec;
  input phy_rddata_en;
  input \gen_byte_sel_div2.calib_in_common_reg_8 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  input [0:0]wrcal_sanity_chk_done_reg;
  input idelay_ld_reg;
  input [0:0]SR;
  input \idelay_tap_cnt_r_reg[0][1][4] ;
  input wrcal_done_reg_0;
  input complex_row0_rd_done_reg;
  input [143:0]\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 ;
  input \wr_ptr_timing_reg[0] ;
  input wr_en_inferred__0_i_1;
  input \wr_ptr_timing_reg[0]_0 ;
  input wr_en_inferred__0_i_1__0;
  input \wr_ptr_timing_reg[0]_1 ;
  input wr_en_inferred__0_i_1__1;
  input dqs_po_stg2_f_incdec_reg;
  input [8:0]\po_rdval_cnt_reg[8] ;
  input [5:0]\pi_rdval_cnt_reg[5] ;
  input store_sr_req_r_reg;
  input mc_wrdata_en;
  input [2:0]mc_cas_n;
  input [2:0]mc_ras_n;
  input [0:0]mc_odt;
  input [0:0]mc_cke;
  input [2:0]mc_we_n;
  input idelay_ld_rst;
  input A_rst_primitives;
  input [71:0]out_fifo;
  input out_fifo_0;
  input [71:0]out_fifo_1;
  input out_fifo_2;
  input [38:0]mc_address;
  input [35:0]mem_out;
  input out_fifo_3;
  input [13:0]app_rd_data;
  input [0:0]\gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  input [0:0]\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  input [0:0]my_empty;
  input [0:0]\gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  input [0:0]\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  input [0:0]SS;
  input [0:0]\wait_cnt_r_reg[0] ;
  input [0:0]\tap_cnt_cpt_r_reg[5] ;
  input [0:0]\cnt_shift_r_reg[0] ;
  input [0:0]\wait_cnt_r_reg[0]_0 ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  input [0:0]\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126] ;
  input [11:0]\device_temp_101_reg[11] ;
  input [1:0]mc_cmd;
  input \phy_ctl_wd_i1_reg[17] ;
  input \phy_ctl_wd_i1_reg[18] ;
  input \phy_ctl_wd_i1_reg[19] ;
  input [0:0]mc_data_offset;
  input \phy_ctl_wd_i1_reg[21] ;
  input \phy_ctl_wd_i1_reg[22] ;
  input [8:0]mc_bank;
  input [43:0]out_fifo_4;
  input out_fifo_5;
  input [0:0]mc_cs_n;
  input [1:0]pi_dqs_found_lanes;

  wire A_rst_primitives;
  wire CLK;
  wire [5:0]COUNTERLOADVAL;
  wire [10:0]D;
  wire [7:0]D0;
  wire [7:0]D1;
  wire [7:0]D2;
  wire [7:0]D3;
  wire [7:0]D4;
  wire [7:0]D5;
  wire [7:0]D6;
  wire [7:0]D7;
  wire [7:0]D8;
  wire [7:0]D9;
  wire [0:0]E;
  wire LD0;
  wire LD0_0;
  wire [0:0]Q;
  wire RSTB;
  wire [0:0]SR;
  wire [0:0]SS;
  wire [13:0]app_rd_data;
  wire calib_cmd_wren;
  wire calib_complete;
  wire calib_ctl_wren_reg;
  wire calib_in_common;
  wire calib_in_common4_out;
  wire [1:0]calib_sel;
  wire calib_sel0;
  wire calib_sel15_out;
  wire \calib_sel[0]_i_2_n_0 ;
  wire \calib_sel_reg[0]_0 ;
  wire \calib_sel_reg[1]_0 ;
  wire \calib_sel_reg[1]_1 ;
  wire \calib_sel_reg[1]_2 ;
  wire \calib_sel_reg[1]_3 ;
  wire \calib_sel_reg[1]_4 ;
  wire \calib_sel_reg[1]_5 ;
  wire \calib_sel_reg[1]_6 ;
  wire \calib_sel_reg[1]_7 ;
  wire \calib_sel_reg[1]_8 ;
  wire \calib_sel_reg[1]_9 ;
  wire calib_wrdata_en;
  wire calib_zero_inputs;
  wire ck_addr_cmd_delay_done;
  wire ck_po_stg2_f_en;
  wire ck_po_stg2_f_indec;
  wire ck_po_stg2_f_indec_reg;
  wire cmd_delay_start0;
  wire [5:0]\cmd_pipe_plus.mc_cas_n_reg[2] ;
  wire [7:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  wire [7:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  wire [2:0]\cmd_pipe_plus.mc_ras_n_reg[2] ;
  wire [2:0]\cmd_pipe_plus.mc_we_n_reg[2] ;
  wire cmd_po_en_stg2_f;
  wire [3:0]\cnt_pwron_ce_r_reg[9] ;
  wire [0:0]\cnt_shift_r_reg[0] ;
  wire complex_row0_rd_done_reg;
  wire [0:0]ctl_lane_cnt;
  wire ddr3_lm_done_r;
  wire [143:0]\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_11 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_12 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_24 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_26 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_8 ;
  wire ddr_phy_tempmon_0_n_2;
  wire ddr_phy_tempmon_0_n_3;
  wire ddr_phy_tempmon_0_n_5;
  wire ddr_phy_tempmon_0_n_6;
  wire detect_pi_found_dqs;
  wire [11:0]\device_temp_101_reg[11] ;
  wire done_dqs_dec237_out;
  wire done_dqs_tap_inc;
  wire dqs_found_done_r_reg;
  wire dqs_found_prech_req;
  wire dqs_po_dec_done;
  wire dqs_po_en_stg2_f;
  wire dqs_po_stg2_f_incdec;
  wire dqs_po_stg2_f_incdec_reg;
  wire dqs_wl_po_stg2_c_incdec_reg;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_12 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_21 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_22 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_23 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_24 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_25 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_26 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_3 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_31 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_32 ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  wire [0:0]fine_adj_state_r;
  wire first_rdlvl_pat_r;
  wire first_wrcal_pat_r;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_1 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_2 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_3 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_4 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_5 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_6 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_7 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_8 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire [32:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[1] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[2] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[3] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[4] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[8] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ;
  wire [0:0]\gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  wire [0:0]\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  wire [0:0]\gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  wire [0:0]\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  wire idelay_ce;
  wire idelay_ce_int;
  wire idelay_ce_r1;
  wire idelay_ce_r2_reg_0;
  wire idelay_inc;
  wire idelay_inc_int;
  wire idelay_inc_r1;
  wire idelay_ld_reg;
  wire idelay_ld_rst;
  wire \idelay_tap_cnt_r_reg[0][1][4] ;
  wire ififo_rst_reg0;
  wire ififo_rst_reg0_1;
  wire in0;
  wire init_calib_complete_reg_0;
  wire init_calib_complete_reg_rep_0;
  wire init_calib_complete_reg_rep__0_0;
  wire [59:0]init_calib_complete_reg_rep__0_1;
  wire init_calib_complete_reg_rep__1_0;
  wire init_calib_complete_reg_rep__2_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__3_n_0;
  wire [7:0]init_calib_complete_reg_rep__4_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__4_n_0;
  wire init_calib_complete_reg_rep__5_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__6_n_0;
  wire init_calib_complete_reg_rep__7_0;
  wire init_calib_complete_reg_rep__8_0;
  wire init_calib_complete_reg_rep__9_0;
  wire \init_state_r_reg[2] ;
  wire \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_4 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_16 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_17 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_18 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_20 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_21 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_22 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_4 ;
  wire [38:0]mc_address;
  wire [8:0]mc_bank;
  wire [2:0]mc_cas_n;
  wire [0:0]mc_cke;
  wire [1:0]mc_cmd;
  wire [0:0]mc_cs_n;
  wire [0:0]mc_data_offset;
  wire [0:0]mc_odt;
  wire [2:0]mc_ras_n;
  wire mc_ref_zq_wip;
  wire [2:0]mc_we_n;
  wire mc_wrdata_en;
  wire mem_init_done_r;
  wire [35:0]mem_out;
  wire mux_cmd_wren;
  wire mux_reset_n;
  wire mux_wrdata_en;
  wire [0:0]my_empty;
  wire \my_empty_reg[3] ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[3]_1 ;
  wire [0:0]\my_empty_reg[5] ;
  wire [0:0]\my_empty_reg[5]_0 ;
  wire new_cnt_cpt_r_reg;
  wire ofifo_rst_reg0;
  wire ofifo_rst_reg0_2;
  wire out;
  wire [71:0]out_fifo;
  wire out_fifo_0;
  wire [71:0]out_fifo_1;
  wire out_fifo_2;
  wire out_fifo_3;
  wire [43:0]out_fifo_4;
  wire out_fifo_5;
  wire p_1_in;
  wire \phy_ctl_wd_i1_reg[17] ;
  wire \phy_ctl_wd_i1_reg[18] ;
  wire \phy_ctl_wd_i1_reg[19] ;
  wire \phy_ctl_wd_i1_reg[21] ;
  wire \phy_ctl_wd_i1_reg[22] ;
  wire [38:0]phy_dout;
  wire phy_if_reset;
  wire phy_if_reset0__0;
  wire phy_if_reset_w;
  wire phy_rddata_en;
  wire phy_read_calib;
  wire phy_write_calib;
  wire pi_calib_done;
  wire pi_cnt_dec_reg;
  wire pi_dqs_found_done_r1;
  wire [1:0]pi_dqs_found_lanes;
  wire pi_dqs_found_rank_done;
  wire pi_en_stg2_f_reg;
  wire pi_f_dec_reg;
  wire pi_fine_dly_dec_done;
  wire pi_phase_locked_all_r1_reg;
  wire [5:0]\pi_rdval_cnt_reg[5] ;
  wire \pi_rst_stg1_cal_reg[0] ;
  wire pi_stg2_f_incdec_reg;
  wire pi_stg2_load_reg;
  wire [5:0]\pi_stg2_reg_l_reg[5] ;
  wire po_cnt_dec_3;
  wire po_cnt_dec_reg;
  wire [2:2]po_enstg2_f;
  wire [8:0]\po_rdval_cnt_reg[8] ;
  wire [1:1]po_stg2_wrcal_cnt;
  wire [0:0]\po_stg2_wrcal_cnt_reg[0] ;
  wire prbs_rdlvl_done_pulse0;
  wire prbs_rdlvl_done_pulse_reg;
  wire prech_done;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;
  wire [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  wire rd_active_r;
  wire rd_data_offset_cal_done;
  wire \rd_mux_sel_r_reg[0] ;
  wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][1][4] ;
  wire rdlvl_last_byte_done;
  wire rdlvl_pi_incdec;
  wire rdlvl_prech_req;
  wire rdlvl_stg1_done_int_reg;
  wire rdlvl_stg1_done_r1;
  wire rdlvl_stg1_rank_done;
  wire rdlvl_stg1_start_reg;
  wire reset_if;
  wire reset_if_r8_reg_srl8_n_0;
  wire reset_if_r9;
  wire samp_edge_cnt0_en_r;
  wire \samp_edge_cnt1_r_reg[0] ;
  wire [1:0]\smallest_reg[1][0] ;
  wire store_sr_req_r_reg;
  wire [0:0]\tap_cnt_cpt_r_reg[5] ;
  wire tempmon_pi_f_dec;
  wire tempmon_pi_f_en_r;
  wire tempmon_pi_f_inc;
  wire tempmon_pi_f_inc_r;
  wire tempmon_sel_pi_incdec;
  wire u_ddr_phy_init_n_14;
  wire u_ddr_phy_init_n_16;
  wire u_ddr_phy_init_n_2;
  wire u_ddr_phy_init_n_278;
  wire u_ddr_phy_init_n_351;
  wire u_ddr_phy_init_n_352;
  wire u_ddr_phy_init_n_353;
  wire u_ddr_phy_wrcal_n_12;
  wire u_ddr_phy_wrcal_n_13;
  wire u_ddr_phy_wrcal_n_14;
  wire u_ddr_phy_wrcal_n_15;
  wire u_ddr_phy_wrcal_n_16;
  wire u_ddr_phy_wrcal_n_17;
  wire u_ddr_phy_wrcal_n_18;
  wire u_ddr_phy_wrcal_n_19;
  wire u_ddr_phy_wrcal_n_20;
  wire u_ddr_phy_wrcal_n_4;
  wire u_ddr_phy_wrcal_n_6;
  wire u_ddr_phy_wrcal_n_9;
  wire [0:0]\wait_cnt_r_reg[0] ;
  wire [0:0]\wait_cnt_r_reg[0]_0 ;
  wire wl_sm_start;
  wire wr_en_inferred__0_i_1;
  wire wr_en_inferred__0_i_1__0;
  wire wr_en_inferred__0_i_1__1;
  wire \wr_ptr_timing_reg[0] ;
  wire \wr_ptr_timing_reg[0]_0 ;
  wire \wr_ptr_timing_reg[0]_1 ;
  wire wrcal_done_reg;
  wire wrcal_done_reg_0;
  wire wrcal_prech_req;
  wire wrcal_rd_wait;
  wire wrcal_resume_w;
  wire wrcal_sanity_chk;
  wire [0:0]wrcal_sanity_chk_done_reg;
  wire [0:0]\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[121] ;
  wire [59:0]\write_buffer.wr_buf_out_data_reg[122] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[122]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[123] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[124] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[125] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[126] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[127] ;
  wire wrlvl_byte_done;
  wire wrlvl_byte_redo;
  wire wrlvl_byte_redo_r;
  wire wrlvl_done_r1;
  wire wrlvl_final_if_rst;
  wire wrlvl_rank_done;

  LUT2 #(
    .INIT(4'h2)) 
    \calib_sel[0]_i_2 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0] ),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ),
        .O(\calib_sel[0]_i_2_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \calib_sel_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_22 ),
        .Q(calib_sel[0]),
        .R(1'b0));
  (* syn_maxfan = "10" *) 
  FDRE \calib_sel_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_32 ),
        .Q(calib_sel[1]),
        .R(1'b0));
  (* syn_maxfan = "10" *) 
  FDSE \calib_zero_inputs_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(ddr_phy_tempmon_0_n_5),
        .Q(calib_zero_inputs),
        .S(in0));
  (* SOFT_HLUTNM = "soft_lutpair447" *) 
  LUT4 #(
    .INIT(16'hBBF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_11 
       (.I0(mc_ras_n[2]),
        .I1(init_calib_complete_reg_rep__8_0),
        .I2(out_fifo_4[10]),
        .I3(out_fifo_5),
        .O(\cmd_pipe_plus.mc_ras_n_reg[2] [2]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_13 
       (.I0(mc_cs_n),
        .I1(init_calib_complete_reg_rep__8_0),
        .I2(out_fifo_4[8]),
        .I3(out_fifo_5),
        .O(\cmd_pipe_plus.mc_ras_n_reg[2] [0]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_31 
       (.I0(mc_cas_n[2]),
        .I1(init_calib_complete_reg_rep__7_0),
        .I2(out_fifo_4[32]),
        .I3(out_fifo_5),
        .O(\cmd_pipe_plus.mc_cas_n_reg[2] [5]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_33 
       (.I0(mc_cas_n[0]),
        .I1(init_calib_complete_reg_rep__7_0),
        .I2(out_fifo_4[30]),
        .I3(out_fifo_5),
        .O(\cmd_pipe_plus.mc_cas_n_reg[2] [3]));
  (* SOFT_HLUTNM = "soft_lutpair447" *) 
  LUT4 #(
    .INIT(16'hBBF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_35 
       (.I0(mc_ras_n[2]),
        .I1(init_calib_complete_reg_rep__8_0),
        .I2(out_fifo_4[29]),
        .I3(out_fifo_5),
        .O(\cmd_pipe_plus.mc_cas_n_reg[2] [2]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_37 
       (.I0(mc_ras_n[0]),
        .I1(init_calib_complete_reg_rep__7_0),
        .I2(out_fifo_4[27]),
        .I3(out_fifo_5),
        .O(\cmd_pipe_plus.mc_cas_n_reg[2] [0]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_39 
       (.I0(mc_we_n[2]),
        .I1(init_calib_complete_reg_rep__7_0),
        .I2(out_fifo_4[35]),
        .I3(out_fifo_5),
        .O(\cmd_pipe_plus.mc_we_n_reg[2] [2]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_41 
       (.I0(mc_we_n[0]),
        .I1(init_calib_complete_reg_rep__7_0),
        .I2(out_fifo_4[33]),
        .I3(out_fifo_5),
        .O(\cmd_pipe_plus.mc_we_n_reg[2] [0]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_rdlvl \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl 
       (.CLK(CLK),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .D({\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_8 ,rdlvl_stg1_done_int_reg,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_11 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_12 }),
        .E(rd_active_r),
        .Q({po_stg2_wrcal_cnt,\po_stg2_wrcal_cnt_reg[0] }),
        .\cal1_cnt_cpt_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_24 ),
        .\calib_sel_reg[1] (\calib_sel_reg[1]_7 ),
        .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_8 ),
        .\calib_sel_reg[1]_1 (\calib_sel_reg[1]_9 ),
        .calib_zero_inputs(calib_zero_inputs),
        .\cnt_shift_r_reg[0]_0 (\cnt_shift_r_reg[0] ),
        .dqs_po_dec_done_r1_reg_0(dqs_po_dec_done),
        .first_rdlvl_pat_r(first_rdlvl_pat_r),
        .first_wrcal_pat_r(first_wrcal_pat_r),
        .found_first_edge_r_reg_0(\en_cnt_div4.enable_wrlvl_cnt_reg[2] ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0] (wrcal_done_reg),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg0 (\gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg0 (\gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg0 (\gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg0 (\gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg0 (\gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg0 (\gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg0 (\gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg0 (\gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg0 (\gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg0 (\gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg0 (\gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg0 (\gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg0 (\gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg0 (\gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg0 (\gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg0 (\gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg0 (\gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg0 (\gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg0 (\gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg0 (\gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg0 (\gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg0 (\gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg0 (\gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg0 (\gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg0 (\gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg0 (\gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg0 (\gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg0 (\gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg0 (\gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg0 (\gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg0 (\gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg0 (\gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg0 (\gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg0 (\gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg0 (\gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg0 (\gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg0 (\gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg0 (\gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg0 (\gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg0 (\gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg0 (\gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg0 (\gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg0 (\gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg0 (\gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg0 (\gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg0 (\gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg0 (\gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg0 (\gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg0 (\gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg0 (\gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg0 (\gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg0 (\gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg0 (\gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg0 (\gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg0 (\gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg0 (\gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg0 (\gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg0 (\gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg0 (\gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg0 (\gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg0 (\gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg0 (\gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg0 (\gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg0 (\gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .idelay_ce_int(idelay_ce_int),
        .idelay_inc_int(idelay_inc_int),
        .\idelay_tap_cnt_r_reg[0][0][0]_0 (u_ddr_phy_wrcal_n_13),
        .\idelay_tap_cnt_r_reg[0][1][1]_0 (\idelay_tap_cnt_r_reg[0][1][4] ),
        .\idelay_tap_cnt_r_reg[0][1][4]_0 (u_ddr_phy_wrcal_n_12),
        .in0(in0),
        .\init_state_r[2]_i_17 (u_ddr_phy_init_n_14),
        .mpr_rdlvl_start_r_reg_0(u_ddr_phy_init_n_353),
        .new_cnt_cpt_r_reg_0(new_cnt_cpt_r_reg),
        .p_1_in(p_1_in),
        .pi_calib_done(pi_calib_done),
        .pi_calib_done_r1_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25 ),
        .pi_cnt_dec_reg_0(pi_cnt_dec_reg),
        .pi_dqs_found_done(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2 ),
        .\pi_dqs_found_lanes_r1_reg[3] (calib_sel[1]),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (calib_sel[0]),
        .\pi_dqs_found_lanes_r1_reg[3]_1 (calib_in_common),
        .pi_en_stg2_f_reg_0(pi_en_stg2_f_reg),
        .pi_fine_dly_dec_done_reg_0(pi_fine_dly_dec_done),
        .\pi_rdval_cnt_reg[5]_0 (\pi_rdval_cnt_reg[5] ),
        .pi_stg2_f_incdec_reg_0(pi_stg2_f_incdec_reg),
        .pi_stg2_load_reg_0(pi_stg2_load_reg),
        .\pi_stg2_reg_l_reg[5]_0 (\pi_stg2_reg_l_reg[5] ),
        .po_cnt_dec_reg(dqs_po_stg2_f_incdec_reg),
        .\po_stg2_wrcal_cnt_reg[0] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27 ),
        .\po_stg2_wrcal_cnt_reg[1] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_26 ),
        .prech_done(prech_done),
        .\rd_mux_sel_r_reg[0]_0 (\rd_mux_sel_r_reg[0] ),
        .\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 (\rdlvl_dqs_tap_cnt_r_reg[0][1][4] ),
        .rdlvl_last_byte_done(rdlvl_last_byte_done),
        .rdlvl_pi_incdec(rdlvl_pi_incdec),
        .rdlvl_prech_req(rdlvl_prech_req),
        .rdlvl_stg1_done_int_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22 ),
        .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done),
        .rdlvl_stg1_start_r_reg_0(rdlvl_stg1_start_reg),
        .reset_if(reset_if),
        .reset_if_r9(reset_if_r9),
        .reset_if_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28 ),
        .reset_if_reg_0(rdlvl_stg1_done_r1),
        .reset_if_reg_1(wrcal_done_reg_0),
        .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),
        .\samp_edge_cnt1_r_reg[0]_0 (\samp_edge_cnt1_r_reg[0] ),
        .store_sr_req_r_reg_0(store_sr_req_r_reg),
        .\tap_cnt_cpt_r_reg[5]_0 (\tap_cnt_cpt_r_reg[5] ),
        .tempmon_pi_f_en_r(tempmon_pi_f_en_r),
        .tempmon_pi_f_inc_r(tempmon_pi_f_inc_r),
        .\wait_cnt_r_reg[0]_0 (\wait_cnt_r_reg[0]_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_tempmon ddr_phy_tempmon_0
       (.CLK(CLK),
        .D(rdlvl_stg1_done_int_reg),
        .calib_complete(calib_complete),
        .calib_sel0(calib_sel0),
        .\calib_sel_reg[0] (wrcal_done_reg_0),
        .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
        .delay_done_r4_reg(ddr_phy_tempmon_0_n_2),
        .\device_temp_101_reg[11]_0 (\device_temp_101_reg[11] ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[1] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_4 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 (wrcal_done_reg),
        .init_calib_complete_reg(ddr_phy_tempmon_0_n_5),
        .mc_ref_zq_wip(mc_ref_zq_wip),
        .pi_dqs_found_done(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2 ),
        .pi_f_dec_reg_0(tempmon_pi_f_dec),
        .pi_f_dec_reg_1(pi_f_dec_reg),
        .pi_f_inc_reg_0(tempmon_pi_f_inc),
        .rdlvl_stg1_done_int_reg(ddr_phy_tempmon_0_n_3),
        .\three_dec_max_limit_reg[0]_0 (\cnt_pwron_ce_r_reg[9] ),
        .wrcal_done_reg(ddr_phy_tempmon_0_n_6));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr 
       (.A_rst_primitives(A_rst_primitives),
        .CLK(CLK),
        .D(rdlvl_stg1_done_int_reg),
        .Q(fine_adj_state_r),
        .RSTB(RSTB),
        .calib_in_common4_out(calib_in_common4_out),
        .calib_sel0(calib_sel0),
        .calib_sel15_out(calib_sel15_out),
        .\calib_sel_reg[1] (\calib_sel_reg[1]_5 ),
        .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_6 ),
        .\calib_sel_reg[1]_1 (\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ),
        .calib_zero_inputs(calib_zero_inputs),
        .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
        .ck_po_stg2_f_en(ck_po_stg2_f_en),
        .ck_po_stg2_f_en_reg_0(wrcal_sanity_chk_done_reg),
        .ck_po_stg2_f_indec(ck_po_stg2_f_indec),
        .ck_po_stg2_f_indec_reg_0(ck_po_stg2_f_indec_reg),
        .cmd_delay_start0(cmd_delay_start0),
        .ctl_lane_cnt(ctl_lane_cnt),
        .\ctl_lane_cnt_reg[0]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_31 ),
        .detect_pi_found_dqs(detect_pi_found_dqs),
        .\detect_rd_cnt_reg[2]_0 (\idelay_tap_cnt_r_reg[0][1][4] ),
        .dqs_found_done_r_reg_0(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_26 ),
        .dqs_found_done_r_reg_1(dqs_found_done_r_reg),
        .dqs_found_prech_req(dqs_found_prech_req),
        .dqs_found_start_r_reg_0(u_ddr_phy_init_n_352),
        .dqs_po_stg2_f_incdec(dqs_po_stg2_f_incdec),
        .fine_adjust_done_r_reg_0(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_3 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[1] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_32 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 (wrcal_done_reg_0),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_1 ),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (ddr_phy_tempmon_0_n_6),
        .\gen_byte_sel_div2.calib_in_common_reg_1 (ddr_phy_tempmon_0_n_3),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[0] (\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0] ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[0]_0 (pi_fine_dly_dec_done),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[0]_1 (dqs_po_dec_done),
        .ififo_rst_reg0(ififo_rst_reg0),
        .ififo_rst_reg0_1(ififo_rst_reg0_1),
        .in0(in0),
        .ofifo_rst_reg(calib_in_common),
        .ofifo_rst_reg0(ofifo_rst_reg0),
        .ofifo_rst_reg0_2(ofifo_rst_reg0_2),
        .ofifo_rst_reg_0(calib_sel[0]),
        .ofifo_rst_reg_1(calib_sel[1]),
        .phy_if_reset(phy_if_reset),
        .pi_calib_done(pi_calib_done),
        .pi_dqs_found_done(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2 ),
        .pi_dqs_found_done_r1(pi_dqs_found_done_r1),
        .pi_dqs_found_done_r1_reg(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_21 ),
        .pi_dqs_found_done_r1_reg_0(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_22 ),
        .pi_dqs_found_done_r1_reg_1(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_23 ),
        .pi_dqs_found_done_r1_reg_2(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_24 ),
        .pi_dqs_found_done_r1_reg_3(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_25 ),
        .pi_dqs_found_lanes(pi_dqs_found_lanes),
        .pi_dqs_found_rank_done(pi_dqs_found_rank_done),
        .\pi_rst_stg1_cal_r_reg[0]_0 (dqs_po_stg2_f_incdec_reg),
        .\pi_rst_stg1_cal_reg[0]_0 (\pi_rst_stg1_cal_reg[0] ),
        .prech_done(prech_done),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 (\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 (\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]_0 (\smallest_reg[1][0] [0]),
        .\rd_byte_data_offset_reg[0][3]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_12 ),
        .rd_data_offset_cal_done(rd_data_offset_cal_done),
        .rst_dqs_find_i_4_0(u_ddr_phy_init_n_278));
  FDRE \gen_byte_sel_div2.byte_sel_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_21 ),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_byte_sel_div2.byte_sel_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_20 ),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ),
        .R(1'b0));
  (* syn_maxfan = "10" *) 
  FDRE \gen_byte_sel_div2.calib_in_common_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_byte_sel_div2.calib_in_common_reg_8 ),
        .Q(calib_in_common),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4] [0]));
  FDRE \gen_byte_sel_div2.ctl_lane_sel_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_31 ),
        .Q(\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4] [0]));
  FDRE \gen_byte_sel_div2.ctl_lane_sel_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_4 ),
        .Q(\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4] [0]));
  FDRE idelay_ce_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ce_int),
        .Q(idelay_ce_r1),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4] [0]));
  FDRE idelay_ce_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ce_r1),
        .Q(idelay_ce),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4] [0]));
  FDRE idelay_inc_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_inc_int),
        .Q(idelay_inc_r1),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4] [0]));
  (* syn_maxfan = "30" *) 
  FDRE idelay_inc_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_inc_r1),
        .Q(idelay_inc),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4] [0]));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(phy_dout[13]),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__0
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__0_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__1
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__1_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__2
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__2_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__3
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__3_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__4
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__4_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__5
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__5_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__6
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__6_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__7
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__7_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__8
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__8_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__9
       (.C(CLK),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__9_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair446" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_1 
       (.I0(calib_sel[1]),
        .I1(idelay_ce),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs),
        .O(\calib_sel_reg[1]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair446" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1 
       (.I0(idelay_ce),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs),
        .O(idelay_ce_r2_reg_0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay 
       (.CLK(CLK),
        .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
        .cmd_delay_start0(cmd_delay_start0),
        .cmd_po_en_stg2_f(cmd_po_en_stg2_f),
        .\ctl_lane_cnt_reg[0]_0 (ctl_lane_cnt),
        .\ctl_lane_cnt_reg[1]_0 (\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_4 ),
        .\delaydec_cnt_r_reg[4]_0 (dqs_po_stg2_f_incdec_reg),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[1] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_3 ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[1]_0 (\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1] ),
        .in0(in0),
        .p_1_in(p_1_in),
        .po_cnt_dec_3(po_cnt_dec_3),
        .rd_data_offset_cal_done(rd_data_offset_cal_done),
        .\wait_cnt_r_reg[0]_0 (dqs_po_dec_done),
        .\wait_cnt_r_reg[0]_1 (pi_fine_dly_dec_done),
        .\wait_cnt_r_reg[0]_2 (\wait_cnt_r_reg[0] ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_wrlvl \mb_wrlvl_inst.u_ddr_phy_wrlvl 
       (.CLK(CLK),
        .\FSM_sequential_wl_state_r[4]_i_4_0 (u_ddr_phy_wrcal_n_9),
        .Q(Q),
        .RSTB(RSTB),
        .SS(SS),
        .app_rd_data(app_rd_data),
        .calib_sel0(calib_sel0),
        .calib_sel15_out(calib_sel15_out),
        .\calib_sel_reg[0] (\calib_sel_reg[0]_0 ),
        .\calib_sel_reg[0]_0 (\calib_sel[0]_i_2_n_0 ),
        .\calib_sel_reg[0]_1 (\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1] ),
        .\calib_sel_reg[0]_2 (\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0] ),
        .\calib_sel_reg[0]_3 (pi_fine_dly_dec_done),
        .\calib_sel_reg[1] (\calib_sel_reg[1]_1 ),
        .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_4 ),
        .calib_zero_inputs(calib_zero_inputs),
        .ck_po_stg2_f_indec(ck_po_stg2_f_indec),
        .cmd_delay_start0(cmd_delay_start0),
        .done_dqs_dec237_out(done_dqs_dec237_out),
        .done_dqs_tap_inc(done_dqs_tap_inc),
        .\dqs_count_r_reg[1]_0 ({po_stg2_wrcal_cnt,\po_stg2_wrcal_cnt_reg[0] }),
        .dqs_po_dec_done_reg_0(dqs_po_dec_done),
        .dqs_po_en_stg2_f(dqs_po_en_stg2_f),
        .dqs_po_stg2_f_incdec(dqs_po_stg2_f_incdec),
        .dqs_po_stg2_f_incdec_reg_0(dqs_po_stg2_f_incdec_reg),
        .dqs_wl_po_stg2_c_incdec_reg_0(dqs_wl_po_stg2_c_incdec_reg),
        .\final_coarse_tap_reg[0][0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_18 ),
        .\final_coarse_tap_reg[1][0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_17 ),
        .\final_coarse_tap_reg[1][1]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_16 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_21 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 (\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0] ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[1] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_20 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 (\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[1]_1 (ddr_phy_tempmon_0_n_2),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[1]_2 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_26 ),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_2 ),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (\gen_byte_sel_div2.calib_in_common_reg_3 ),
        .\gen_byte_sel_div2.calib_in_common_reg_1 (\gen_byte_sel_div2.calib_in_common_reg_4 ),
        .\gen_byte_sel_div2.calib_in_common_reg_2 (\gen_byte_sel_div2.calib_in_common_reg_5 ),
        .\gen_byte_sel_div2.calib_in_common_reg_3 (\gen_byte_sel_div2.calib_in_common_reg_6 ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[1] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_22 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 (\gen_rd[0].rd_data_rise_wl_r_reg[0] ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ),
        .in0(in0),
        .my_empty(my_empty),
        .phaser_out(calib_in_common),
        .phaser_out_0(calib_sel[0]),
        .phaser_out_1(calib_sel[1]),
        .po_cnt_dec_reg_0(po_cnt_dec_reg),
        .po_enstg2_f(po_enstg2_f),
        .\po_rdval_cnt_reg[8]_0 (\po_rdval_cnt_reg[8] ),
        .\single_rank.done_dqs_dec_reg_0 (wrcal_done_reg_0),
        .\smallest_reg[1][0]_0 (\smallest_reg[1][0] ),
        .\wl_dqs_tap_count_r_reg[0][0][2]_0 (\rdlvl_dqs_tap_cnt_r_reg[0][1][4] [0]),
        .wl_sm_start(wl_sm_start),
        .wr_level_done_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_4 ),
        .wr_level_start_r_reg_0(u_ddr_phy_init_n_16),
        .wrlvl_byte_done(wrlvl_byte_done),
        .wrlvl_byte_redo(wrlvl_byte_redo),
        .wrlvl_byte_redo_r(wrlvl_byte_redo_r),
        .wrlvl_rank_done(wrlvl_rank_done),
        .\wrlvl_redo_corse_inc[1]_i_2_0 (u_ddr_phy_wrcal_n_6));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_1__0
       (.I0(init_calib_complete_reg_rep__1_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [22]),
        .O(init_calib_complete_reg_rep__0_1[8]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_3
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [120]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [6]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_18_23_i_5__0
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [124]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [13]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_24_29_i_1
       (.I0(init_calib_complete_reg_rep__3_n_0),
        .I1(mc_address[13]),
        .O(phy_dout[10]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_24_29_i_1__1
       (.I0(init_calib_complete_reg_rep__1_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [19]),
        .O(init_calib_complete_reg_rep__0_1[13]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_24_29_i_1__2
       (.I0(init_calib_complete_reg_rep__1_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [30]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [15]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_24_29_i_2__0
       (.I0(init_calib_complete_reg_rep__2_0),
        .I1(mc_address[38]),
        .O(phy_dout[12]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_2__1
       (.I0(init_calib_complete_reg_rep__1_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [65]),
        .O(init_calib_complete_reg_rep__0_1[22]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_2__2
       (.I0(init_calib_complete_reg_rep__0_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [73]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [23]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_5__0
       (.I0(init_calib_complete_reg_rep__1_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [27]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [27]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_4
       (.I0(init_calib_complete_reg_rep__0_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [69]),
        .O(init_calib_complete_reg_rep__0_1[29]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_48_53_i_1__0
       (.I0(init_calib_complete_reg_rep__2_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [18]),
        .O(init_calib_complete_reg_rep__0_1[34]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_48_53_i_1__1
       (.I0(init_calib_complete_reg_rep__1_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [31]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [33]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_54_59_i_3
       (.I0(init_calib_complete_reg_rep__1_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [23]),
        .O(init_calib_complete_reg_rep__0_1[39]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_60_65_i_2__2
       (.I0(init_calib_complete_reg_rep__0_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [77]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [42]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_60_65_i_5
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [130]),
        .O(init_calib_complete_reg_rep__0_1[46]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_60_65_i_5__0
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [131]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [47]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_60_65_i_6
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [128]),
        .O(init_calib_complete_reg_rep__0_1[45]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_60_65_i_6__0
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [129]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [46]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_1__1
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [134]),
        .O(init_calib_complete_reg_rep__0_1[48]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_1__2
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [135]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [49]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_2__1
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [132]),
        .O(init_calib_complete_reg_rep__0_1[47]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_2__2
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [133]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [48]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_3
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [138]),
        .O(init_calib_complete_reg_rep__0_1[50]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_3__0
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [139]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [51]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_4
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [136]),
        .O(init_calib_complete_reg_rep__0_1[49]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_4__0
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [137]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [50]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_5
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [142]),
        .O(init_calib_complete_reg_rep__0_1[52]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_5__0
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [143]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [53]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_6
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [140]),
        .O(init_calib_complete_reg_rep__0_1[51]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_66_71_i_6__0
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [141]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [52]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__0
       (.I0(init_calib_complete_reg_rep__2_0),
        .I1(mc_cas_n[1]),
        .O(phy_dout[11]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__2
       (.I0(init_calib_complete_reg_rep_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [116]),
        .O(init_calib_complete_reg_rep__0_1[6]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_2
       (.I0(init_calib_complete_reg_rep__3_n_0),
        .I1(mc_address[11]),
        .O(phy_dout[4]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_3
       (.I0(init_calib_complete_reg_rep__2_0),
        .I1(mc_address[36]),
        .O(phy_dout[5]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_72_77_i_1__2
       (.I0(init_calib_complete_reg_rep__1_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [26]),
        .O(\write_buffer.wr_buf_out_data_reg[122] [55]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_78_79_i_1
       (.I0(init_calib_complete_reg_rep__0_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [112]),
        .O(init_calib_complete_reg_rep__0_1[59]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_10__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [124]),
        .I1(init_calib_complete_reg_rep__5_0),
        .I2(out_fifo_1[15]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[124] [7]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_13
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [70]),
        .I1(init_calib_complete_reg_rep__7_0),
        .I2(out_fifo[12]),
        .I3(out_fifo_0),
        .O(D2[4]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_14
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [54]),
        .I1(init_calib_complete_reg_rep__7_0),
        .I2(out_fifo[11]),
        .I3(out_fifo_0),
        .O(D2[3]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_16
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [22]),
        .I1(init_calib_complete_reg_rep__7_0),
        .I2(out_fifo[9]),
        .I3(out_fifo_0),
        .O(D2[1]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_17__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [12]),
        .I1(init_calib_complete_reg_rep__5_0),
        .I2(out_fifo_1[8]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[124] [0]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_2
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [116]),
        .I1(init_calib_complete_reg_rep__7_0),
        .I2(out_fifo[7]),
        .I3(out_fifo_0),
        .O(D0[7]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_20
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [83]),
        .I1(init_calib_complete_reg_rep__6_n_0),
        .I2(out_fifo[21]),
        .I3(out_fifo_0),
        .O(D3[5]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_21__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [78]),
        .I1(init_calib_complete_reg_rep__5_0),
        .I2(out_fifo_1[20]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[126] [4]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_22__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [62]),
        .I1(init_calib_complete_reg_rep__5_0),
        .I2(out_fifo_1[19]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[126] [3]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_24
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [19]),
        .I1(init_calib_complete_reg_rep__6_n_0),
        .I2(out_fifo[17]),
        .I3(out_fifo_0),
        .O(D3[1]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_24__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [30]),
        .I1(init_calib_complete_reg_rep__5_0),
        .I2(out_fifo_1[17]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[126] [1]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_25
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [3]),
        .I1(init_calib_complete_reg_rep__6_n_0),
        .I2(out_fifo[16]),
        .I3(out_fifo_0),
        .O(D3[0]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_29
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [65]),
        .I1(init_calib_complete_reg_rep__6_n_0),
        .I2(out_fifo[28]),
        .I3(out_fifo_0),
        .O(D4[4]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_29__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [73]),
        .I1(init_calib_complete_reg_rep__5_0),
        .I2(out_fifo_1[28]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[121] [4]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_2__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [120]),
        .I1(init_calib_complete_reg_rep__5_0),
        .I2(out_fifo_1[7]),
        .I3(out_fifo_2),
        .O(D1[7]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_31
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [33]),
        .I1(init_calib_complete_reg_rep__6_n_0),
        .I2(out_fifo[26]),
        .I3(out_fifo_0),
        .O(D4[2]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_31__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [41]),
        .I1(init_calib_complete_reg_rep__5_0),
        .I2(out_fifo_1[26]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[121] [2]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_36__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [91]),
        .I1(init_calib_complete_reg_rep__4_n_0),
        .I2(out_fifo_1[37]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[123] [5]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_37
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [69]),
        .I1(init_calib_complete_reg_rep__6_n_0),
        .I2(out_fifo[36]),
        .I3(out_fifo_0),
        .O(D5[4]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_39
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [37]),
        .I1(init_calib_complete_reg_rep__6_n_0),
        .I2(out_fifo[34]),
        .I3(out_fifo_0),
        .O(D5[2]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_40__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [27]),
        .I1(init_calib_complete_reg_rep__5_0),
        .I2(out_fifo_1[33]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[123] [1]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_41__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [11]),
        .I1(init_calib_complete_reg_rep__5_0),
        .I2(out_fifo_1[32]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[123] [0]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_44__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [95]),
        .I1(init_calib_complete_reg_rep__4_n_0),
        .I2(out_fifo_1[45]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[127] [5]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_45
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [66]),
        .I1(init_calib_complete_reg_rep__6_n_0),
        .I2(out_fifo[44]),
        .I3(out_fifo_0),
        .O(D6[4]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_46
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [50]),
        .I1(init_calib_complete_reg_rep__6_n_0),
        .I2(out_fifo[43]),
        .I3(out_fifo_0),
        .O(D6[3]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_48
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [18]),
        .I1(init_calib_complete_reg_rep__6_n_0),
        .I2(out_fifo[41]),
        .I3(out_fifo_0),
        .O(D6[1]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_48__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [31]),
        .I1(init_calib_complete_reg_rep__4_n_0),
        .I2(out_fifo_1[41]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[127] [1]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_49__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [15]),
        .I1(init_calib_complete_reg_rep__4_n_0),
        .I2(out_fifo_1[40]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[127] [0]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_52
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [87]),
        .I1(init_calib_complete_reg_rep__6_n_0),
        .I2(out_fifo[53]),
        .I3(out_fifo_0),
        .O(D7[5]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_53__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [77]),
        .I1(init_calib_complete_reg_rep__4_n_0),
        .I2(out_fifo_1[52]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[125] [4]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_55__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [45]),
        .I1(init_calib_complete_reg_rep__4_n_0),
        .I2(out_fifo_1[50]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[125] [2]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_56
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [23]),
        .I1(init_calib_complete_reg_rep__6_n_0),
        .I2(out_fifo[49]),
        .I3(out_fifo_0),
        .O(D7[1]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_57
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [7]),
        .I1(init_calib_complete_reg_rep__6_n_0),
        .I2(out_fifo[48]),
        .I3(out_fifo_0),
        .O(D7[0]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_58
       (.I0(init_calib_complete_reg_rep__5_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [142]),
        .I2(out_fifo[63]),
        .I3(out_fifo_0),
        .O(D8[7]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_58__0
       (.I0(init_calib_complete_reg_rep__4_n_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [143]),
        .I2(out_fifo_1[63]),
        .I3(out_fifo_2),
        .O(init_calib_complete_reg_rep__4_0[7]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_59
       (.I0(init_calib_complete_reg_rep__5_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [140]),
        .I2(out_fifo[62]),
        .I3(out_fifo_0),
        .O(D8[6]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_59__0
       (.I0(init_calib_complete_reg_rep__4_n_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [141]),
        .I2(out_fifo_1[62]),
        .I3(out_fifo_2),
        .O(init_calib_complete_reg_rep__4_0[6]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_60
       (.I0(init_calib_complete_reg_rep__5_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [138]),
        .I2(out_fifo[61]),
        .I3(out_fifo_0),
        .O(D8[5]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_60__0
       (.I0(init_calib_complete_reg_rep__4_n_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [139]),
        .I2(out_fifo_1[61]),
        .I3(out_fifo_2),
        .O(init_calib_complete_reg_rep__4_0[5]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_61
       (.I0(init_calib_complete_reg_rep__5_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [136]),
        .I2(out_fifo[60]),
        .I3(out_fifo_0),
        .O(D8[4]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_61__0
       (.I0(init_calib_complete_reg_rep__4_n_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [137]),
        .I2(out_fifo_1[60]),
        .I3(out_fifo_2),
        .O(init_calib_complete_reg_rep__4_0[4]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_62
       (.I0(init_calib_complete_reg_rep__6_n_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [134]),
        .I2(out_fifo[59]),
        .I3(out_fifo_0),
        .O(D8[3]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_62__0
       (.I0(init_calib_complete_reg_rep__4_n_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [135]),
        .I2(out_fifo_1[59]),
        .I3(out_fifo_2),
        .O(init_calib_complete_reg_rep__4_0[3]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_63
       (.I0(init_calib_complete_reg_rep__6_n_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [132]),
        .I2(out_fifo[58]),
        .I3(out_fifo_0),
        .O(D8[2]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_63__0
       (.I0(init_calib_complete_reg_rep__4_n_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [133]),
        .I2(out_fifo_1[58]),
        .I3(out_fifo_2),
        .O(init_calib_complete_reg_rep__4_0[2]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_64
       (.I0(init_calib_complete_reg_rep__6_n_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [130]),
        .I2(out_fifo[57]),
        .I3(out_fifo_0),
        .O(D8[1]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_64__0
       (.I0(init_calib_complete_reg_rep__4_n_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [131]),
        .I2(out_fifo_1[57]),
        .I3(out_fifo_2),
        .O(init_calib_complete_reg_rep__4_0[1]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_65
       (.I0(init_calib_complete_reg_rep__6_n_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [128]),
        .I2(out_fifo[56]),
        .I3(out_fifo_0),
        .O(D8[0]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_65__0
       (.I0(init_calib_complete_reg_rep__4_n_0),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [129]),
        .I2(out_fifo_1[56]),
        .I3(out_fifo_2),
        .O(init_calib_complete_reg_rep__4_0[0]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_66
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [112]),
        .I1(init_calib_complete_reg_rep__5_0),
        .I2(out_fifo[71]),
        .I3(out_fifo_0),
        .O(D9[7]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_69__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [74]),
        .I1(init_calib_complete_reg_rep__4_n_0),
        .I2(out_fifo_1[68]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[122]_0 [4]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_70__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [58]),
        .I1(init_calib_complete_reg_rep__4_n_0),
        .I2(out_fifo_1[67]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[122]_0 [3]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_72__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [26]),
        .I1(init_calib_complete_reg_rep__4_n_0),
        .I2(out_fifo_1[65]),
        .I3(out_fifo_2),
        .O(\write_buffer.wr_buf_out_data_reg[122]_0 [1]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_73
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [0]),
        .I1(init_calib_complete_reg_rep__5_0),
        .I2(out_fifo[64]),
        .I3(out_fifo_0),
        .O(D9[0]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_9
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [4]),
        .I1(init_calib_complete_reg_rep__7_0),
        .I2(out_fifo[0]),
        .I3(out_fifo_0),
        .O(D0[0]));
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_9__0
       (.I0(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [8]),
        .I1(init_calib_complete_reg_rep__5_0),
        .I2(out_fifo_1[0]),
        .I3(out_fifo_2),
        .O(D1[0]));
  (* SOFT_HLUTNM = "soft_lutpair448" *) 
  LUT4 #(
    .INIT(16'h00F8)) 
    \phaser_in_gen.phaser_in_i_2 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs),
        .O(\calib_sel_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair448" *) 
  LUT4 #(
    .INIT(16'h00F2)) 
    \phaser_in_gen.phaser_in_i_2__0 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs),
        .O(\calib_sel_reg[1]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair449" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    phaser_out_i_2
       (.I0(calib_in_common),
        .I1(calib_sel[1]),
        .I2(calib_sel[0]),
        .I3(calib_zero_inputs),
        .O(\gen_byte_sel_div2.calib_in_common_reg_0 ));
  (* SOFT_HLUTNM = "soft_lutpair449" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    phaser_out_i_2__2
       (.I0(calib_in_common),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_zero_inputs),
        .O(\gen_byte_sel_div2.calib_in_common_reg_7 ));
  LUT3 #(
    .INIT(8'hFE)) 
    phy_if_reset0
       (.I0(phy_if_reset_w),
        .I1(reset_if),
        .I2(wrlvl_final_if_rst),
        .O(phy_if_reset0__0));
  FDRE phy_if_reset_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_if_reset0__0),
        .Q(phy_if_reset),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hFE)) 
    po_en_stg2_f0
       (.I0(dqs_po_en_stg2_f),
        .I1(cmd_po_en_stg2_f),
        .I2(ck_po_stg2_f_en),
        .O(po_enstg2_f));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r8_reg_srl8 " *) 
  SRL16E reset_if_r8_reg_srl8
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(reset_if),
        .Q(reset_if_r8_reg_srl8_n_0));
  FDRE reset_if_r9_reg
       (.C(CLK),
        .CE(1'b1),
        .D(reset_if_r8_reg_srl8_n_0),
        .Q(reset_if_r9),
        .R(1'b0));
  FDRE reset_if_reg
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28 ),
        .Q(reset_if),
        .R(1'b0));
  FDRE tempmon_pi_f_en_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tempmon_sel_pi_incdec),
        .Q(tempmon_pi_f_en_r),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4] [0]));
  FDRE tempmon_pi_f_inc_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tempmon_pi_f_inc),
        .Q(tempmon_pi_f_inc_r),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4] [0]));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_init u_ddr_phy_init
       (.CLK(CLK),
        .D({\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_8 ,rdlvl_stg1_done_int_reg,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_11 ,\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_12 }),
        .D0(D0[6:1]),
        .D1(D1[6:1]),
        .D2({D2[7:5],D2[2],D2[0]}),
        .D3({D3[7:6],D3[4:2]}),
        .D4({D4[7:5],D4[3],D4[1:0]}),
        .D5({D5[7:5],D5[3],D5[1:0]}),
        .D6({D6[7:5],D6[2],D6[0]}),
        .D7({D7[7:6],D7[4:2]}),
        .D9(D9[6:1]),
        .E(E),
        .Q(Q),
        .burst_addr_r_reg_0(wrcal_done_reg),
        .calib_complete(calib_complete),
        .calib_ctl_wren_reg_0(calib_cmd_wren),
        .calib_ctl_wren_reg_1(calib_ctl_wren_reg),
        .\calib_data_offset_0_reg[0]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_25 ),
        .\calib_data_offset_0_reg[1]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_24 ),
        .\calib_data_offset_0_reg[2]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_23 ),
        .\calib_data_offset_0_reg[3]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_12 ),
        .\calib_data_offset_0_reg[4]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_22 ),
        .\calib_data_offset_0_reg[5]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_21 ),
        .\calib_seq_reg[1]_0 (D),
        .calib_wrdata_en(calib_wrdata_en),
        .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
        .\cmd_pipe_plus.mc_cas_n_reg[1] (\cmd_pipe_plus.mc_ras_n_reg[2] [1]),
        .\cmd_pipe_plus.mc_cas_n_reg[1]_0 ({\cmd_pipe_plus.mc_cas_n_reg[2] [4],\cmd_pipe_plus.mc_cas_n_reg[2] [1]}),
        .\cmd_pipe_plus.mc_cke_reg[3] (\cmd_pipe_plus.mc_cke_reg[3] ),
        .\cmd_pipe_plus.mc_odt_reg[0] (\cmd_pipe_plus.mc_odt_reg[0] ),
        .\cmd_pipe_plus.mc_we_n_reg[1] (\cmd_pipe_plus.mc_we_n_reg[2] [1]),
        .\cnt_pwron_ce_r_reg[9]_0 (\cnt_pwron_ce_r_reg[9] ),
        .complex_row0_rd_done_reg_0(complex_row0_rd_done_reg),
        .ddr3_lm_done_r(ddr3_lm_done_r),
        .\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 (init_calib_complete_reg_rep__2_0),
        .\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 (init_calib_complete_reg_rep__1_0),
        .\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 (init_calib_complete_reg_rep__0_0),
        .detect_pi_found_dqs(detect_pi_found_dqs),
        .detect_pi_found_dqs_reg_0(u_ddr_phy_init_n_278),
        .done_dqs_tap_inc(done_dqs_tap_inc),
        .dqs_found_prech_req(dqs_found_prech_req),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 (\en_cnt_div4.enable_wrlvl_cnt_reg[2] ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 (\en_cnt_div4.enable_wrlvl_cnt_reg[4] ),
        .first_rdlvl_pat_r(first_rdlvl_pat_r),
        .first_wrcal_pat_r(first_wrcal_pat_r),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_1 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[1] ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[2] ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[3] ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[4] ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[8] ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_1 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_26 ),
        .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ),
        .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] ),
        .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0 (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] ),
        .init_calib_complete_reg_0(init_calib_complete_reg_0),
        .\init_state_r[0]_i_7_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25 ),
        .\init_state_r[1]_i_3_0 (u_ddr_phy_wrcal_n_18),
        .\init_state_r[2]_i_6_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22 ),
        .\init_state_r[2]_i_7_0 (u_ddr_phy_wrcal_n_15),
        .\init_state_r[2]_i_7_1 (u_ddr_phy_wrcal_n_4),
        .\init_state_r[2]_i_7_2 (u_ddr_phy_wrcal_n_16),
        .\init_state_r[2]_i_7_3 (u_ddr_phy_wrcal_n_20),
        .\init_state_r[4]_i_4_0 (u_ddr_phy_wrcal_n_17),
        .\init_state_r[4]_i_7_0 (u_ddr_phy_wrcal_n_19),
        .\init_state_r_reg[0]_0 (u_ddr_phy_wrcal_n_14),
        .\init_state_r_reg[2]_0 (\init_state_r_reg[2] ),
        .mc_address({mc_address[37],mc_address[35:14],mc_address[12],mc_address[10:0]}),
        .mc_bank(mc_bank),
        .mc_cas_n(mc_cas_n[1]),
        .mc_cke(mc_cke),
        .mc_cmd(mc_cmd),
        .mc_data_offset(mc_data_offset),
        .mc_odt(mc_odt),
        .mc_ras_n(mc_ras_n[1]),
        .mc_we_n(mc_we_n[1]),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_init_done_r(mem_init_done_r),
        .mem_out(mem_out),
        .mpr_rdlvl_start_reg_0(u_ddr_phy_init_n_353),
        .mux_cmd_wren(mux_cmd_wren),
        .mux_reset_n(mux_reset_n),
        .mux_wrdata_en(mux_wrdata_en),
        .\my_empty_reg[3] (\my_empty_reg[3] ),
        .\my_empty_reg[3]_0 (\my_empty_reg[3]_0 ),
        .\my_empty_reg[3]_1 (\my_empty_reg[3]_1 ),
        .\my_empty_reg[5] (\my_empty_reg[5] ),
        .\my_empty_reg[5]_0 (\my_empty_reg[5]_0 ),
        .\num_refresh_reg[3]_0 (\idelay_tap_cnt_r_reg[0][1][4] ),
        .\one_rank.stg1_wr_done_reg_0 (u_ddr_phy_init_n_14),
        .out(out),
        .out_fifo({\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [127:125],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [123:121],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [119:117],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [115:113],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [111:96],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [94:92],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [90:88],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [86:84],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [82:79],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [76:75],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [72:71],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [68:67],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [64:63],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [61:59],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [57:55],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [53:51],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [49:46],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [44:42],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [40:38],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [36:34],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [32],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [29:28],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [25:24],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [21:20],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [17:16],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [14:13],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [10:9],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [6:5],\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 [2:1]}),
        .out_fifo_0(init_calib_complete_reg_rep__7_0),
        .out_fifo_1({out_fifo[70:65],out_fifo[55:54],out_fifo[52:50],out_fifo[47:45],out_fifo[42],out_fifo[40:37],out_fifo[35],out_fifo[33:29],out_fifo[27],out_fifo[25:22],out_fifo[20:18],out_fifo[15:13],out_fifo[10],out_fifo[8],out_fifo[6:1]}),
        .out_fifo_10(init_calib_complete_reg_rep__9_0),
        .out_fifo_11(out_fifo_3),
        .out_fifo_2(out_fifo_0),
        .out_fifo_3(init_calib_complete_reg_rep__6_n_0),
        .out_fifo_4(init_calib_complete_reg_rep__5_0),
        .out_fifo_5({out_fifo_1[71:69],out_fifo_1[66],out_fifo_1[64],out_fifo_1[55:53],out_fifo_1[51],out_fifo_1[49:46],out_fifo_1[44:42],out_fifo_1[39:38],out_fifo_1[36:34],out_fifo_1[31:29],out_fifo_1[27],out_fifo_1[25:21],out_fifo_1[18],out_fifo_1[16],out_fifo_1[14:9],out_fifo_1[6:1]}),
        .out_fifo_6(out_fifo_2),
        .out_fifo_7(init_calib_complete_reg_rep__8_0),
        .out_fifo_8({out_fifo_4[43:36],out_fifo_4[34],out_fifo_4[31],out_fifo_4[28],out_fifo_4[26:11],out_fifo_4[9],out_fifo_4[7:0]}),
        .out_fifo_9(out_fifo_5),
        .\phy_ctl_wd_i1_reg[17] (\phy_ctl_wd_i1_reg[17] ),
        .\phy_ctl_wd_i1_reg[18] (\phy_ctl_wd_i1_reg[18] ),
        .\phy_ctl_wd_i1_reg[19] (\phy_ctl_wd_i1_reg[19] ),
        .\phy_ctl_wd_i1_reg[21] (\phy_ctl_wd_i1_reg[21] ),
        .\phy_ctl_wd_i1_reg[22] (init_calib_complete_reg_rep__3_n_0),
        .\phy_ctl_wd_i1_reg[22]_0 (\phy_ctl_wd_i1_reg[22] ),
        .phy_ctl_wr_i1_reg(init_calib_complete_reg_rep__4_n_0),
        .phy_dout({phy_dout[38:14],phy_dout[9:6],phy_dout[3:0]}),
        .phy_read_calib(phy_read_calib),
        .phy_write_calib(phy_write_calib),
        .pi_calib_done(pi_calib_done),
        .pi_dqs_found_done(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2 ),
        .pi_dqs_found_done_r1(pi_dqs_found_done_r1),
        .pi_dqs_found_rank_done(pi_dqs_found_rank_done),
        .pi_dqs_found_start_reg_0(u_ddr_phy_init_n_352),
        .pi_phase_locked_all_r1_reg_0(pi_phase_locked_all_r1_reg),
        .prbs_rdlvl_done_pulse0(prbs_rdlvl_done_pulse0),
        .prbs_rdlvl_done_pulse_reg_0(prbs_rdlvl_done_pulse_reg),
        .prech_done(prech_done),
        .prech_req_posedge_r_reg_0(u_ddr_phy_init_n_2),
        .rdlvl_last_byte_done(rdlvl_last_byte_done),
        .rdlvl_pi_incdec(rdlvl_pi_incdec),
        .rdlvl_prech_req(rdlvl_prech_req),
        .rdlvl_stg1_done_r1_reg_0(rdlvl_stg1_done_r1),
        .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done),
        .rdlvl_stg1_start_reg_0(rdlvl_stg1_start_reg),
        .rst_dqs_find_i_12(fine_adj_state_r),
        .wl_sm_start(wl_sm_start),
        .wr_en_inferred__0_i_1_0(wr_en_inferred__0_i_1),
        .wr_en_inferred__0_i_1__0_0(wr_en_inferred__0_i_1__0),
        .wr_en_inferred__0_i_1__1_0(wr_en_inferred__0_i_1__1),
        .wr_lvl_start_reg_0(u_ddr_phy_init_n_16),
        .wr_lvl_start_reg_1(wrcal_done_reg_0),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0] ),
        .\wr_ptr_timing_reg[0]_0 (init_calib_complete_reg_rep_0),
        .\wr_ptr_timing_reg[0]_1 (\wr_ptr_timing_reg[0]_0 ),
        .\wr_ptr_timing_reg[0]_2 (\wr_ptr_timing_reg[0]_1 ),
        .wrcal_prech_req(wrcal_prech_req),
        .wrcal_rd_wait(wrcal_rd_wait),
        .wrcal_resume_w(wrcal_resume_w),
        .wrcal_sanity_chk(wrcal_sanity_chk),
        .wrcal_start_reg_0(u_ddr_phy_init_n_351),
        .\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0 (\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126] ),
        .\write_buffer.wr_buf_out_data_reg[108] (\write_buffer.wr_buf_out_data_reg[124] [6:1]),
        .\write_buffer.wr_buf_out_data_reg[121] ({\write_buffer.wr_buf_out_data_reg[121] [7:5],\write_buffer.wr_buf_out_data_reg[121] [3],\write_buffer.wr_buf_out_data_reg[121] [1:0]}),
        .\write_buffer.wr_buf_out_data_reg[122] ({\write_buffer.wr_buf_out_data_reg[122] [59:56],\write_buffer.wr_buf_out_data_reg[122] [54],\write_buffer.wr_buf_out_data_reg[122] [45:43],\write_buffer.wr_buf_out_data_reg[122] [41:34],\write_buffer.wr_buf_out_data_reg[122] [32:28],\write_buffer.wr_buf_out_data_reg[122] [26:24],\write_buffer.wr_buf_out_data_reg[122] [22:16],\write_buffer.wr_buf_out_data_reg[122] [14],\write_buffer.wr_buf_out_data_reg[122] [12:7],\write_buffer.wr_buf_out_data_reg[122] [5:0]}),
        .\write_buffer.wr_buf_out_data_reg[122]_0 ({\write_buffer.wr_buf_out_data_reg[122]_0 [7:5],\write_buffer.wr_buf_out_data_reg[122]_0 [2],\write_buffer.wr_buf_out_data_reg[122]_0 [0]}),
        .\write_buffer.wr_buf_out_data_reg[123] ({\write_buffer.wr_buf_out_data_reg[123] [7:6],\write_buffer.wr_buf_out_data_reg[123] [4:2]}),
        .\write_buffer.wr_buf_out_data_reg[125] ({\write_buffer.wr_buf_out_data_reg[125] [7:5],\write_buffer.wr_buf_out_data_reg[125] [3],\write_buffer.wr_buf_out_data_reg[125] [1:0]}),
        .\write_buffer.wr_buf_out_data_reg[126] ({\write_buffer.wr_buf_out_data_reg[126] [7:5],\write_buffer.wr_buf_out_data_reg[126] [2],\write_buffer.wr_buf_out_data_reg[126] [0]}),
        .\write_buffer.wr_buf_out_data_reg[127] ({\write_buffer.wr_buf_out_data_reg[127] [7:6],\write_buffer.wr_buf_out_data_reg[127] [4:2]}),
        .\write_buffer.wr_buf_out_data_reg[96] ({init_calib_complete_reg_rep__0_1[58:53],init_calib_complete_reg_rep__0_1[44:40],init_calib_complete_reg_rep__0_1[38:35],init_calib_complete_reg_rep__0_1[33:30],init_calib_complete_reg_rep__0_1[28:23],init_calib_complete_reg_rep__0_1[21:14],init_calib_complete_reg_rep__0_1[12:9],init_calib_complete_reg_rep__0_1[7],init_calib_complete_reg_rep__0_1[5:0]}),
        .wrlvl_byte_redo(wrlvl_byte_redo),
        .wrlvl_done_r1(wrlvl_done_r1),
        .wrlvl_done_r_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_4 ),
        .wrlvl_final_if_rst(wrlvl_final_if_rst),
        .wrlvl_rank_done(wrlvl_rank_done));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_wrcal u_ddr_phy_wrcal
       (.CLK(CLK),
        .D(rdlvl_stg1_done_int_reg),
        .E(rd_active_r),
        .\FSM_sequential_wl_state_r[4]_i_14 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_16 ),
        .\FSM_sequential_wl_state_r[4]_i_14_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_18 ),
        .\FSM_sequential_wl_state_r[4]_i_14_1 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_17 ),
        .LD0(LD0),
        .LD0_0(LD0_0),
        .Q({po_stg2_wrcal_cnt,\po_stg2_wrcal_cnt_reg[0] }),
        .SR(SR),
        .cal1_dq_idel_ce_reg(u_ddr_phy_wrcal_n_13),
        .\cal2_state_r_reg[0]_0 (u_ddr_phy_init_n_351),
        .calib_zero_inputs(calib_zero_inputs),
        .ddr3_lm_done_r(ddr3_lm_done_r),
        .done_dqs_dec237_out(done_dqs_dec237_out),
        .early1_data_reg_0(u_ddr_phy_wrcal_n_6),
        .early2_data_reg_0(u_ddr_phy_wrcal_n_9),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .idelay_ce_int(idelay_ce_int),
        .idelay_ld_reg_0(idelay_ld_reg),
        .idelay_ld_rst(idelay_ld_rst),
        .\idelay_tap_cnt_r_reg[0][1][4] (\idelay_tap_cnt_r_reg[0][1][4] ),
        .\idelay_tap_cnt_r_reg[0][1][4]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_24 ),
        .\init_state_r[4]_i_15 (u_ddr_phy_init_n_2),
        .\input_[9].iserdes_dq_.idelay_dq.idelaye2 (calib_in_common),
        .\input_[9].iserdes_dq_.idelay_dq.idelaye2_0 (calib_sel[0]),
        .\input_[9].iserdes_dq_.idelay_dq.idelaye2_1 (calib_sel[1]),
        .mem_init_done_r(mem_init_done_r),
        .mem_init_done_r_reg(u_ddr_phy_wrcal_n_19),
        .phy_if_reset_w(phy_if_reset_w),
        .phy_rddata_en(phy_rddata_en),
        .pi_dqs_found_done(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2 ),
        .\po_stg2_wrcal_cnt_reg[0]_0 (u_ddr_phy_wrcal_n_12),
        .prech_done(prech_done),
        .rdlvl_stg1_done_int_reg(u_ddr_phy_wrcal_n_18),
        .wrcal_done_reg_0(wrcal_done_reg),
        .wrcal_done_reg_1(u_ddr_phy_wrcal_n_15),
        .wrcal_done_reg_2(wrcal_done_reg_0),
        .wrcal_prech_req(wrcal_prech_req),
        .wrcal_rd_wait(wrcal_rd_wait),
        .wrcal_resume_w(wrcal_resume_w),
        .wrcal_sanity_chk(wrcal_sanity_chk),
        .wrcal_sanity_chk_done_reg_0(u_ddr_phy_wrcal_n_4),
        .wrcal_sanity_chk_done_reg_1(u_ddr_phy_wrcal_n_14),
        .wrcal_sanity_chk_done_reg_2(wrcal_sanity_chk_done_reg),
        .wrlvl_byte_done(wrlvl_byte_done),
        .wrlvl_byte_redo(wrlvl_byte_redo),
        .wrlvl_byte_redo_r(wrlvl_byte_redo_r),
        .wrlvl_byte_redo_reg_0(u_ddr_phy_wrcal_n_16),
        .wrlvl_byte_redo_reg_1(u_ddr_phy_wrcal_n_17),
        .wrlvl_byte_redo_reg_2(u_ddr_phy_wrcal_n_20),
        .wrlvl_done_r1(wrlvl_done_r1));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_if_post_fifo
   (\rd_ptr_timing_reg[1]_0 ,
    app_rd_data_valid,
    \my_empty_reg[0]_0 ,
    \my_empty_reg[0]_1 ,
    \my_empty_reg[0]_2 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_reg[0]_0 ,
    \my_empty_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \my_empty_reg[4]_rep__0_0 ,
    p_1_in,
    \my_empty_reg[4]_rep__1_0 ,
    \my_empty_reg[4]_rep__1_1 ,
    if_empty_r_0,
    app_rd_data_valid_0,
    app_rd_data_valid_1,
    \read_fifo.tail_r_reg ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    app_rd_data,
    ififo_rst,
    CLK);
  output [1:0]\rd_ptr_timing_reg[1]_0 ;
  output app_rd_data_valid;
  output \my_empty_reg[0]_0 ;
  output \my_empty_reg[0]_1 ;
  output \my_empty_reg[0]_2 ;
  output \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  output \wr_ptr_reg[1]_0 ;
  output \wr_ptr_reg[0]_0 ;
  output \my_empty_reg[3]_0 ;
  output [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \my_empty_reg[4]_rep__0_0 ;
  output p_1_in;
  input \my_empty_reg[4]_rep__1_0 ;
  input [1:0]\my_empty_reg[4]_rep__1_1 ;
  input [0:0]if_empty_r_0;
  input app_rd_data_valid_0;
  input [0:0]app_rd_data_valid_1;
  input [0:0]\read_fifo.tail_r_reg ;
  input [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input [63:0]app_rd_data;
  input ififo_rst;
  input CLK;

  wire CLK;
  wire [63:0]app_rd_data;
  wire app_rd_data_valid;
  wire app_rd_data_valid_0;
  wire [0:0]app_rd_data_valid_1;
  wire [63:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire [0:0]if_empty_r_0;
  wire ififo_rst;
  wire [4:1]my_empty;
  wire [1:1]my_empty1;
  wire \my_empty[0]_i_1_n_0 ;
  wire \my_empty[1]_i_1_n_0 ;
  wire \my_empty[1]_i_2_n_0 ;
  wire \my_empty[2]_i_1_n_0 ;
  wire \my_empty[3]_i_1_n_0 ;
  wire \my_empty[4]_i_1_n_0 ;
  wire \my_empty[4]_i_2__0_n_0 ;
  wire \my_empty_reg[0]_0 ;
  wire \my_empty_reg[0]_1 ;
  wire \my_empty_reg[0]_2 ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[4]_rep__0_0 ;
  wire \my_empty_reg[4]_rep__1_0 ;
  wire [1:0]\my_empty_reg[4]_rep__1_1 ;
  wire \my_empty_reg[4]_rep__1_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1_n_0 ;
  wire \my_full[0]_i_2__0_n_0 ;
  wire \my_full[1]_i_1_n_0 ;
  wire \my_full[1]_i_2_n_0 ;
  wire \my_full[1]_i_3_n_0 ;
  wire p_1_in;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__0_n_0 ;
  wire \rd_ptr[1]_i_1__0_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__1_n_0 ;
  wire \rd_ptr_timing[1]_i_1__1_n_0 ;
  wire [0:0]\read_fifo.tail_r_reg ;
  wire \wr_ptr[0]_i_1__1_n_0 ;
  wire \wr_ptr[1]_i_1__1_n_0 ;
  wire \wr_ptr[1]_i_2_n_0 ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[1]_0 ;

  assign \rd_ptr_timing_reg[1]_0 [1:0] = rd_ptr_timing;
  (* SOFT_HLUTNM = "soft_lutpair523" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[104]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [6]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [6]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [48]));
  (* SOFT_HLUTNM = "soft_lutpair525" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[105]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [30]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [30]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [49]));
  (* SOFT_HLUTNM = "soft_lutpair530" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[106]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [62]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [62]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [50]));
  (* SOFT_HLUTNM = "soft_lutpair521" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[107]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [38]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [38]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [51]));
  (* SOFT_HLUTNM = "soft_lutpair532" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[108]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [14]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [14]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [52]));
  (* SOFT_HLUTNM = "soft_lutpair527" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[109]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [54]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [54]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [53]));
  (* SOFT_HLUTNM = "soft_lutpair530" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[10]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [56]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [56]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [2]));
  (* SOFT_HLUTNM = "soft_lutpair528" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[110]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [22]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [22]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [54]));
  (* SOFT_HLUTNM = "soft_lutpair521" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[111]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [46]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [46]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [55]));
  (* SOFT_HLUTNM = "soft_lutpair533" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[11]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [32]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [32]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [3]));
  (* SOFT_HLUTNM = "soft_lutpair536" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[120]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [7]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [7]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [56]));
  (* SOFT_HLUTNM = "soft_lutpair538" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[121]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [31]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [31]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [57]));
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[122]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [63]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [63]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [58]));
  (* SOFT_HLUTNM = "soft_lutpair547" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[123]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [39]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [39]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [59]));
  (* SOFT_HLUTNM = "soft_lutpair543" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[124]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [15]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [15]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [60]));
  (* SOFT_HLUTNM = "soft_lutpair540" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[125]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [55]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [55]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [61]));
  (* SOFT_HLUTNM = "soft_lutpair544" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[126]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [23]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [23]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [62]));
  (* SOFT_HLUTNM = "soft_lutpair548" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[127]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [47]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [47]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [63]));
  (* SOFT_HLUTNM = "soft_lutpair531" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[12]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [8]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [8]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [4]));
  (* SOFT_HLUTNM = "soft_lutpair522" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[13]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [48]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [48]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [5]));
  (* SOFT_HLUTNM = "soft_lutpair523" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[14]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [16]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [16]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [6]));
  (* SOFT_HLUTNM = "soft_lutpair522" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[15]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [40]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [40]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [7]));
  (* SOFT_HLUTNM = "soft_lutpair536" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[24]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [1]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [1]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [8]));
  (* SOFT_HLUTNM = "soft_lutpair538" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[25]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [25]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [25]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [9]));
  (* SOFT_HLUTNM = "soft_lutpair550" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[26]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [57]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [57]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [10]));
  (* SOFT_HLUTNM = "soft_lutpair546" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[27]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [33]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [33]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [11]));
  (* SOFT_HLUTNM = "soft_lutpair542" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[28]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [9]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [9]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [12]));
  (* SOFT_HLUTNM = "soft_lutpair539" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[29]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [49]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [49]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [13]));
  (* SOFT_HLUTNM = "soft_lutpair543" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[30]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [17]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [17]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [14]));
  (* SOFT_HLUTNM = "soft_lutpair547" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[31]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [41]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [41]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [15]));
  (* SOFT_HLUTNM = "soft_lutpair531" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[40]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [2]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [2]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [16]));
  (* SOFT_HLUTNM = "soft_lutpair533" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[41]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [26]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [26]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [17]));
  (* SOFT_HLUTNM = "soft_lutpair527" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[42]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [58]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [58]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [18]));
  (* SOFT_HLUTNM = "soft_lutpair529" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[43]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [34]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [34]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [19]));
  (* SOFT_HLUTNM = "soft_lutpair525" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[44]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [10]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [10]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [20]));
  (* SOFT_HLUTNM = "soft_lutpair534" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[45]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [50]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [50]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [21]));
  (* SOFT_HLUTNM = "soft_lutpair524" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[46]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [18]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [18]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [22]));
  (* SOFT_HLUTNM = "soft_lutpair526" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[47]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [42]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [42]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [23]));
  (* SOFT_HLUTNM = "soft_lutpair541" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[56]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [3]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [3]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [24]));
  (* SOFT_HLUTNM = "soft_lutpair545" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[57]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [27]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [27]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [25]));
  (* SOFT_HLUTNM = "soft_lutpair540" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[58]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [59]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [59]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [26]));
  (* SOFT_HLUTNM = "soft_lutpair546" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[59]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [35]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [35]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [27]));
  (* SOFT_HLUTNM = "soft_lutpair542" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[60]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [11]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [11]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [28]));
  (* SOFT_HLUTNM = "soft_lutpair549" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[61]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [51]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [51]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [29]));
  (* SOFT_HLUTNM = "soft_lutpair537" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[62]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [19]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [19]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [30]));
  (* SOFT_HLUTNM = "soft_lutpair539" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[63]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [43]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [43]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [31]));
  (* SOFT_HLUTNM = "soft_lutpair520" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[72]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [4]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [4]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [32]));
  (* SOFT_HLUTNM = "soft_lutpair528" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[73]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [28]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [28]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [33]));
  (* SOFT_HLUTNM = "soft_lutpair535" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[74]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [60]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [60]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [34]));
  (* SOFT_HLUTNM = "soft_lutpair526" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[75]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [36]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [36]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [35]));
  (* SOFT_HLUTNM = "soft_lutpair520" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[76]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [12]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [12]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [36]));
  (* SOFT_HLUTNM = "soft_lutpair529" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[77]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [52]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [52]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [37]));
  (* SOFT_HLUTNM = "soft_lutpair532" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[78]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [20]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [20]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [38]));
  (* SOFT_HLUTNM = "soft_lutpair534" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[79]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [44]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [44]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [39]));
  (* SOFT_HLUTNM = "soft_lutpair541" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[88]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [5]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [5]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [40]));
  (* SOFT_HLUTNM = "soft_lutpair545" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[89]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [29]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [29]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [41]));
  (* SOFT_HLUTNM = "soft_lutpair517" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[8]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [0]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [0]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [0]));
  (* SOFT_HLUTNM = "soft_lutpair550" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[90]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [61]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [61]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [42]));
  (* SOFT_HLUTNM = "soft_lutpair535" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[91]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [37]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [37]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [43]));
  (* SOFT_HLUTNM = "soft_lutpair537" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[92]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [13]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [13]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [44]));
  (* SOFT_HLUTNM = "soft_lutpair549" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[93]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [53]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [53]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [45]));
  (* SOFT_HLUTNM = "soft_lutpair544" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[94]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [21]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [21]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [46]));
  (* SOFT_HLUTNM = "soft_lutpair548" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[95]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [45]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [45]),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [47]));
  (* SOFT_HLUTNM = "soft_lutpair524" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[9]_INST_0 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [24]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [24]),
        .I2(\my_empty_reg[4]_rep__0_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] [1]));
  LUT6 #(
    .INIT(64'h0000000007770000)) 
    app_rd_data_valid_INST_0
       (.I0(\my_empty_reg[0]_0 ),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\my_empty_reg[4]_rep__1_1 [0]),
        .I3(if_empty_r_0),
        .I4(app_rd_data_valid_0),
        .I5(app_rd_data_valid_1),
        .O(app_rd_data_valid));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[0].mux_rd_fall0_r[0]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [1]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [1]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[8]),
        .O(\gen_mux_rd[0].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[0].mux_rd_fall1_r[0]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [3]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [3]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[24]),
        .O(\gen_mux_rd[0].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[0].mux_rd_fall2_r[0]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [5]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [5]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[40]),
        .O(\gen_mux_rd[0].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[0].mux_rd_fall3_r[0]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [7]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [7]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[56]),
        .O(\gen_mux_rd[0].mux_rd_fall3_r_reg0 ));
  (* SOFT_HLUTNM = "soft_lutpair517" *) 
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[0].mux_rd_rise0_r[0]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [0]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [0]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[0]),
        .O(\gen_mux_rd[0].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[0].mux_rd_rise1_r[0]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [2]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [2]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[16]),
        .O(\gen_mux_rd[0].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[0].mux_rd_rise2_r[0]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [4]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [4]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[32]),
        .O(\gen_mux_rd[0].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[0].mux_rd_rise3_r[0]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [6]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [6]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[48]),
        .O(\gen_mux_rd[0].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[1].mux_rd_fall0_r[1]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [25]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [25]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[9]),
        .O(\gen_mux_rd[1].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[1].mux_rd_fall1_r[1]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [27]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [27]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[25]),
        .O(\gen_mux_rd[1].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[1].mux_rd_fall2_r[1]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [29]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [29]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[41]),
        .O(\gen_mux_rd[1].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[1].mux_rd_fall3_r[1]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [31]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [31]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[57]),
        .O(\gen_mux_rd[1].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[1].mux_rd_rise0_r[1]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [24]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [24]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[1]),
        .O(\gen_mux_rd[1].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[1].mux_rd_rise1_r[1]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [26]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [26]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[17]),
        .O(\gen_mux_rd[1].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[1].mux_rd_rise2_r[1]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [28]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [28]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[33]),
        .O(\gen_mux_rd[1].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[1].mux_rd_rise3_r[1]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [30]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [30]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[49]),
        .O(\gen_mux_rd[1].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[2].mux_rd_fall0_r[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [57]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [57]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[10]),
        .O(\gen_mux_rd[2].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[2].mux_rd_fall1_r[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [59]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [59]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[26]),
        .O(\gen_mux_rd[2].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[2].mux_rd_fall2_r[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [61]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [61]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[42]),
        .O(\gen_mux_rd[2].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[2].mux_rd_fall3_r[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [63]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [63]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[58]),
        .O(\gen_mux_rd[2].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[2].mux_rd_rise0_r[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [56]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [56]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[2]),
        .O(\gen_mux_rd[2].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[2].mux_rd_rise1_r[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [58]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [58]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[18]),
        .O(\gen_mux_rd[2].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[2].mux_rd_rise2_r[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [60]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [60]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[34]),
        .O(\gen_mux_rd[2].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[2].mux_rd_rise3_r[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [62]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [62]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[50]),
        .O(\gen_mux_rd[2].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[3].mux_rd_fall0_r[3]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [33]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [33]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[11]),
        .O(\gen_mux_rd[3].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[3].mux_rd_fall1_r[3]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [35]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [35]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[27]),
        .O(\gen_mux_rd[3].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[3].mux_rd_fall2_r[3]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [37]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [37]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[43]),
        .O(\gen_mux_rd[3].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[3].mux_rd_fall3_r[3]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [39]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [39]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[59]),
        .O(\gen_mux_rd[3].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[3].mux_rd_rise0_r[3]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [32]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [32]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[3]),
        .O(\gen_mux_rd[3].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[3].mux_rd_rise1_r[3]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [34]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [34]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[19]),
        .O(\gen_mux_rd[3].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[3].mux_rd_rise2_r[3]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [36]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [36]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[35]),
        .O(\gen_mux_rd[3].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[3].mux_rd_rise3_r[3]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [38]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [38]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[51]),
        .O(\gen_mux_rd[3].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[4].mux_rd_fall0_r[4]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [9]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [9]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[12]),
        .O(\gen_mux_rd[4].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[4].mux_rd_fall1_r[4]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [11]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [11]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[28]),
        .O(\gen_mux_rd[4].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[4].mux_rd_fall2_r[4]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [13]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [13]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[44]),
        .O(\gen_mux_rd[4].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[4].mux_rd_fall3_r[4]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [15]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [15]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[60]),
        .O(\gen_mux_rd[4].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[4].mux_rd_rise0_r[4]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [8]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [8]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[4]),
        .O(\gen_mux_rd[4].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[4].mux_rd_rise1_r[4]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [10]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [10]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[20]),
        .O(\gen_mux_rd[4].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[4].mux_rd_rise2_r[4]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [12]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [12]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[36]),
        .O(\gen_mux_rd[4].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[4].mux_rd_rise3_r[4]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [14]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [14]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[52]),
        .O(\gen_mux_rd[4].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[5].mux_rd_fall0_r[5]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [49]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [49]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[13]),
        .O(\gen_mux_rd[5].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[5].mux_rd_fall1_r[5]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [51]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [51]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[29]),
        .O(\gen_mux_rd[5].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[5].mux_rd_fall2_r[5]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [53]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [53]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[45]),
        .O(\gen_mux_rd[5].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[5].mux_rd_fall3_r[5]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [55]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [55]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[61]),
        .O(\gen_mux_rd[5].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[5].mux_rd_rise0_r[5]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [48]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [48]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[5]),
        .O(\gen_mux_rd[5].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[5].mux_rd_rise1_r[5]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [50]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [50]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[21]),
        .O(\gen_mux_rd[5].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[5].mux_rd_rise2_r[5]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [52]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [52]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[37]),
        .O(\gen_mux_rd[5].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[5].mux_rd_rise3_r[5]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [54]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [54]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[53]),
        .O(\gen_mux_rd[5].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[6].mux_rd_fall0_r[6]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [17]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [17]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[14]),
        .O(\gen_mux_rd[6].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[6].mux_rd_fall1_r[6]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [19]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [19]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[30]),
        .O(\gen_mux_rd[6].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[6].mux_rd_fall2_r[6]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [21]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [21]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[46]),
        .O(\gen_mux_rd[6].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[6].mux_rd_fall3_r[6]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [23]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [23]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[62]),
        .O(\gen_mux_rd[6].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[6].mux_rd_rise0_r[6]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [16]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [16]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[6]),
        .O(\gen_mux_rd[6].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[6].mux_rd_rise1_r[6]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [18]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [18]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[22]),
        .O(\gen_mux_rd[6].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[6].mux_rd_rise2_r[6]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [20]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [20]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[38]),
        .O(\gen_mux_rd[6].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[6].mux_rd_rise3_r[6]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [22]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [22]),
        .I2(my_empty[4]),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[54]),
        .O(\gen_mux_rd[6].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[7].mux_rd_fall0_r[7]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [41]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [41]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[15]),
        .O(\gen_mux_rd[7].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[7].mux_rd_fall1_r[7]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [43]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [43]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[31]),
        .O(\gen_mux_rd[7].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[7].mux_rd_fall2_r[7]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [45]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [45]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[47]),
        .O(\gen_mux_rd[7].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[7].mux_rd_fall3_r[7]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [47]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [47]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[63]),
        .O(\gen_mux_rd[7].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[7].mux_rd_rise0_r[7]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [40]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [40]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[7]),
        .O(\gen_mux_rd[7].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[7].mux_rd_rise1_r[7]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [42]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [42]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[23]),
        .O(\gen_mux_rd[7].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[7].mux_rd_rise2_r[7]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [44]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [44]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[39]),
        .O(\gen_mux_rd[7].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hACFFAC00)) 
    \gen_mux_rd[7].mux_rd_rise3_r[7]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [46]),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 [46]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(app_rd_data[55]),
        .O(\gen_mux_rd[7].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'h0000078F)) 
    mem_reg_0_3_6_11_i_1
       (.I0(if_empty_r_0),
        .I1(\my_empty_reg[4]_rep__1_1 [1]),
        .I2(my_empty[2]),
        .I3(my_full[0]),
        .I4(\my_empty_reg[4]_rep__1_0 ),
        .O(p_1_in));
  LUT6 #(
    .INIT(64'hAAABBAAAAAA88AAA)) 
    \my_empty[0]_i_1 
       (.I0(\my_empty_reg[0]_0 ),
        .I1(my_full[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(\wr_ptr[1]_i_2_n_0 ),
        .I4(my_empty[1]),
        .I5(\my_empty[4]_i_2__0_n_0 ),
        .O(\my_empty[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA00411400)) 
    \my_empty[1]_i_1 
       (.I0(\my_empty[1]_i_2_n_0 ),
        .I1(\wr_ptr_reg[1]_0 ),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[0]),
        .I4(\wr_ptr_reg[0]_0 ),
        .I5(my_empty[1]),
        .O(\my_empty[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFFFBFFFFFEAFF)) 
    \my_empty[1]_i_2 
       (.I0(my_full[1]),
        .I1(if_empty_r_0),
        .I2(\my_empty_reg[4]_rep__1_1 [1]),
        .I3(\my_empty_reg[4]_rep__1_0 ),
        .I4(\my_empty_reg[3]_0 ),
        .I5(my_empty[1]),
        .O(\my_empty[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAABBAAAAAA88AAA)) 
    \my_empty[2]_i_1 
       (.I0(my_empty[2]),
        .I1(my_full[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(\wr_ptr[1]_i_2_n_0 ),
        .I4(my_empty[1]),
        .I5(\my_empty[4]_i_2__0_n_0 ),
        .O(\my_empty[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAABBAAAAAA88AAA)) 
    \my_empty[3]_i_1 
       (.I0(\my_empty_reg[3]_0 ),
        .I1(my_full[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(\wr_ptr[1]_i_2_n_0 ),
        .I4(my_empty[1]),
        .I5(\my_empty[4]_i_2__0_n_0 ),
        .O(\my_empty[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAABBAAAAAA88AAA)) 
    \my_empty[4]_i_1 
       (.I0(my_empty[4]),
        .I1(my_full[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(\wr_ptr[1]_i_2_n_0 ),
        .I4(my_empty[1]),
        .I5(\my_empty[4]_i_2__0_n_0 ),
        .O(\my_empty[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000960)) 
    \my_empty[4]_i_2__0 
       (.I0(\wr_ptr_reg[1]_0 ),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(\wr_ptr_reg[0]_0 ),
        .I4(my_empty[1]),
        .O(\my_empty[4]_i_2__0_n_0 ));
  FDSE \my_empty_reg[0] 
       (.C(CLK),
        .CE(\my_full[1]_i_1_n_0 ),
        .D(\my_empty[0]_i_1_n_0 ),
        .Q(\my_empty_reg[0]_0 ),
        .S(ififo_rst));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(\my_full[1]_i_1_n_0 ),
        .D(\my_empty[1]_i_1_n_0 ),
        .Q(my_empty[1]),
        .S(ififo_rst));
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(\my_full[1]_i_1_n_0 ),
        .D(\my_empty[2]_i_1_n_0 ),
        .Q(my_empty[2]),
        .S(ififo_rst));
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(\my_full[1]_i_1_n_0 ),
        .D(\my_empty[3]_i_1_n_0 ),
        .Q(\my_empty_reg[3]_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(CLK),
        .CE(\my_full[1]_i_1_n_0 ),
        .D(\my_empty[4]_i_1_n_0 ),
        .Q(my_empty[4]),
        .S(ififo_rst));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(CLK),
        .CE(\my_full[1]_i_1_n_0 ),
        .D(\my_empty[4]_i_1_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(CLK),
        .CE(\my_full[1]_i_1_n_0 ),
        .D(\my_empty[4]_i_1_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_0 ),
        .S(ififo_rst));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__1 
       (.C(CLK),
        .CE(\my_full[1]_i_1_n_0 ),
        .D(\my_empty[4]_i_1_n_0 ),
        .Q(\my_empty_reg[4]_rep__1_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hBAAAAAAB8AAAAAA8)) 
    \my_full[0]_i_1 
       (.I0(my_full[0]),
        .I1(my_empty[1]),
        .I2(my_full[1]),
        .I3(\my_empty_reg[4]_rep__1_0 ),
        .I4(\wr_ptr[1]_i_2_n_0 ),
        .I5(\my_full[0]_i_2__0_n_0 ),
        .O(\my_full[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair518" *) 
  LUT5 #(
    .INIT(32'h00000960)) 
    \my_full[0]_i_2__0 
       (.I0(rd_ptr[1]),
        .I1(\wr_ptr_reg[1]_0 ),
        .I2(\wr_ptr_reg[0]_0 ),
        .I3(rd_ptr[0]),
        .I4(my_full[1]),
        .O(\my_full[0]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAFFFF)) 
    \my_full[1]_i_1 
       (.I0(my_full[1]),
        .I1(if_empty_r_0),
        .I2(\my_empty_reg[4]_rep__1_1 [1]),
        .I3(\my_empty_reg[4]_rep__1_0 ),
        .I4(my_empty[1]),
        .O(\my_full[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA00411400)) 
    \my_full[1]_i_2 
       (.I0(\my_full[1]_i_3_n_0 ),
        .I1(rd_ptr[1]),
        .I2(\wr_ptr_reg[1]_0 ),
        .I3(\wr_ptr_reg[0]_0 ),
        .I4(rd_ptr[0]),
        .I5(my_full[1]),
        .O(\my_full[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFFFFFFEBFBFBF)) 
    \my_full[1]_i_3 
       (.I0(my_empty[1]),
        .I1(my_full[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(if_empty_r_0),
        .I4(\my_empty_reg[4]_rep__1_1 [1]),
        .I5(\my_empty_reg[3]_0 ),
        .O(\my_full[1]_i_3_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(\my_full[1]_i_1_n_0 ),
        .D(\my_full[0]_i_1_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(CLK),
        .CE(\my_full[1]_i_1_n_0 ),
        .D(\my_full[1]_i_2_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  (* SOFT_HLUTNM = "soft_lutpair519" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr[0]_i_1__0 
       (.I0(my_empty[1]),
        .I1(\wr_ptr[1]_i_2_n_0 ),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair519" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rd_ptr[1]_i_1__0 
       (.I0(rd_ptr[0]),
        .I1(\wr_ptr[1]_i_2_n_0 ),
        .I2(my_empty[1]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__0_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__0_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__0_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT6 #(
    .INIT(64'hEF0F0000FFFF10F0)) 
    \rd_ptr_timing[0]_i_1__1 
       (.I0(\my_empty_reg[4]_rep__1_0 ),
        .I1(my_full[1]),
        .I2(\wr_ptr[1]_i_2_n_0 ),
        .I3(my_empty[1]),
        .I4(rd_ptr_timing[0]),
        .I5(rd_ptr[0]),
        .O(\rd_ptr_timing[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF10F0EF0F0000)) 
    \rd_ptr_timing[1]_i_1__1 
       (.I0(\my_empty_reg[4]_rep__1_0 ),
        .I1(my_full[1]),
        .I2(\wr_ptr[1]_i_2_n_0 ),
        .I3(my_empty[1]),
        .I4(rd_ptr_timing[1]),
        .I5(my_empty1),
        .O(\rd_ptr_timing[1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair518" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_ptr_timing[1]_i_2__0 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .O(my_empty1));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\my_full[1]_i_1_n_0 ),
        .D(\rd_ptr_timing[0]_i_1__1_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\my_full[1]_i_1_n_0 ),
        .D(\rd_ptr_timing[1]_i_1__1_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT6 #(
    .INIT(64'h0777000000000000)) 
    \read_fifo.fifo_ram[1].RAM32M0_i_6 
       (.I0(\my_empty_reg[0]_0 ),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\my_empty_reg[4]_rep__1_1 [0]),
        .I3(if_empty_r_0),
        .I4(app_rd_data_valid_0),
        .I5(\read_fifo.tail_r_reg ),
        .O(\my_empty_reg[0]_1 ));
  LUT6 #(
    .INIT(64'hF888FFFF07770000)) 
    \read_fifo.tail_r[0]_i_1 
       (.I0(\my_empty_reg[0]_0 ),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\my_empty_reg[4]_rep__1_1 [0]),
        .I3(if_empty_r_0),
        .I4(app_rd_data_valid_0),
        .I5(\read_fifo.tail_r_reg ),
        .O(\my_empty_reg[0]_2 ));
  LUT5 #(
    .INIT(32'hEFEC1013)) 
    \wr_ptr[0]_i_1__1 
       (.I0(my_empty[1]),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\wr_ptr[1]_i_2_n_0 ),
        .I3(my_full[1]),
        .I4(\wr_ptr_reg[0]_0 ),
        .O(\wr_ptr[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFDFF5D000200A2)) 
    \wr_ptr[1]_i_1__1 
       (.I0(\wr_ptr_reg[0]_0 ),
        .I1(my_full[1]),
        .I2(\wr_ptr[1]_i_2_n_0 ),
        .I3(\my_empty_reg[4]_rep__1_0 ),
        .I4(my_empty[1]),
        .I5(\wr_ptr_reg[1]_0 ),
        .O(\wr_ptr[1]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0777)) 
    \wr_ptr[1]_i_2 
       (.I0(\my_empty_reg[3]_0 ),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\my_empty_reg[4]_rep__1_1 [1]),
        .I3(if_empty_r_0),
        .O(\wr_ptr[1]_i_2_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__1_n_0 ),
        .Q(\wr_ptr_reg[0]_0 ),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__1_n_0 ),
        .Q(\wr_ptr_reg[1]_0 ),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_if_post_fifo" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_if_post_fifo_7
   (out,
    init_complete_r1_timing_reg,
    \my_empty_reg[0]_0 ,
    phy_rddata_en,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_reg[0]_0 ,
    \my_empty_reg[3]_0 ,
    \my_empty_reg[4]_0 ,
    app_rd_data,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    \read_fifo.tail_r_reg[1] ,
    \my_empty_reg[4]_rep__1_0 ,
    if_empty_r_0,
    my_empty,
    \app_rd_data[112] ,
    \app_rd_data[112]_0 ,
    ififo_rst,
    CLK,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] );
  output [1:0]out;
  output init_complete_r1_timing_reg;
  output \my_empty_reg[0]_0 ;
  output phy_rddata_en;
  output \wr_ptr_reg[1]_0 ;
  output \wr_ptr_reg[0]_0 ;
  output \my_empty_reg[3]_0 ;
  output \my_empty_reg[4]_0 ;
  output [63:0]app_rd_data;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  input \read_fifo.tail_r_reg[1] ;
  input \my_empty_reg[4]_rep__1_0 ;
  input [0:0]if_empty_r_0;
  input [1:0]my_empty;
  input [63:0]\app_rd_data[112] ;
  input [63:0]\app_rd_data[112]_0 ;
  input ififo_rst;
  input CLK;
  input [63:0]\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input [0:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;

  wire CLK;
  wire [63:0]app_rd_data;
  wire [63:0]\app_rd_data[112] ;
  wire [63:0]\app_rd_data[112]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire [0:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire [63:0]\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire [0:0]if_empty_r_0;
  wire ififo_rst;
  wire init_complete_r1_timing_reg;
  wire [1:0]my_empty;
  wire [1:1]my_empty1;
  wire \my_empty[0]_i_1__0_n_0 ;
  wire \my_empty[1]_i_1__0_n_0 ;
  wire \my_empty[1]_i_2__0_n_0 ;
  wire \my_empty[2]_i_1__0_n_0 ;
  wire \my_empty[3]_i_1__0_n_0 ;
  wire \my_empty[4]_i_1__0_n_0 ;
  wire \my_empty[4]_i_2_n_0 ;
  wire [2:1]my_empty_0;
  wire \my_empty_reg[0]_0 ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[4]_0 ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep__1_0 ;
  wire \my_empty_reg[4]_rep__1_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1__0_n_0 ;
  wire \my_full[0]_i_2_n_0 ;
  wire \my_full[1]_i_1__0_n_0 ;
  wire \my_full[1]_i_2__0_n_0 ;
  wire \my_full[1]_i_3__0_n_0 ;
  wire phy_rddata_en;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1_n_0 ;
  wire \rd_ptr[1]_i_1_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__2_n_0 ;
  wire \rd_ptr_timing[1]_i_1__2_n_0 ;
  wire \read_fifo.tail_r_reg[1] ;
  wire \wr_ptr[0]_i_1__0_n_0 ;
  wire \wr_ptr[1]_i_1__0_n_0 ;
  wire \wr_ptr[1]_i_2__0_n_0 ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[1]_0 ;

  assign out[1:0] = rd_ptr_timing;
  (* SOFT_HLUTNM = "soft_lutpair490" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[0]_INST_0 
       (.I0(\app_rd_data[112] [56]),
        .I1(\app_rd_data[112]_0 [56]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[0]));
  (* SOFT_HLUTNM = "soft_lutpair485" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[100]_INST_0 
       (.I0(\app_rd_data[112] [6]),
        .I1(\app_rd_data[112]_0 [6]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[52]));
  (* SOFT_HLUTNM = "soft_lutpair493" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[101]_INST_0 
       (.I0(\app_rd_data[112] [38]),
        .I1(\app_rd_data[112]_0 [38]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[53]));
  (* SOFT_HLUTNM = "soft_lutpair491" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[102]_INST_0 
       (.I0(\app_rd_data[112] [14]),
        .I1(\app_rd_data[112]_0 [14]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[54]));
  (* SOFT_HLUTNM = "soft_lutpair484" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[103]_INST_0 
       (.I0(\app_rd_data[112] [54]),
        .I1(\app_rd_data[112]_0 [54]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[55]));
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[112]_INST_0 
       (.I0(\app_rd_data[112] [63]),
        .I1(\app_rd_data[112]_0 [63]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[56]));
  (* SOFT_HLUTNM = "soft_lutpair497" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[113]_INST_0 
       (.I0(\app_rd_data[112] [31]),
        .I1(\app_rd_data[112]_0 [31]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[57]));
  (* SOFT_HLUTNM = "soft_lutpair507" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[114]_INST_0 
       (.I0(\app_rd_data[112] [47]),
        .I1(\app_rd_data[112]_0 [47]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[58]));
  (* SOFT_HLUTNM = "soft_lutpair504" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[115]_INST_0 
       (.I0(\app_rd_data[112] [23]),
        .I1(\app_rd_data[112]_0 [23]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[59]));
  (* SOFT_HLUTNM = "soft_lutpair501" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[116]_INST_0 
       (.I0(\app_rd_data[112] [7]),
        .I1(\app_rd_data[112]_0 [7]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[60]));
  (* SOFT_HLUTNM = "soft_lutpair506" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[117]_INST_0 
       (.I0(\app_rd_data[112] [39]),
        .I1(\app_rd_data[112]_0 [39]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[61]));
  (* SOFT_HLUTNM = "soft_lutpair502" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[118]_INST_0 
       (.I0(\app_rd_data[112] [15]),
        .I1(\app_rd_data[112]_0 [15]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[62]));
  (* SOFT_HLUTNM = "soft_lutpair499" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[119]_INST_0 
       (.I0(\app_rd_data[112] [55]),
        .I1(\app_rd_data[112]_0 [55]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[63]));
  (* SOFT_HLUTNM = "soft_lutpair509" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[16]_INST_0 
       (.I0(\app_rd_data[112] [57]),
        .I1(\app_rd_data[112]_0 [57]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[8]));
  (* SOFT_HLUTNM = "soft_lutpair496" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[17]_INST_0 
       (.I0(\app_rd_data[112] [25]),
        .I1(\app_rd_data[112]_0 [25]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[9]));
  (* SOFT_HLUTNM = "soft_lutpair506" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[18]_INST_0 
       (.I0(\app_rd_data[112] [41]),
        .I1(\app_rd_data[112]_0 [41]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[10]));
  (* SOFT_HLUTNM = "soft_lutpair503" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[19]_INST_0 
       (.I0(\app_rd_data[112] [17]),
        .I1(\app_rd_data[112]_0 [17]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[11]));
  (* SOFT_HLUTNM = "soft_lutpair482" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[1]_INST_0 
       (.I0(\app_rd_data[112] [24]),
        .I1(\app_rd_data[112]_0 [24]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[1]));
  (* SOFT_HLUTNM = "soft_lutpair500" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[20]_INST_0 
       (.I0(\app_rd_data[112] [1]),
        .I1(\app_rd_data[112]_0 [1]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[12]));
  (* SOFT_HLUTNM = "soft_lutpair505" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[21]_INST_0 
       (.I0(\app_rd_data[112] [33]),
        .I1(\app_rd_data[112]_0 [33]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[13]));
  (* SOFT_HLUTNM = "soft_lutpair501" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[22]_INST_0 
       (.I0(\app_rd_data[112] [9]),
        .I1(\app_rd_data[112]_0 [9]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[14]));
  (* SOFT_HLUTNM = "soft_lutpair498" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[23]_INST_0 
       (.I0(\app_rd_data[112] [49]),
        .I1(\app_rd_data[112]_0 [49]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[15]));
  (* SOFT_HLUTNM = "soft_lutpair488" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[2]_INST_0 
       (.I0(\app_rd_data[112] [40]),
        .I1(\app_rd_data[112]_0 [40]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[2]));
  (* SOFT_HLUTNM = "soft_lutpair484" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[32]_INST_0 
       (.I0(\app_rd_data[112] [58]),
        .I1(\app_rd_data[112]_0 [58]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[16]));
  (* SOFT_HLUTNM = "soft_lutpair492" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[33]_INST_0 
       (.I0(\app_rd_data[112] [26]),
        .I1(\app_rd_data[112]_0 [26]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[17]));
  (* SOFT_HLUTNM = "soft_lutpair483" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[34]_INST_0 
       (.I0(\app_rd_data[112] [42]),
        .I1(\app_rd_data[112]_0 [42]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[18]));
  (* SOFT_HLUTNM = "soft_lutpair481" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[35]_INST_0 
       (.I0(\app_rd_data[112] [18]),
        .I1(\app_rd_data[112]_0 [18]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[19]));
  (* SOFT_HLUTNM = "soft_lutpair480" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[36]_INST_0 
       (.I0(\app_rd_data[112] [2]),
        .I1(\app_rd_data[112]_0 [2]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[20]));
  (* SOFT_HLUTNM = "soft_lutpair488" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[37]_INST_0 
       (.I0(\app_rd_data[112] [34]),
        .I1(\app_rd_data[112]_0 [34]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[21]));
  (* SOFT_HLUTNM = "soft_lutpair486" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[38]_INST_0 
       (.I0(\app_rd_data[112] [10]),
        .I1(\app_rd_data[112]_0 [10]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[22]));
  (* SOFT_HLUTNM = "soft_lutpair494" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[39]_INST_0 
       (.I0(\app_rd_data[112] [50]),
        .I1(\app_rd_data[112]_0 [50]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[23]));
  (* SOFT_HLUTNM = "soft_lutpair486" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[3]_INST_0 
       (.I0(\app_rd_data[112] [16]),
        .I1(\app_rd_data[112]_0 [16]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[3]));
  (* SOFT_HLUTNM = "soft_lutpair499" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[48]_INST_0 
       (.I0(\app_rd_data[112] [59]),
        .I1(\app_rd_data[112]_0 [59]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[24]));
  (* SOFT_HLUTNM = "soft_lutpair504" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[49]_INST_0 
       (.I0(\app_rd_data[112] [27]),
        .I1(\app_rd_data[112]_0 [27]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[25]));
  (* SOFT_HLUTNM = "soft_lutpair485" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[4]_INST_0 
       (.I0(\app_rd_data[112] [0]),
        .I1(\app_rd_data[112]_0 [0]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[4]));
  (* SOFT_HLUTNM = "soft_lutpair498" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[50]_INST_0 
       (.I0(\app_rd_data[112] [43]),
        .I1(\app_rd_data[112]_0 [43]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[26]));
  (* SOFT_HLUTNM = "soft_lutpair496" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[51]_INST_0 
       (.I0(\app_rd_data[112] [19]),
        .I1(\app_rd_data[112]_0 [19]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[27]));
  (* SOFT_HLUTNM = "soft_lutpair495" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[52]_INST_0 
       (.I0(\app_rd_data[112] [3]),
        .I1(\app_rd_data[112]_0 [3]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[28]));
  (* SOFT_HLUTNM = "soft_lutpair505" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[53]_INST_0 
       (.I0(\app_rd_data[112] [35]),
        .I1(\app_rd_data[112]_0 [35]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[29]));
  (* SOFT_HLUTNM = "soft_lutpair502" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[54]_INST_0 
       (.I0(\app_rd_data[112] [11]),
        .I1(\app_rd_data[112]_0 [11]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[30]));
  (* SOFT_HLUTNM = "soft_lutpair508" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[55]_INST_0 
       (.I0(\app_rd_data[112] [51]),
        .I1(\app_rd_data[112]_0 [51]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[31]));
  (* SOFT_HLUTNM = "soft_lutpair479" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[5]_INST_0 
       (.I0(\app_rd_data[112] [32]),
        .I1(\app_rd_data[112]_0 [32]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[5]));
  (* SOFT_HLUTNM = "soft_lutpair494" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[64]_INST_0 
       (.I0(\app_rd_data[112] [60]),
        .I1(\app_rd_data[112]_0 [60]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[32]));
  (* SOFT_HLUTNM = "soft_lutpair487" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[65]_INST_0 
       (.I0(\app_rd_data[112] [28]),
        .I1(\app_rd_data[112]_0 [28]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[33]));
  (* SOFT_HLUTNM = "soft_lutpair493" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[66]_INST_0 
       (.I0(\app_rd_data[112] [44]),
        .I1(\app_rd_data[112]_0 [44]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[34]));
  (* SOFT_HLUTNM = "soft_lutpair492" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[67]_INST_0 
       (.I0(\app_rd_data[112] [20]),
        .I1(\app_rd_data[112]_0 [20]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[35]));
  (* SOFT_HLUTNM = "soft_lutpair491" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[68]_INST_0 
       (.I0(\app_rd_data[112] [4]),
        .I1(\app_rd_data[112]_0 [4]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[36]));
  (* SOFT_HLUTNM = "soft_lutpair483" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[69]_INST_0 
       (.I0(\app_rd_data[112] [36]),
        .I1(\app_rd_data[112]_0 [36]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[37]));
  (* SOFT_HLUTNM = "soft_lutpair480" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[6]_INST_0 
       (.I0(\app_rd_data[112] [8]),
        .I1(\app_rd_data[112]_0 [8]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[6]));
  (* SOFT_HLUTNM = "soft_lutpair481" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[70]_INST_0 
       (.I0(\app_rd_data[112] [12]),
        .I1(\app_rd_data[112]_0 [12]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[38]));
  (* SOFT_HLUTNM = "soft_lutpair489" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[71]_INST_0 
       (.I0(\app_rd_data[112] [52]),
        .I1(\app_rd_data[112]_0 [52]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[39]));
  (* SOFT_HLUTNM = "soft_lutpair479" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[7]_INST_0 
       (.I0(\app_rd_data[112] [48]),
        .I1(\app_rd_data[112]_0 [48]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[7]));
  (* SOFT_HLUTNM = "soft_lutpair509" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[80]_INST_0 
       (.I0(\app_rd_data[112] [61]),
        .I1(\app_rd_data[112]_0 [61]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[40]));
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[81]_INST_0 
       (.I0(\app_rd_data[112] [29]),
        .I1(\app_rd_data[112]_0 [29]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[41]));
  (* SOFT_HLUTNM = "soft_lutpair507" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[82]_INST_0 
       (.I0(\app_rd_data[112] [45]),
        .I1(\app_rd_data[112]_0 [45]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[42]));
  (* SOFT_HLUTNM = "soft_lutpair503" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[83]_INST_0 
       (.I0(\app_rd_data[112] [21]),
        .I1(\app_rd_data[112]_0 [21]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[43]));
  (* SOFT_HLUTNM = "soft_lutpair500" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[84]_INST_0 
       (.I0(\app_rd_data[112] [5]),
        .I1(\app_rd_data[112]_0 [5]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[44]));
  (* SOFT_HLUTNM = "soft_lutpair497" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[85]_INST_0 
       (.I0(\app_rd_data[112] [37]),
        .I1(\app_rd_data[112]_0 [37]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[45]));
  (* SOFT_HLUTNM = "soft_lutpair495" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[86]_INST_0 
       (.I0(\app_rd_data[112] [13]),
        .I1(\app_rd_data[112]_0 [13]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[46]));
  (* SOFT_HLUTNM = "soft_lutpair508" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[87]_INST_0 
       (.I0(\app_rd_data[112] [53]),
        .I1(\app_rd_data[112]_0 [53]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[47]));
  (* SOFT_HLUTNM = "soft_lutpair490" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[96]_INST_0 
       (.I0(\app_rd_data[112] [62]),
        .I1(\app_rd_data[112]_0 [62]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[48]));
  (* SOFT_HLUTNM = "soft_lutpair482" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[97]_INST_0 
       (.I0(\app_rd_data[112] [30]),
        .I1(\app_rd_data[112]_0 [30]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[49]));
  (* SOFT_HLUTNM = "soft_lutpair489" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[98]_INST_0 
       (.I0(\app_rd_data[112] [46]),
        .I1(\app_rd_data[112]_0 [46]),
        .I2(\my_empty_reg[4]_rep_n_0 ),
        .O(app_rd_data[50]));
  (* SOFT_HLUTNM = "soft_lutpair487" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \app_rd_data[99]_INST_0 
       (.I0(\app_rd_data[112] [22]),
        .I1(\app_rd_data[112]_0 [22]),
        .I2(\my_empty_reg[4]_0 ),
        .O(app_rd_data[51]));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [8]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [57]),
        .I4(\app_rd_data[112] [57]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [24]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [59]),
        .I4(\app_rd_data[112] [59]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [40]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [61]),
        .I4(\app_rd_data[112] [61]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [56]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [63]),
        .I4(\app_rd_data[112] [63]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [0]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [56]),
        .I4(\app_rd_data[112] [56]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [16]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [58]),
        .I4(\app_rd_data[112] [58]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [48]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [62]),
        .I4(\app_rd_data[112] [62]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [9]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [25]),
        .I4(\app_rd_data[112] [25]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [25]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [27]),
        .I4(\app_rd_data[112] [27]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [41]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [29]),
        .I4(\app_rd_data[112] [29]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [57]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [31]),
        .I4(\app_rd_data[112] [31]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [1]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [24]),
        .I4(\app_rd_data[112] [24]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [17]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [26]),
        .I4(\app_rd_data[112] [26]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [33]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [28]),
        .I4(\app_rd_data[112] [28]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [49]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [30]),
        .I4(\app_rd_data[112] [30]),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [10]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [41]),
        .I4(\app_rd_data[112] [41]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [26]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [43]),
        .I4(\app_rd_data[112] [43]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [42]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [45]),
        .I4(\app_rd_data[112] [45]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [58]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [47]),
        .I4(\app_rd_data[112] [47]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [2]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [40]),
        .I4(\app_rd_data[112] [40]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [18]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [42]),
        .I4(\app_rd_data[112] [42]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [34]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [44]),
        .I4(\app_rd_data[112] [44]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [50]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [46]),
        .I4(\app_rd_data[112] [46]),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [11]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [17]),
        .I4(\app_rd_data[112] [17]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [27]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [19]),
        .I4(\app_rd_data[112] [19]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [43]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [21]),
        .I4(\app_rd_data[112] [21]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [59]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [23]),
        .I4(\app_rd_data[112] [23]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [3]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [16]),
        .I4(\app_rd_data[112] [16]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [19]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [18]),
        .I4(\app_rd_data[112] [18]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [35]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [20]),
        .I4(\app_rd_data[112] [20]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [12]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [1]),
        .I4(\app_rd_data[112] [1]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [28]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [3]),
        .I4(\app_rd_data[112] [3]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [44]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [5]),
        .I4(\app_rd_data[112] [5]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [60]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [7]),
        .I4(\app_rd_data[112] [7]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [4]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [0]),
        .I4(\app_rd_data[112] [0]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [20]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [2]),
        .I4(\app_rd_data[112] [2]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [52]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [6]),
        .I4(\app_rd_data[112] [6]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [13]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [33]),
        .I4(\app_rd_data[112] [33]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [29]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [35]),
        .I4(\app_rd_data[112] [35]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [45]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [37]),
        .I4(\app_rd_data[112] [37]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [61]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [39]),
        .I4(\app_rd_data[112] [39]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [5]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [32]),
        .I4(\app_rd_data[112] [32]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [21]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [34]),
        .I4(\app_rd_data[112] [34]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [37]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [36]),
        .I4(\app_rd_data[112] [36]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [53]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [38]),
        .I4(\app_rd_data[112] [38]),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [14]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [9]),
        .I4(\app_rd_data[112] [9]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [30]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [11]),
        .I4(\app_rd_data[112] [11]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [46]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [13]),
        .I4(\app_rd_data[112] [13]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [62]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [15]),
        .I4(\app_rd_data[112] [15]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [6]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [8]),
        .I4(\app_rd_data[112] [8]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [22]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [10]),
        .I4(\app_rd_data[112] [10]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [38]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [12]),
        .I4(\app_rd_data[112] [12]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [54]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [14]),
        .I4(\app_rd_data[112] [14]),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [15]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [49]),
        .I4(\app_rd_data[112] [49]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [31]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [51]),
        .I4(\app_rd_data[112] [51]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [47]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [53]),
        .I4(\app_rd_data[112] [53]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [63]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [55]),
        .I4(\app_rd_data[112] [55]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [7]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [48]),
        .I4(\app_rd_data[112] [48]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [23]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [50]),
        .I4(\app_rd_data[112] [50]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [39]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [52]),
        .I4(\app_rd_data[112] [52]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [32]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [60]),
        .I4(\app_rd_data[112] [60]),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [51]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [22]),
        .I4(\app_rd_data[112] [22]),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [36]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__0_n_0 ),
        .I3(\app_rd_data[112]_0 [4]),
        .I4(\app_rd_data[112] [4]),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ));
  LUT5 #(
    .INIT(32'hBBB88B88)) 
    \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] [55]),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\my_empty_reg[4]_rep__1_n_0 ),
        .I3(\app_rd_data[112]_0 [54]),
        .I4(\app_rd_data[112] [54]),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ));
  LUT5 #(
    .INIT(32'h0000078F)) 
    mem_reg_0_3_0_5_i_1
       (.I0(if_empty_r_0),
        .I1(my_empty[1]),
        .I2(my_empty_0[2]),
        .I3(my_full[0]),
        .I4(\my_empty_reg[4]_rep__1_0 ),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ));
  LUT6 #(
    .INIT(64'hAAABBAAAAAA88AAA)) 
    \my_empty[0]_i_1__0 
       (.I0(\my_empty_reg[0]_0 ),
        .I1(my_full[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(\wr_ptr[1]_i_2__0_n_0 ),
        .I4(my_empty_0[1]),
        .I5(\my_empty[4]_i_2_n_0 ),
        .O(\my_empty[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA00411400)) 
    \my_empty[1]_i_1__0 
       (.I0(\my_empty[1]_i_2__0_n_0 ),
        .I1(\wr_ptr_reg[1]_0 ),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[0]),
        .I4(\wr_ptr_reg[0]_0 ),
        .I5(my_empty_0[1]),
        .O(\my_empty[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFBFFFBFFFFFEAFF)) 
    \my_empty[1]_i_2__0 
       (.I0(my_full[1]),
        .I1(if_empty_r_0),
        .I2(my_empty[1]),
        .I3(\my_empty_reg[4]_rep__1_0 ),
        .I4(\my_empty_reg[3]_0 ),
        .I5(my_empty_0[1]),
        .O(\my_empty[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAABBAAAAAA88AAA)) 
    \my_empty[2]_i_1__0 
       (.I0(my_empty_0[2]),
        .I1(my_full[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(\wr_ptr[1]_i_2__0_n_0 ),
        .I4(my_empty_0[1]),
        .I5(\my_empty[4]_i_2_n_0 ),
        .O(\my_empty[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAABBAAAAAA88AAA)) 
    \my_empty[3]_i_1__0 
       (.I0(\my_empty_reg[3]_0 ),
        .I1(my_full[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(\wr_ptr[1]_i_2__0_n_0 ),
        .I4(my_empty_0[1]),
        .I5(\my_empty[4]_i_2_n_0 ),
        .O(\my_empty[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAABBAAAAAA88AAA)) 
    \my_empty[4]_i_1__0 
       (.I0(\my_empty_reg[4]_0 ),
        .I1(my_full[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(\wr_ptr[1]_i_2__0_n_0 ),
        .I4(my_empty_0[1]),
        .I5(\my_empty[4]_i_2_n_0 ),
        .O(\my_empty[4]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00000960)) 
    \my_empty[4]_i_2 
       (.I0(\wr_ptr_reg[1]_0 ),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(\wr_ptr_reg[0]_0 ),
        .I4(my_empty_0[1]),
        .O(\my_empty[4]_i_2_n_0 ));
  FDSE \my_empty_reg[0] 
       (.C(CLK),
        .CE(\my_full[1]_i_1__0_n_0 ),
        .D(\my_empty[0]_i_1__0_n_0 ),
        .Q(\my_empty_reg[0]_0 ),
        .S(ififo_rst));
  FDSE \my_empty_reg[1] 
       (.C(CLK),
        .CE(\my_full[1]_i_1__0_n_0 ),
        .D(\my_empty[1]_i_1__0_n_0 ),
        .Q(my_empty_0[1]),
        .S(ififo_rst));
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(\my_full[1]_i_1__0_n_0 ),
        .D(\my_empty[2]_i_1__0_n_0 ),
        .Q(my_empty_0[2]),
        .S(ififo_rst));
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(\my_full[1]_i_1__0_n_0 ),
        .D(\my_empty[3]_i_1__0_n_0 ),
        .Q(\my_empty_reg[3]_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(CLK),
        .CE(\my_full[1]_i_1__0_n_0 ),
        .D(\my_empty[4]_i_1__0_n_0 ),
        .Q(\my_empty_reg[4]_0 ),
        .S(ififo_rst));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(CLK),
        .CE(\my_full[1]_i_1__0_n_0 ),
        .D(\my_empty[4]_i_1__0_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(CLK),
        .CE(\my_full[1]_i_1__0_n_0 ),
        .D(\my_empty[4]_i_1__0_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__1 
       (.C(CLK),
        .CE(\my_full[1]_i_1__0_n_0 ),
        .D(\my_empty[4]_i_1__0_n_0 ),
        .Q(\my_empty_reg[4]_rep__1_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hBAAAAAAB8AAAAAA8)) 
    \my_full[0]_i_1__0 
       (.I0(my_full[0]),
        .I1(my_empty_0[1]),
        .I2(my_full[1]),
        .I3(\my_empty_reg[4]_rep__1_0 ),
        .I4(\wr_ptr[1]_i_2__0_n_0 ),
        .I5(\my_full[0]_i_2_n_0 ),
        .O(\my_full[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair477" *) 
  LUT5 #(
    .INIT(32'h00000960)) 
    \my_full[0]_i_2 
       (.I0(rd_ptr[1]),
        .I1(\wr_ptr_reg[1]_0 ),
        .I2(\wr_ptr_reg[0]_0 ),
        .I3(rd_ptr[0]),
        .I4(my_full[1]),
        .O(\my_full[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFEAFFFF)) 
    \my_full[1]_i_1__0 
       (.I0(my_full[1]),
        .I1(if_empty_r_0),
        .I2(my_empty[1]),
        .I3(\my_empty_reg[4]_rep__1_0 ),
        .I4(my_empty_0[1]),
        .O(\my_full[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA00411400)) 
    \my_full[1]_i_2__0 
       (.I0(\my_full[1]_i_3__0_n_0 ),
        .I1(rd_ptr[1]),
        .I2(\wr_ptr_reg[1]_0 ),
        .I3(\wr_ptr_reg[0]_0 ),
        .I4(rd_ptr[0]),
        .I5(my_full[1]),
        .O(\my_full[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFFFFFFEBFBFBF)) 
    \my_full[1]_i_3__0 
       (.I0(my_empty_0[1]),
        .I1(my_full[1]),
        .I2(\my_empty_reg[4]_rep__1_0 ),
        .I3(if_empty_r_0),
        .I4(my_empty[1]),
        .I5(\my_empty_reg[3]_0 ),
        .O(\my_full[1]_i_3__0_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(\my_full[1]_i_1__0_n_0 ),
        .D(\my_full[0]_i_1__0_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(CLK),
        .CE(\my_full[1]_i_1__0_n_0 ),
        .D(\my_full[1]_i_2__0_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  (* SOFT_HLUTNM = "soft_lutpair476" *) 
  LUT4 #(
    .INIT(16'h0777)) 
    rd_active_r_i_1
       (.I0(\my_empty_reg[4]_rep__1_0 ),
        .I1(\my_empty_reg[0]_0 ),
        .I2(if_empty_r_0),
        .I3(my_empty[0]),
        .O(phy_rddata_en));
  (* SOFT_HLUTNM = "soft_lutpair478" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr[0]_i_1 
       (.I0(my_empty_0[1]),
        .I1(\wr_ptr[1]_i_2__0_n_0 ),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair478" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rd_ptr[1]_i_1 
       (.I0(rd_ptr[0]),
        .I1(\wr_ptr[1]_i_2__0_n_0 ),
        .I2(my_empty_0[1]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT6 #(
    .INIT(64'hEF0F0000FFFF10F0)) 
    \rd_ptr_timing[0]_i_1__2 
       (.I0(\my_empty_reg[4]_rep__1_0 ),
        .I1(my_full[1]),
        .I2(\wr_ptr[1]_i_2__0_n_0 ),
        .I3(my_empty_0[1]),
        .I4(rd_ptr_timing[0]),
        .I5(rd_ptr[0]),
        .O(\rd_ptr_timing[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF10F0EF0F0000)) 
    \rd_ptr_timing[1]_i_1__2 
       (.I0(\my_empty_reg[4]_rep__1_0 ),
        .I1(my_full[1]),
        .I2(\wr_ptr[1]_i_2__0_n_0 ),
        .I3(my_empty_0[1]),
        .I4(rd_ptr_timing[1]),
        .I5(my_empty1),
        .O(\rd_ptr_timing[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair477" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_ptr_timing[1]_i_2 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .O(my_empty1));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\my_full[1]_i_1__0_n_0 ),
        .D(\rd_ptr_timing[0]_i_1__2_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\my_full[1]_i_1__0_n_0 ),
        .D(\rd_ptr_timing[1]_i_1__2_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  (* SOFT_HLUTNM = "soft_lutpair476" *) 
  LUT5 #(
    .INIT(32'h002A2A2A)) 
    \read_fifo.fifo_ram[1].RAM32M0_i_7 
       (.I0(\read_fifo.tail_r_reg[1] ),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\my_empty_reg[0]_0 ),
        .I3(if_empty_r_0),
        .I4(my_empty[0]),
        .O(init_complete_r1_timing_reg));
  LUT5 #(
    .INIT(32'hEFEC1013)) 
    \wr_ptr[0]_i_1__0 
       (.I0(my_empty_0[1]),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(\wr_ptr[1]_i_2__0_n_0 ),
        .I3(my_full[1]),
        .I4(\wr_ptr_reg[0]_0 ),
        .O(\wr_ptr[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFDFF5D000200A2)) 
    \wr_ptr[1]_i_1__0 
       (.I0(\wr_ptr_reg[0]_0 ),
        .I1(my_full[1]),
        .I2(\wr_ptr[1]_i_2__0_n_0 ),
        .I3(\my_empty_reg[4]_rep__1_0 ),
        .I4(my_empty_0[1]),
        .I5(\wr_ptr_reg[1]_0 ),
        .O(\wr_ptr[1]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h0777)) 
    \wr_ptr[1]_i_2__0 
       (.I0(\my_empty_reg[3]_0 ),
        .I1(\my_empty_reg[4]_rep__1_0 ),
        .I2(my_empty[1]),
        .I3(if_empty_r_0),
        .O(\wr_ptr[1]_i_2__0_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__0_n_0 ),
        .Q(\wr_ptr_reg[0]_0 ),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__0_n_0 ),
        .Q(\wr_ptr_reg[1]_0 ),
        .R(ififo_rst));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_mc_phy
   (A_rst_primitives_reg,
    \rd_ptr_reg[0] ,
    \rd_ptr_reg[1] ,
    \rd_ptr_reg[2] ,
    \rd_ptr_reg[3] ,
    out,
    A_rst_primitives_reg_0,
    mem_dq_out,
    mem_dq_ts,
    out_dqs_0,
    ts_dqs_0,
    pi_dqs_found_lanes,
    \rd_ptr_reg[0]_0 ,
    \rd_ptr_reg[1]_0 ,
    \rd_ptr_reg[2]_0 ,
    \rd_ptr_reg[3]_0 ,
    \rd_ptr_timing_reg[1] ,
    A_rst_primitives_reg_1,
    out_dqs_1,
    ts_dqs_1,
    \rd_ptr_reg[0]_1 ,
    \rd_ptr_reg[1]_1 ,
    \rd_ptr_reg[2]_1 ,
    \rd_ptr_reg[3]_1 ,
    phy_mc_ctl_full,
    ref_dll_lock,
    idelay_ld_rst,
    ddr_ck_out,
    \my_empty_reg[1] ,
    \my_empty_reg[1]_0 ,
    init_complete_r1_timing_reg,
    \my_empty_reg[1]_1 ,
    \my_empty_reg[1]_2 ,
    app_rd_data_valid,
    \my_empty_reg[0] ,
    \my_empty_reg[0]_0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    app_rd_data,
    \gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    \pi_counter_read_val_reg[5] ,
    \pi_counter_read_val_reg[5]_0 ,
    phy_rddata_en,
    A_rst_primitives_reg_2,
    phy_mc_data_full,
    wr_en,
    wr_en_2,
    phy_mc_cmd_full,
    wr_en_3,
    \wr_ptr_reg[3] ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[3]_0 ,
    \my_empty_reg[4] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_reg[3]_1 ,
    \my_empty_reg[4]_rep__0 ,
    \po_counter_read_val_reg[8] ,
    \mcGo_r_reg[15]_0 ,
    \rd_ptr_reg[3]_2 ,
    p_1_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \po_counter_read_val_reg[8]_2 ,
    \po_counter_read_val_reg[8]_3 ,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    CLK,
    \rd_ptr_reg[3]_3 ,
    \rd_ptr_reg[3]_4 ,
    \rd_ptr_reg[3]_5 ,
    \rd_ptr_reg[3]_6 ,
    \rd_ptr_reg[3]_7 ,
    \rd_ptr_reg[3]_8 ,
    \rd_ptr_reg[3]_9 ,
    \rd_ptr_reg[3]_10 ,
    \rd_ptr_reg[3]_11 ,
    \rd_ptr_reg[3]_12 ,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0,
    CLKB0,
    \pi_dqs_found_lanes_r1_reg[2] ,
    \pi_dqs_found_lanes_r1_reg[2]_0 ,
    \pi_dqs_found_lanes_r1_reg[2]_1 ,
    \pi_dqs_found_lanes_r1_reg[2]_2 ,
    mem_dqs_in,
    \pi_dqs_found_lanes_r1_reg[2]_3 ,
    COUNTERLOADVAL,
    \po_counter_read_val_reg[8]_4 ,
    \po_counter_read_val_reg[8]_5 ,
    \po_counter_read_val_reg[8]_6 ,
    D0,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    D9,
    ififo_rst_reg0,
    ofifo_rst_reg0,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    LD0_0,
    CLKB0_4,
    \pi_dqs_found_lanes_r1_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    \pi_dqs_found_lanes_r1_reg[3]_1 ,
    \pi_dqs_found_lanes_r1_reg[3]_2 ,
    \pi_dqs_found_lanes_r1_reg[3]_3 ,
    \pi_dqs_found_lanes_r1_reg[3]_4 ,
    \po_counter_read_val_reg[8]_7 ,
    \po_counter_read_val_reg[8]_8 ,
    \po_counter_read_val_reg[8]_9 ,
    D1,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    ififo_rst_reg0_1,
    ofifo_rst_reg0_2,
    phy_ctl_wr_i2,
    pll_locked,
    phy_read_calib,
    in0,
    phy_write_calib,
    Q,
    RST0,
    SR,
    \po_counter_read_val_reg[8]_10 ,
    \po_counter_read_val_reg[8]_11 ,
    \po_counter_read_val_reg[8]_12 ,
    \po_counter_read_val_reg[8]_13 ,
    \my_empty_reg[7]_7 ,
    \my_empty_reg[7]_8 ,
    \my_empty_reg[7]_9 ,
    \my_empty_reg[7]_10 ,
    \my_empty_reg[7]_11 ,
    \my_empty_reg[7]_12 ,
    \my_empty_reg[7]_13 ,
    \my_empty_reg[7]_14 ,
    \wr_ptr_timing_reg[0] ,
    calib_cmd_wren,
    \wr_ptr_timing_reg[0]_0 ,
    mem_out,
    app_rd_data_valid_0,
    mux_wrdata_en,
    mc_wrdata_en,
    \wr_ptr_timing_reg[0]_1 ,
    calib_wrdata_en,
    out_fifo,
    app_rd_data_valid_1,
    \read_fifo.tail_r_reg ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    mux_cmd_wren,
    mc_address,
    mc_cas_n,
    phy_dout,
    \app_rd_data[112] ,
    calib_sel,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] );
  output A_rst_primitives_reg;
  output \rd_ptr_reg[0] ;
  output \rd_ptr_reg[1] ;
  output \rd_ptr_reg[2] ;
  output \rd_ptr_reg[3] ;
  output [1:0]out;
  output A_rst_primitives_reg_0;
  output [40:0]mem_dq_out;
  output [17:0]mem_dq_ts;
  output out_dqs_0;
  output ts_dqs_0;
  output [1:0]pi_dqs_found_lanes;
  output \rd_ptr_reg[0]_0 ;
  output \rd_ptr_reg[1]_0 ;
  output \rd_ptr_reg[2]_0 ;
  output \rd_ptr_reg[3]_0 ;
  output [1:0]\rd_ptr_timing_reg[1] ;
  output A_rst_primitives_reg_1;
  output out_dqs_1;
  output ts_dqs_1;
  output \rd_ptr_reg[0]_1 ;
  output \rd_ptr_reg[1]_1 ;
  output \rd_ptr_reg[2]_1 ;
  output \rd_ptr_reg[3]_1 ;
  output phy_mc_ctl_full;
  output ref_dll_lock;
  output idelay_ld_rst;
  output [1:0]ddr_ck_out;
  output \my_empty_reg[1] ;
  output \my_empty_reg[1]_0 ;
  output init_complete_r1_timing_reg;
  output \my_empty_reg[1]_1 ;
  output \my_empty_reg[1]_2 ;
  output app_rd_data_valid;
  output \my_empty_reg[0] ;
  output \my_empty_reg[0]_0 ;
  output \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  output [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output [127:0]app_rd_data;
  output \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  output \pi_counter_read_val_reg[5] ;
  output [5:0]\pi_counter_read_val_reg[5]_0 ;
  output phy_rddata_en;
  output A_rst_primitives_reg_2;
  output phy_mc_data_full;
  output wr_en;
  output wr_en_2;
  output phy_mc_cmd_full;
  output wr_en_3;
  output [3:0]\wr_ptr_reg[3] ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1] ;
  output [3:0]\wr_ptr_reg[3]_0 ;
  output \my_empty_reg[4] ;
  output [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_0 ;
  output [3:0]\wr_ptr_reg[3]_1 ;
  output \my_empty_reg[4]_rep__0 ;
  output [8:0]\po_counter_read_val_reg[8] ;
  output [0:0]\mcGo_r_reg[15]_0 ;
  output [35:0]\rd_ptr_reg[3]_2 ;
  output p_1_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input \po_counter_read_val_reg[8]_2 ;
  input \po_counter_read_val_reg[8]_3 ;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input CLK;
  input [3:0]\rd_ptr_reg[3]_3 ;
  input [3:0]\rd_ptr_reg[3]_4 ;
  input [2:0]\rd_ptr_reg[3]_5 ;
  input [3:0]\rd_ptr_reg[3]_6 ;
  input [3:0]\rd_ptr_reg[3]_7 ;
  input [7:0]\rd_ptr_reg[3]_8 ;
  input [5:0]\rd_ptr_reg[3]_9 ;
  input [2:0]\rd_ptr_reg[3]_10 ;
  input [3:0]\rd_ptr_reg[3]_11 ;
  input [3:0]\rd_ptr_reg[3]_12 ;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [15:0]mem_dq_in;
  input idelay_inc;
  input LD0;
  input CLKB0;
  input \pi_dqs_found_lanes_r1_reg[2] ;
  input \pi_dqs_found_lanes_r1_reg[2]_0 ;
  input \pi_dqs_found_lanes_r1_reg[2]_1 ;
  input \pi_dqs_found_lanes_r1_reg[2]_2 ;
  input [1:0]mem_dqs_in;
  input \pi_dqs_found_lanes_r1_reg[2]_3 ;
  input [5:0]COUNTERLOADVAL;
  input \po_counter_read_val_reg[8]_4 ;
  input \po_counter_read_val_reg[8]_5 ;
  input \po_counter_read_val_reg[8]_6 ;
  input [7:0]D0;
  input [7:0]D2;
  input [7:0]D3;
  input [7:0]D4;
  input [7:0]D5;
  input [7:0]D6;
  input [7:0]D7;
  input [7:0]D8;
  input [7:0]D9;
  input ififo_rst_reg0;
  input ofifo_rst_reg0;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input LD0_0;
  input CLKB0_4;
  input \pi_dqs_found_lanes_r1_reg[3] ;
  input \pi_dqs_found_lanes_r1_reg[3]_0 ;
  input \pi_dqs_found_lanes_r1_reg[3]_1 ;
  input \pi_dqs_found_lanes_r1_reg[3]_2 ;
  input \pi_dqs_found_lanes_r1_reg[3]_3 ;
  input [5:0]\pi_dqs_found_lanes_r1_reg[3]_4 ;
  input \po_counter_read_val_reg[8]_7 ;
  input \po_counter_read_val_reg[8]_8 ;
  input \po_counter_read_val_reg[8]_9 ;
  input [7:0]D1;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input ififo_rst_reg0_1;
  input ofifo_rst_reg0_2;
  input phy_ctl_wr_i2;
  input pll_locked;
  input phy_read_calib;
  input in0;
  input phy_write_calib;
  input [10:0]Q;
  input RST0;
  input [0:0]SR;
  input \po_counter_read_val_reg[8]_10 ;
  input \po_counter_read_val_reg[8]_11 ;
  input \po_counter_read_val_reg[8]_12 ;
  input \po_counter_read_val_reg[8]_13 ;
  input [3:0]\my_empty_reg[7]_7 ;
  input [3:0]\my_empty_reg[7]_8 ;
  input [3:0]\my_empty_reg[7]_9 ;
  input [3:0]\my_empty_reg[7]_10 ;
  input [7:0]\my_empty_reg[7]_11 ;
  input [3:0]\my_empty_reg[7]_12 ;
  input [3:0]\my_empty_reg[7]_13 ;
  input [3:0]\my_empty_reg[7]_14 ;
  input \wr_ptr_timing_reg[0] ;
  input calib_cmd_wren;
  input \wr_ptr_timing_reg[0]_0 ;
  input [3:0]mem_out;
  input app_rd_data_valid_0;
  input mux_wrdata_en;
  input mc_wrdata_en;
  input \wr_ptr_timing_reg[0]_1 ;
  input calib_wrdata_en;
  input out_fifo;
  input [0:0]app_rd_data_valid_1;
  input [0:0]\read_fifo.tail_r_reg ;
  input [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input mux_cmd_wren;
  input [3:0]mc_address;
  input [0:0]mc_cas_n;
  input [38:0]phy_dout;
  input [63:0]\app_rd_data[112] ;
  input [1:0]calib_sel;
  input [0:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;

  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire CLK;
  wire CLKB0;
  wire CLKB0_4;
  wire [5:0]COUNTERLOADVAL;
  wire [7:0]D0;
  wire [7:0]D1;
  wire [7:0]D2;
  wire [7:0]D3;
  wire [7:0]D4;
  wire [7:0]D5;
  wire [7:0]D6;
  wire [7:0]D7;
  wire [7:0]D8;
  wire [7:0]D9;
  wire LD0;
  wire LD0_0;
  wire [10:0]Q;
  wire RST0;
  wire [0:0]SR;
  wire [127:0]app_rd_data;
  wire [63:0]\app_rd_data[112] ;
  wire app_rd_data_valid;
  wire app_rd_data_valid_0;
  wire [0:0]app_rd_data_valid_1;
  wire calib_cmd_wren;
  wire [1:0]calib_sel;
  wire calib_wrdata_en;
  wire [1:0]ddr_ck_out;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire freq_refclk;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire [0:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire ififo_rst_reg0;
  wire ififo_rst_reg0_1;
  wire in0;
  wire init_complete_r1_timing_reg;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire [0:0]\mcGo_r_reg[15]_0 ;
  wire [0:0]mcGo_w;
  wire [3:0]mc_address;
  wire [0:0]mc_cas_n;
  wire mc_wrdata_en;
  wire [15:0]mem_dq_in;
  wire [40:0]mem_dq_out;
  wire [17:0]mem_dq_ts;
  wire [1:0]mem_dqs_in;
  wire [3:0]mem_out;
  wire mem_refclk;
  wire mux_cmd_wren;
  wire mux_wrdata_en;
  wire \my_empty_reg[0] ;
  wire \my_empty_reg[0]_0 ;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[1]_2 ;
  wire \my_empty_reg[4] ;
  wire \my_empty_reg[4]_rep__0 ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [3:0]\my_empty_reg[7]_10 ;
  wire [7:0]\my_empty_reg[7]_11 ;
  wire [3:0]\my_empty_reg[7]_12 ;
  wire [3:0]\my_empty_reg[7]_13 ;
  wire [3:0]\my_empty_reg[7]_14 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire [3:0]\my_empty_reg[7]_7 ;
  wire [3:0]\my_empty_reg[7]_8 ;
  wire [3:0]\my_empty_reg[7]_9 ;
  wire ofifo_rst_reg0;
  wire ofifo_rst_reg0_2;
  wire [1:0]out;
  wire out_dqs_0;
  wire out_dqs_1;
  wire out_fifo;
  wire [15:1]p_0_in;
  wire p_1_in;
  wire phy_ctl_wr_i2;
  wire [38:0]phy_dout;
  wire phy_mc_cmd_full;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire phy_rddata_en;
  wire phy_read_calib;
  wire phy_write_calib;
  wire \pi_counter_read_val_reg[5] ;
  wire [5:0]\pi_counter_read_val_reg[5]_0 ;
  wire [1:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[2] ;
  wire \pi_dqs_found_lanes_r1_reg[2]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_2 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire \pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_2 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_3 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[3]_4 ;
  wire pll_locked;
  wire [8:0]\po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire \po_counter_read_val_reg[8]_10 ;
  wire \po_counter_read_val_reg[8]_11 ;
  wire \po_counter_read_val_reg[8]_12 ;
  wire \po_counter_read_val_reg[8]_13 ;
  wire \po_counter_read_val_reg[8]_2 ;
  wire \po_counter_read_val_reg[8]_3 ;
  wire \po_counter_read_val_reg[8]_4 ;
  wire \po_counter_read_val_reg[8]_5 ;
  wire \po_counter_read_val_reg[8]_6 ;
  wire \po_counter_read_val_reg[8]_7 ;
  wire \po_counter_read_val_reg[8]_8 ;
  wire \po_counter_read_val_reg[8]_9 ;
  wire \rd_ptr_reg[0] ;
  wire \rd_ptr_reg[0]_0 ;
  wire \rd_ptr_reg[0]_1 ;
  wire \rd_ptr_reg[1] ;
  wire \rd_ptr_reg[1]_0 ;
  wire \rd_ptr_reg[1]_1 ;
  wire \rd_ptr_reg[2] ;
  wire \rd_ptr_reg[2]_0 ;
  wire \rd_ptr_reg[2]_1 ;
  wire \rd_ptr_reg[3] ;
  wire \rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg[3]_1 ;
  wire [2:0]\rd_ptr_reg[3]_10 ;
  wire [3:0]\rd_ptr_reg[3]_11 ;
  wire [3:0]\rd_ptr_reg[3]_12 ;
  wire [35:0]\rd_ptr_reg[3]_2 ;
  wire [3:0]\rd_ptr_reg[3]_3 ;
  wire [3:0]\rd_ptr_reg[3]_4 ;
  wire [2:0]\rd_ptr_reg[3]_5 ;
  wire [3:0]\rd_ptr_reg[3]_6 ;
  wire [3:0]\rd_ptr_reg[3]_7 ;
  wire [7:0]\rd_ptr_reg[3]_8 ;
  wire [5:0]\rd_ptr_reg[3]_9 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire [0:0]\read_fifo.tail_r_reg ;
  wire ref_dll_lock;
  wire sync_pulse;
  wire ts_dqs_0;
  wire ts_dqs_1;
  wire wr_en;
  wire wr_en_2;
  wire wr_en_3;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire [3:0]\wr_ptr_reg[3] ;
  wire [3:0]\wr_ptr_reg[3]_0 ;
  wire [3:0]\wr_ptr_reg[3]_1 ;
  wire \wr_ptr_timing_reg[0] ;
  wire \wr_ptr_timing_reg[0]_0 ;
  wire \wr_ptr_timing_reg[0]_1 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_4lanes \ddr_phy_4lanes_0.u_ddr_phy_4lanes 
       (.A_rst_primitives_reg_0(A_rst_primitives_reg),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_3(A_rst_primitives_reg_2),
        .CLK(CLK),
        .CLKB0(CLKB0),
        .CLKB0_4(CLKB0_4),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .D(mcGo_w),
        .D0(D0),
        .D1(D1),
        .D2(D2),
        .D3(D3),
        .D4(D4),
        .D5(D5),
        .D6(D6),
        .D7(D7),
        .D8(D8),
        .D9(D9),
        .LD0(LD0),
        .LD0_0(LD0_0),
        .Q(Q),
        .RST0(RST0),
        .SR(SR),
        .app_rd_data(app_rd_data),
        .\app_rd_data[112] (\app_rd_data[112] ),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rd_data_valid_0(app_rd_data_valid_0),
        .app_rd_data_valid_1(app_rd_data_valid_1),
        .calib_cmd_wren(calib_cmd_wren),
        .calib_sel(calib_sel),
        .calib_wrdata_en(calib_wrdata_en),
        .ddr_ck_out(ddr_ck_out),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg0 (\gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg0 (\gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg0 (\gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg0 (\gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg0 (\gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg0 (\gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg0 (\gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg0 (\gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg0 (\gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg0 (\gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg0 (\gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg0 (\gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg0 (\gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg0 (\gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg0 (\gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg0 (\gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg0 (\gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg0 (\gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg0 (\gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg0 (\gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg0 (\gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg0 (\gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg0 (\gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg0 (\gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg0 (\gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg0 (\gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg0 (\gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg0 (\gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg0 (\gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg0 (\gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg0 (\gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg0 (\gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg0 (\gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg0 (\gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg0 (\gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg0 (\gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg0 (\gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg0 (\gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg0 (\gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg0 (\gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg0 (\gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg0 (\gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg0 (\gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg0 (\gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg0 (\gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg0 (\gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg0 (\gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg0 (\gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg0 (\gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg0 (\gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg0 (\gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg0 (\gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg0 (\gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg0 (\gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg0 (\gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg0 (\gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg0 (\gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg0 (\gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg0 (\gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg0 (\gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg0 (\gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg0 (\gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg0 (\gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg0 (\gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(idelay_ld_rst),
        .ififo_rst_reg0(ififo_rst_reg0),
        .ififo_rst_reg0_1(ififo_rst_reg0_1),
        .in0(in0),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq ),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq_0 ),
        .mc_address(mc_address),
        .mc_cas_n(mc_cas_n),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_dq_in(mem_dq_in),
        .mem_dq_out(mem_dq_out),
        .mem_dq_ts(mem_dq_ts),
        .mem_dqs_in(mem_dqs_in),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .mux_cmd_wren(mux_cmd_wren),
        .mux_wrdata_en(mux_wrdata_en),
        .\my_empty_reg[0] (\my_empty_reg[0] ),
        .\my_empty_reg[0]_0 (\my_empty_reg[0]_0 ),
        .\my_empty_reg[1] (\my_empty_reg[1] ),
        .\my_empty_reg[1]_0 (\my_empty_reg[1]_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1]_1 ),
        .\my_empty_reg[1]_2 (\my_empty_reg[1]_2 ),
        .\my_empty_reg[4] (\my_empty_reg[4] ),
        .\my_empty_reg[4]_rep__0 (\my_empty_reg[4]_rep__0 ),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ),
        .\my_empty_reg[7]_10 (\my_empty_reg[7]_10 ),
        .\my_empty_reg[7]_11 (\my_empty_reg[7]_11 ),
        .\my_empty_reg[7]_12 (\my_empty_reg[7]_12 ),
        .\my_empty_reg[7]_13 (\my_empty_reg[7]_13 ),
        .\my_empty_reg[7]_14 (\my_empty_reg[7]_14 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_3 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_4 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_5 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_6 ),
        .\my_empty_reg[7]_7 (\my_empty_reg[7]_7 ),
        .\my_empty_reg[7]_8 (\my_empty_reg[7]_8 ),
        .\my_empty_reg[7]_9 (\my_empty_reg[7]_9 ),
        .ofifo_rst_reg0(ofifo_rst_reg0),
        .ofifo_rst_reg0_2(ofifo_rst_reg0_2),
        .out(out),
        .out_dqs_0(out_dqs_0),
        .out_dqs_1(out_dqs_1),
        .out_fifo(out_fifo),
        .p_1_in(p_1_in),
        .phy_ctl_wr_i2(phy_ctl_wr_i2),
        .phy_dout(phy_dout),
        .phy_mc_cmd_full(phy_mc_cmd_full),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .phy_rddata_en(phy_rddata_en),
        .phy_read_calib(phy_read_calib),
        .phy_write_calib(phy_write_calib),
        .\pi_counter_read_val_reg[5]_0 (\pi_counter_read_val_reg[5] ),
        .\pi_counter_read_val_reg[5]_1 (\pi_counter_read_val_reg[5]_0 ),
        .pi_dqs_found_lanes(pi_dqs_found_lanes),
        .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[2] ),
        .\pi_dqs_found_lanes_r1_reg[2]_0 (\pi_dqs_found_lanes_r1_reg[2]_0 ),
        .\pi_dqs_found_lanes_r1_reg[2]_1 (\pi_dqs_found_lanes_r1_reg[2]_1 ),
        .\pi_dqs_found_lanes_r1_reg[2]_2 (\pi_dqs_found_lanes_r1_reg[2]_2 ),
        .\pi_dqs_found_lanes_r1_reg[2]_3 (\pi_dqs_found_lanes_r1_reg[2]_3 ),
        .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] ),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .\pi_dqs_found_lanes_r1_reg[3]_1 (\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .\pi_dqs_found_lanes_r1_reg[3]_2 (\pi_dqs_found_lanes_r1_reg[3]_2 ),
        .\pi_dqs_found_lanes_r1_reg[3]_3 (\pi_dqs_found_lanes_r1_reg[3]_3 ),
        .\pi_dqs_found_lanes_r1_reg[3]_4 (\pi_dqs_found_lanes_r1_reg[3]_4 ),
        .pll_locked(pll_locked),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8] ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_0 ),
        .\po_counter_read_val_reg[8]_10 (\po_counter_read_val_reg[8]_9 ),
        .\po_counter_read_val_reg[8]_11 (\po_counter_read_val_reg[8]_10 ),
        .\po_counter_read_val_reg[8]_12 (\po_counter_read_val_reg[8]_11 ),
        .\po_counter_read_val_reg[8]_13 (\po_counter_read_val_reg[8]_12 ),
        .\po_counter_read_val_reg[8]_14 (\po_counter_read_val_reg[8]_13 ),
        .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_1 ),
        .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_2 ),
        .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_3 ),
        .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_4 ),
        .\po_counter_read_val_reg[8]_6 (\po_counter_read_val_reg[8]_5 ),
        .\po_counter_read_val_reg[8]_7 (\po_counter_read_val_reg[8]_6 ),
        .\po_counter_read_val_reg[8]_8 (\po_counter_read_val_reg[8]_7 ),
        .\po_counter_read_val_reg[8]_9 (\po_counter_read_val_reg[8]_8 ),
        .\rd_ptr_reg[0] (\rd_ptr_reg[0] ),
        .\rd_ptr_reg[0]_0 (\rd_ptr_reg[0]_0 ),
        .\rd_ptr_reg[0]_1 (\rd_ptr_reg[0]_1 ),
        .\rd_ptr_reg[1] (\rd_ptr_reg[1] ),
        .\rd_ptr_reg[1]_0 (\rd_ptr_reg[1]_0 ),
        .\rd_ptr_reg[1]_1 (\rd_ptr_reg[1]_1 ),
        .\rd_ptr_reg[2] (\rd_ptr_reg[2] ),
        .\rd_ptr_reg[2]_0 (\rd_ptr_reg[2]_0 ),
        .\rd_ptr_reg[2]_1 (\rd_ptr_reg[2]_1 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3] ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ),
        .\rd_ptr_reg[3]_1 (\rd_ptr_reg[3]_1 ),
        .\rd_ptr_reg[3]_10 (\rd_ptr_reg[3]_10 ),
        .\rd_ptr_reg[3]_11 (\rd_ptr_reg[3]_11 ),
        .\rd_ptr_reg[3]_12 (\rd_ptr_reg[3]_12 ),
        .\rd_ptr_reg[3]_2 (\rd_ptr_reg[3]_2 ),
        .\rd_ptr_reg[3]_3 (\rd_ptr_reg[3]_3 ),
        .\rd_ptr_reg[3]_4 (\rd_ptr_reg[3]_4 ),
        .\rd_ptr_reg[3]_5 (\rd_ptr_reg[3]_5 ),
        .\rd_ptr_reg[3]_6 (\rd_ptr_reg[3]_6 ),
        .\rd_ptr_reg[3]_7 (\rd_ptr_reg[3]_7 ),
        .\rd_ptr_reg[3]_8 (\rd_ptr_reg[3]_8 ),
        .\rd_ptr_reg[3]_9 (\rd_ptr_reg[3]_9 ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .\read_fifo.tail_r_reg (\read_fifo.tail_r_reg ),
        .ref_dll_lock(ref_dll_lock),
        .sync_pulse(sync_pulse),
        .ts_dqs_0(ts_dqs_0),
        .ts_dqs_1(ts_dqs_1),
        .wr_en(wr_en),
        .wr_en_2(wr_en_2),
        .wr_en_3(wr_en_3),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0]_0 ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_reg[3] (\wr_ptr_reg[3] ),
        .\wr_ptr_reg[3]_0 (\wr_ptr_reg[3]_0 ),
        .\wr_ptr_reg[3]_1 (\wr_ptr_reg[3]_1 ),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0] ),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0]_0 ),
        .\wr_ptr_timing_reg[0]_1 (\wr_ptr_timing_reg[0]_1 ));
  FDRE \mcGo_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mcGo_w),
        .Q(p_0_in[1]),
        .R(SR));
  FDRE \mcGo_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[10]),
        .Q(p_0_in[11]),
        .R(SR));
  FDRE \mcGo_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[11]),
        .Q(p_0_in[12]),
        .R(SR));
  FDRE \mcGo_r_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[12]),
        .Q(p_0_in[13]),
        .R(SR));
  FDRE \mcGo_r_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[13]),
        .Q(p_0_in[14]),
        .R(SR));
  FDRE \mcGo_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[14]),
        .Q(p_0_in[15]),
        .R(SR));
  FDRE \mcGo_r_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[15]),
        .Q(\mcGo_r_reg[15]_0 ),
        .R(SR));
  FDRE \mcGo_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(p_0_in[2]),
        .R(SR));
  FDRE \mcGo_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(p_0_in[3]),
        .R(SR));
  FDRE \mcGo_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(p_0_in[4]),
        .R(SR));
  FDRE \mcGo_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[4]),
        .Q(p_0_in[5]),
        .R(SR));
  FDRE \mcGo_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[5]),
        .Q(p_0_in[6]),
        .R(SR));
  FDRE \mcGo_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[6]),
        .Q(p_0_in[7]),
        .R(SR));
  FDRE \mcGo_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[7]),
        .Q(p_0_in[8]),
        .R(SR));
  FDRE \mcGo_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[8]),
        .Q(p_0_in[9]),
        .R(SR));
  FDRE \mcGo_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[9]),
        .Q(p_0_in[10]),
        .R(SR));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_mc_phy_wrapper
   (A_rst_primitives,
    \rd_ptr_reg[0] ,
    \rd_ptr_reg[1] ,
    \rd_ptr_reg[2] ,
    \rd_ptr_reg[3] ,
    out,
    A_rst_primitives_reg,
    pi_dqs_found_lanes,
    \rd_ptr_reg[0]_0 ,
    \rd_ptr_reg[1]_0 ,
    \rd_ptr_reg[2]_0 ,
    \rd_ptr_reg[3]_0 ,
    \rd_ptr_timing_reg[1] ,
    A_rst_primitives_reg_0,
    \rd_ptr_reg[0]_1 ,
    \rd_ptr_reg[1]_1 ,
    \rd_ptr_reg[2]_1 ,
    \rd_ptr_reg[3]_1 ,
    phy_mc_ctl_full,
    ref_dll_lock,
    idelay_ld_rst,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_reset_n,
    ddr3_dm,
    ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    ddr_ck_out,
    \my_empty_reg[1] ,
    \my_empty_reg[1]_0 ,
    init_complete_r1_timing_reg,
    \my_empty_reg[4] ,
    \my_empty_reg[1]_1 ,
    \my_empty_reg[1]_2 ,
    \my_empty_reg[5] ,
    \my_empty_reg[3] ,
    \my_empty_reg[5]_0 ,
    \my_empty_reg[3]_0 ,
    \my_empty_reg[5]_1 ,
    \my_empty_reg[3]_1 ,
    app_rd_data_valid,
    \my_empty_reg[0] ,
    \my_empty_reg[0]_0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    Q,
    app_rd_data,
    \gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    \pi_counter_read_val_reg[5] ,
    \pi_counter_read_val_reg[5]_0 ,
    phy_rddata_en,
    A_rst_primitives_reg_1,
    phy_mc_data_full,
    wr_en,
    wr_en_2,
    phy_mc_cmd_full,
    wr_en_3,
    \rd_ptr_reg[3]_2 ,
    \wr_ptr_reg[3] ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_reg[3]_1 ,
    \my_empty_reg[4]_rep__0 ,
    \po_counter_read_val_reg[8] ,
    \mcGo_r_reg[15] ,
    p_1_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \po_counter_read_val_reg[8]_2 ,
    \po_counter_read_val_reg[8]_3 ,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    CLK,
    \rd_ptr_reg[3]_3 ,
    \rd_ptr_reg[3]_4 ,
    \rd_ptr_reg[3]_5 ,
    \rd_ptr_reg[3]_6 ,
    \rd_ptr_reg[3]_7 ,
    \rd_ptr_reg[3]_8 ,
    \rd_ptr_reg[3]_9 ,
    \rd_ptr_reg[3]_10 ,
    \rd_ptr_reg[3]_11 ,
    \rd_ptr_reg[3]_12 ,
    \input_[9].iserdes_dq_.iserdesdq ,
    idelay_inc,
    LD0,
    CLKB0,
    \pi_dqs_found_lanes_r1_reg[2] ,
    \pi_dqs_found_lanes_r1_reg[2]_0 ,
    \pi_dqs_found_lanes_r1_reg[2]_1 ,
    \pi_dqs_found_lanes_r1_reg[2]_2 ,
    \pi_dqs_found_lanes_r1_reg[2]_3 ,
    COUNTERLOADVAL,
    \po_counter_read_val_reg[8]_4 ,
    \po_counter_read_val_reg[8]_5 ,
    \po_counter_read_val_reg[8]_6 ,
    D0,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    D9,
    ififo_rst_reg0,
    ofifo_rst_reg0,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    LD0_0,
    CLKB0_4,
    \pi_dqs_found_lanes_r1_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    \pi_dqs_found_lanes_r1_reg[3]_1 ,
    \pi_dqs_found_lanes_r1_reg[3]_2 ,
    \pi_dqs_found_lanes_r1_reg[3]_3 ,
    \pi_dqs_found_lanes_r1_reg[3]_4 ,
    \po_counter_read_val_reg[8]_7 ,
    \po_counter_read_val_reg[8]_8 ,
    \po_counter_read_val_reg[8]_9 ,
    D1,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    ififo_rst_reg0_1,
    ofifo_rst_reg0_2,
    pll_locked,
    phy_read_calib,
    in0,
    phy_write_calib,
    RST0,
    SR,
    mux_reset_n,
    UNCONN_IN,
    UNCONN_IN_0,
    UNCONN_IN_1,
    phy_ctl_wr_i1_reg_0,
    \po_counter_read_val_reg[8]_10 ,
    \po_counter_read_val_reg[8]_11 ,
    \po_counter_read_val_reg[8]_12 ,
    \po_counter_read_val_reg[8]_13 ,
    \my_empty_reg[7]_7 ,
    \my_empty_reg[7]_8 ,
    \my_empty_reg[7]_9 ,
    \my_empty_reg[7]_10 ,
    \my_empty_reg[7]_11 ,
    \my_empty_reg[7]_12 ,
    \my_empty_reg[7]_13 ,
    \my_empty_reg[7]_14 ,
    \wr_ptr_timing_reg[0] ,
    calib_cmd_wren,
    \wr_ptr_timing_reg[0]_0 ,
    mem_out,
    app_rd_data_valid_0,
    mux_wrdata_en,
    mc_wrdata_en,
    \wr_ptr_timing_reg[0]_1 ,
    calib_wrdata_en,
    out_fifo,
    mux_cmd_wren,
    \my_full_reg[5] ,
    app_rd_data_valid_1,
    \read_fifo.tail_r_reg ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    mc_address,
    mc_cas_n,
    \rd_ptr_reg[0]_2 ,
    E,
    \wr_ptr_timing_reg[0]_2 ,
    \wr_ptr_timing_reg[0]_3 ,
    \wr_ptr_timing_reg[2] ,
    D,
    phy_dout,
    \app_rd_data[112] ,
    calib_sel,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] );
  output A_rst_primitives;
  output \rd_ptr_reg[0] ;
  output \rd_ptr_reg[1] ;
  output \rd_ptr_reg[2] ;
  output \rd_ptr_reg[3] ;
  output [1:0]out;
  output A_rst_primitives_reg;
  output [1:0]pi_dqs_found_lanes;
  output \rd_ptr_reg[0]_0 ;
  output \rd_ptr_reg[1]_0 ;
  output \rd_ptr_reg[2]_0 ;
  output \rd_ptr_reg[3]_0 ;
  output [1:0]\rd_ptr_timing_reg[1] ;
  output A_rst_primitives_reg_0;
  output \rd_ptr_reg[0]_1 ;
  output \rd_ptr_reg[1]_1 ;
  output \rd_ptr_reg[2]_1 ;
  output \rd_ptr_reg[3]_1 ;
  output phy_mc_ctl_full;
  output ref_dll_lock;
  output idelay_ld_rst;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output ddr3_reset_n;
  output [1:0]ddr3_dm;
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output [1:0]ddr_ck_out;
  output \my_empty_reg[1] ;
  output \my_empty_reg[1]_0 ;
  output init_complete_r1_timing_reg;
  output [0:0]\my_empty_reg[4] ;
  output \my_empty_reg[1]_1 ;
  output \my_empty_reg[1]_2 ;
  output \my_empty_reg[5] ;
  output \my_empty_reg[3] ;
  output \my_empty_reg[5]_0 ;
  output \my_empty_reg[3]_0 ;
  output \my_empty_reg[5]_1 ;
  output \my_empty_reg[3]_1 ;
  output app_rd_data_valid;
  output \my_empty_reg[0] ;
  output \my_empty_reg[0]_0 ;
  output \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  output [67:0]Q;
  output [127:0]app_rd_data;
  output \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  output \pi_counter_read_val_reg[5] ;
  output [5:0]\pi_counter_read_val_reg[5]_0 ;
  output phy_rddata_en;
  output A_rst_primitives_reg_1;
  output phy_mc_data_full;
  output wr_en;
  output wr_en_2;
  output phy_mc_cmd_full;
  output wr_en_3;
  output [35:0]\rd_ptr_reg[3]_2 ;
  output [3:0]\wr_ptr_reg[3] ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1] ;
  output [3:0]\wr_ptr_reg[3]_0 ;
  output [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_0 ;
  output [3:0]\wr_ptr_reg[3]_1 ;
  output \my_empty_reg[4]_rep__0 ;
  output [8:0]\po_counter_read_val_reg[8] ;
  output [0:0]\mcGo_r_reg[15] ;
  output p_1_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  inout [15:0]ddr3_dq;
  inout [1:0]ddr3_dqs_p;
  inout [1:0]ddr3_dqs_n;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input \po_counter_read_val_reg[8]_2 ;
  input \po_counter_read_val_reg[8]_3 ;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input CLK;
  input [3:0]\rd_ptr_reg[3]_3 ;
  input [3:0]\rd_ptr_reg[3]_4 ;
  input [2:0]\rd_ptr_reg[3]_5 ;
  input [3:0]\rd_ptr_reg[3]_6 ;
  input [3:0]\rd_ptr_reg[3]_7 ;
  input [7:0]\rd_ptr_reg[3]_8 ;
  input [5:0]\rd_ptr_reg[3]_9 ;
  input [2:0]\rd_ptr_reg[3]_10 ;
  input [3:0]\rd_ptr_reg[3]_11 ;
  input [3:0]\rd_ptr_reg[3]_12 ;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input idelay_inc;
  input LD0;
  input CLKB0;
  input \pi_dqs_found_lanes_r1_reg[2] ;
  input \pi_dqs_found_lanes_r1_reg[2]_0 ;
  input \pi_dqs_found_lanes_r1_reg[2]_1 ;
  input \pi_dqs_found_lanes_r1_reg[2]_2 ;
  input \pi_dqs_found_lanes_r1_reg[2]_3 ;
  input [5:0]COUNTERLOADVAL;
  input \po_counter_read_val_reg[8]_4 ;
  input \po_counter_read_val_reg[8]_5 ;
  input \po_counter_read_val_reg[8]_6 ;
  input [7:0]D0;
  input [7:0]D2;
  input [7:0]D3;
  input [7:0]D4;
  input [7:0]D5;
  input [7:0]D6;
  input [7:0]D7;
  input [7:0]D8;
  input [7:0]D9;
  input ififo_rst_reg0;
  input ofifo_rst_reg0;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input LD0_0;
  input CLKB0_4;
  input \pi_dqs_found_lanes_r1_reg[3] ;
  input \pi_dqs_found_lanes_r1_reg[3]_0 ;
  input \pi_dqs_found_lanes_r1_reg[3]_1 ;
  input \pi_dqs_found_lanes_r1_reg[3]_2 ;
  input \pi_dqs_found_lanes_r1_reg[3]_3 ;
  input [5:0]\pi_dqs_found_lanes_r1_reg[3]_4 ;
  input \po_counter_read_val_reg[8]_7 ;
  input \po_counter_read_val_reg[8]_8 ;
  input \po_counter_read_val_reg[8]_9 ;
  input [7:0]D1;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input ififo_rst_reg0_1;
  input ofifo_rst_reg0_2;
  input pll_locked;
  input phy_read_calib;
  input in0;
  input phy_write_calib;
  input RST0;
  input [0:0]SR;
  input mux_reset_n;
  input UNCONN_IN;
  input UNCONN_IN_0;
  input UNCONN_IN_1;
  input phy_ctl_wr_i1_reg_0;
  input \po_counter_read_val_reg[8]_10 ;
  input \po_counter_read_val_reg[8]_11 ;
  input \po_counter_read_val_reg[8]_12 ;
  input \po_counter_read_val_reg[8]_13 ;
  input [3:0]\my_empty_reg[7]_7 ;
  input [3:0]\my_empty_reg[7]_8 ;
  input [3:0]\my_empty_reg[7]_9 ;
  input [3:0]\my_empty_reg[7]_10 ;
  input [7:0]\my_empty_reg[7]_11 ;
  input [3:0]\my_empty_reg[7]_12 ;
  input [3:0]\my_empty_reg[7]_13 ;
  input [3:0]\my_empty_reg[7]_14 ;
  input \wr_ptr_timing_reg[0] ;
  input calib_cmd_wren;
  input \wr_ptr_timing_reg[0]_0 ;
  input [3:0]mem_out;
  input app_rd_data_valid_0;
  input mux_wrdata_en;
  input mc_wrdata_en;
  input \wr_ptr_timing_reg[0]_1 ;
  input calib_wrdata_en;
  input out_fifo;
  input mux_cmd_wren;
  input \my_full_reg[5] ;
  input [0:0]app_rd_data_valid_1;
  input [0:0]\read_fifo.tail_r_reg ;
  input [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input [3:0]mc_address;
  input [0:0]mc_cas_n;
  input \rd_ptr_reg[0]_2 ;
  input [0:0]E;
  input [0:0]\wr_ptr_timing_reg[0]_2 ;
  input [0:0]\wr_ptr_timing_reg[0]_3 ;
  input [0:0]\wr_ptr_timing_reg[2] ;
  input [10:0]D;
  input [38:0]phy_dout;
  input [63:0]\app_rd_data[112] ;
  input [1:0]calib_sel;
  input [0:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire CLK;
  wire CLKB0;
  wire CLKB0_4;
  wire [5:0]COUNTERLOADVAL;
  wire [10:0]D;
  wire [7:0]D0;
  wire [7:0]D1;
  wire [7:0]D2;
  wire [7:0]D3;
  wire [7:0]D4;
  wire [7:0]D5;
  wire [7:0]D6;
  wire [7:0]D7;
  wire [7:0]D8;
  wire [7:0]D9;
  wire [0:0]E;
  wire LD0;
  wire LD0_0;
  wire [67:0]Q;
  wire RST0;
  wire [0:0]SR;
  wire UNCONN_IN;
  wire UNCONN_IN_0;
  wire UNCONN_IN_1;
  wire [127:0]app_rd_data;
  wire [63:0]\app_rd_data[112] ;
  wire app_rd_data_valid;
  wire app_rd_data_valid_0;
  wire [0:0]app_rd_data_valid_1;
  wire calib_cmd_wren;
  wire [1:0]calib_sel;
  wire calib_wrdata_en;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [1:0]ddr3_dm;
  wire [15:0]ddr3_dq;
  wire [1:0]ddr3_dqs_n;
  wire [1:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire freq_refclk;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire [0:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire ififo_rst_reg0;
  wire ififo_rst_reg0_1;
  wire in0;
  wire init_complete_r1_timing_reg;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire [0:0]\mcGo_r_reg[15] ;
  wire [3:0]mc_address;
  wire [0:0]mc_cas_n;
  wire mc_wrdata_en;
  wire [39:20]mem_dq_in;
  wire [45:0]mem_dq_out;
  wire [45:24]mem_dq_ts;
  wire [3:2]mem_dqs_in;
  wire [3:0]mem_out;
  wire mem_refclk;
  wire mux_cmd_wren;
  wire mux_reset_n;
  wire mux_wrdata_en;
  wire \my_empty_reg[0] ;
  wire \my_empty_reg[0]_0 ;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[1]_2 ;
  wire \my_empty_reg[3] ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[3]_1 ;
  wire [0:0]\my_empty_reg[4] ;
  wire \my_empty_reg[4]_rep__0 ;
  wire \my_empty_reg[5] ;
  wire \my_empty_reg[5]_0 ;
  wire \my_empty_reg[5]_1 ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [3:0]\my_empty_reg[7]_10 ;
  wire [7:0]\my_empty_reg[7]_11 ;
  wire [3:0]\my_empty_reg[7]_12 ;
  wire [3:0]\my_empty_reg[7]_13 ;
  wire [3:0]\my_empty_reg[7]_14 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire [3:0]\my_empty_reg[7]_7 ;
  wire [3:0]\my_empty_reg[7]_8 ;
  wire [3:0]\my_empty_reg[7]_9 ;
  wire \my_full_reg[5] ;
  wire ofifo_rst_reg0;
  wire ofifo_rst_reg0_2;
  wire [1:0]out;
  wire out_dqs_0;
  wire out_dqs_1;
  wire out_fifo;
  wire p_1_in;
  wire [24:0]phy_ctl_wd_i1;
  wire [24:0]phy_ctl_wd_i2;
  wire phy_ctl_wr_i1;
  wire phy_ctl_wr_i1_reg_0;
  wire phy_ctl_wr_i2;
  wire [38:0]phy_dout;
  wire phy_mc_cmd_full;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire phy_rddata_en;
  wire phy_read_calib;
  wire phy_write_calib;
  wire \pi_counter_read_val_reg[5] ;
  wire [5:0]\pi_counter_read_val_reg[5]_0 ;
  wire [1:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[2] ;
  wire \pi_dqs_found_lanes_r1_reg[2]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_2 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire \pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_2 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_3 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[3]_4 ;
  wire pll_locked;
  wire [8:0]\po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire \po_counter_read_val_reg[8]_10 ;
  wire \po_counter_read_val_reg[8]_11 ;
  wire \po_counter_read_val_reg[8]_12 ;
  wire \po_counter_read_val_reg[8]_13 ;
  wire \po_counter_read_val_reg[8]_2 ;
  wire \po_counter_read_val_reg[8]_3 ;
  wire \po_counter_read_val_reg[8]_4 ;
  wire \po_counter_read_val_reg[8]_5 ;
  wire \po_counter_read_val_reg[8]_6 ;
  wire \po_counter_read_val_reg[8]_7 ;
  wire \po_counter_read_val_reg[8]_8 ;
  wire \po_counter_read_val_reg[8]_9 ;
  wire \rd_ptr_reg[0] ;
  wire \rd_ptr_reg[0]_0 ;
  wire \rd_ptr_reg[0]_1 ;
  wire \rd_ptr_reg[0]_2 ;
  wire \rd_ptr_reg[1] ;
  wire \rd_ptr_reg[1]_0 ;
  wire \rd_ptr_reg[1]_1 ;
  wire \rd_ptr_reg[2] ;
  wire \rd_ptr_reg[2]_0 ;
  wire \rd_ptr_reg[2]_1 ;
  wire \rd_ptr_reg[3] ;
  wire \rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg[3]_1 ;
  wire [2:0]\rd_ptr_reg[3]_10 ;
  wire [3:0]\rd_ptr_reg[3]_11 ;
  wire [3:0]\rd_ptr_reg[3]_12 ;
  wire [35:0]\rd_ptr_reg[3]_2 ;
  wire [3:0]\rd_ptr_reg[3]_3 ;
  wire [3:0]\rd_ptr_reg[3]_4 ;
  wire [2:0]\rd_ptr_reg[3]_5 ;
  wire [3:0]\rd_ptr_reg[3]_6 ;
  wire [3:0]\rd_ptr_reg[3]_7 ;
  wire [7:0]\rd_ptr_reg[3]_8 ;
  wire [5:0]\rd_ptr_reg[3]_9 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire [0:0]\read_fifo.tail_r_reg ;
  wire ref_dll_lock;
  wire sync_pulse;
  wire ts_dqs_0;
  wire ts_dqs_1;
  wire wr_en;
  wire wr_en_2;
  wire wr_en_3;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire [3:0]\wr_ptr_reg[3] ;
  wire [3:0]\wr_ptr_reg[3]_0 ;
  wire [3:0]\wr_ptr_reg[3]_1 ;
  wire \wr_ptr_timing_reg[0] ;
  wire \wr_ptr_timing_reg[0]_0 ;
  wire \wr_ptr_timing_reg[0]_1 ;
  wire [0:0]\wr_ptr_timing_reg[0]_2 ;
  wire [0:0]\wr_ptr_timing_reg[0]_3 ;
  wire [0:0]\wr_ptr_timing_reg[2] ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf 
       (.I(mem_dq_out[22]),
        .O(ddr3_cke));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf 
       (.I(mem_dq_out[11]),
        .O(ddr3_odt));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[0].u_addr_obuf 
       (.I(mem_dq_out[17]),
        .O(ddr3_addr[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[10].u_addr_obuf 
       (.I(mem_dq_out[21]),
        .O(ddr3_addr[10]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[11].u_addr_obuf 
       (.I(mem_dq_out[1]),
        .O(ddr3_addr[11]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[12].u_addr_obuf 
       (.I(mem_dq_out[16]),
        .O(ddr3_addr[12]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[13].u_addr_obuf 
       (.I(mem_dq_out[3]),
        .O(ddr3_addr[13]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[1].u_addr_obuf 
       (.I(mem_dq_out[4]),
        .O(ddr3_addr[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[2].u_addr_obuf 
       (.I(mem_dq_out[0]),
        .O(ddr3_addr[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[3].u_addr_obuf 
       (.I(mem_dq_out[15]),
        .O(ddr3_addr[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[4].u_addr_obuf 
       (.I(mem_dq_out[9]),
        .O(ddr3_addr[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[5].u_addr_obuf 
       (.I(mem_dq_out[8]),
        .O(ddr3_addr[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[6].u_addr_obuf 
       (.I(mem_dq_out[5]),
        .O(ddr3_addr[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[7].u_addr_obuf 
       (.I(mem_dq_out[7]),
        .O(ddr3_addr[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[8].u_addr_obuf 
       (.I(mem_dq_out[2]),
        .O(ddr3_addr[8]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[9].u_addr_obuf 
       (.I(mem_dq_out[6]),
        .O(ddr3_addr[9]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_bank_obuf[0].u_bank_obuf 
       (.I(mem_dq_out[20]),
        .O(ddr3_ba[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_bank_obuf[1].u_bank_obuf 
       (.I(mem_dq_out[13]),
        .O(ddr3_ba[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_bank_obuf[2].u_bank_obuf 
       (.I(mem_dq_out[12]),
        .O(ddr3_ba[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf 
       (.I(mem_dq_out[14]),
        .O(ddr3_cs_n));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[0].u_dm_obuf 
       (.I(mem_dq_out[32]),
        .O(ddr3_dm[0]),
        .T(mem_dq_ts[32]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[1].u_dm_obuf 
       (.I(mem_dq_out[44]),
        .O(ddr3_dm[1]),
        .T(mem_dq_ts[44]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[0].u_iobuf_dq 
       (.I(mem_dq_out[33]),
        .IO(ddr3_dq[0]),
        .O(mem_dq_in[29]),
        .T(mem_dq_ts[33]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[10].u_iobuf_dq 
       (.I(mem_dq_out[45]),
        .IO(ddr3_dq[10]),
        .O(mem_dq_in[39]),
        .T(mem_dq_ts[45]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[11].u_iobuf_dq 
       (.I(mem_dq_out[41]),
        .IO(ddr3_dq[11]),
        .O(mem_dq_in[35]),
        .T(mem_dq_ts[41]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[12].u_iobuf_dq 
       (.I(mem_dq_out[38]),
        .IO(ddr3_dq[12]),
        .O(mem_dq_in[32]),
        .T(mem_dq_ts[38]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[13].u_iobuf_dq 
       (.I(mem_dq_out[43]),
        .IO(ddr3_dq[13]),
        .O(mem_dq_in[37]),
        .T(mem_dq_ts[43]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[14].u_iobuf_dq 
       (.I(mem_dq_out[39]),
        .IO(ddr3_dq[14]),
        .O(mem_dq_in[33]),
        .T(mem_dq_ts[39]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[15].u_iobuf_dq 
       (.I(mem_dq_out[42]),
        .IO(ddr3_dq[15]),
        .O(mem_dq_in[36]),
        .T(mem_dq_ts[42]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[1].u_iobuf_dq 
       (.I(mem_dq_out[28]),
        .IO(ddr3_dq[1]),
        .O(mem_dq_in[24]),
        .T(mem_dq_ts[28]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[2].u_iobuf_dq 
       (.I(mem_dq_out[30]),
        .IO(ddr3_dq[2]),
        .O(mem_dq_in[26]),
        .T(mem_dq_ts[30]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[3].u_iobuf_dq 
       (.I(mem_dq_out[27]),
        .IO(ddr3_dq[3]),
        .O(mem_dq_in[23]),
        .T(mem_dq_ts[27]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[4].u_iobuf_dq 
       (.I(mem_dq_out[24]),
        .IO(ddr3_dq[4]),
        .O(mem_dq_in[20]),
        .T(mem_dq_ts[24]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[5].u_iobuf_dq 
       (.I(mem_dq_out[29]),
        .IO(ddr3_dq[5]),
        .O(mem_dq_in[25]),
        .T(mem_dq_ts[29]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[6].u_iobuf_dq 
       (.I(mem_dq_out[26]),
        .IO(ddr3_dq[6]),
        .O(mem_dq_in[22]),
        .T(mem_dq_ts[26]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[7].u_iobuf_dq 
       (.I(mem_dq_out[31]),
        .IO(ddr3_dq[7]),
        .O(mem_dq_in[27]),
        .T(mem_dq_ts[31]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[8].u_iobuf_dq 
       (.I(mem_dq_out[37]),
        .IO(ddr3_dq[8]),
        .O(mem_dq_in[31]),
        .T(mem_dq_ts[37]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dq_iobuf_default.gen_dq_iobuf[9].u_iobuf_dq 
       (.I(mem_dq_out[40]),
        .IO(ddr3_dq[9]),
        .O(mem_dq_in[34]),
        .T(mem_dq_ts[40]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs 
       (.I(out_dqs_0),
        .IBUFDISABLE(1'b0),
        .INTERMDISABLE(1'b0),
        .IO(ddr3_dqs_p[0]),
        .IOB(ddr3_dqs_n[0]),
        .O(mem_dqs_in[2]),
        .T(ts_dqs_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_ddr2_or_low_dqs_diff.u_iobuf_dqs 
       (.I(out_dqs_1),
        .IBUFDISABLE(1'b0),
        .INTERMDISABLE(1'b0),
        .IO(ddr3_dqs_p[1]),
        .IOB(ddr3_dqs_n[1]),
        .O(mem_dqs_in[3]),
        .T(ts_dqs_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_reset_obuf.u_reset_obuf 
       (.I(mux_reset_n),
        .O(ddr3_reset_n));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo \genblk24.phy_ctl_pre_fifo_0 
       (.CLK(CLK),
        .E(E),
        .UNCONN_IN(UNCONN_IN),
        .in0(in0),
        .mux_cmd_wren(mux_cmd_wren),
        .\my_empty_reg[3]_0 (\my_empty_reg[3] ),
        .\my_empty_reg[5]_0 (\my_empty_reg[5] ),
        .\my_full_reg[5]_0 (\my_full_reg[5] ),
        .\rd_ptr_timing_reg[0]_0 (\rd_ptr_reg[0]_2 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0 \genblk24.phy_ctl_pre_fifo_1 
       (.CLK(CLK),
        .UNCONN_IN(UNCONN_IN_0),
        .in0(in0),
        .mux_cmd_wren(mux_cmd_wren),
        .\my_empty_reg[3]_0 (\my_empty_reg[3]_0 ),
        .\my_empty_reg[5]_0 (\my_empty_reg[5]_0 ),
        .\my_full_reg[5]_0 (\my_full_reg[5] ),
        .\wr_ptr_timing_reg[0]_0 (\rd_ptr_reg[0]_2 ),
        .\wr_ptr_timing_reg[0]_1 (\wr_ptr_timing_reg[0]_2 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_6 \genblk24.phy_ctl_pre_fifo_2 
       (.CLK(CLK),
        .SR(SR),
        .UNCONN_IN(UNCONN_IN_1),
        .in0(in0),
        .mux_cmd_wren(mux_cmd_wren),
        .\my_empty_reg[3]_0 (\my_empty_reg[3]_1 ),
        .\my_empty_reg[5]_0 (\my_empty_reg[5]_1 ),
        .\my_full_reg[5]_0 (\my_full_reg[5] ),
        .\rd_ptr_reg[0]_0 (\rd_ptr_reg[0]_2 ),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0]_3 ),
        .\wr_ptr_timing_reg[2]_0 (\wr_ptr_timing_reg[2] ));
  FDRE \phy_ctl_wd_i1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[0]),
        .Q(phy_ctl_wd_i1[0]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(phy_ctl_wd_i1[17]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[4]),
        .Q(phy_ctl_wd_i1[18]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[5]),
        .Q(phy_ctl_wd_i1[19]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[1]),
        .Q(phy_ctl_wd_i1[1]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[6]),
        .Q(phy_ctl_wd_i1[20]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[7]),
        .Q(phy_ctl_wd_i1[21]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[8]),
        .Q(phy_ctl_wd_i1[22]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[9]),
        .Q(phy_ctl_wd_i1[23]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[10]),
        .Q(phy_ctl_wd_i1[24]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(D[2]),
        .Q(phy_ctl_wd_i1[2]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[0]),
        .Q(phy_ctl_wd_i2[0]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[17]),
        .Q(phy_ctl_wd_i2[17]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[18]),
        .Q(phy_ctl_wd_i2[18]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[19]),
        .Q(phy_ctl_wd_i2[19]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[1]),
        .Q(phy_ctl_wd_i2[1]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[20]),
        .Q(phy_ctl_wd_i2[20]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[21]),
        .Q(phy_ctl_wd_i2[21]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[22]),
        .Q(phy_ctl_wd_i2[22]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[23]),
        .Q(phy_ctl_wd_i2[23]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[24]),
        .Q(phy_ctl_wd_i2[24]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[2]),
        .Q(phy_ctl_wd_i2[2]),
        .R(1'b0));
  FDRE phy_ctl_wr_i1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wr_i1_reg_0),
        .Q(phy_ctl_wr_i1),
        .R(1'b0));
  FDRE phy_ctl_wr_i2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_wr_i1),
        .Q(phy_ctl_wr_i2),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    u_cas_n_obuf
       (.I(mem_dq_out[23]),
        .O(ddr3_cas_n));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_mc_phy u_ddr_mc_phy
       (.A_rst_primitives_reg(A_rst_primitives),
        .A_rst_primitives_reg_0(A_rst_primitives_reg),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_1),
        .CLK(CLK),
        .CLKB0(CLKB0),
        .CLKB0_4(CLKB0_4),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .D0(D0),
        .D1(D1),
        .D2(D2),
        .D3(D3),
        .D4(D4),
        .D5(D5),
        .D6(D6),
        .D7(D7),
        .D8(D8),
        .D9(D9),
        .LD0(LD0),
        .LD0_0(LD0_0),
        .Q({phy_ctl_wd_i2[24:17],phy_ctl_wd_i2[2:0]}),
        .RST0(RST0),
        .SR(SR),
        .app_rd_data(app_rd_data),
        .\app_rd_data[112] (\app_rd_data[112] ),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rd_data_valid_0(app_rd_data_valid_0),
        .app_rd_data_valid_1(app_rd_data_valid_1),
        .calib_cmd_wren(calib_cmd_wren),
        .calib_sel(calib_sel),
        .calib_wrdata_en(calib_wrdata_en),
        .ddr_ck_out(ddr_ck_out),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (Q),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg0 (\gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg0 (\gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg0 (\gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg0 (\gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg0 (\gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg0 (\gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg0 (\gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg0 (\gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg0 (\gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg0 (\gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg0 (\gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg0 (\gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg0 (\gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg0 (\gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg0 (\gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg0 (\gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg0 (\gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg0 (\gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg0 (\gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg0 (\gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg0 (\gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg0 (\gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg0 (\gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg0 (\gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg0 (\gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg0 (\gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg0 (\gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg0 (\gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg0 (\gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg0 (\gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg0 (\gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg0 (\gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg0 (\gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg0 (\gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg0 (\gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg0 (\gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg0 (\gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg0 (\gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg0 (\gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg0 (\gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg0 (\gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg0 (\gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg0 (\gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg0 (\gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg0 (\gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg0 (\gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg0 (\gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg0 (\gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg0 (\gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg0 (\gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg0 (\gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg0 (\gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg0 (\gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg0 (\gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg0 (\gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg0 (\gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg0 (\gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg0 (\gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg0 (\gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg0 (\gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg0 (\gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg0 (\gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg0 (\gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg0 (\gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(idelay_ld_rst),
        .ififo_rst_reg0(ififo_rst_reg0),
        .ififo_rst_reg0_1(ififo_rst_reg0_1),
        .in0(in0),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq ),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq_0 ),
        .\mcGo_r_reg[15]_0 (\mcGo_r_reg[15] ),
        .mc_address(mc_address),
        .mc_cas_n(mc_cas_n),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_dq_in({mem_dq_in[39],mem_dq_in[37:31],mem_dq_in[29],mem_dq_in[27:22],mem_dq_in[20]}),
        .mem_dq_out({mem_dq_out[45:37],mem_dq_out[33:26],mem_dq_out[24:11],mem_dq_out[9:0]}),
        .mem_dq_ts({mem_dq_ts[45:37],mem_dq_ts[33:26],mem_dq_ts[24]}),
        .mem_dqs_in(mem_dqs_in),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .mux_cmd_wren(mux_cmd_wren),
        .mux_wrdata_en(mux_wrdata_en),
        .\my_empty_reg[0] (\my_empty_reg[0] ),
        .\my_empty_reg[0]_0 (\my_empty_reg[0]_0 ),
        .\my_empty_reg[1] (\my_empty_reg[1] ),
        .\my_empty_reg[1]_0 (\my_empty_reg[1]_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1]_1 ),
        .\my_empty_reg[1]_2 (\my_empty_reg[1]_2 ),
        .\my_empty_reg[4] (\my_empty_reg[4] ),
        .\my_empty_reg[4]_rep__0 (\my_empty_reg[4]_rep__0 ),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ),
        .\my_empty_reg[7]_10 (\my_empty_reg[7]_10 ),
        .\my_empty_reg[7]_11 (\my_empty_reg[7]_11 ),
        .\my_empty_reg[7]_12 (\my_empty_reg[7]_12 ),
        .\my_empty_reg[7]_13 (\my_empty_reg[7]_13 ),
        .\my_empty_reg[7]_14 (\my_empty_reg[7]_14 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_3 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_4 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_5 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_6 ),
        .\my_empty_reg[7]_7 (\my_empty_reg[7]_7 ),
        .\my_empty_reg[7]_8 (\my_empty_reg[7]_8 ),
        .\my_empty_reg[7]_9 (\my_empty_reg[7]_9 ),
        .ofifo_rst_reg0(ofifo_rst_reg0),
        .ofifo_rst_reg0_2(ofifo_rst_reg0_2),
        .out(out),
        .out_dqs_0(out_dqs_0),
        .out_dqs_1(out_dqs_1),
        .out_fifo(out_fifo),
        .p_1_in(p_1_in),
        .phy_ctl_wr_i2(phy_ctl_wr_i2),
        .phy_dout(phy_dout),
        .phy_mc_cmd_full(phy_mc_cmd_full),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .phy_rddata_en(phy_rddata_en),
        .phy_read_calib(phy_read_calib),
        .phy_write_calib(phy_write_calib),
        .\pi_counter_read_val_reg[5] (\pi_counter_read_val_reg[5] ),
        .\pi_counter_read_val_reg[5]_0 (\pi_counter_read_val_reg[5]_0 ),
        .pi_dqs_found_lanes(pi_dqs_found_lanes),
        .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[2] ),
        .\pi_dqs_found_lanes_r1_reg[2]_0 (\pi_dqs_found_lanes_r1_reg[2]_0 ),
        .\pi_dqs_found_lanes_r1_reg[2]_1 (\pi_dqs_found_lanes_r1_reg[2]_1 ),
        .\pi_dqs_found_lanes_r1_reg[2]_2 (\pi_dqs_found_lanes_r1_reg[2]_2 ),
        .\pi_dqs_found_lanes_r1_reg[2]_3 (\pi_dqs_found_lanes_r1_reg[2]_3 ),
        .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] ),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .\pi_dqs_found_lanes_r1_reg[3]_1 (\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .\pi_dqs_found_lanes_r1_reg[3]_2 (\pi_dqs_found_lanes_r1_reg[3]_2 ),
        .\pi_dqs_found_lanes_r1_reg[3]_3 (\pi_dqs_found_lanes_r1_reg[3]_3 ),
        .\pi_dqs_found_lanes_r1_reg[3]_4 (\pi_dqs_found_lanes_r1_reg[3]_4 ),
        .pll_locked(pll_locked),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8] ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_0 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_1 ),
        .\po_counter_read_val_reg[8]_10 (\po_counter_read_val_reg[8]_10 ),
        .\po_counter_read_val_reg[8]_11 (\po_counter_read_val_reg[8]_11 ),
        .\po_counter_read_val_reg[8]_12 (\po_counter_read_val_reg[8]_12 ),
        .\po_counter_read_val_reg[8]_13 (\po_counter_read_val_reg[8]_13 ),
        .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_2 ),
        .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_3 ),
        .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_4 ),
        .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_5 ),
        .\po_counter_read_val_reg[8]_6 (\po_counter_read_val_reg[8]_6 ),
        .\po_counter_read_val_reg[8]_7 (\po_counter_read_val_reg[8]_7 ),
        .\po_counter_read_val_reg[8]_8 (\po_counter_read_val_reg[8]_8 ),
        .\po_counter_read_val_reg[8]_9 (\po_counter_read_val_reg[8]_9 ),
        .\rd_ptr_reg[0] (\rd_ptr_reg[0] ),
        .\rd_ptr_reg[0]_0 (\rd_ptr_reg[0]_0 ),
        .\rd_ptr_reg[0]_1 (\rd_ptr_reg[0]_1 ),
        .\rd_ptr_reg[1] (\rd_ptr_reg[1] ),
        .\rd_ptr_reg[1]_0 (\rd_ptr_reg[1]_0 ),
        .\rd_ptr_reg[1]_1 (\rd_ptr_reg[1]_1 ),
        .\rd_ptr_reg[2] (\rd_ptr_reg[2] ),
        .\rd_ptr_reg[2]_0 (\rd_ptr_reg[2]_0 ),
        .\rd_ptr_reg[2]_1 (\rd_ptr_reg[2]_1 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3] ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ),
        .\rd_ptr_reg[3]_1 (\rd_ptr_reg[3]_1 ),
        .\rd_ptr_reg[3]_10 (\rd_ptr_reg[3]_10 ),
        .\rd_ptr_reg[3]_11 (\rd_ptr_reg[3]_11 ),
        .\rd_ptr_reg[3]_12 (\rd_ptr_reg[3]_12 ),
        .\rd_ptr_reg[3]_2 (\rd_ptr_reg[3]_2 ),
        .\rd_ptr_reg[3]_3 (\rd_ptr_reg[3]_3 ),
        .\rd_ptr_reg[3]_4 (\rd_ptr_reg[3]_4 ),
        .\rd_ptr_reg[3]_5 (\rd_ptr_reg[3]_5 ),
        .\rd_ptr_reg[3]_6 (\rd_ptr_reg[3]_6 ),
        .\rd_ptr_reg[3]_7 (\rd_ptr_reg[3]_7 ),
        .\rd_ptr_reg[3]_8 (\rd_ptr_reg[3]_8 ),
        .\rd_ptr_reg[3]_9 (\rd_ptr_reg[3]_9 ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .\read_fifo.tail_r_reg (\read_fifo.tail_r_reg ),
        .ref_dll_lock(ref_dll_lock),
        .sync_pulse(sync_pulse),
        .ts_dqs_0(ts_dqs_0),
        .ts_dqs_1(ts_dqs_1),
        .wr_en(wr_en),
        .wr_en_2(wr_en_2),
        .wr_en_3(wr_en_3),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0]_0 ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_reg[3] (\wr_ptr_reg[3] ),
        .\wr_ptr_reg[3]_0 (\wr_ptr_reg[3]_0 ),
        .\wr_ptr_reg[3]_1 (\wr_ptr_reg[3]_1 ),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0] ),
        .\wr_ptr_timing_reg[0]_0 (\wr_ptr_timing_reg[0]_0 ),
        .\wr_ptr_timing_reg[0]_1 (\wr_ptr_timing_reg[0]_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    u_ras_n_obuf
       (.I(mem_dq_out[18]),
        .O(ddr3_ras_n));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    u_we_n_obuf
       (.I(mem_dq_out[19]),
        .O(ddr3_we_n));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo
   (\my_empty_reg[5]_0 ,
    \my_empty_reg[3]_0 ,
    UNCONN_IN,
    mux_cmd_wren,
    \my_full_reg[5]_0 ,
    \rd_ptr_timing_reg[0]_0 ,
    CLK,
    E,
    in0);
  output \my_empty_reg[5]_0 ;
  output \my_empty_reg[3]_0 ;
  input UNCONN_IN;
  input mux_cmd_wren;
  input \my_full_reg[5]_0 ;
  input \rd_ptr_timing_reg[0]_0 ;
  input CLK;
  input [0:0]E;
  input in0;

  wire CLK;
  wire [0:0]E;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire UNCONN_IN;
  wire in0;
  wire mux_cmd_wren;
  wire my_empty0__0_n_0;
  wire my_empty0__1_n_0;
  wire my_empty0__2_n_0;
  wire my_empty0__3_n_0;
  wire my_empty0__4_n_0;
  wire my_empty0_n_0;
  wire \my_empty[2]_i_1__1_n_0 ;
  wire \my_empty[3]_i_1__1_n_0 ;
  wire \my_empty[4]_inv_i_1_n_0 ;
  wire \my_empty[5]_i_1_n_0 ;
  wire \my_empty[6]_i_1_n_0 ;
  wire \my_empty[8]_i_1_n_0 ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[4]_inv_n_0 ;
  wire \my_empty_reg[5]_0 ;
  wire \my_empty_reg_n_0_[6] ;
  wire \my_full[0]_i_1__1_n_0 ;
  wire \my_full[3]_i_1__0_n_0 ;
  wire \my_full[5]_i_1_n_0 ;
  wire \my_full_reg[5]_0 ;
  wire \my_full_reg_n_0_[0] ;
  wire \my_full_reg_n_0_[3] ;
  wire \my_full_reg_n_0_[5] ;
  wire p_1_in;
  wire p_3_in;
  wire [2:0]rd_ptr;
  wire [2:0]rd_ptr0;
  (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing;
  wire \rd_ptr_timing_reg[0]_0 ;
  wire [2:0]wr_ptr;
  wire [2:0]wr_ptr0;
  wire [2:0]wr_ptr_timing;

  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__0
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__0_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__1
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__1_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__2
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__2_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__3
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__3_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__4
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__4_n_0));
  LUT4 #(
    .INIT(16'hF1F0)) 
    \my_empty[2]_i_1__1 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(p_1_in),
        .I3(my_empty0__0_n_0),
        .O(\my_empty[2]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFE0100)) 
    \my_empty[3]_i_1__1 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(p_1_in),
        .I3(my_empty0__1_n_0),
        .I4(\my_empty_reg[3]_0 ),
        .O(\my_empty[3]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hFEFF0001)) 
    \my_empty[4]_inv_i_1 
       (.I0(mux_cmd_wren),
        .I1(p_3_in),
        .I2(\my_full_reg_n_0_[5] ),
        .I3(my_empty0__2_n_0),
        .I4(\my_empty_reg[4]_inv_n_0 ),
        .O(\my_empty[4]_inv_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFE0100)) 
    \my_empty[5]_i_1 
       (.I0(mux_cmd_wren),
        .I1(p_3_in),
        .I2(\my_full_reg_n_0_[5] ),
        .I3(my_empty0__3_n_0),
        .I4(\my_empty_reg[5]_0 ),
        .O(\my_empty[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFE0100)) 
    \my_empty[6]_i_1 
       (.I0(mux_cmd_wren),
        .I1(p_3_in),
        .I2(\my_full_reg_n_0_[5] ),
        .I3(my_empty0__4_n_0),
        .I4(\my_empty_reg_n_0_[6] ),
        .O(\my_empty[6]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hCDCC)) 
    \my_empty[8]_i_1 
       (.I0(mux_cmd_wren),
        .I1(p_3_in),
        .I2(\my_full_reg_n_0_[5] ),
        .I3(my_empty0_n_0),
        .O(\my_empty[8]_i_1_n_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[2]_i_1__1_n_0 ),
        .Q(p_1_in),
        .S(\rd_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[3]_i_1__1_n_0 ),
        .Q(\my_empty_reg[3]_0 ),
        .S(\rd_ptr_timing_reg[0]_0 ));
  (* inverted = "yes" *) 
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[4]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_inv_i_1_n_0 ),
        .Q(\my_empty_reg[4]_inv_n_0 ),
        .R(in0));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[5]_i_1_n_0 ),
        .Q(\my_empty_reg[5]_0 ),
        .S(\rd_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[6]_i_1_n_0 ),
        .Q(\my_empty_reg_n_0_[6] ),
        .S(\rd_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[8]_i_1_n_0 ),
        .Q(p_3_in),
        .S(\rd_ptr_timing_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair450" *) 
  LUT4 #(
    .INIT(16'h00C8)) 
    \my_full[0]_i_1__1 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[0] ),
        .I2(\my_empty_reg_n_0_[6] ),
        .I3(\my_full_reg[5]_0 ),
        .O(\my_full[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair450" *) 
  LUT5 #(
    .INIT(32'h0000C8CC)) 
    \my_full[3]_i_1__0 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(\my_empty_reg_n_0_[6] ),
        .I3(\my_full_reg_n_0_[0] ),
        .I4(\my_full_reg[5]_0 ),
        .O(\my_full[3]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h0000C8CC)) 
    \my_full[5]_i_1 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[5] ),
        .I2(\my_empty_reg_n_0_[6] ),
        .I3(\my_full_reg_n_0_[0] ),
        .I4(\my_full_reg[5]_0 ),
        .O(\my_full[5]_i_1_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1__1_n_0 ),
        .Q(\my_full_reg_n_0_[0] ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[3]_i_1__0_n_0 ),
        .Q(\my_full_reg_n_0_[3] ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[5]_i_1_n_0 ),
        .Q(\my_full_reg_n_0_[5] ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \rd_ptr[0]_i_1 
       (.I0(rd_ptr[0]),
        .O(rd_ptr0[0]));
  (* SOFT_HLUTNM = "soft_lutpair451" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_ptr[1]_i_1 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .O(rd_ptr0[1]));
  (* SOFT_HLUTNM = "soft_lutpair451" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rd_ptr[2]_i_1 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[2]),
        .O(rd_ptr0[2]));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[0]),
        .Q(rd_ptr[0]),
        .R(\rd_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[1]),
        .Q(rd_ptr[1]),
        .R(\rd_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[2]),
        .Q(rd_ptr[2]),
        .R(\rd_ptr_timing_reg[0]_0 ));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[0]),
        .Q(rd_ptr_timing[0]),
        .R(\rd_ptr_timing_reg[0]_0 ));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[1]),
        .Q(rd_ptr_timing[1]),
        .R(\rd_ptr_timing_reg[0]_0 ));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[2]),
        .Q(rd_ptr_timing[2]),
        .R(\rd_ptr_timing_reg[0]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_ptr[0]_i_1 
       (.I0(wr_ptr[0]),
        .O(wr_ptr0[0]));
  (* SOFT_HLUTNM = "soft_lutpair452" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \wr_ptr[1]_i_1 
       (.I0(wr_ptr[0]),
        .I1(wr_ptr[1]),
        .O(wr_ptr0[1]));
  (* SOFT_HLUTNM = "soft_lutpair452" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \wr_ptr[2]_i_2 
       (.I0(wr_ptr[0]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[2]),
        .O(wr_ptr0[2]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(wr_ptr0[0]),
        .Q(wr_ptr[0]),
        .R(\rd_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(wr_ptr0[1]),
        .Q(wr_ptr[1]),
        .R(\rd_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(wr_ptr0[2]),
        .Q(wr_ptr[2]),
        .R(\rd_ptr_timing_reg[0]_0 ));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(wr_ptr0[0]),
        .Q(wr_ptr_timing[0]),
        .R(\rd_ptr_timing_reg[0]_0 ));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(wr_ptr0[1]),
        .Q(wr_ptr_timing[1]),
        .R(\rd_ptr_timing_reg[0]_0 ));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(wr_ptr0[2]),
        .Q(wr_ptr_timing[2]),
        .R(\rd_ptr_timing_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0
   (\my_empty_reg[5]_0 ,
    \my_empty_reg[3]_0 ,
    UNCONN_IN,
    mux_cmd_wren,
    \my_full_reg[5]_0 ,
    \wr_ptr_timing_reg[0]_0 ,
    CLK,
    \wr_ptr_timing_reg[0]_1 ,
    in0);
  output \my_empty_reg[5]_0 ;
  output \my_empty_reg[3]_0 ;
  input UNCONN_IN;
  input mux_cmd_wren;
  input \my_full_reg[5]_0 ;
  input \wr_ptr_timing_reg[0]_0 ;
  input CLK;
  input [0:0]\wr_ptr_timing_reg[0]_1 ;
  input in0;

  wire CLK;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire UNCONN_IN;
  wire in0;
  wire mux_cmd_wren;
  wire my_empty0__0_n_0;
  wire my_empty0__1_n_0;
  wire my_empty0__2_n_0;
  wire my_empty0__3_n_0;
  wire my_empty0__4_n_0;
  wire my_empty0_n_0;
  wire \my_empty[2]_i_1__2_n_0 ;
  wire \my_empty[3]_i_1__2_n_0 ;
  wire \my_empty[4]_inv_i_1__0_n_0 ;
  wire \my_empty[5]_i_1__0_n_0 ;
  wire \my_empty[6]_i_1__0_n_0 ;
  wire \my_empty[8]_i_1__0_n_0 ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[4]_inv_n_0 ;
  wire \my_empty_reg[5]_0 ;
  wire \my_empty_reg_n_0_[6] ;
  wire \my_full[0]_i_1__2_n_0 ;
  wire \my_full[3]_i_1__1_n_0 ;
  wire \my_full[5]_i_1__0_n_0 ;
  wire \my_full_reg[5]_0 ;
  wire \my_full_reg_n_0_[0] ;
  wire \my_full_reg_n_0_[3] ;
  wire \my_full_reg_n_0_[5] ;
  wire p_1_in;
  wire p_3_in;
  wire [2:0]rd_ptr;
  wire [2:0]rd_ptr0;
  (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing;
  wire [2:0]wr_ptr;
  wire [2:0]wr_ptr0;
  wire [2:0]wr_ptr_timing;
  wire \wr_ptr_timing_reg[0]_0 ;
  wire [0:0]\wr_ptr_timing_reg[0]_1 ;

  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__0
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__0_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__1
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__1_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__2
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__2_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__3
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__3_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__4
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__4_n_0));
  LUT4 #(
    .INIT(16'hF1F0)) 
    \my_empty[2]_i_1__2 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(p_1_in),
        .I3(my_empty0__0_n_0),
        .O(\my_empty[2]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFE0100)) 
    \my_empty[3]_i_1__2 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(p_1_in),
        .I3(my_empty0__1_n_0),
        .I4(\my_empty_reg[3]_0 ),
        .O(\my_empty[3]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hFEFF0001)) 
    \my_empty[4]_inv_i_1__0 
       (.I0(mux_cmd_wren),
        .I1(p_3_in),
        .I2(\my_full_reg_n_0_[5] ),
        .I3(my_empty0__2_n_0),
        .I4(\my_empty_reg[4]_inv_n_0 ),
        .O(\my_empty[4]_inv_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFE0100)) 
    \my_empty[5]_i_1__0 
       (.I0(mux_cmd_wren),
        .I1(p_3_in),
        .I2(\my_full_reg_n_0_[5] ),
        .I3(my_empty0__3_n_0),
        .I4(\my_empty_reg[5]_0 ),
        .O(\my_empty[5]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFFE0100)) 
    \my_empty[6]_i_1__0 
       (.I0(mux_cmd_wren),
        .I1(p_3_in),
        .I2(\my_full_reg_n_0_[5] ),
        .I3(my_empty0__4_n_0),
        .I4(\my_empty_reg_n_0_[6] ),
        .O(\my_empty[6]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hCDCC)) 
    \my_empty[8]_i_1__0 
       (.I0(mux_cmd_wren),
        .I1(p_3_in),
        .I2(\my_full_reg_n_0_[5] ),
        .I3(my_empty0_n_0),
        .O(\my_empty[8]_i_1__0_n_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[2]_i_1__2_n_0 ),
        .Q(p_1_in),
        .S(\wr_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[3]_i_1__2_n_0 ),
        .Q(\my_empty_reg[3]_0 ),
        .S(\wr_ptr_timing_reg[0]_0 ));
  (* inverted = "yes" *) 
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[4]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_inv_i_1__0_n_0 ),
        .Q(\my_empty_reg[4]_inv_n_0 ),
        .R(in0));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[5]_i_1__0_n_0 ),
        .Q(\my_empty_reg[5]_0 ),
        .S(\wr_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[6]_i_1__0_n_0 ),
        .Q(\my_empty_reg_n_0_[6] ),
        .S(\wr_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[8]_i_1__0_n_0 ),
        .Q(p_3_in),
        .S(\wr_ptr_timing_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair453" *) 
  LUT4 #(
    .INIT(16'h00C8)) 
    \my_full[0]_i_1__2 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[0] ),
        .I2(\my_empty_reg_n_0_[6] ),
        .I3(\my_full_reg[5]_0 ),
        .O(\my_full[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair453" *) 
  LUT5 #(
    .INIT(32'h0000C8CC)) 
    \my_full[3]_i_1__1 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(\my_empty_reg_n_0_[6] ),
        .I3(\my_full_reg_n_0_[0] ),
        .I4(\my_full_reg[5]_0 ),
        .O(\my_full[3]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h0000C8CC)) 
    \my_full[5]_i_1__0 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[5] ),
        .I2(\my_empty_reg_n_0_[6] ),
        .I3(\my_full_reg_n_0_[0] ),
        .I4(\my_full_reg[5]_0 ),
        .O(\my_full[5]_i_1__0_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1__2_n_0 ),
        .Q(\my_full_reg_n_0_[0] ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[3]_i_1__1_n_0 ),
        .Q(\my_full_reg_n_0_[3] ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[5]_i_1__0_n_0 ),
        .Q(\my_full_reg_n_0_[5] ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \rd_ptr[0]_i_1 
       (.I0(rd_ptr[0]),
        .O(rd_ptr0[0]));
  (* SOFT_HLUTNM = "soft_lutpair454" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_ptr[1]_i_1 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .O(rd_ptr0[1]));
  (* SOFT_HLUTNM = "soft_lutpair454" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rd_ptr[2]_i_1 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[2]),
        .O(rd_ptr0[2]));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[0]),
        .Q(rd_ptr[0]),
        .R(\wr_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[1]),
        .Q(rd_ptr[1]),
        .R(\wr_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[2]),
        .Q(rd_ptr[2]),
        .R(\wr_ptr_timing_reg[0]_0 ));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[0]),
        .Q(rd_ptr_timing[0]),
        .R(\wr_ptr_timing_reg[0]_0 ));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[1]),
        .Q(rd_ptr_timing[1]),
        .R(\wr_ptr_timing_reg[0]_0 ));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[2]),
        .Q(rd_ptr_timing[2]),
        .R(\wr_ptr_timing_reg[0]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_ptr[0]_i_1 
       (.I0(wr_ptr[0]),
        .O(wr_ptr0[0]));
  (* SOFT_HLUTNM = "soft_lutpair455" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \wr_ptr[1]_i_1 
       (.I0(wr_ptr[0]),
        .I1(wr_ptr[1]),
        .O(wr_ptr0[1]));
  (* SOFT_HLUTNM = "soft_lutpair455" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \wr_ptr[2]_i_2 
       (.I0(wr_ptr[0]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[2]),
        .O(wr_ptr0[2]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(\wr_ptr_timing_reg[0]_1 ),
        .D(wr_ptr0[0]),
        .Q(wr_ptr[0]),
        .R(\wr_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(\wr_ptr_timing_reg[0]_1 ),
        .D(wr_ptr0[1]),
        .Q(wr_ptr[1]),
        .R(\wr_ptr_timing_reg[0]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(\wr_ptr_timing_reg[0]_1 ),
        .D(wr_ptr0[2]),
        .Q(wr_ptr[2]),
        .R(\wr_ptr_timing_reg[0]_0 ));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\wr_ptr_timing_reg[0]_1 ),
        .D(wr_ptr0[0]),
        .Q(wr_ptr_timing[0]),
        .R(\wr_ptr_timing_reg[0]_0 ));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\wr_ptr_timing_reg[0]_1 ),
        .D(wr_ptr0[1]),
        .Q(wr_ptr_timing[1]),
        .R(\wr_ptr_timing_reg[0]_0 ));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\wr_ptr_timing_reg[0]_1 ),
        .D(wr_ptr0[2]),
        .Q(wr_ptr_timing[2]),
        .R(\wr_ptr_timing_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_6
   (\my_empty_reg[5]_0 ,
    \my_empty_reg[3]_0 ,
    UNCONN_IN,
    mux_cmd_wren,
    \my_full_reg[5]_0 ,
    \rd_ptr_reg[0]_0 ,
    CLK,
    \wr_ptr_timing_reg[0]_0 ,
    in0,
    SR,
    \wr_ptr_timing_reg[2]_0 );
  output \my_empty_reg[5]_0 ;
  output \my_empty_reg[3]_0 ;
  input UNCONN_IN;
  input mux_cmd_wren;
  input \my_full_reg[5]_0 ;
  input \rd_ptr_reg[0]_0 ;
  input CLK;
  input [0:0]\wr_ptr_timing_reg[0]_0 ;
  input in0;
  input [0:0]SR;
  input [0:0]\wr_ptr_timing_reg[2]_0 ;

  wire CLK;
  wire [0:0]SR;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire UNCONN_IN;
  wire in0;
  wire mux_cmd_wren;
  wire my_empty0__0_n_0;
  wire my_empty0__1_n_0;
  wire my_empty0__2_n_0;
  wire my_empty0__3_n_0;
  wire my_empty0__4_n_0;
  wire my_empty0_n_0;
  wire \my_empty[2]_i_1__3_n_0 ;
  wire \my_empty[3]_i_1__3_n_0 ;
  wire \my_empty[4]_inv_i_1__1_n_0 ;
  wire \my_empty[5]_i_1__1_n_0 ;
  wire \my_empty[6]_i_1__1_n_0 ;
  wire \my_empty[8]_i_1__1_n_0 ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[4]_inv_n_0 ;
  wire \my_empty_reg[5]_0 ;
  wire \my_empty_reg_n_0_[6] ;
  wire \my_full[0]_i_1__3_n_0 ;
  wire \my_full[3]_i_1__2_n_0 ;
  wire \my_full[5]_i_1__1_n_0 ;
  wire \my_full_reg[5]_0 ;
  wire \my_full_reg_n_0_[0] ;
  wire \my_full_reg_n_0_[3] ;
  wire \my_full_reg_n_0_[5] ;
  wire p_1_in;
  wire p_3_in;
  wire [2:0]rd_ptr;
  wire [2:0]rd_ptr0;
  wire \rd_ptr_reg[0]_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing;
  wire [2:0]wr_ptr;
  wire [2:0]wr_ptr0;
  wire [2:0]wr_ptr_timing;
  wire [0:0]\wr_ptr_timing_reg[0]_0 ;
  wire [0:0]\wr_ptr_timing_reg[2]_0 ;

  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__0
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__0_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__1
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__1_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__2
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__2_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__3
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__3_n_0));
  LUT6 #(
    .INIT(64'h0041820014000082)) 
    my_empty0__4
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[2]),
        .I2(rd_ptr[2]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[0]),
        .I5(wr_ptr_timing[1]),
        .O(my_empty0__4_n_0));
  LUT4 #(
    .INIT(16'hF1F0)) 
    \my_empty[2]_i_1__3 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(p_1_in),
        .I3(my_empty0__0_n_0),
        .O(\my_empty[2]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFE0100)) 
    \my_empty[3]_i_1__3 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(p_1_in),
        .I3(my_empty0__1_n_0),
        .I4(\my_empty_reg[3]_0 ),
        .O(\my_empty[3]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'hFEFF0001)) 
    \my_empty[4]_inv_i_1__1 
       (.I0(mux_cmd_wren),
        .I1(p_3_in),
        .I2(\my_full_reg_n_0_[5] ),
        .I3(my_empty0__2_n_0),
        .I4(\my_empty_reg[4]_inv_n_0 ),
        .O(\my_empty[4]_inv_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFE0100)) 
    \my_empty[5]_i_1__1 
       (.I0(mux_cmd_wren),
        .I1(p_3_in),
        .I2(\my_full_reg_n_0_[5] ),
        .I3(my_empty0__3_n_0),
        .I4(\my_empty_reg[5]_0 ),
        .O(\my_empty[5]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFE0100)) 
    \my_empty[6]_i_1__1 
       (.I0(mux_cmd_wren),
        .I1(p_3_in),
        .I2(\my_full_reg_n_0_[5] ),
        .I3(my_empty0__4_n_0),
        .I4(\my_empty_reg_n_0_[6] ),
        .O(\my_empty[6]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hCDCC)) 
    \my_empty[8]_i_1__1 
       (.I0(mux_cmd_wren),
        .I1(p_3_in),
        .I2(\my_full_reg_n_0_[5] ),
        .I3(my_empty0_n_0),
        .O(\my_empty[8]_i_1__1_n_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[2]_i_1__3_n_0 ),
        .Q(p_1_in),
        .S(\rd_ptr_reg[0]_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[3]_i_1__3_n_0 ),
        .Q(\my_empty_reg[3]_0 ),
        .S(\rd_ptr_reg[0]_0 ));
  (* inverted = "yes" *) 
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[4]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[4]_inv_i_1__1_n_0 ),
        .Q(\my_empty_reg[4]_inv_n_0 ),
        .R(in0));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[5]_i_1__1_n_0 ),
        .Q(\my_empty_reg[5]_0 ),
        .S(\rd_ptr_reg[0]_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[6]_i_1__1_n_0 ),
        .Q(\my_empty_reg_n_0_[6] ),
        .S(\rd_ptr_reg[0]_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[8]_i_1__1_n_0 ),
        .Q(p_3_in),
        .S(\rd_ptr_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair456" *) 
  LUT4 #(
    .INIT(16'h00C8)) 
    \my_full[0]_i_1__3 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[0] ),
        .I2(\my_empty_reg_n_0_[6] ),
        .I3(\my_full_reg[5]_0 ),
        .O(\my_full[0]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair456" *) 
  LUT5 #(
    .INIT(32'h0000C8CC)) 
    \my_full[3]_i_1__2 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(\my_empty_reg_n_0_[6] ),
        .I3(\my_full_reg_n_0_[0] ),
        .I4(\my_full_reg[5]_0 ),
        .O(\my_full[3]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h0000C8CC)) 
    \my_full[5]_i_1__1 
       (.I0(mux_cmd_wren),
        .I1(\my_full_reg_n_0_[5] ),
        .I2(\my_empty_reg_n_0_[6] ),
        .I3(\my_full_reg_n_0_[0] ),
        .I4(\my_full_reg[5]_0 ),
        .O(\my_full[5]_i_1__1_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[0]_i_1__3_n_0 ),
        .Q(\my_full_reg_n_0_[0] ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[3]_i_1__2_n_0 ),
        .Q(\my_full_reg_n_0_[3] ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[5]_i_1__1_n_0 ),
        .Q(\my_full_reg_n_0_[5] ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \rd_ptr[0]_i_1 
       (.I0(rd_ptr[0]),
        .O(rd_ptr0[0]));
  (* SOFT_HLUTNM = "soft_lutpair457" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_ptr[1]_i_1 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .O(rd_ptr0[1]));
  (* SOFT_HLUTNM = "soft_lutpair457" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rd_ptr[2]_i_1 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[2]),
        .O(rd_ptr0[2]));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[0]),
        .Q(rd_ptr[0]),
        .R(\rd_ptr_reg[0]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[1]),
        .Q(rd_ptr[1]),
        .R(\rd_ptr_reg[0]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[2]),
        .Q(rd_ptr[2]),
        .R(\rd_ptr_reg[0]_0 ));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[0]),
        .Q(rd_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[1]),
        .Q(rd_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\my_empty_reg[4]_inv_n_0 ),
        .D(rd_ptr0[2]),
        .Q(rd_ptr_timing[2]),
        .R(SR));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_ptr[0]_i_1 
       (.I0(wr_ptr[0]),
        .O(wr_ptr0[0]));
  (* SOFT_HLUTNM = "soft_lutpair458" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \wr_ptr[1]_i_1 
       (.I0(wr_ptr[0]),
        .I1(wr_ptr[1]),
        .O(wr_ptr0[1]));
  (* SOFT_HLUTNM = "soft_lutpair458" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \wr_ptr[2]_i_2 
       (.I0(wr_ptr[0]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[2]),
        .O(wr_ptr0[2]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(\wr_ptr_timing_reg[0]_0 ),
        .D(wr_ptr0[0]),
        .Q(wr_ptr[0]),
        .R(\rd_ptr_reg[0]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(\wr_ptr_timing_reg[0]_0 ),
        .D(wr_ptr0[1]),
        .Q(wr_ptr[1]),
        .R(\rd_ptr_reg[0]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(\wr_ptr_timing_reg[0]_0 ),
        .D(wr_ptr0[2]),
        .Q(wr_ptr[2]),
        .R(\rd_ptr_reg[0]_0 ));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\wr_ptr_timing_reg[0]_0 ),
        .D(wr_ptr0[0]),
        .Q(wr_ptr_timing[0]),
        .R(\wr_ptr_timing_reg[2]_0 ));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\wr_ptr_timing_reg[0]_0 ),
        .D(wr_ptr0[1]),
        .Q(wr_ptr_timing[1]),
        .R(\wr_ptr_timing_reg[2]_0 ));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\wr_ptr_timing_reg[0]_0 ),
        .D(wr_ptr0[2]),
        .Q(wr_ptr_timing[2]),
        .R(\wr_ptr_timing_reg[2]_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1
   (\rd_ptr_reg[0]_0 ,
    \rd_ptr_reg[1]_0 ,
    \rd_ptr_reg[2]_0 ,
    \rd_ptr_reg[3]_0 ,
    \my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    Q,
    wr_en,
    \wr_ptr_reg[3]_0 ,
    ofifo_rst,
    CLK,
    D_of_full,
    mux_wrdata_en,
    mc_wrdata_en,
    out_fifo,
    calib_wrdata_en,
    \wr_ptr_timing_reg[0]_0 );
  output \rd_ptr_reg[0]_0 ;
  output \rd_ptr_reg[1]_0 ;
  output \rd_ptr_reg[2]_0 ;
  output \rd_ptr_reg[3]_0 ;
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [2:0]Q;
  output wr_en;
  output [3:0]\wr_ptr_reg[3]_0 ;
  input ofifo_rst;
  input CLK;
  input D_of_full;
  input mux_wrdata_en;
  input mc_wrdata_en;
  input out_fifo;
  input calib_wrdata_en;
  input \wr_ptr_timing_reg[0]_0 ;

  wire CLK;
  wire D_of_full;
  wire [2:0]Q;
  wire calib_wrdata_en;
  wire entry_cnt10_out__0;
  wire \entry_cnt[0]_i_1__0_n_0 ;
  wire \entry_cnt[1]_i_1__0_n_0 ;
  wire \entry_cnt[2]_i_1__0_n_0 ;
  wire \entry_cnt[3]_i_1__0_n_0 ;
  wire \entry_cnt[4]_i_1__0_n_0 ;
  wire \entry_cnt[4]_i_2__0_n_0 ;
  wire \entry_cnt_reg_n_0_[0] ;
  wire \entry_cnt_reg_n_0_[1] ;
  wire mc_wrdata_en;
  wire mux_wrdata_en;
  wire my_empty0;
  wire \my_empty[1]_i_1__2_n_0 ;
  wire \my_empty[7]_i_1__1_n_0 ;
  wire \my_empty[7]_i_3__1_n_0 ;
  wire \my_empty[7]_i_4__1_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg_n_0_[7] ;
  wire my_full0;
  wire \my_full[4]_i_1__1_n_0 ;
  wire \my_full[4]_i_3__1_n_0 ;
  wire \my_full[4]_i_4__1_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire ofifo_rst;
  wire out_fifo;
  wire \rd_ptr_reg[0]_0 ;
  wire \rd_ptr_reg[1]_0 ;
  wire \rd_ptr_reg[2]_0 ;
  wire \rd_ptr_reg[3]_0 ;
  wire [3:0]rd_ptr_timing;
  wire \rd_ptr_timing[3]_i_1__2_n_0 ;
  wire wr_en;
  wire wr_ptr0;
  wire [3:0]\wr_ptr_reg[3]_0 ;
  wire [3:0]wr_ptr_timing;
  wire \wr_ptr_timing_reg[0]_0 ;

  (* SOFT_HLUTNM = "soft_lutpair551" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__0 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .O(\entry_cnt[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair551" *) 
  LUT5 #(
    .INIT(32'hAA6A5595)) 
    \entry_cnt[1]_i_1__0 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(D_of_full),
        .I2(mux_wrdata_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFF7F0080AAEA5515)) 
    \entry_cnt[2]_i_1__0 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(D_of_full),
        .I2(mux_wrdata_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(Q[0]),
        .I5(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[2]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1__0 
       (.I0(entry_cnt10_out__0),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(\entry_cnt_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\entry_cnt[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h5050500303035003)) 
    \entry_cnt[4]_i_1__0 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(\my_empty_reg_n_0_[7] ),
        .I2(D_of_full),
        .I3(calib_wrdata_en),
        .I4(\wr_ptr_timing_reg[0]_0 ),
        .I5(mc_wrdata_en),
        .O(\entry_cnt[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h7FFF8000FFFE0001)) 
    \entry_cnt[4]_i_2__0 
       (.I0(\entry_cnt_reg_n_0_[1] ),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(entry_cnt10_out__0),
        .I3(Q[0]),
        .I4(Q[2]),
        .I5(Q[1]),
        .O(\entry_cnt[4]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008A80)) 
    \entry_cnt[4]_i_3__0 
       (.I0(D_of_full),
        .I1(mc_wrdata_en),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .I3(calib_wrdata_en),
        .I4(\my_full_reg_n_0_[4] ),
        .O(entry_cnt10_out__0));
  FDRE \entry_cnt_reg[0] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[0]_i_1__0_n_0 ),
        .Q(\entry_cnt_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[1]_i_1__0_n_0 ),
        .Q(\entry_cnt_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[2]_i_1__0_n_0 ),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[3]_i_1__0_n_0 ),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[4]_i_2__0_n_0 ),
        .Q(Q[2]),
        .R(ofifo_rst));
  LUT6 #(
    .INIT(64'h2727270000002700)) 
    mem_reg_0_15_6_11_i_1
       (.I0(D_of_full),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(calib_wrdata_en),
        .I4(\wr_ptr_timing_reg[0]_0 ),
        .I5(mc_wrdata_en),
        .O(wr_en));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[1]_i_1__2 
       (.I0(D_of_full),
        .I1(mux_wrdata_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg[1]_1 ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[7]_i_1__1 
       (.I0(D_of_full),
        .I1(mux_wrdata_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[7]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[7]_i_2 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[7]_i_3__1_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[7]_i_4__1_n_0 ),
        .I4(\rd_ptr_reg[2]_0 ),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair552" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[7]_i_3__1 
       (.I0(wr_ptr_timing[1]),
        .I1(\rd_ptr_reg[0]_0 ),
        .I2(\rd_ptr_reg[1]_0 ),
        .I3(\rd_ptr_reg[3]_0 ),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[7]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair552" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[7]_i_4__1 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg[0]_0 ),
        .I3(\rd_ptr_reg[1]_0 ),
        .I4(\rd_ptr_reg[3]_0 ),
        .O(\my_empty[7]_i_4__1_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__2_n_0 ),
        .Q(\my_empty_reg[1]_1 ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[7]_i_1__1_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[4]_i_1__1 
       (.I0(my_full0),
        .I1(mux_wrdata_en),
        .I2(D_of_full),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[4]_i_2__1 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[4]_i_3__1_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[4]_i_4__1_n_0 ),
        .I4(\wr_ptr_reg[3]_0 [2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair553" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[4]_i_3__1 
       (.I0(rd_ptr_timing[1]),
        .I1(\wr_ptr_reg[3]_0 [0]),
        .I2(\wr_ptr_reg[3]_0 [1]),
        .I3(\wr_ptr_reg[3]_0 [3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[4]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair553" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[4]_i_4__1 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(\wr_ptr_reg[3]_0 [0]),
        .I3(\wr_ptr_reg[3]_0 [1]),
        .I4(\wr_ptr_reg[3]_0 [3]),
        .O(\my_full[4]_i_4__1_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[4]_i_1__1_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000DFD5)) 
    out_fifo_i_1__2
       (.I0(\my_empty_reg[1]_1 ),
        .I1(mc_wrdata_en),
        .I2(out_fifo),
        .I3(calib_wrdata_en),
        .I4(D_of_full),
        .O(\my_empty_reg[1]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg[0]_0 ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg[1]_0 ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg[2]_0 ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg[3]_0 ),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair556" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_timing[0]_i_1__4 
       (.I0(\rd_ptr_reg[3]_0 ),
        .I1(\rd_ptr_reg[0]_0 ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair556" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr_timing[1]_i_1__4 
       (.I0(\rd_ptr_reg[3]_0 ),
        .I1(\rd_ptr_reg[0]_0 ),
        .I2(\rd_ptr_reg[1]_0 ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair554" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_timing[2]_i_1__2 
       (.I0(\rd_ptr_reg[2]_0 ),
        .I1(\rd_ptr_reg[0]_0 ),
        .I2(\rd_ptr_reg[1]_0 ),
        .I3(\rd_ptr_reg[3]_0 ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_timing[3]_i_1__2 
       (.I0(D_of_full),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(\rd_ptr_timing[3]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair554" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr_timing[3]_i_2__2 
       (.I0(\rd_ptr_reg[3]_0 ),
        .I1(\rd_ptr_reg[1]_0 ),
        .I2(\rd_ptr_reg[0]_0 ),
        .I3(\rd_ptr_reg[2]_0 ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair557" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__4 
       (.I0(\wr_ptr_reg[3]_0 [3]),
        .I1(\wr_ptr_reg[3]_0 [0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair557" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1__4 
       (.I0(\wr_ptr_reg[3]_0 [3]),
        .I1(\wr_ptr_reg[3]_0 [0]),
        .I2(\wr_ptr_reg[3]_0 [1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair555" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__2 
       (.I0(\wr_ptr_reg[3]_0 [2]),
        .I1(\wr_ptr_reg[3]_0 [0]),
        .I2(\wr_ptr_reg[3]_0 [1]),
        .I3(\wr_ptr_reg[3]_0 [3]),
        .O(nxt_wr_ptr[2]));
  LUT6 #(
    .INIT(64'h0000E20000E2E2E2)) 
    \wr_ptr[3]_i_1__1 
       (.I0(calib_wrdata_en),
        .I1(\wr_ptr_timing_reg[0]_0 ),
        .I2(mc_wrdata_en),
        .I3(D_of_full),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(\my_empty_reg_n_0_[7] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair555" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_2__0 
       (.I0(\wr_ptr_reg[3]_0 [3]),
        .I1(\wr_ptr_reg[3]_0 [1]),
        .I2(\wr_ptr_reg[3]_0 [0]),
        .I3(\wr_ptr_reg[3]_0 [2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(\wr_ptr_reg[3]_0 [0]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(\wr_ptr_reg[3]_0 [1]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(\wr_ptr_reg[3]_0 [2]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(\wr_ptr_reg[3]_0 [3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_10
   (\my_empty_reg[1]_0 ,
    D1,
    D3,
    \my_empty_reg[1]_1 ,
    \rd_ptr_reg[3]_0 ,
    SR,
    CLK,
    calib_cmd_wren,
    \wr_ptr_timing_reg[0]_0 ,
    A_of_full,
    mc_address,
    mc_cas_n,
    mux_cmd_wren,
    phy_dout);
  output \my_empty_reg[1]_0 ;
  output [3:0]D1;
  output [3:0]D3;
  output \my_empty_reg[1]_1 ;
  output [35:0]\rd_ptr_reg[3]_0 ;
  input [0:0]SR;
  input CLK;
  input calib_cmd_wren;
  input \wr_ptr_timing_reg[0]_0 ;
  input A_of_full;
  input [3:0]mc_address;
  input [0:0]mc_cas_n;
  input mux_cmd_wren;
  input [38:0]phy_dout;

  wire A_of_full;
  wire CLK;
  wire [3:0]D1;
  wire [3:0]D3;
  wire [0:0]SR;
  wire calib_cmd_wren;
  wire [3:0]mc_address;
  wire [0:0]mc_cas_n;
  wire [27:8]mem_out;
  wire mux_cmd_wren;
  wire my_empty0;
  wire \my_empty[1]_i_1_n_0 ;
  wire \my_empty[7]_i_1_n_0 ;
  wire \my_empty[7]_i_4_n_0 ;
  wire \my_empty[7]_i_5_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg_n_0_[7] ;
  wire my_full0;
  wire \my_full[4]_i_1_n_0 ;
  wire \my_full[4]_i_3_n_0 ;
  wire \my_full[4]_i_4_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire [38:0]phy_dout;
  wire [3:0]rd_ptr;
  wire [35:0]\rd_ptr_reg[3]_0 ;
  wire [3:0]rd_ptr_timing;
  wire \rd_ptr_timing[3]_i_1_n_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0__0;
  wire [3:0]wr_ptr_timing;
  wire \wr_ptr_timing_reg[0]_0 ;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOA_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOA_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOA_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOA_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOA_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;

  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[1:0]),
        .DIB(phy_dout[3:2]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [1:0]),
        .DOB(\rd_ptr_reg[3]_0 [3:2]),
        .DOC(NLW_mem_reg_0_15_0_5_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(phy_dout[7:6]),
        .DID({1'b0,1'b0}),
        .DOA(NLW_mem_reg_0_15_12_17_DOA_UNCONNECTED[1:0]),
        .DOB(NLW_mem_reg_0_15_12_17_DOB_UNCONNECTED[1:0]),
        .DOC(\rd_ptr_reg[3]_0 [5:4]),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[9:8]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [7:6]),
        .DOB(NLW_mem_reg_0_15_18_23_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_18_23_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[11:10]),
        .DIB(phy_dout[13:12]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[25:24]),
        .DOB(mem_out[27:26]),
        .DOC(NLW_mem_reg_0_15_24_29_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(phy_dout[15:14]),
        .DIC(phy_dout[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(NLW_mem_reg_0_15_30_35_DOA_UNCONNECTED[1:0]),
        .DOB(\rd_ptr_reg[3]_0 [9:8]),
        .DOC(\rd_ptr_reg[3]_0 [11:10]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(phy_dout[19:18]),
        .DID({1'b0,1'b0}),
        .DOA(NLW_mem_reg_0_15_36_41_DOA_UNCONNECTED[1:0]),
        .DOB(NLW_mem_reg_0_15_36_41_DOB_UNCONNECTED[1:0]),
        .DOC(\rd_ptr_reg[3]_0 [13:12]),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[21:20]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [15:14]),
        .DOB(NLW_mem_reg_0_15_42_47_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_42_47_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[23:22]),
        .DIB(phy_dout[25:24]),
        .DIC({phy_dout[26],phy_dout[26]}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [17:16]),
        .DOB(\rd_ptr_reg[3]_0 [19:18]),
        .DOC(\rd_ptr_reg[3]_0 [21:20]),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({phy_dout[26],phy_dout[26]}),
        .DIB(phy_dout[28:27]),
        .DIC(phy_dout[30:29]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [23:22]),
        .DOB(\rd_ptr_reg[3]_0 [25:24]),
        .DOC(\rd_ptr_reg[3]_0 [27:26]),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(phy_dout[32:31]),
        .DID({1'b0,1'b0}),
        .DOA(NLW_mem_reg_0_15_60_65_DOA_UNCONNECTED[1:0]),
        .DOB(NLW_mem_reg_0_15_60_65_DOB_UNCONNECTED[1:0]),
        .DOC(\rd_ptr_reg[3]_0 [29:28]),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[34:33]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [31:30]),
        .DOB(NLW_mem_reg_0_15_66_71_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_66_71_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({phy_dout[11],phy_dout[4]}),
        .DIC({phy_dout[13],phy_dout[5]}),
        .DID({1'b0,1'b0}),
        .DOA(NLW_mem_reg_0_15_6_11_DOA_UNCONNECTED[1:0]),
        .DOB(mem_out[9:8]),
        .DOC(mem_out[11:10]),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* RTL_RAM_TYPE = "RAM_SDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[36:35]),
        .DIB(phy_dout[38:37]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [33:32]),
        .DOB(\rd_ptr_reg[3]_0 [35:34]),
        .DOC(NLW_mem_reg_0_15_72_77_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(CLK),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[1]_i_1 
       (.I0(A_of_full),
        .I1(mux_cmd_wren),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg[1]_0 ),
        .I4(my_empty0),
        .I5(SR),
        .O(\my_empty[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[7]_i_1 
       (.I0(A_of_full),
        .I1(mux_cmd_wren),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(my_empty0),
        .I5(SR),
        .O(\my_empty[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[7]_i_3 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[7]_i_4_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[7]_i_5_n_0 ),
        .I4(rd_ptr[2]),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair459" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[7]_i_4 
       (.I0(wr_ptr_timing[1]),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[3]),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[7]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair459" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[7]_i_5 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[3]),
        .O(\my_empty[7]_i_5_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[1]_i_1_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[7]_i_1_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[4]_i_1 
       (.I0(my_full0),
        .I1(mux_cmd_wren),
        .I2(A_of_full),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(SR),
        .O(\my_full[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[4]_i_2 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[4]_i_3_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[4]_i_4_n_0 ),
        .I4(wr_ptr[2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair460" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[4]_i_3 
       (.I0(rd_ptr_timing[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair460" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[4]_i_4 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[1]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_4_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[4]_i_1_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00FD)) 
    out_fifo_i_1
       (.I0(\my_empty_reg[1]_0 ),
        .I1(\wr_ptr_timing_reg[0]_0 ),
        .I2(calib_cmd_wren),
        .I3(A_of_full),
        .O(\my_empty_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair462" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    out_fifo_i_14
       (.I0(\wr_ptr_timing_reg[0]_0 ),
        .I1(mem_out[27]),
        .I2(\my_empty_reg[1]_0 ),
        .O(D3[3]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_15
       (.I0(mc_address[3]),
        .I1(\wr_ptr_timing_reg[0]_0 ),
        .I2(mem_out[26]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D3[2]));
  (* SOFT_HLUTNM = "soft_lutpair463" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_16
       (.I0(mc_cas_n),
        .I1(\wr_ptr_timing_reg[0]_0 ),
        .I2(mem_out[25]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D3[1]));
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_17
       (.I0(mc_address[1]),
        .I1(\wr_ptr_timing_reg[0]_0 ),
        .I2(mem_out[24]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D3[0]));
  (* SOFT_HLUTNM = "soft_lutpair461" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    out_fifo_i_6
       (.I0(\wr_ptr_timing_reg[0]_0 ),
        .I1(mem_out[11]),
        .I2(\my_empty_reg[1]_0 ),
        .O(D1[3]));
  (* SOFT_HLUTNM = "soft_lutpair462" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_7
       (.I0(mc_address[2]),
        .I1(\wr_ptr_timing_reg[0]_0 ),
        .I2(mem_out[10]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D1[2]));
  (* SOFT_HLUTNM = "soft_lutpair463" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_8
       (.I0(mc_cas_n),
        .I1(\wr_ptr_timing_reg[0]_0 ),
        .I2(mem_out[9]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D1[1]));
  (* SOFT_HLUTNM = "soft_lutpair461" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_9
       (.I0(mc_address[0]),
        .I1(\wr_ptr_timing_reg[0]_0 ),
        .I2(mem_out[8]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D1[0]));
  LUT5 #(
    .INIT(32'h27272700)) 
    p_17_out
       (.I0(A_of_full),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(calib_cmd_wren),
        .I4(\wr_ptr_timing_reg[0]_0 ),
        .O(wr_en));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr[0]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr[1]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr[2]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr[3]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair466" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_timing[0]_i_1 
       (.I0(rd_ptr[3]),
        .I1(rd_ptr[0]),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair466" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr_timing[1]_i_1 
       (.I0(rd_ptr[3]),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[1]),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair464" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_timing[2]_i_1 
       (.I0(rd_ptr[2]),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[3]),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_timing[3]_i_1 
       (.I0(A_of_full),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(\rd_ptr_timing[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair464" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr_timing[3]_i_2 
       (.I0(rd_ptr[3]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[2]),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(SR));
  LUT5 #(
    .INIT(32'h00E00EEE)) 
    wr_ptr0
       (.I0(calib_cmd_wren),
        .I1(\wr_ptr_timing_reg[0]_0 ),
        .I2(A_of_full),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\my_empty_reg_n_0_[7] ),
        .O(wr_ptr0__0));
  (* SOFT_HLUTNM = "soft_lutpair467" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair467" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair465" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  (* SOFT_HLUTNM = "soft_lutpair465" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_1 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_8
   (\rd_ptr_reg[0]_0 ,
    \rd_ptr_reg[1]_0 ,
    \rd_ptr_reg[2]_0 ,
    \rd_ptr_reg[3]_0 ,
    \my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    phy_mc_data_full,
    wr_en_2,
    \wr_ptr_reg[3]_0 ,
    ofifo_rst,
    CLK,
    C_of_full,
    mux_wrdata_en,
    mc_wrdata_en,
    \wr_ptr_timing_reg[0]_0 ,
    calib_wrdata_en,
    Q);
  output \rd_ptr_reg[0]_0 ;
  output \rd_ptr_reg[1]_0 ;
  output \rd_ptr_reg[2]_0 ;
  output \rd_ptr_reg[3]_0 ;
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output phy_mc_data_full;
  output wr_en_2;
  output [3:0]\wr_ptr_reg[3]_0 ;
  input ofifo_rst;
  input CLK;
  input C_of_full;
  input mux_wrdata_en;
  input mc_wrdata_en;
  input \wr_ptr_timing_reg[0]_0 ;
  input calib_wrdata_en;
  input [2:0]Q;

  wire CLK;
  wire C_of_full;
  wire [2:0]Q;
  wire calib_wrdata_en;
  wire entry_cnt10_out__0;
  wire \entry_cnt[0]_i_1_n_0 ;
  wire \entry_cnt[1]_i_1_n_0 ;
  wire \entry_cnt[2]_i_1_n_0 ;
  wire \entry_cnt[3]_i_1_n_0 ;
  wire \entry_cnt[4]_i_1_n_0 ;
  wire \entry_cnt[4]_i_2_n_0 ;
  wire [4:2]entry_cnt_reg;
  wire \entry_cnt_reg_n_0_[0] ;
  wire \entry_cnt_reg_n_0_[1] ;
  wire mc_wrdata_en;
  wire mux_wrdata_en;
  wire my_empty0;
  wire \my_empty[1]_i_1__1_n_0 ;
  wire \my_empty[7]_i_1__0_n_0 ;
  wire \my_empty[7]_i_4__0_n_0 ;
  wire \my_empty[7]_i_5__0_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg_n_0_[7] ;
  wire my_full0;
  wire \my_full[4]_i_1__0_n_0 ;
  wire \my_full[4]_i_3__0_n_0 ;
  wire \my_full[4]_i_4__0_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire ofifo_rst;
  wire phy_mc_data_full;
  wire \rd_ptr_reg[0]_0 ;
  wire \rd_ptr_reg[1]_0 ;
  wire \rd_ptr_reg[2]_0 ;
  wire \rd_ptr_reg[3]_0 ;
  wire [3:0]rd_ptr_timing;
  wire \rd_ptr_timing[3]_i_1__1_n_0 ;
  wire wr_en_2;
  wire wr_ptr0;
  wire [3:0]\wr_ptr_reg[3]_0 ;
  wire [3:0]wr_ptr_timing;
  wire \wr_ptr_timing_reg[0]_0 ;

  (* SOFT_HLUTNM = "soft_lutpair510" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .O(\entry_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair510" *) 
  LUT5 #(
    .INIT(32'hAA6A5595)) 
    \entry_cnt[1]_i_1 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(C_of_full),
        .I2(mux_wrdata_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF7F0080AAEA5515)) 
    \entry_cnt[2]_i_1 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(C_of_full),
        .I2(mux_wrdata_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(entry_cnt_reg[2]),
        .I5(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1 
       (.I0(entry_cnt10_out__0),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(\entry_cnt_reg_n_0_[1] ),
        .I3(entry_cnt_reg[3]),
        .I4(entry_cnt_reg[2]),
        .O(\entry_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5050500303035003)) 
    \entry_cnt[4]_i_1 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(\my_empty_reg_n_0_[7] ),
        .I2(C_of_full),
        .I3(calib_wrdata_en),
        .I4(\wr_ptr_timing_reg[0]_0 ),
        .I5(mc_wrdata_en),
        .O(\entry_cnt[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFF8000FFFE0001)) 
    \entry_cnt[4]_i_2 
       (.I0(\entry_cnt_reg_n_0_[1] ),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(entry_cnt10_out__0),
        .I3(entry_cnt_reg[2]),
        .I4(entry_cnt_reg[4]),
        .I5(entry_cnt_reg[3]),
        .O(\entry_cnt[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008A80)) 
    \entry_cnt[4]_i_3 
       (.I0(C_of_full),
        .I1(mc_wrdata_en),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .I3(calib_wrdata_en),
        .I4(\my_full_reg_n_0_[4] ),
        .O(entry_cnt10_out__0));
  FDRE \entry_cnt_reg[0] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[0]_i_1_n_0 ),
        .Q(\entry_cnt_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[1]_i_1_n_0 ),
        .Q(\entry_cnt_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[2]_i_1_n_0 ),
        .Q(entry_cnt_reg[2]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[3]_i_1_n_0 ),
        .Q(entry_cnt_reg[3]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(CLK),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[4]_i_2_n_0 ),
        .Q(entry_cnt_reg[4]),
        .R(ofifo_rst));
  LUT6 #(
    .INIT(64'h2727270000002700)) 
    mem_reg_0_15_0_5_i_1
       (.I0(C_of_full),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(calib_wrdata_en),
        .I4(\wr_ptr_timing_reg[0]_0 ),
        .I5(mc_wrdata_en),
        .O(wr_en_2));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[1]_i_1__1 
       (.I0(C_of_full),
        .I1(mux_wrdata_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg[1]_1 ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[7]_i_1__0 
       (.I0(C_of_full),
        .I1(mux_wrdata_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[7]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[7]_i_3__0 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[7]_i_4__0_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[7]_i_5__0_n_0 ),
        .I4(\rd_ptr_reg[2]_0 ),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair511" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[7]_i_4__0 
       (.I0(wr_ptr_timing[1]),
        .I1(\rd_ptr_reg[0]_0 ),
        .I2(\rd_ptr_reg[1]_0 ),
        .I3(\rd_ptr_reg[3]_0 ),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[7]_i_4__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair511" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[7]_i_5__0 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg[0]_0 ),
        .I3(\rd_ptr_reg[1]_0 ),
        .I4(\rd_ptr_reg[3]_0 ),
        .O(\my_empty[7]_i_5__0_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__1_n_0 ),
        .Q(\my_empty_reg[1]_1 ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[7]_i_1__0_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[4]_i_1__0 
       (.I0(my_full0),
        .I1(mux_wrdata_en),
        .I2(C_of_full),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[4]_i_2__0 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[4]_i_3__0_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[4]_i_4__0_n_0 ),
        .I4(\wr_ptr_reg[3]_0 [2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair512" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[4]_i_3__0 
       (.I0(rd_ptr_timing[1]),
        .I1(\wr_ptr_reg[3]_0 [0]),
        .I2(\wr_ptr_reg[3]_0 [1]),
        .I3(\wr_ptr_reg[3]_0 [3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[4]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair512" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[4]_i_4__0 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(\wr_ptr_reg[3]_0 [0]),
        .I3(\wr_ptr_reg[3]_0 [1]),
        .I4(\wr_ptr_reg[3]_0 [3]),
        .O(\my_full[4]_i_4__0_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[4]_i_1__0_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    ofs_rdy_r_i_2
       (.I0(entry_cnt_reg[4]),
        .I1(entry_cnt_reg[2]),
        .I2(entry_cnt_reg[3]),
        .I3(Q[2]),
        .I4(Q[0]),
        .I5(Q[1]),
        .O(phy_mc_data_full));
  LUT5 #(
    .INIT(32'h0000DFD5)) 
    out_fifo_i_1__1
       (.I0(\my_empty_reg[1]_1 ),
        .I1(mc_wrdata_en),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .I3(calib_wrdata_en),
        .I4(C_of_full),
        .O(\my_empty_reg[1]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg[0]_0 ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg[1]_0 ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg[2]_0 ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg[3]_0 ),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair515" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_timing[0]_i_1__3 
       (.I0(\rd_ptr_reg[3]_0 ),
        .I1(\rd_ptr_reg[0]_0 ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair515" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr_timing[1]_i_1__3 
       (.I0(\rd_ptr_reg[3]_0 ),
        .I1(\rd_ptr_reg[0]_0 ),
        .I2(\rd_ptr_reg[1]_0 ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair513" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_timing[2]_i_1__1 
       (.I0(\rd_ptr_reg[2]_0 ),
        .I1(\rd_ptr_reg[0]_0 ),
        .I2(\rd_ptr_reg[1]_0 ),
        .I3(\rd_ptr_reg[3]_0 ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_timing[3]_i_1__1 
       (.I0(C_of_full),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(\rd_ptr_timing[3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair513" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr_timing[3]_i_2__1 
       (.I0(\rd_ptr_reg[3]_0 ),
        .I1(\rd_ptr_reg[1]_0 ),
        .I2(\rd_ptr_reg[0]_0 ),
        .I3(\rd_ptr_reg[2]_0 ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair516" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__3 
       (.I0(\wr_ptr_reg[3]_0 [3]),
        .I1(\wr_ptr_reg[3]_0 [0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair516" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1__3 
       (.I0(\wr_ptr_reg[3]_0 [3]),
        .I1(\wr_ptr_reg[3]_0 [0]),
        .I2(\wr_ptr_reg[3]_0 [1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair514" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__1 
       (.I0(\wr_ptr_reg[3]_0 [2]),
        .I1(\wr_ptr_reg[3]_0 [0]),
        .I2(\wr_ptr_reg[3]_0 [1]),
        .I3(\wr_ptr_reg[3]_0 [3]),
        .O(nxt_wr_ptr[2]));
  LUT6 #(
    .INIT(64'h0000E20000E2E2E2)) 
    \wr_ptr[3]_i_1__2 
       (.I0(calib_wrdata_en),
        .I1(\wr_ptr_timing_reg[0]_0 ),
        .I2(mc_wrdata_en),
        .I3(C_of_full),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(\my_empty_reg_n_0_[7] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair514" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_2 
       (.I0(\wr_ptr_reg[3]_0 [3]),
        .I1(\wr_ptr_reg[3]_0 [1]),
        .I2(\wr_ptr_reg[3]_0 [0]),
        .I3(\wr_ptr_reg[3]_0 [2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(\wr_ptr_reg[3]_0 [0]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(\wr_ptr_reg[3]_0 [1]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(\wr_ptr_reg[3]_0 [2]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(\wr_ptr_reg[3]_0 [3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_9
   (\rd_ptr_reg[0]_0 ,
    \rd_ptr_reg[1]_0 ,
    \rd_ptr_reg[2]_0 ,
    \rd_ptr_reg[3]_0 ,
    wr_en_3,
    \my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    D2,
    D6,
    D7,
    Q,
    ofifo_rst,
    CLK,
    calib_cmd_wren,
    \wr_ptr_timing_reg[0]_0 ,
    \rd_ptr_reg[3]_1 ,
    mem_out,
    mux_cmd_wren);
  output \rd_ptr_reg[0]_0 ;
  output \rd_ptr_reg[1]_0 ;
  output \rd_ptr_reg[2]_0 ;
  output \rd_ptr_reg[3]_0 ;
  output wr_en_3;
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [0:0]D2;
  output [1:0]D6;
  output [0:0]D7;
  output [3:0]Q;
  input ofifo_rst;
  input CLK;
  input calib_cmd_wren;
  input \wr_ptr_timing_reg[0]_0 ;
  input \rd_ptr_reg[3]_1 ;
  input [3:0]mem_out;
  input mux_cmd_wren;

  wire CLK;
  wire [0:0]D2;
  wire [1:0]D6;
  wire [0:0]D7;
  wire [3:0]Q;
  wire calib_cmd_wren;
  wire [3:0]mem_out;
  wire mux_cmd_wren;
  wire my_empty0;
  wire \my_empty[1]_i_1__0_n_0 ;
  wire \my_empty[6]_i_1_n_0 ;
  wire \my_empty[6]_i_3_n_0 ;
  wire \my_empty[6]_i_4_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg_n_0_[6] ;
  wire my_full0;
  wire \my_full[3]_i_1_n_0 ;
  wire \my_full[3]_i_3_n_0 ;
  wire \my_full[3]_i_4_n_0 ;
  wire \my_full_reg_n_0_[3] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire ofifo_rst;
  wire \rd_ptr_reg[0]_0 ;
  wire \rd_ptr_reg[1]_0 ;
  wire \rd_ptr_reg[2]_0 ;
  wire \rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg[3]_1 ;
  wire [3:0]rd_ptr_timing;
  wire \rd_ptr_timing[3]_i_1__0_n_0 ;
  wire wr_en_3;
  wire wr_ptr0__0;
  wire [3:0]wr_ptr_timing;
  wire \wr_ptr_timing_reg[0]_0 ;

  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[1]_i_1__0 
       (.I0(\rd_ptr_reg[3]_1 ),
        .I1(mux_cmd_wren),
        .I2(\my_full_reg_n_0_[3] ),
        .I3(\my_empty_reg[1]_0 ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[6]_i_1 
       (.I0(\rd_ptr_reg[3]_1 ),
        .I1(mux_cmd_wren),
        .I2(\my_full_reg_n_0_[3] ),
        .I3(\my_empty_reg_n_0_[6] ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[6]_i_2 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[6]_i_3_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[6]_i_4_n_0 ),
        .I4(\rd_ptr_reg[2]_0 ),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair468" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[6]_i_3 
       (.I0(wr_ptr_timing[1]),
        .I1(\rd_ptr_reg[0]_0 ),
        .I2(\rd_ptr_reg[1]_0 ),
        .I3(\rd_ptr_reg[3]_0 ),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[6]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair468" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[6]_i_4 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg[0]_0 ),
        .I3(\rd_ptr_reg[1]_0 ),
        .I4(\rd_ptr_reg[3]_0 ),
        .O(\my_empty[6]_i_4_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__0_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_empty[6]_i_1_n_0 ),
        .Q(\my_empty_reg_n_0_[6] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[3]_i_1 
       (.I0(my_full0),
        .I1(mux_cmd_wren),
        .I2(\rd_ptr_reg[3]_1 ),
        .I3(\my_empty_reg_n_0_[6] ),
        .I4(\my_full_reg_n_0_[3] ),
        .I5(ofifo_rst),
        .O(\my_full[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[3]_i_2 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[3]_i_3_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[3]_i_4_n_0 ),
        .I4(Q[2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair469" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[3]_i_3 
       (.I0(rd_ptr_timing[1]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair469" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[3]_i_4 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .O(\my_full[3]_i_4_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\my_full[3]_i_1_n_0 ),
        .Q(\my_full_reg_n_0_[3] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair470" *) 
  LUT2 #(
    .INIT(4'hE)) 
    out_fifo_i_10__1
       (.I0(mem_out[0]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2));
  (* SOFT_HLUTNM = "soft_lutpair470" *) 
  LUT4 #(
    .INIT(16'h00FD)) 
    out_fifo_i_1__0
       (.I0(\my_empty_reg[1]_0 ),
        .I1(\wr_ptr_timing_reg[0]_0 ),
        .I2(calib_cmd_wren),
        .I3(\rd_ptr_reg[3]_1 ),
        .O(\my_empty_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair475" *) 
  LUT2 #(
    .INIT(4'hE)) 
    out_fifo_i_30__1
       (.I0(mem_out[2]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D6[1]));
  (* SOFT_HLUTNM = "soft_lutpair475" *) 
  LUT2 #(
    .INIT(4'hE)) 
    out_fifo_i_34__1
       (.I0(mem_out[1]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D6[0]));
  LUT2 #(
    .INIT(4'hE)) 
    out_fifo_i_38__1
       (.I0(mem_out[3]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7));
  LUT5 #(
    .INIT(32'h27272700)) 
    p_17_out
       (.I0(\rd_ptr_reg[3]_1 ),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(calib_cmd_wren),
        .I4(\wr_ptr_timing_reg[0]_0 ),
        .O(wr_en_3));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg[0]_0 ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg[1]_0 ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg[2]_0 ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg[3]_0 ),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair473" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_timing[0]_i_1__0 
       (.I0(\rd_ptr_reg[3]_0 ),
        .I1(\rd_ptr_reg[0]_0 ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair473" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr_timing[1]_i_1__0 
       (.I0(\rd_ptr_reg[3]_0 ),
        .I1(\rd_ptr_reg[0]_0 ),
        .I2(\rd_ptr_reg[1]_0 ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair471" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_timing[2]_i_1__0 
       (.I0(\rd_ptr_reg[2]_0 ),
        .I1(\rd_ptr_reg[0]_0 ),
        .I2(\rd_ptr_reg[1]_0 ),
        .I3(\rd_ptr_reg[3]_0 ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_timing[3]_i_1__0 
       (.I0(\rd_ptr_reg[3]_1 ),
        .I1(\my_empty_reg_n_0_[6] ),
        .O(\rd_ptr_timing[3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair471" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr_timing[3]_i_2__0 
       (.I0(\rd_ptr_reg[3]_0 ),
        .I1(\rd_ptr_reg[1]_0 ),
        .I2(\rd_ptr_reg[0]_0 ),
        .I3(\rd_ptr_reg[2]_0 ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  LUT5 #(
    .INIT(32'h00E00EEE)) 
    wr_ptr0
       (.I0(calib_cmd_wren),
        .I1(\wr_ptr_timing_reg[0]_0 ),
        .I2(\rd_ptr_reg[3]_1 ),
        .I3(\my_full_reg_n_0_[3] ),
        .I4(\my_empty_reg_n_0_[6] ),
        .O(wr_ptr0__0));
  (* SOFT_HLUTNM = "soft_lutpair474" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__2 
       (.I0(Q[3]),
        .I1(Q[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair474" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1__2 
       (.I0(Q[3]),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair472" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__0 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .O(nxt_wr_ptr[2]));
  (* SOFT_HLUTNM = "soft_lutpair472" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_1__0 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[0]),
        .Q(Q[0]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[1]),
        .Q(Q[1]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[2]),
        .Q(Q[2]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[3]),
        .Q(Q[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(CLK),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_4lanes
   (A_rst_primitives_reg_0,
    \rd_ptr_reg[0] ,
    \rd_ptr_reg[1] ,
    \rd_ptr_reg[2] ,
    \rd_ptr_reg[3] ,
    out,
    A_rst_primitives_reg_1,
    mem_dq_out,
    mem_dq_ts,
    out_dqs_0,
    ts_dqs_0,
    pi_dqs_found_lanes,
    \rd_ptr_reg[0]_0 ,
    \rd_ptr_reg[1]_0 ,
    \rd_ptr_reg[2]_0 ,
    \rd_ptr_reg[3]_0 ,
    \rd_ptr_timing_reg[1] ,
    A_rst_primitives_reg_2,
    out_dqs_1,
    ts_dqs_1,
    \rd_ptr_reg[0]_1 ,
    \rd_ptr_reg[1]_1 ,
    \rd_ptr_reg[2]_1 ,
    \rd_ptr_reg[3]_1 ,
    phy_mc_ctl_full,
    ref_dll_lock,
    D,
    idelay_ld_rst,
    ddr_ck_out,
    \my_empty_reg[1] ,
    \my_empty_reg[1]_0 ,
    init_complete_r1_timing_reg,
    \my_empty_reg[1]_1 ,
    \my_empty_reg[1]_2 ,
    app_rd_data_valid,
    \my_empty_reg[0] ,
    \my_empty_reg[0]_0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    app_rd_data,
    \gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    \pi_counter_read_val_reg[5]_0 ,
    \pi_counter_read_val_reg[5]_1 ,
    phy_rddata_en,
    A_rst_primitives_reg_3,
    phy_mc_data_full,
    wr_en,
    wr_en_2,
    phy_mc_cmd_full,
    wr_en_3,
    \wr_ptr_reg[3] ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[3]_0 ,
    \my_empty_reg[4] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_reg[3]_1 ,
    \my_empty_reg[4]_rep__0 ,
    \po_counter_read_val_reg[8]_0 ,
    \rd_ptr_reg[3]_2 ,
    p_1_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    \po_counter_read_val_reg[8]_1 ,
    \po_counter_read_val_reg[8]_2 ,
    \po_counter_read_val_reg[8]_3 ,
    \po_counter_read_val_reg[8]_4 ,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    CLK,
    \rd_ptr_reg[3]_3 ,
    \rd_ptr_reg[3]_4 ,
    \rd_ptr_reg[3]_5 ,
    \rd_ptr_reg[3]_6 ,
    \rd_ptr_reg[3]_7 ,
    \rd_ptr_reg[3]_8 ,
    \rd_ptr_reg[3]_9 ,
    \rd_ptr_reg[3]_10 ,
    \rd_ptr_reg[3]_11 ,
    \rd_ptr_reg[3]_12 ,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0,
    CLKB0,
    \pi_dqs_found_lanes_r1_reg[2] ,
    \pi_dqs_found_lanes_r1_reg[2]_0 ,
    \pi_dqs_found_lanes_r1_reg[2]_1 ,
    \pi_dqs_found_lanes_r1_reg[2]_2 ,
    mem_dqs_in,
    \pi_dqs_found_lanes_r1_reg[2]_3 ,
    COUNTERLOADVAL,
    \po_counter_read_val_reg[8]_5 ,
    \po_counter_read_val_reg[8]_6 ,
    \po_counter_read_val_reg[8]_7 ,
    D0,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    D9,
    ififo_rst_reg0,
    ofifo_rst_reg0,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    LD0_0,
    CLKB0_4,
    \pi_dqs_found_lanes_r1_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    \pi_dqs_found_lanes_r1_reg[3]_1 ,
    \pi_dqs_found_lanes_r1_reg[3]_2 ,
    \pi_dqs_found_lanes_r1_reg[3]_3 ,
    \pi_dqs_found_lanes_r1_reg[3]_4 ,
    \po_counter_read_val_reg[8]_8 ,
    \po_counter_read_val_reg[8]_9 ,
    \po_counter_read_val_reg[8]_10 ,
    D1,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    ififo_rst_reg0_1,
    ofifo_rst_reg0_2,
    phy_ctl_wr_i2,
    pll_locked,
    phy_read_calib,
    in0,
    phy_write_calib,
    Q,
    RST0,
    SR,
    \po_counter_read_val_reg[8]_11 ,
    \po_counter_read_val_reg[8]_12 ,
    \po_counter_read_val_reg[8]_13 ,
    \po_counter_read_val_reg[8]_14 ,
    \my_empty_reg[7]_7 ,
    \my_empty_reg[7]_8 ,
    \my_empty_reg[7]_9 ,
    \my_empty_reg[7]_10 ,
    \my_empty_reg[7]_11 ,
    \my_empty_reg[7]_12 ,
    \my_empty_reg[7]_13 ,
    \my_empty_reg[7]_14 ,
    \wr_ptr_timing_reg[0] ,
    calib_cmd_wren,
    \wr_ptr_timing_reg[0]_0 ,
    mem_out,
    app_rd_data_valid_0,
    mux_wrdata_en,
    mc_wrdata_en,
    \wr_ptr_timing_reg[0]_1 ,
    calib_wrdata_en,
    out_fifo,
    app_rd_data_valid_1,
    \read_fifo.tail_r_reg ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    mux_cmd_wren,
    mc_address,
    mc_cas_n,
    phy_dout,
    \app_rd_data[112] ,
    calib_sel,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] );
  output A_rst_primitives_reg_0;
  output \rd_ptr_reg[0] ;
  output \rd_ptr_reg[1] ;
  output \rd_ptr_reg[2] ;
  output \rd_ptr_reg[3] ;
  output [1:0]out;
  output A_rst_primitives_reg_1;
  output [40:0]mem_dq_out;
  output [17:0]mem_dq_ts;
  output out_dqs_0;
  output ts_dqs_0;
  output [1:0]pi_dqs_found_lanes;
  output \rd_ptr_reg[0]_0 ;
  output \rd_ptr_reg[1]_0 ;
  output \rd_ptr_reg[2]_0 ;
  output \rd_ptr_reg[3]_0 ;
  output [1:0]\rd_ptr_timing_reg[1] ;
  output A_rst_primitives_reg_2;
  output out_dqs_1;
  output ts_dqs_1;
  output \rd_ptr_reg[0]_1 ;
  output \rd_ptr_reg[1]_1 ;
  output \rd_ptr_reg[2]_1 ;
  output \rd_ptr_reg[3]_1 ;
  output phy_mc_ctl_full;
  output ref_dll_lock;
  output [0:0]D;
  output idelay_ld_rst;
  output [1:0]ddr_ck_out;
  output \my_empty_reg[1] ;
  output \my_empty_reg[1]_0 ;
  output init_complete_r1_timing_reg;
  output \my_empty_reg[1]_1 ;
  output \my_empty_reg[1]_2 ;
  output app_rd_data_valid;
  output \my_empty_reg[0] ;
  output \my_empty_reg[0]_0 ;
  output \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  output [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output [127:0]app_rd_data;
  output \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  output \pi_counter_read_val_reg[5]_0 ;
  output [5:0]\pi_counter_read_val_reg[5]_1 ;
  output phy_rddata_en;
  output A_rst_primitives_reg_3;
  output phy_mc_data_full;
  output wr_en;
  output wr_en_2;
  output phy_mc_cmd_full;
  output wr_en_3;
  output [3:0]\wr_ptr_reg[3] ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1] ;
  output [3:0]\wr_ptr_reg[3]_0 ;
  output \my_empty_reg[4] ;
  output [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_0 ;
  output [3:0]\wr_ptr_reg[3]_1 ;
  output \my_empty_reg[4]_rep__0 ;
  output [8:0]\po_counter_read_val_reg[8]_0 ;
  output [35:0]\rd_ptr_reg[3]_2 ;
  output p_1_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  output \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input \po_counter_read_val_reg[8]_2 ;
  input \po_counter_read_val_reg[8]_3 ;
  input \po_counter_read_val_reg[8]_4 ;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input CLK;
  input [3:0]\rd_ptr_reg[3]_3 ;
  input [3:0]\rd_ptr_reg[3]_4 ;
  input [2:0]\rd_ptr_reg[3]_5 ;
  input [3:0]\rd_ptr_reg[3]_6 ;
  input [3:0]\rd_ptr_reg[3]_7 ;
  input [7:0]\rd_ptr_reg[3]_8 ;
  input [5:0]\rd_ptr_reg[3]_9 ;
  input [2:0]\rd_ptr_reg[3]_10 ;
  input [3:0]\rd_ptr_reg[3]_11 ;
  input [3:0]\rd_ptr_reg[3]_12 ;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [15:0]mem_dq_in;
  input idelay_inc;
  input LD0;
  input CLKB0;
  input \pi_dqs_found_lanes_r1_reg[2] ;
  input \pi_dqs_found_lanes_r1_reg[2]_0 ;
  input \pi_dqs_found_lanes_r1_reg[2]_1 ;
  input \pi_dqs_found_lanes_r1_reg[2]_2 ;
  input [1:0]mem_dqs_in;
  input \pi_dqs_found_lanes_r1_reg[2]_3 ;
  input [5:0]COUNTERLOADVAL;
  input \po_counter_read_val_reg[8]_5 ;
  input \po_counter_read_val_reg[8]_6 ;
  input \po_counter_read_val_reg[8]_7 ;
  input [7:0]D0;
  input [7:0]D2;
  input [7:0]D3;
  input [7:0]D4;
  input [7:0]D5;
  input [7:0]D6;
  input [7:0]D7;
  input [7:0]D8;
  input [7:0]D9;
  input ififo_rst_reg0;
  input ofifo_rst_reg0;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input LD0_0;
  input CLKB0_4;
  input \pi_dqs_found_lanes_r1_reg[3] ;
  input \pi_dqs_found_lanes_r1_reg[3]_0 ;
  input \pi_dqs_found_lanes_r1_reg[3]_1 ;
  input \pi_dqs_found_lanes_r1_reg[3]_2 ;
  input \pi_dqs_found_lanes_r1_reg[3]_3 ;
  input [5:0]\pi_dqs_found_lanes_r1_reg[3]_4 ;
  input \po_counter_read_val_reg[8]_8 ;
  input \po_counter_read_val_reg[8]_9 ;
  input \po_counter_read_val_reg[8]_10 ;
  input [7:0]D1;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input ififo_rst_reg0_1;
  input ofifo_rst_reg0_2;
  input phy_ctl_wr_i2;
  input pll_locked;
  input phy_read_calib;
  input in0;
  input phy_write_calib;
  input [10:0]Q;
  input RST0;
  input [0:0]SR;
  input \po_counter_read_val_reg[8]_11 ;
  input \po_counter_read_val_reg[8]_12 ;
  input \po_counter_read_val_reg[8]_13 ;
  input \po_counter_read_val_reg[8]_14 ;
  input [3:0]\my_empty_reg[7]_7 ;
  input [3:0]\my_empty_reg[7]_8 ;
  input [3:0]\my_empty_reg[7]_9 ;
  input [3:0]\my_empty_reg[7]_10 ;
  input [7:0]\my_empty_reg[7]_11 ;
  input [3:0]\my_empty_reg[7]_12 ;
  input [3:0]\my_empty_reg[7]_13 ;
  input [3:0]\my_empty_reg[7]_14 ;
  input \wr_ptr_timing_reg[0] ;
  input calib_cmd_wren;
  input \wr_ptr_timing_reg[0]_0 ;
  input [3:0]mem_out;
  input app_rd_data_valid_0;
  input mux_wrdata_en;
  input mc_wrdata_en;
  input \wr_ptr_timing_reg[0]_1 ;
  input calib_wrdata_en;
  input out_fifo;
  input [0:0]app_rd_data_valid_1;
  input [0:0]\read_fifo.tail_r_reg ;
  input [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input mux_cmd_wren;
  input [3:0]mc_address;
  input [0:0]mc_cas_n;
  input [38:0]phy_dout;
  input [63:0]\app_rd_data[112] ;
  input [1:0]calib_sel;
  input [0:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;

  (* async_reg = "true" *) wire A_pi_rst_div2;
  wire [8:0]A_po_counter_read_val;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire B_of_full;
  (* async_reg = "true" *) wire B_pi_rst_div2;
  wire CLK;
  wire CLKB0;
  wire CLKB0_4;
  wire [5:0]COUNTERLOADVAL;
  (* async_reg = "true" *) wire C_pi_rst_div2;
  wire [8:0]C_po_counter_read_val;
  wire [0:0]D;
  wire [7:0]D0;
  wire [7:0]D1;
  wire [7:0]D2;
  wire [7:0]D3;
  wire [7:0]D4;
  wire [7:0]D5;
  wire [7:0]D6;
  wire [7:0]D7;
  wire [7:0]D8;
  wire [7:0]D9;
  wire [5:0]D_pi_counter_read_val;
  (* async_reg = "true" *) wire D_pi_rst_div2;
  wire [8:0]D_po_counter_read_val;
  wire LD0;
  wire LD0_0;
  wire [10:0]Q;
  wire RST0;
  wire [0:0]SR;
  wire [127:0]app_rd_data;
  wire [63:0]\app_rd_data[112] ;
  wire app_rd_data_valid;
  wire app_rd_data_valid_0;
  wire [0:0]app_rd_data_valid_1;
  wire calib_cmd_wren;
  wire [1:0]calib_sel;
  wire calib_wrdata_en;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_23 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_24 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_25 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_26 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_27 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_28 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_29 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_30 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_31 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C_n_193 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C_n_194 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C_n_195 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C_n_196 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C_n_197 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C_n_198 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_24 ;
  wire [1:0]ddr_ck_out;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire [3:0]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;
  wire [3:0]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0 ;
  wire freq_refclk;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire [0:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire [3:3]if_empty_r;
  wire [3:3]if_empty_r_1;
  wire ififo_rst_reg0;
  wire ififo_rst_reg0_1;
  wire in0;
  wire init_complete_r1_timing_reg;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire [3:0]mc_address;
  wire [0:0]mc_cas_n;
  wire mc_wrdata_en;
  wire [15:0]mem_dq_in;
  wire [40:0]mem_dq_out;
  wire [17:0]mem_dq_ts;
  wire [1:0]mem_dqs_in;
  wire [3:0]mem_out;
  wire mem_refclk;
  wire mux_cmd_wren;
  wire mux_wrdata_en;
  wire \my_empty_reg[0] ;
  wire \my_empty_reg[0]_0 ;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[1]_2 ;
  wire \my_empty_reg[4] ;
  wire \my_empty_reg[4]_rep__0 ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [3:0]\my_empty_reg[7]_10 ;
  wire [7:0]\my_empty_reg[7]_11 ;
  wire [3:0]\my_empty_reg[7]_12 ;
  wire [3:0]\my_empty_reg[7]_13 ;
  wire [3:0]\my_empty_reg[7]_14 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire [3:0]\my_empty_reg[7]_7 ;
  wire [3:0]\my_empty_reg[7]_8 ;
  wire [3:0]\my_empty_reg[7]_9 ;
  wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg ;
  wire ofifo_rst;
  wire ofifo_rst_reg0;
  wire ofifo_rst_reg0_2;
  wire [1:0]out;
  wire out_dqs_0;
  wire out_dqs_1;
  wire out_fifo;
  wire p_1_in;
  wire [0:0]phaser_ctl_bus;
  wire phy_control_i_n_0;
  wire phy_control_i_n_1;
  wire phy_control_i_n_10;
  wire phy_control_i_n_11;
  wire phy_control_i_n_14;
  wire phy_control_i_n_15;
  wire phy_control_i_n_16;
  wire phy_control_i_n_17;
  wire phy_control_i_n_18;
  wire phy_control_i_n_19;
  wire phy_control_i_n_20;
  wire phy_control_i_n_21;
  wire phy_control_i_n_22;
  wire phy_control_i_n_23;
  wire phy_control_i_n_24;
  wire phy_control_i_n_3;
  wire phy_control_i_n_4;
  wire phy_control_i_n_5;
  wire phy_control_i_n_6;
  wire phy_control_i_n_7;
  wire phy_control_i_n_8;
  wire phy_control_i_n_9;
  wire phy_ctl_wr_i2;
  wire [38:0]phy_dout;
  wire [1:0]phy_encalib;
  wire phy_mc_cmd_full;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire phy_rddata_en;
  wire phy_read_calib;
  wire phy_write_calib;
  wire \pi_counter_read_val_reg[5]_0 ;
  wire [5:0]\pi_counter_read_val_reg[5]_1 ;
  wire [1:0]pi_dqs_found_lanes;
  wire \pi_dqs_found_lanes_r1_reg[2] ;
  wire \pi_dqs_found_lanes_r1_reg[2]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_2 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire \pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_2 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_3 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[3]_4 ;
  wire pll_locked;
  wire [8:0]\po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire \po_counter_read_val_reg[8]_10 ;
  wire \po_counter_read_val_reg[8]_11 ;
  wire \po_counter_read_val_reg[8]_12 ;
  wire \po_counter_read_val_reg[8]_13 ;
  wire \po_counter_read_val_reg[8]_14 ;
  wire \po_counter_read_val_reg[8]_2 ;
  wire \po_counter_read_val_reg[8]_3 ;
  wire \po_counter_read_val_reg[8]_4 ;
  wire \po_counter_read_val_reg[8]_5 ;
  wire \po_counter_read_val_reg[8]_6 ;
  wire \po_counter_read_val_reg[8]_7 ;
  wire \po_counter_read_val_reg[8]_8 ;
  wire \po_counter_read_val_reg[8]_9 ;
  wire rclk_delay_11;
  wire \rclk_delay_reg[10]_srl11_i_1_n_0 ;
  wire \rclk_delay_reg[10]_srl11_n_0 ;
  wire \rd_ptr_reg[0] ;
  wire \rd_ptr_reg[0]_0 ;
  wire \rd_ptr_reg[0]_1 ;
  wire \rd_ptr_reg[1] ;
  wire \rd_ptr_reg[1]_0 ;
  wire \rd_ptr_reg[1]_1 ;
  wire \rd_ptr_reg[2] ;
  wire \rd_ptr_reg[2]_0 ;
  wire \rd_ptr_reg[2]_1 ;
  wire \rd_ptr_reg[3] ;
  wire \rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg[3]_1 ;
  wire [2:0]\rd_ptr_reg[3]_10 ;
  wire [3:0]\rd_ptr_reg[3]_11 ;
  wire [3:0]\rd_ptr_reg[3]_12 ;
  wire [35:0]\rd_ptr_reg[3]_2 ;
  wire [3:0]\rd_ptr_reg[3]_3 ;
  wire [3:0]\rd_ptr_reg[3]_4 ;
  wire [2:0]\rd_ptr_reg[3]_5 ;
  wire [3:0]\rd_ptr_reg[3]_6 ;
  wire [3:0]\rd_ptr_reg[3]_7 ;
  wire [7:0]\rd_ptr_reg[3]_8 ;
  wire [5:0]\rd_ptr_reg[3]_9 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire [0:0]\read_fifo.tail_r_reg ;
  wire ref_dll_lock;
  wire rst_out_i_1_n_0;
  wire rst_out_reg_n_0;
  wire rst_primitives;
  wire rst_primitives_i_1_n_0;
  wire sync_pulse;
  wire ts_dqs_0;
  wire ts_dqs_1;
  wire wr_en;
  wire wr_en_2;
  wire wr_en_3;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire [3:0]\wr_ptr_reg[3] ;
  wire [3:0]\wr_ptr_reg[3]_0 ;
  wire [3:0]\wr_ptr_reg[3]_1 ;
  wire \wr_ptr_timing_reg[0] ;
  wire \wr_ptr_timing_reg[0]_0 ;
  wire \wr_ptr_timing_reg[0]_1 ;

  FDRE #(
    .INIT(1'b0)) 
    A_rst_primitives_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_primitives),
        .Q(A_rst_primitives_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \FSM_onehot_cal1_state_r[16]_i_2 
       (.I0(\pi_counter_read_val_reg[5]_1 [5]),
        .I1(\pi_counter_read_val_reg[5]_1 [3]),
        .I2(\pi_counter_read_val_reg[5]_1 [0]),
        .I3(\pi_counter_read_val_reg[5]_1 [2]),
        .I4(\pi_counter_read_val_reg[5]_1 [1]),
        .I5(\pi_counter_read_val_reg[5]_1 [4]),
        .O(\pi_counter_read_val_reg[5]_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_lane \ddr_byte_lane_A.ddr_byte_lane_A 
       (.B_of_full(B_of_full),
        .CLK(CLK),
        .COUNTERREADVAL(A_po_counter_read_val),
        .OUTBURSTPENDING(phaser_ctl_bus),
        .PCENABLECALIB(phy_encalib),
        .calib_cmd_wren(calib_cmd_wren),
        .ddr_ck_out(ddr_ck_out),
        .freq_refclk(freq_refclk),
        .mc_address(mc_address),
        .mc_cas_n(mc_cas_n),
        .mem_dq_out(mem_dq_out[10:0]),
        .mem_refclk(mem_refclk),
        .mux_cmd_wren(mux_cmd_wren),
        .\my_empty_reg[1] (\my_empty_reg[1] ),
        .\my_empty_reg[7] (\my_empty_reg[7]_7 ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_8 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_9 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_10 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_11 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_12 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_13 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_14 ),
        .ofifo_rst(ofifo_rst),
        .ofifo_rst_reg_0(A_rst_primitives_reg_0),
        .phy_dout(phy_dout),
        .phy_mc_cmd_full(phy_mc_cmd_full),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_11 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_12 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_13 ),
        .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_14 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3]_2 ),
        .sync_pulse(sync_pulse),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0] ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_lane__parameterized0 \ddr_byte_lane_B.ddr_byte_lane_B 
       (.B_of_full(B_of_full),
        .CLK(CLK),
        .COUNTERREADVAL(A_po_counter_read_val),
        .D({\ddr_byte_lane_B.ddr_byte_lane_B_n_23 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_24 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_25 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_26 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_27 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_28 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_29 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_30 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_31 }),
        .OUTBURSTPENDING(phy_control_i_n_24),
        .PCENABLECALIB(phy_encalib),
        .Q(\wr_ptr_reg[3] ),
        .calib_cmd_wren(calib_cmd_wren),
        .calib_sel(calib_sel),
        .freq_refclk(freq_refclk),
        .mem_dq_out(mem_dq_out[22:11]),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .mux_cmd_wren(mux_cmd_wren),
        .\my_empty_reg[1] (\my_empty_reg[1]_0 ),
        .ofifo_rst(ofifo_rst),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_1 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_2 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_3 ),
        .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_4 ),
        .\po_counter_read_val_reg[8]_3 (A_rst_primitives_reg_0),
        .\po_counter_read_val_reg[8]_4 (D_po_counter_read_val),
        .\po_counter_read_val_reg[8]_5 (C_po_counter_read_val),
        .\rd_ptr_reg[0] (\rd_ptr_reg[0] ),
        .\rd_ptr_reg[1] (\rd_ptr_reg[1] ),
        .\rd_ptr_reg[2] (\rd_ptr_reg[2] ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3] ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_3 ),
        .\rd_ptr_reg[3]_1 (\rd_ptr_reg[3]_4 ),
        .\rd_ptr_reg[3]_2 (\rd_ptr_reg[3]_5 ),
        .\rd_ptr_reg[3]_3 (\rd_ptr_reg[3]_6 ),
        .\rd_ptr_reg[3]_4 (\rd_ptr_reg[3]_7 ),
        .\rd_ptr_reg[3]_5 (\rd_ptr_reg[3]_8 ),
        .\rd_ptr_reg[3]_6 (\rd_ptr_reg[3]_9 ),
        .\rd_ptr_reg[3]_7 (\rd_ptr_reg[3]_10 ),
        .\rd_ptr_reg[3]_8 (\rd_ptr_reg[3]_11 ),
        .\rd_ptr_reg[3]_9 (\rd_ptr_reg[3]_12 ),
        .sync_pulse(sync_pulse),
        .wr_en_3(wr_en_3),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0]_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_lane__parameterized1 \ddr_byte_lane_C.ddr_byte_lane_C 
       (.A_rst_primitives_reg(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_0(C_po_counter_read_val),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_3),
        .CLK(CLK),
        .CLKB0(CLKB0),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .COUNTERREADVAL(D_pi_counter_read_val),
        .D({\ddr_byte_lane_C.ddr_byte_lane_C_n_193 ,\ddr_byte_lane_C.ddr_byte_lane_C_n_194 ,\ddr_byte_lane_C.ddr_byte_lane_C_n_195 ,\ddr_byte_lane_C.ddr_byte_lane_C_n_196 ,\ddr_byte_lane_C.ddr_byte_lane_C_n_197 ,\ddr_byte_lane_C.ddr_byte_lane_C_n_198 }),
        .D0(D0),
        .D2(D2),
        .D3(D3),
        .D4(D4),
        .D5(D5),
        .D6(D6),
        .D7(D7),
        .D8(D8),
        .D9(D9),
        .INBURSTPENDING(phy_control_i_n_19),
        .INRANKC({phy_control_i_n_8,phy_control_i_n_9}),
        .LD0(LD0),
        .OUTBURSTPENDING(phy_control_i_n_23),
        .PCENABLECALIB(phy_encalib),
        .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg ),
        .app_rd_data({app_rd_data[119:112],app_rd_data[103:96],app_rd_data[87:80],app_rd_data[71:64],app_rd_data[55:48],app_rd_data[39:32],app_rd_data[23:16],app_rd_data[7:0]}),
        .\app_rd_data[112] (\app_rd_data[112] ),
        .calib_sel(calib_sel),
        .calib_wrdata_en(calib_wrdata_en),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ({app_rd_data[127:120],app_rd_data[111:104],app_rd_data[95:88],app_rd_data[79:72],app_rd_data[63:56],app_rd_data[47:40],app_rd_data[31:24],app_rd_data[15:8]}),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(idelay_ld_rst),
        .idelay_ld_rst_reg(A_rst_primitives_reg_0),
        .if_empty_r(if_empty_r),
        .if_empty_r_0(if_empty_r_1),
        .ififo_rst_reg0(ififo_rst_reg0),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq ),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_dq_in(mem_dq_in[7:0]),
        .mem_dq_out(mem_dq_out[31:23]),
        .mem_dq_ts(mem_dq_ts[8:0]),
        .mem_dqs_in(mem_dqs_in[0]),
        .mem_refclk(mem_refclk),
        .mux_wrdata_en(mux_wrdata_en),
        .my_empty({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0 [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0 [0]}),
        .\my_empty_reg[1] (\my_empty_reg[1]_1 ),
        .\my_empty_reg[3] ({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty [0]}),
        .\my_empty_reg[4] (\my_empty_reg[4] ),
        .ofifo_rst_reg0(ofifo_rst_reg0),
        .out(out),
        .out_dqs_0(out_dqs_0),
        .phy_mc_data_full(phy_mc_data_full),
        .phy_rddata_en(phy_rddata_en),
        .pi_dqs_found_lanes(pi_dqs_found_lanes[0]),
        .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[2] ),
        .\pi_dqs_found_lanes_r1_reg[2]_0 (\pi_dqs_found_lanes_r1_reg[2]_0 ),
        .\pi_dqs_found_lanes_r1_reg[2]_1 (\pi_dqs_found_lanes_r1_reg[2]_1 ),
        .\pi_dqs_found_lanes_r1_reg[2]_2 (\pi_dqs_found_lanes_r1_reg[2]_2 ),
        .\pi_dqs_found_lanes_r1_reg[2]_3 (\pi_dqs_found_lanes_r1_reg[2]_3 ),
        .pi_phase_locked_all_r1_reg(\ddr_byte_lane_D.ddr_byte_lane_D_n_24 ),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_5 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_6 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_7 ),
        .\rd_ptr_reg[0] (\rd_ptr_reg[0]_0 ),
        .\rd_ptr_reg[1] (\rd_ptr_reg[1]_0 ),
        .\rd_ptr_reg[2] (\rd_ptr_reg[2]_0 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3]_0 ),
        .\read_fifo.tail_r_reg[1] (app_rd_data_valid_0),
        .sync_pulse(sync_pulse),
        .ts_dqs_0(ts_dqs_0),
        .wr_en_2(wr_en_2),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1] ),
        .\wr_ptr_reg[3] (\wr_ptr_reg[3]_0 ),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0]_1 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_byte_lane__parameterized2 \ddr_byte_lane_D.ddr_byte_lane_D 
       (.A_rst_primitives_reg(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_0(\ddr_byte_lane_D.ddr_byte_lane_D_n_24 ),
        .A_rst_primitives_reg_1(D_po_counter_read_val),
        .CLK(CLK),
        .CLKB0_4(CLKB0_4),
        .COUNTERREADVAL(D_pi_counter_read_val),
        .D1(D1),
        .INBURSTPENDING(phy_control_i_n_18),
        .INRANKD({phy_control_i_n_10,phy_control_i_n_11}),
        .LD0_0(LD0_0),
        .OUTBURSTPENDING(phy_control_i_n_22),
        .PCENABLECALIB(phy_encalib),
        .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg ),
        .app_rd_data({app_rd_data[119:112],app_rd_data[103:96],app_rd_data[87:80],app_rd_data[71:64],app_rd_data[55:48],app_rd_data[39:32],app_rd_data[23:16],app_rd_data[7:0]}),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rd_data_valid_0(app_rd_data_valid_0),
        .app_rd_data_valid_1(app_rd_data_valid_1),
        .calib_wrdata_en(calib_wrdata_en),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ({app_rd_data[127:120],app_rd_data[111:104],app_rd_data[95:88],app_rd_data[79:72],app_rd_data[63:56],app_rd_data[47:40],app_rd_data[31:24],app_rd_data[15:8]}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg0 (\gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg0 (\gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg0 (\gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg0 (\gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg0 (\gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg0 (\gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg0 (\gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg0 (\gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg0 (\gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg0 (\gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg0 (\gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg0 (\gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg0 (\gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg0 (\gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg0 (\gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg0 (\gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg0 (\gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg0 (\gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg0 (\gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg0 (\gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg0 (\gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg0 (\gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg0 (\gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg0 (\gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg0 (\gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg0 (\gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg0 (\gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg0 (\gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg0 (\gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg0 (\gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg0 (\gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg0 (\gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg0 (\gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg0 (\gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg0 (\gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg0 (\gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg0 (\gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg0 (\gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg0 (\gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg0 (\gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg0 (\gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg0 (\gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg0 (\gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg0 (\gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg0 (\gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg0 (\gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg0 (\gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg0 (\gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg0 (\gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg0 (\gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg0 (\gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg0 (\gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg0 (\gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg0 (\gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg0 (\gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg0 (\gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg0 (\gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg0 (\gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg0 (\gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg0 (\gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg0 (\gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg0 (\gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg0 (\gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg0 (\gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .idelay_inc(idelay_inc),
        .if_empty_r(if_empty_r_1),
        .if_empty_r_0(if_empty_r),
        .ififo_rst_reg0_1(ififo_rst_reg0_1),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq_0 ),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_dq_in(mem_dq_in[15:8]),
        .mem_dq_out(mem_dq_out[40:32]),
        .mem_dq_ts(mem_dq_ts[17:9]),
        .mem_dqs_in(mem_dqs_in[1]),
        .mem_refclk(mem_refclk),
        .mux_wrdata_en(mux_wrdata_en),
        .\my_empty_reg[0] (\my_empty_reg[0] ),
        .\my_empty_reg[0]_0 (\my_empty_reg[0]_0 ),
        .\my_empty_reg[1] (\my_empty_reg[1]_2 ),
        .\my_empty_reg[3] ({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0 [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_0 [0]}),
        .\my_empty_reg[4]_rep__0 (\my_empty_reg[4]_rep__0 ),
        .\my_empty_reg[4]_rep__1 ({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty [0]}),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_3 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_4 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_5 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_6 ),
        .ofifo_rst_reg0_2(ofifo_rst_reg0_2),
        .out_dqs_1(out_dqs_1),
        .out_fifo_0(out_fifo),
        .p_1_in(p_1_in),
        .pi_dqs_found_lanes(pi_dqs_found_lanes[1]),
        .\pi_dqs_found_lanes_r1_reg[3] (A_rst_primitives_reg_0),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (\pi_dqs_found_lanes_r1_reg[3] ),
        .\pi_dqs_found_lanes_r1_reg[3]_1 (\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .\pi_dqs_found_lanes_r1_reg[3]_2 (\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .\pi_dqs_found_lanes_r1_reg[3]_3 (\pi_dqs_found_lanes_r1_reg[3]_2 ),
        .\pi_dqs_found_lanes_r1_reg[3]_4 (\pi_dqs_found_lanes_r1_reg[3]_3 ),
        .\pi_dqs_found_lanes_r1_reg[3]_5 (\pi_dqs_found_lanes_r1_reg[3]_4 ),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_8 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_9 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_10 ),
        .\rd_ptr_reg[0] (\rd_ptr_reg[0]_1 ),
        .\rd_ptr_reg[1] (\rd_ptr_reg[1]_1 ),
        .\rd_ptr_reg[2] (\rd_ptr_reg[2]_1 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3]_1 ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .\read_fifo.tail_r_reg (\read_fifo.tail_r_reg ),
        .sync_pulse(sync_pulse),
        .ts_dqs_1(ts_dqs_1),
        .wr_en(wr_en),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0]_0 ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_reg[3] (\wr_ptr_reg[3]_1 ),
        .\wr_ptr_timing_reg[0] (\wr_ptr_timing_reg[0]_1 ));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(A_pi_rst_div2));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(B_pi_rst_div2));
  LUT1 #(
    .INIT(2'h2)) 
    i_2
       (.I0(1'b0),
        .O(C_pi_rst_div2));
  LUT1 #(
    .INIT(2'h2)) 
    i_3
       (.I0(1'b0),
        .O(D_pi_rst_div2));
  FDRE #(
    .INIT(1'b0)) 
    mcGo_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_out_reg_n_0),
        .Q(D),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_REF #(
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0)) 
    phaser_ref_i
       (.CLKIN(freq_refclk),
        .LOCKED(ref_dll_lock),
        .PWRDWN(1'b0),
        .RST(RST0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHY_CONTROL #(
    .AO_TOGGLE(1),
    .AO_WRLVL_EN(4'b0000),
    .BURST_MODE("TRUE"),
    .CLK_RATIO(4),
    .CMD_OFFSET(8),
    .CO_DURATION(1),
    .DATA_CTL_A_N("FALSE"),
    .DATA_CTL_B_N("FALSE"),
    .DATA_CTL_C_N("TRUE"),
    .DATA_CTL_D_N("TRUE"),
    .DISABLE_SEQ_MATCH("TRUE"),
    .DI_DURATION(1),
    .DO_DURATION(1),
    .EVENTS_DELAY(18),
    .FOUR_WINDOW_CLOCKS(63),
    .MULTI_REGION("FALSE"),
    .PHY_COUNT_ENABLE("FALSE"),
    .RD_CMD_OFFSET_0(10),
    .RD_CMD_OFFSET_1(10),
    .RD_CMD_OFFSET_2(10),
    .RD_CMD_OFFSET_3(10),
    .RD_DURATION_0(6),
    .RD_DURATION_1(6),
    .RD_DURATION_2(6),
    .RD_DURATION_3(6),
    .SYNC_MODE("FALSE"),
    .WR_CMD_OFFSET_0(8),
    .WR_CMD_OFFSET_1(8),
    .WR_CMD_OFFSET_2(8),
    .WR_CMD_OFFSET_3(8),
    .WR_DURATION_0(7),
    .WR_DURATION_1(7),
    .WR_DURATION_2(7),
    .WR_DURATION_3(7)) 
    phy_control_i
       (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}),
        .INBURSTPENDING({phy_control_i_n_18,phy_control_i_n_19,phy_control_i_n_20,phy_control_i_n_21}),
        .INRANKA({phy_control_i_n_4,phy_control_i_n_5}),
        .INRANKB({phy_control_i_n_6,phy_control_i_n_7}),
        .INRANKC({phy_control_i_n_8,phy_control_i_n_9}),
        .INRANKD({phy_control_i_n_10,phy_control_i_n_11}),
        .MEMREFCLK(mem_refclk),
        .OUTBURSTPENDING({phy_control_i_n_22,phy_control_i_n_23,phy_control_i_n_24,phaser_ctl_bus}),
        .PCENABLECALIB(phy_encalib),
        .PHYCLK(CLK),
        .PHYCTLALMOSTFULL(phy_control_i_n_0),
        .PHYCTLEMPTY(phy_control_i_n_1),
        .PHYCTLFULL(phy_mc_ctl_full),
        .PHYCTLMSTREMPTY(phy_control_i_n_1),
        .PHYCTLREADY(phy_control_i_n_3),
        .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,Q[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,Q[2:0]}),
        .PHYCTLWRENABLE(phy_ctl_wr_i2),
        .PLLLOCK(pll_locked),
        .READCALIBENABLE(phy_read_calib),
        .REFDLLLOCK(ref_dll_lock),
        .RESET(in0),
        .SYNCIN(sync_pulse),
        .WRITECALIBENABLE(phy_write_calib));
  FDRE \pi_counter_read_val_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_C.ddr_byte_lane_C_n_198 ),
        .Q(\pi_counter_read_val_reg[5]_1 [0]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_C.ddr_byte_lane_C_n_197 ),
        .Q(\pi_counter_read_val_reg[5]_1 [1]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_C.ddr_byte_lane_C_n_196 ),
        .Q(\pi_counter_read_val_reg[5]_1 [2]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_C.ddr_byte_lane_C_n_195 ),
        .Q(\pi_counter_read_val_reg[5]_1 [3]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_C.ddr_byte_lane_C_n_194 ),
        .Q(\pi_counter_read_val_reg[5]_1 [4]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_C.ddr_byte_lane_C_n_193 ),
        .Q(\pi_counter_read_val_reg[5]_1 [5]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_31 ),
        .Q(\po_counter_read_val_reg[8]_0 [0]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_30 ),
        .Q(\po_counter_read_val_reg[8]_0 [1]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_29 ),
        .Q(\po_counter_read_val_reg[8]_0 [2]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_28 ),
        .Q(\po_counter_read_val_reg[8]_0 [3]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_27 ),
        .Q(\po_counter_read_val_reg[8]_0 [4]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_26 ),
        .Q(\po_counter_read_val_reg[8]_0 [5]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_25 ),
        .Q(\po_counter_read_val_reg[8]_0 [6]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_24 ),
        .Q(\po_counter_read_val_reg[8]_0 [7]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_23 ),
        .Q(\po_counter_read_val_reg[8]_0 [8]),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 " *) 
  SRL16E \rclk_delay_reg[10]_srl11 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(CLK),
        .D(\rclk_delay_reg[10]_srl11_i_1_n_0 ),
        .Q(\rclk_delay_reg[10]_srl11_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rclk_delay_reg[10]_srl11_i_1 
       (.I0(rst_primitives),
        .O(\rclk_delay_reg[10]_srl11_i_1_n_0 ));
  FDRE \rclk_delay_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rclk_delay_reg[10]_srl11_n_0 ),
        .Q(rclk_delay_11),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    rst_out_i_1
       (.I0(rclk_delay_11),
        .I1(rst_out_reg_n_0),
        .O(rst_out_i_1_n_0));
  FDCE #(
    .INIT(1'b0)) 
    rst_out_reg
       (.C(CLK),
        .CE(1'b1),
        .CLR(SR),
        .D(rst_out_i_1_n_0),
        .Q(rst_out_reg_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    rst_primitives_i_1
       (.I0(phy_control_i_n_3),
        .O(rst_primitives_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rst_primitives_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_primitives_i_1_n_0),
        .Q(rst_primitives),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay
   (ck_addr_cmd_delay_done,
    cmd_po_en_stg2_f,
    po_cnt_dec_3,
    \ctl_lane_cnt_reg[0]_0 ,
    \ctl_lane_cnt_reg[1]_0 ,
    CLK,
    in0,
    p_1_in,
    \wait_cnt_r_reg[0]_0 ,
    \wait_cnt_r_reg[0]_1 ,
    \delaydec_cnt_r_reg[4]_0 ,
    cmd_delay_start0,
    rd_data_offset_cal_done,
    \gen_byte_sel_div2.ctl_lane_sel_reg[1] ,
    \gen_byte_sel_div2.ctl_lane_sel_reg[1]_0 ,
    \wait_cnt_r_reg[0]_2 );
  output ck_addr_cmd_delay_done;
  output cmd_po_en_stg2_f;
  output po_cnt_dec_3;
  output [0:0]\ctl_lane_cnt_reg[0]_0 ;
  output \ctl_lane_cnt_reg[1]_0 ;
  input CLK;
  input in0;
  input p_1_in;
  input \wait_cnt_r_reg[0]_0 ;
  input \wait_cnt_r_reg[0]_1 ;
  input \delaydec_cnt_r_reg[4]_0 ;
  input cmd_delay_start0;
  input rd_data_offset_cal_done;
  input \gen_byte_sel_div2.ctl_lane_sel_reg[1] ;
  input \gen_byte_sel_div2.ctl_lane_sel_reg[1]_0 ;
  input [0:0]\wait_cnt_r_reg[0]_2 ;

  wire CLK;
  wire ck_addr_cmd_delay_done;
  wire cmd_delay_start0;
  wire cmd_po_en_stg2_f;
  wire [1:1]ctl_lane_cnt;
  wire \ctl_lane_cnt[0]_i_1_n_0 ;
  wire \ctl_lane_cnt[1]_i_1_n_0 ;
  wire \ctl_lane_cnt[1]_i_3_n_0 ;
  wire [0:0]\ctl_lane_cnt_reg[0]_0 ;
  wire \ctl_lane_cnt_reg[1]_0 ;
  wire delay_dec_done;
  wire delay_dec_done_i_1_n_0;
  wire delay_dec_done_i_2_n_0;
  wire delay_done_r3_reg_srl3_n_0;
  wire delaydec_cnt_r0;
  wire [5:1]delaydec_cnt_r0__0;
  wire \delaydec_cnt_r[0]_i_1_n_0 ;
  wire \delaydec_cnt_r[5]_i_1_n_0 ;
  wire [5:0]delaydec_cnt_r_reg;
  wire \delaydec_cnt_r_reg[4]_0 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[1] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[1]_0 ;
  wire in0;
  wire p_1_in;
  wire po_cnt_dec_3;
  wire po_cnt_dec_i_1__0_n_0;
  wire rd_data_offset_cal_done;
  wire wait_cnt_r0;
  wire [3:0]wait_cnt_r0__0;
  wire [3:0]wait_cnt_r_reg;
  wire \wait_cnt_r_reg[0]_0 ;
  wire \wait_cnt_r_reg[0]_1 ;
  wire [0:0]\wait_cnt_r_reg[0]_2 ;

  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT5 #(
    .INIT(32'h0000CCC7)) 
    \ctl_lane_cnt[0]_i_1 
       (.I0(ctl_lane_cnt),
        .I1(\ctl_lane_cnt_reg[0]_0 ),
        .I2(delaydec_cnt_r_reg[0]),
        .I3(\ctl_lane_cnt[1]_i_3_n_0 ),
        .I4(p_1_in),
        .O(\ctl_lane_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT5 #(
    .INIT(32'h54550000)) 
    \ctl_lane_cnt[1]_i_1 
       (.I0(p_1_in),
        .I1(\ctl_lane_cnt[1]_i_3_n_0 ),
        .I2(delaydec_cnt_r_reg[0]),
        .I3(\ctl_lane_cnt_reg[0]_0 ),
        .I4(ctl_lane_cnt),
        .O(\ctl_lane_cnt[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \ctl_lane_cnt[1]_i_3 
       (.I0(delaydec_cnt_r_reg[4]),
        .I1(delaydec_cnt_r_reg[2]),
        .I2(delaydec_cnt_r_reg[1]),
        .I3(delaydec_cnt_r_reg[3]),
        .I4(delaydec_cnt_r_reg[5]),
        .O(\ctl_lane_cnt[1]_i_3_n_0 ));
  FDRE \ctl_lane_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ctl_lane_cnt[0]_i_1_n_0 ),
        .Q(\ctl_lane_cnt_reg[0]_0 ),
        .R(1'b0));
  FDRE \ctl_lane_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ctl_lane_cnt[1]_i_1_n_0 ),
        .Q(ctl_lane_cnt),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000AAAE0000)) 
    delay_dec_done_i_1
       (.I0(delay_dec_done),
        .I1(\ctl_lane_cnt_reg[0]_0 ),
        .I2(ctl_lane_cnt),
        .I3(delay_dec_done_i_2_n_0),
        .I4(cmd_delay_start0),
        .I5(\delaydec_cnt_r_reg[4]_0 ),
        .O(delay_dec_done_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    delay_dec_done_i_2
       (.I0(delaydec_cnt_r_reg[5]),
        .I1(delaydec_cnt_r_reg[3]),
        .I2(delaydec_cnt_r_reg[1]),
        .I3(delaydec_cnt_r_reg[2]),
        .I4(delaydec_cnt_r_reg[4]),
        .I5(delaydec_cnt_r_reg[0]),
        .O(delay_dec_done_i_2_n_0));
  FDRE delay_dec_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(delay_dec_done_i_1_n_0),
        .Q(delay_dec_done),
        .R(1'b0));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r3_reg_srl3 " *) 
  SRL16E delay_done_r3_reg_srl3
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(delay_dec_done),
        .Q(delay_done_r3_reg_srl3_n_0));
  (* syn_maxfan = "10" *) 
  FDRE delay_done_r4_reg
       (.C(CLK),
        .CE(1'b1),
        .D(delay_done_r3_reg_srl3_n_0),
        .Q(ck_addr_cmd_delay_done),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \delaydec_cnt_r[0]_i_1 
       (.I0(delaydec_cnt_r_reg[0]),
        .O(\delaydec_cnt_r[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \delaydec_cnt_r[1]_i_1 
       (.I0(delaydec_cnt_r_reg[1]),
        .I1(delaydec_cnt_r_reg[0]),
        .O(delaydec_cnt_r0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \delaydec_cnt_r[2]_i_1 
       (.I0(delaydec_cnt_r_reg[0]),
        .I1(delaydec_cnt_r_reg[1]),
        .I2(delaydec_cnt_r_reg[2]),
        .O(delaydec_cnt_r0__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \delaydec_cnt_r[3]_i_1 
       (.I0(delaydec_cnt_r_reg[0]),
        .I1(delaydec_cnt_r_reg[2]),
        .I2(delaydec_cnt_r_reg[1]),
        .I3(delaydec_cnt_r_reg[3]),
        .O(delaydec_cnt_r0__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \delaydec_cnt_r[4]_i_1 
       (.I0(delaydec_cnt_r_reg[0]),
        .I1(delaydec_cnt_r_reg[3]),
        .I2(delaydec_cnt_r_reg[1]),
        .I3(delaydec_cnt_r_reg[2]),
        .I4(delaydec_cnt_r_reg[4]),
        .O(delaydec_cnt_r0__0[4]));
  LUT6 #(
    .INIT(64'hFFFFFFFF45FFFFFF)) 
    \delaydec_cnt_r[5]_i_1 
       (.I0(delay_dec_done_i_2_n_0),
        .I1(ctl_lane_cnt),
        .I2(\ctl_lane_cnt_reg[0]_0 ),
        .I3(\wait_cnt_r_reg[0]_0 ),
        .I4(\wait_cnt_r_reg[0]_1 ),
        .I5(\delaydec_cnt_r_reg[4]_0 ),
        .O(\delaydec_cnt_r[5]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \delaydec_cnt_r[5]_i_2 
       (.I0(delay_dec_done_i_2_n_0),
        .I1(po_cnt_dec_3),
        .O(delaydec_cnt_r0));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    \delaydec_cnt_r[5]_i_3 
       (.I0(delaydec_cnt_r_reg[0]),
        .I1(delaydec_cnt_r_reg[4]),
        .I2(delaydec_cnt_r_reg[2]),
        .I3(delaydec_cnt_r_reg[1]),
        .I4(delaydec_cnt_r_reg[3]),
        .I5(delaydec_cnt_r_reg[5]),
        .O(delaydec_cnt_r0__0[5]));
  FDSE \delaydec_cnt_r_reg[0] 
       (.C(CLK),
        .CE(delaydec_cnt_r0),
        .D(\delaydec_cnt_r[0]_i_1_n_0 ),
        .Q(delaydec_cnt_r_reg[0]),
        .S(\delaydec_cnt_r[5]_i_1_n_0 ));
  FDRE \delaydec_cnt_r_reg[1] 
       (.C(CLK),
        .CE(delaydec_cnt_r0),
        .D(delaydec_cnt_r0__0[1]),
        .Q(delaydec_cnt_r_reg[1]),
        .R(\delaydec_cnt_r[5]_i_1_n_0 ));
  FDSE \delaydec_cnt_r_reg[2] 
       (.C(CLK),
        .CE(delaydec_cnt_r0),
        .D(delaydec_cnt_r0__0[2]),
        .Q(delaydec_cnt_r_reg[2]),
        .S(\delaydec_cnt_r[5]_i_1_n_0 ));
  FDSE \delaydec_cnt_r_reg[3] 
       (.C(CLK),
        .CE(delaydec_cnt_r0),
        .D(delaydec_cnt_r0__0[3]),
        .Q(delaydec_cnt_r_reg[3]),
        .S(\delaydec_cnt_r[5]_i_1_n_0 ));
  FDSE \delaydec_cnt_r_reg[4] 
       (.C(CLK),
        .CE(delaydec_cnt_r0),
        .D(delaydec_cnt_r0__0[4]),
        .Q(delaydec_cnt_r_reg[4]),
        .S(\delaydec_cnt_r[5]_i_1_n_0 ));
  FDRE \delaydec_cnt_r_reg[5] 
       (.C(CLK),
        .CE(delaydec_cnt_r0),
        .D(delaydec_cnt_r0__0[5]),
        .Q(delaydec_cnt_r_reg[5]),
        .R(\delaydec_cnt_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFBFB3BFB08080808)) 
    \gen_byte_sel_div2.ctl_lane_sel[1]_i_1 
       (.I0(ctl_lane_cnt),
        .I1(cmd_delay_start0),
        .I2(ck_addr_cmd_delay_done),
        .I3(rd_data_offset_cal_done),
        .I4(\gen_byte_sel_div2.ctl_lane_sel_reg[1] ),
        .I5(\gen_byte_sel_div2.ctl_lane_sel_reg[1]_0 ),
        .O(\ctl_lane_cnt_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h0000001000000000)) 
    po_cnt_dec_i_1__0
       (.I0(p_1_in),
        .I1(wait_cnt_r_reg[1]),
        .I2(wait_cnt_r_reg[0]),
        .I3(wait_cnt_r_reg[3]),
        .I4(wait_cnt_r_reg[2]),
        .I5(delay_dec_done_i_2_n_0),
        .O(po_cnt_dec_i_1__0_n_0));
  FDRE po_cnt_dec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(po_cnt_dec_i_1__0_n_0),
        .Q(po_cnt_dec_3),
        .R(1'b0));
  FDRE po_en_stg2_f_reg
       (.C(CLK),
        .CE(1'b1),
        .D(po_cnt_dec_3),
        .Q(cmd_po_en_stg2_f),
        .R(in0));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_cnt_r[0]_i_1 
       (.I0(wait_cnt_r_reg[0]),
        .O(wait_cnt_r0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wait_cnt_r[1]_i_1 
       (.I0(wait_cnt_r_reg[1]),
        .I1(wait_cnt_r_reg[0]),
        .O(wait_cnt_r0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wait_cnt_r[2]_i_1 
       (.I0(wait_cnt_r_reg[2]),
        .I1(wait_cnt_r_reg[0]),
        .I2(wait_cnt_r_reg[1]),
        .O(wait_cnt_r0__0[2]));
  LUT6 #(
    .INIT(64'hFFFE000000000000)) 
    \wait_cnt_r[3]_i_2 
       (.I0(wait_cnt_r_reg[3]),
        .I1(wait_cnt_r_reg[1]),
        .I2(wait_cnt_r_reg[0]),
        .I3(wait_cnt_r_reg[2]),
        .I4(\wait_cnt_r_reg[0]_1 ),
        .I5(\wait_cnt_r_reg[0]_0 ),
        .O(wait_cnt_r0));
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wait_cnt_r[3]_i_3 
       (.I0(wait_cnt_r_reg[3]),
        .I1(wait_cnt_r_reg[1]),
        .I2(wait_cnt_r_reg[0]),
        .I3(wait_cnt_r_reg[2]),
        .O(wait_cnt_r0__0[3]));
  FDRE \wait_cnt_r_reg[0] 
       (.C(CLK),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0[0]),
        .Q(wait_cnt_r_reg[0]),
        .R(\wait_cnt_r_reg[0]_2 ));
  FDRE \wait_cnt_r_reg[1] 
       (.C(CLK),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0[1]),
        .Q(wait_cnt_r_reg[1]),
        .R(\wait_cnt_r_reg[0]_2 ));
  FDRE \wait_cnt_r_reg[2] 
       (.C(CLK),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0[2]),
        .Q(wait_cnt_r_reg[2]),
        .R(\wait_cnt_r_reg[0]_2 ));
  FDSE \wait_cnt_r_reg[3] 
       (.C(CLK),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0[3]),
        .Q(wait_cnt_r_reg[3]),
        .S(\wait_cnt_r_reg[0]_2 ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr
   (rd_data_offset_cal_done,
    pi_dqs_found_rank_done,
    pi_dqs_found_done,
    fine_adjust_done_r_reg_0,
    dqs_found_prech_req,
    ck_po_stg2_f_indec,
    ck_po_stg2_f_en,
    \gen_byte_sel_div2.calib_in_common_reg ,
    \calib_sel_reg[1] ,
    \calib_sel_reg[1]_0 ,
    ck_po_stg2_f_indec_reg_0,
    \pi_rst_stg1_cal_reg[0]_0 ,
    \rd_byte_data_offset_reg[0][3]_0 ,
    calib_sel15_out,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 ,
    pi_dqs_found_done_r1_reg,
    pi_dqs_found_done_r1_reg_0,
    pi_dqs_found_done_r1_reg_1,
    pi_dqs_found_done_r1_reg_2,
    pi_dqs_found_done_r1_reg_3,
    dqs_found_done_r_reg_0,
    ififo_rst_reg0,
    ofifo_rst_reg0,
    ififo_rst_reg0_1,
    ofifo_rst_reg0_2,
    \ctl_lane_cnt_reg[0]_0 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[1] ,
    RSTB,
    calib_in_common4_out,
    dqs_found_done_r_reg_1,
    Q,
    CLK,
    pi_dqs_found_lanes,
    dqs_found_start_r_reg_0,
    ck_po_stg2_f_en_reg_0,
    in0,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]_0 ,
    ofifo_rst_reg,
    dqs_po_stg2_f_incdec,
    ofifo_rst_reg_0,
    ofifo_rst_reg_1,
    calib_zero_inputs,
    pi_dqs_found_done_r1,
    pi_calib_done,
    ck_addr_cmd_delay_done,
    D,
    phy_if_reset,
    A_rst_primitives,
    ctl_lane_cnt,
    \gen_byte_sel_div2.ctl_lane_sel_reg[0] ,
    \calib_sel_reg[1]_1 ,
    cmd_delay_start0,
    calib_sel0,
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ,
    \gen_byte_sel_div2.ctl_lane_sel_reg[0]_0 ,
    \gen_byte_sel_div2.ctl_lane_sel_reg[0]_1 ,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    \gen_byte_sel_div2.calib_in_common_reg_1 ,
    \pi_rst_stg1_cal_r_reg[0]_0 ,
    \detect_rd_cnt_reg[2]_0 ,
    detect_pi_found_dqs,
    prech_done,
    rst_dqs_find_i_4_0);
  output rd_data_offset_cal_done;
  output pi_dqs_found_rank_done;
  output pi_dqs_found_done;
  output fine_adjust_done_r_reg_0;
  output dqs_found_prech_req;
  output ck_po_stg2_f_indec;
  output ck_po_stg2_f_en;
  output \gen_byte_sel_div2.calib_in_common_reg ;
  output \calib_sel_reg[1] ;
  output \calib_sel_reg[1]_0 ;
  output ck_po_stg2_f_indec_reg_0;
  output \pi_rst_stg1_cal_reg[0]_0 ;
  output \rd_byte_data_offset_reg[0][3]_0 ;
  output calib_sel15_out;
  output \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ;
  output [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 ;
  output pi_dqs_found_done_r1_reg;
  output pi_dqs_found_done_r1_reg_0;
  output pi_dqs_found_done_r1_reg_1;
  output pi_dqs_found_done_r1_reg_2;
  output pi_dqs_found_done_r1_reg_3;
  output dqs_found_done_r_reg_0;
  output ififo_rst_reg0;
  output ofifo_rst_reg0;
  output ififo_rst_reg0_1;
  output ofifo_rst_reg0_2;
  output \ctl_lane_cnt_reg[0]_0 ;
  output \gen_byte_sel_div2.byte_sel_cnt_reg[1] ;
  output RSTB;
  output calib_in_common4_out;
  output dqs_found_done_r_reg_1;
  output [0:0]Q;
  input CLK;
  input [1:0]pi_dqs_found_lanes;
  input dqs_found_start_r_reg_0;
  input [0:0]ck_po_stg2_f_en_reg_0;
  input in0;
  input [0:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]_0 ;
  input ofifo_rst_reg;
  input dqs_po_stg2_f_incdec;
  input ofifo_rst_reg_0;
  input ofifo_rst_reg_1;
  input calib_zero_inputs;
  input pi_dqs_found_done_r1;
  input pi_calib_done;
  input ck_addr_cmd_delay_done;
  input [0:0]D;
  input phy_if_reset;
  input A_rst_primitives;
  input [0:0]ctl_lane_cnt;
  input \gen_byte_sel_div2.ctl_lane_sel_reg[0] ;
  input \calib_sel_reg[1]_1 ;
  input cmd_delay_start0;
  input calib_sel0;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ;
  input \gen_byte_sel_div2.ctl_lane_sel_reg[0]_0 ;
  input \gen_byte_sel_div2.ctl_lane_sel_reg[0]_1 ;
  input \gen_byte_sel_div2.calib_in_common_reg_0 ;
  input \gen_byte_sel_div2.calib_in_common_reg_1 ;
  input \pi_rst_stg1_cal_r_reg[0]_0 ;
  input \detect_rd_cnt_reg[2]_0 ;
  input detect_pi_found_dqs;
  input prech_done;
  input rst_dqs_find_i_4_0;

  wire A_rst_primitives;
  wire CLK;
  wire [0:0]D;
  wire \FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[0]_i_3_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[0]_i_6_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_1_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_4_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_6_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_7_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_8_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_9_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_7_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ;
  wire [0:0]Q;
  wire RSTB;
  wire byte_sel_cnt1;
  wire calib_in_common4_out;
  wire calib_sel0;
  wire calib_sel15_out;
  wire \calib_sel_reg[1] ;
  wire \calib_sel_reg[1]_0 ;
  wire \calib_sel_reg[1]_1 ;
  wire calib_zero_inputs;
  wire ck_addr_cmd_delay_done;
  wire ck_po_stg2_f_en;
  wire ck_po_stg2_f_en_i_1_n_0;
  wire [0:0]ck_po_stg2_f_en_reg_0;
  wire ck_po_stg2_f_indec;
  wire ck_po_stg2_f_indec_i_1_n_0;
  wire ck_po_stg2_f_indec_reg_0;
  wire cmd_delay_start0;
  wire [0:0]ctl_lane_cnt;
  wire \ctl_lane_cnt[0]_i_1__0_n_0 ;
  wire \ctl_lane_cnt_reg[0]_0 ;
  wire ctl_lane_sel;
  wire [5:0]dec_cnt;
  wire \dec_cnt[0]_i_2_n_0 ;
  wire \dec_cnt[0]_i_3_n_0 ;
  wire \dec_cnt[0]_i_4_n_0 ;
  wire \dec_cnt[0]_i_5_n_0 ;
  wire \dec_cnt[1]_i_2_n_0 ;
  wire \dec_cnt[1]_i_3_n_0 ;
  wire \dec_cnt[2]_i_2_n_0 ;
  wire \dec_cnt[2]_i_3_n_0 ;
  wire \dec_cnt[2]_i_5_n_0 ;
  wire \dec_cnt[2]_i_6_n_0 ;
  wire \dec_cnt[2]_i_7_n_0 ;
  wire \dec_cnt[2]_i_8_n_0 ;
  wire \dec_cnt[3]_i_2_n_0 ;
  wire \dec_cnt[3]_i_3_n_0 ;
  wire \dec_cnt[4]_i_10_n_0 ;
  wire \dec_cnt[4]_i_11_n_0 ;
  wire \dec_cnt[4]_i_12_n_0 ;
  wire \dec_cnt[4]_i_13_n_0 ;
  wire \dec_cnt[4]_i_2_n_0 ;
  wire \dec_cnt[4]_i_3_n_0 ;
  wire \dec_cnt[4]_i_4_n_0 ;
  wire \dec_cnt[4]_i_6_n_0 ;
  wire \dec_cnt[4]_i_7_n_0 ;
  wire \dec_cnt[4]_i_8_n_0 ;
  wire \dec_cnt[4]_i_9_n_0 ;
  wire \dec_cnt[5]_i_10_n_0 ;
  wire \dec_cnt[5]_i_11_n_0 ;
  wire \dec_cnt[5]_i_12_n_0 ;
  wire \dec_cnt[5]_i_13_n_0 ;
  wire \dec_cnt[5]_i_14_n_0 ;
  wire \dec_cnt[5]_i_1_n_0 ;
  wire \dec_cnt[5]_i_3_n_0 ;
  wire \dec_cnt[5]_i_4_n_0 ;
  wire \dec_cnt[5]_i_5_n_0 ;
  wire \dec_cnt[5]_i_6_n_0 ;
  wire \dec_cnt[5]_i_7_n_0 ;
  wire \dec_cnt[5]_i_8_n_0 ;
  wire \dec_cnt[5]_i_9_n_0 ;
  wire \dec_cnt_reg[2]_i_4_n_0 ;
  wire \dec_cnt_reg[2]_i_4_n_1 ;
  wire \dec_cnt_reg[2]_i_4_n_2 ;
  wire \dec_cnt_reg[2]_i_4_n_3 ;
  wire \dec_cnt_reg[2]_i_4_n_4 ;
  wire \dec_cnt_reg[2]_i_4_n_5 ;
  wire \dec_cnt_reg[2]_i_4_n_6 ;
  wire \dec_cnt_reg[4]_i_5_n_3 ;
  wire \dec_cnt_reg[4]_i_5_n_6 ;
  wire \dec_cnt_reg[4]_i_5_n_7 ;
  wire \dec_cnt_reg_n_0_[0] ;
  wire \dec_cnt_reg_n_0_[1] ;
  wire \dec_cnt_reg_n_0_[2] ;
  wire \dec_cnt_reg_n_0_[3] ;
  wire \dec_cnt_reg_n_0_[4] ;
  wire \dec_cnt_reg_n_0_[5] ;
  wire detect_pi_found_dqs;
  wire detect_rd_cnt0;
  wire [0:0]detect_rd_cnt0__0;
  wire \detect_rd_cnt[1]_i_1_n_0 ;
  wire \detect_rd_cnt[2]_i_1_n_0 ;
  wire \detect_rd_cnt[3]_i_1_n_0 ;
  wire \detect_rd_cnt[3]_i_3_n_0 ;
  wire [3:0]detect_rd_cnt_reg;
  wire \detect_rd_cnt_reg[2]_0 ;
  wire dqs_found_done_r0;
  wire dqs_found_done_r_i_2_n_0;
  wire dqs_found_done_r_reg_0;
  wire dqs_found_done_r_reg_1;
  wire dqs_found_prech_req;
  wire dqs_found_prech_req_i_1_n_0;
  wire dqs_found_prech_req_i_2_n_0;
  wire dqs_found_prech_req_i_3_n_0;
  wire dqs_found_prech_req_i_4_n_0;
  wire dqs_found_prech_req_i_5_n_0;
  wire dqs_found_prech_req_i_6_n_0;
  wire dqs_found_prech_req_i_7_n_0;
  wire dqs_found_start_r;
  wire dqs_found_start_r_reg_0;
  wire dqs_po_stg2_f_incdec;
  wire final_data_offset_mc;
  wire final_dec_done_i_1_n_0;
  wire final_dec_done_reg_n_0;
  wire [3:1]fine_adj_state_r;
  wire fine_adjust;
  wire fine_adjust_done_r;
  wire fine_adjust_done_r_i_1_n_0;
  wire fine_adjust_done_r_reg_0;
  wire fine_adjust_i_1_n_0;
  wire [0:0]fine_adjust_lane_cnt;
  wire fine_adjust_reg_n_0;
  wire first_fail_detect;
  wire first_fail_detect_i_1_n_0;
  wire first_fail_detect_reg_n_0;
  wire \first_fail_taps[5]_i_2_n_0 ;
  wire \first_fail_taps_reg_n_0_[0] ;
  wire \first_fail_taps_reg_n_0_[1] ;
  wire \first_fail_taps_reg_n_0_[2] ;
  wire \first_fail_taps_reg_n_0_[3] ;
  wire \first_fail_taps_reg_n_0_[4] ;
  wire \first_fail_taps_reg_n_0_[5] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[1] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_1 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[0] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[0]_0 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[0]_1 ;
  wire ififo_rst_reg0;
  wire ififo_rst_reg0_1;
  wire in0;
  wire inc_cnt;
  wire \inc_cnt[5]_i_2_n_0 ;
  wire \inc_cnt_reg_n_0_[0] ;
  wire \inc_cnt_reg_n_0_[1] ;
  wire \inc_cnt_reg_n_0_[2] ;
  wire \inc_cnt_reg_n_0_[3] ;
  wire \inc_cnt_reg_n_0_[4] ;
  wire \inc_cnt_reg_n_0_[5] ;
  wire init_dec_cnt;
  wire [0:0]init_dec_cnt0;
  wire \init_dec_cnt[1]_i_1_n_0 ;
  wire \init_dec_cnt[2]_i_1_n_0 ;
  wire \init_dec_cnt[3]_i_1_n_0 ;
  wire \init_dec_cnt[4]_i_1_n_0 ;
  wire \init_dec_cnt[5]_i_2_n_0 ;
  wire [5:0]init_dec_cnt_reg;
  wire init_dec_done_i_1_n_0;
  wire init_dec_done_i_2_n_0;
  wire init_dec_done_reg_n_0;
  wire init_dqsfound_done_r1_reg_n_0;
  wire init_dqsfound_done_r2;
  wire init_dqsfound_done_r4_reg_srl2_n_0;
  wire init_dqsfound_done_r5;
  wire init_dqsfound_done_r_i_1_n_0;
  wire n_0_0;
  wire n_0_1;
  wire ofifo_rst_reg;
  wire ofifo_rst_reg0;
  wire ofifo_rst_reg0_2;
  wire ofifo_rst_reg_0;
  wire ofifo_rst_reg_1;
  wire [5:2]p_0_in;
  wire [4:0]p_0_in__0;
  wire [5:0]p_0_in__1;
  wire p_44_out;
  wire phy_if_reset;
  wire pi_calib_done;
  wire pi_dqs_found_all_bank;
  wire \pi_dqs_found_all_bank[0]_i_1_n_0 ;
  wire pi_dqs_found_all_bank_r;
  wire pi_dqs_found_any_bank;
  wire \pi_dqs_found_any_bank[0]_i_1_n_0 ;
  wire pi_dqs_found_any_bank_r;
  wire pi_dqs_found_done;
  wire pi_dqs_found_done_r1;
  wire pi_dqs_found_done_r1_reg;
  wire pi_dqs_found_done_r1_reg_0;
  wire pi_dqs_found_done_r1_reg_1;
  wire pi_dqs_found_done_r1_reg_2;
  wire pi_dqs_found_done_r1_reg_3;
  wire [1:0]pi_dqs_found_lanes;
  (* async_reg = "true" *) wire [3:0]pi_dqs_found_lanes_r1;
  (* async_reg = "true" *) wire [3:0]pi_dqs_found_lanes_r2;
  (* async_reg = "true" *) wire [3:0]pi_dqs_found_lanes_r3;
  wire pi_dqs_found_rank_done;
  wire \pi_rst_stg1_cal[0]_i_1_n_0 ;
  wire pi_rst_stg1_cal_r;
  wire \pi_rst_stg1_cal_r1[0]_i_1_n_0 ;
  wire \pi_rst_stg1_cal_r1_reg_n_0_[0] ;
  wire \pi_rst_stg1_cal_r[0]_i_1_n_0 ;
  wire \pi_rst_stg1_cal_r[0]_i_2_n_0 ;
  wire \pi_rst_stg1_cal_r_reg[0]_0 ;
  wire \pi_rst_stg1_cal_reg[0]_0 ;
  wire prech_done;
  wire rank_done_r1;
  wire rank_done_r_i_1_n_0;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ;
  wire [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 ;
  wire [0:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]_0 ;
  wire rd_byte_data_offset;
  wire \rd_byte_data_offset[0][1]_i_1_n_0 ;
  wire \rd_byte_data_offset[0][5]_i_1_n_0 ;
  wire \rd_byte_data_offset[0][5]_i_4_n_0 ;
  wire \rd_byte_data_offset[0][5]_i_5_n_0 ;
  wire \rd_byte_data_offset[0][5]_i_6_n_0 ;
  wire \rd_byte_data_offset_reg[0][3]_0 ;
  wire [5:0]\rd_byte_data_offset_reg[0]_10 ;
  wire rd_data_offset_cal_done;
  wire [5:0]rd_data_offset_ranks_0;
  wire \rnk_cnt_r[0]_i_1_n_0 ;
  wire \rnk_cnt_r[1]_i_1_n_0 ;
  wire \rnk_cnt_r_reg_n_0_[0] ;
  wire \rnk_cnt_r_reg_n_0_[1] ;
  wire rst_dqs_find;
  wire rst_dqs_find__0;
  wire rst_dqs_find_i_10_n_0;
  wire rst_dqs_find_i_11_n_0;
  wire rst_dqs_find_i_12_n_0;
  wire rst_dqs_find_i_14_n_0;
  wire rst_dqs_find_i_16_n_0;
  wire rst_dqs_find_i_18_n_0;
  wire rst_dqs_find_i_19_n_0;
  wire rst_dqs_find_i_1_n_0;
  wire rst_dqs_find_i_3_n_0;
  wire rst_dqs_find_i_4_0;
  wire rst_dqs_find_i_4_n_0;
  wire rst_dqs_find_i_5_n_0;
  wire rst_dqs_find_i_6_n_0;
  wire rst_dqs_find_i_7_n_0;
  wire rst_dqs_find_i_8_n_0;
  wire rst_dqs_find_i_9_n_0;
  wire rst_dqs_find_r1;
  wire rst_dqs_find_r2;
  wire rst_stg1_cal;
  wire stable_pass_cnt;
  wire \stable_pass_cnt[5]_i_3_n_0 ;
  wire [5:1]stable_pass_cnt_reg;
  wire \stable_pass_cnt_reg_n_0_[0] ;
  wire [0:0]\NLW_dec_cnt_reg[2]_i_4_O_UNCONNECTED ;
  wire [3:1]\NLW_dec_cnt_reg[4]_i_5_CO_UNCONNECTED ;
  wire [3:2]\NLW_dec_cnt_reg[4]_i_5_O_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT5 #(
    .INIT(32'hEEFEEEEE)) 
    \FSM_sequential_fine_adj_state_r[0]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[0]_i_3_n_0 ),
        .I2(fine_adj_state_r[2]),
        .I3(Q),
        .I4(\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAEF)) 
    \FSM_sequential_fine_adj_state_r[0]_i_2 
       (.I0(\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ),
        .I2(final_dec_done_reg_n_0),
        .I3(fine_adj_state_r[3]),
        .I4(fine_adj_state_r[1]),
        .I5(fine_adj_state_r[2]),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT5 #(
    .INIT(32'hCFE00000)) 
    \FSM_sequential_fine_adj_state_r[0]_i_3 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ),
        .I1(fine_adj_state_r[2]),
        .I2(Q),
        .I3(fine_adj_state_r[1]),
        .I4(fine_adj_state_r[3]),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_sequential_fine_adj_state_r[0]_i_4 
       (.I0(fine_adjust_lane_cnt),
        .I1(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[0]_i_6_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT5 #(
    .INIT(32'hF0110011)) 
    \FSM_sequential_fine_adj_state_r[0]_i_5 
       (.I0(Q),
        .I1(fine_adj_state_r[3]),
        .I2(fine_adj_state_r[2]),
        .I3(fine_adj_state_r[1]),
        .I4(fine_adjust_lane_cnt),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \FSM_sequential_fine_adj_state_r[0]_i_6 
       (.I0(\dec_cnt_reg_n_0_[4] ),
        .I1(\dec_cnt_reg_n_0_[2] ),
        .I2(\dec_cnt_reg_n_0_[0] ),
        .I3(\dec_cnt_reg_n_0_[1] ),
        .I4(\dec_cnt_reg_n_0_[3] ),
        .I5(\dec_cnt_reg_n_0_[5] ),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFAABA)) 
    \FSM_sequential_fine_adj_state_r[1]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_4_n_0 ),
        .I3(fine_adj_state_r[2]),
        .I4(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I5(\FSM_sequential_fine_adj_state_r[1]_i_6_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF19090808)) 
    \FSM_sequential_fine_adj_state_r[1]_i_2 
       (.I0(fine_adj_state_r[2]),
        .I1(Q),
        .I2(fine_adj_state_r[1]),
        .I3(\FSM_sequential_fine_adj_state_r[1]_i_7_n_0 ),
        .I4(fine_adj_state_r[3]),
        .I5(\FSM_sequential_fine_adj_state_r[1]_i_8_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \FSM_sequential_fine_adj_state_r[1]_i_3 
       (.I0(detect_pi_found_dqs),
        .I1(detect_rd_cnt_reg[0]),
        .I2(detect_rd_cnt_reg[3]),
        .I3(detect_rd_cnt_reg[1]),
        .I4(detect_rd_cnt_reg[2]),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_fine_adj_state_r[1]_i_4 
       (.I0(fine_adj_state_r[3]),
        .I1(fine_adj_state_r[1]),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0800080008000000)) 
    \FSM_sequential_fine_adj_state_r[1]_i_5 
       (.I0(\dec_cnt[5]_i_5_n_0 ),
        .I1(fine_adj_state_r[3]),
        .I2(fine_adj_state_r[2]),
        .I3(\dec_cnt[5]_i_12_n_0 ),
        .I4(first_fail_detect_reg_n_0),
        .I5(\FSM_sequential_fine_adj_state_r[1]_i_9_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h000000005500D000)) 
    \FSM_sequential_fine_adj_state_r[1]_i_6 
       (.I0(fine_adj_state_r[3]),
        .I1(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),
        .I2(pi_dqs_found_all_bank),
        .I3(fine_adj_state_r[1]),
        .I4(fine_adj_state_r[2]),
        .I5(Q),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF8AFF)) 
    \FSM_sequential_fine_adj_state_r[1]_i_7 
       (.I0(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),
        .I1(first_fail_detect_reg_n_0),
        .I2(detect_pi_found_dqs),
        .I3(\dec_cnt[5]_i_3_n_0 ),
        .I4(\FSM_sequential_fine_adj_state_r[3]_i_7_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h000F004400000044)) 
    \FSM_sequential_fine_adj_state_r[1]_i_8 
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ),
        .I1(Q),
        .I2(\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ),
        .I3(fine_adj_state_r[1]),
        .I4(fine_adj_state_r[3]),
        .I5(fine_adj_state_r[2]),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \FSM_sequential_fine_adj_state_r[1]_i_9 
       (.I0(\inc_cnt_reg_n_0_[5] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[0] ),
        .I3(\inc_cnt_reg_n_0_[2] ),
        .I4(\inc_cnt_reg_n_0_[4] ),
        .I5(\inc_cnt_reg_n_0_[3] ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAABBEEFEBBFFBBAA)) 
    \FSM_sequential_fine_adj_state_r[2]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ),
        .I1(fine_adj_state_r[1]),
        .I2(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ),
        .I3(fine_adj_state_r[3]),
        .I4(fine_adj_state_r[2]),
        .I5(Q),
        .O(\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF3FAA0800000000)) 
    \FSM_sequential_fine_adj_state_r[2]_i_2 
       (.I0(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),
        .I1(first_fail_detect_reg_n_0),
        .I2(\dec_cnt[5]_i_12_n_0 ),
        .I3(\first_fail_taps[5]_i_2_n_0 ),
        .I4(\FSM_sequential_fine_adj_state_r[3]_i_7_n_0 ),
        .I5(\dec_cnt[5]_i_6_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0200000000020200)) 
    \FSM_sequential_fine_adj_state_r[2]_i_3 
       (.I0(\inc_cnt_reg_n_0_[5] ),
        .I1(\inc_cnt_reg_n_0_[0] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(\inc_cnt_reg_n_0_[4] ),
        .I4(\inc_cnt_reg_n_0_[2] ),
        .I5(\inc_cnt_reg_n_0_[3] ),
        .O(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hBFFEBFEEAFFEAFEE)) 
    \FSM_sequential_fine_adj_state_r[3]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ),
        .I1(fine_adj_state_r[2]),
        .I2(fine_adj_state_r[1]),
        .I3(fine_adj_state_r[3]),
        .I4(pi_dqs_found_all_bank),
        .I5(detect_pi_found_dqs),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBEFBBEFABAAABAAA)) 
    \FSM_sequential_fine_adj_state_r[3]_i_2 
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[3]),
        .I3(fine_adj_state_r[2]),
        .I4(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ),
        .I5(Q),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFAFF4450FAFF44)) 
    \FSM_sequential_fine_adj_state_r[3]_i_3 
       (.I0(fine_adj_state_r[1]),
        .I1(init_dqsfound_done_r5),
        .I2(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),
        .I3(fine_adj_state_r[2]),
        .I4(Q),
        .I5(prech_done),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF40004040)) 
    \FSM_sequential_fine_adj_state_r[3]_i_4 
       (.I0(fine_adj_state_r[2]),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[3]),
        .I3(\FSM_sequential_fine_adj_state_r[3]_i_7_n_0 ),
        .I4(\dec_cnt[5]_i_3_n_0 ),
        .I5(\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \FSM_sequential_fine_adj_state_r[3]_i_5 
       (.I0(init_dec_cnt_reg[4]),
        .I1(init_dec_cnt_reg[2]),
        .I2(init_dec_cnt_reg[0]),
        .I3(init_dec_cnt_reg[1]),
        .I4(init_dec_cnt_reg[3]),
        .I5(init_dec_cnt_reg[5]),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_fine_adj_state_r[3]_i_6 
       (.I0(rst_dqs_find_r2),
        .I1(pi_dqs_found_any_bank),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000001000100000)) 
    \FSM_sequential_fine_adj_state_r[3]_i_7 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[3] ),
        .I3(\inc_cnt_reg_n_0_[5] ),
        .I4(\inc_cnt_reg_n_0_[4] ),
        .I5(\inc_cnt_reg_n_0_[2] ),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hCCCCFAC000000000)) 
    \FSM_sequential_fine_adj_state_r[3]_i_8 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_9_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),
        .I2(first_fail_detect_reg_n_0),
        .I3(\dec_cnt[5]_i_12_n_0 ),
        .I4(\first_fail_taps[5]_i_2_n_0 ),
        .I5(\dec_cnt[5]_i_6_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ));
  (* FSM_ENCODED_STATES = "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110" *) 
  FDRE \FSM_sequential_fine_adj_state_r_reg[0] 
       (.C(CLK),
        .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),
        .D(\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ),
        .Q(Q),
        .R(ck_po_stg2_f_en_reg_0));
  (* FSM_ENCODED_STATES = "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110" *) 
  FDRE \FSM_sequential_fine_adj_state_r_reg[1] 
       (.C(CLK),
        .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),
        .D(\FSM_sequential_fine_adj_state_r[1]_i_1_n_0 ),
        .Q(fine_adj_state_r[1]),
        .R(ck_po_stg2_f_en_reg_0));
  (* FSM_ENCODED_STATES = "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110" *) 
  FDRE \FSM_sequential_fine_adj_state_r_reg[2] 
       (.C(CLK),
        .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),
        .D(\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ),
        .Q(fine_adj_state_r[2]),
        .R(ck_po_stg2_f_en_reg_0));
  (* FSM_ENCODED_STATES = "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110" *) 
  FDRE \FSM_sequential_fine_adj_state_r_reg[3] 
       (.C(CLK),
        .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),
        .D(\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ),
        .Q(fine_adj_state_r[3]),
        .R(ck_po_stg2_f_en_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[0]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[0]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg[0]_10 [0]),
        .O(pi_dqs_found_done_r1_reg_3));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[1]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[1]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg[0]_10 [1]),
        .O(pi_dqs_found_done_r1_reg_2));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[2]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[2]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg[0]_10 [2]),
        .O(pi_dqs_found_done_r1_reg_1));
  LUT5 #(
    .INIT(32'hF0E20000)) 
    \calib_data_offset_0[3]_i_2 
       (.I0(\rd_byte_data_offset_reg[0]_10 [3]),
        .I1(init_dqsfound_done_r2),
        .I2(rd_data_offset_ranks_0[3]),
        .I3(pi_dqs_found_done_r1),
        .I4(pi_calib_done),
        .O(\rd_byte_data_offset_reg[0][3]_0 ));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[4]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[4]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg[0]_10 [4]),
        .O(pi_dqs_found_done_r1_reg_0));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[5]_i_2 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[5]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg[0]_10 [5]),
        .O(pi_dqs_found_done_r1_reg));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT3 #(
    .INIT(8'h4F)) 
    \calib_sel[0]_i_3 
       (.I0(fine_adjust_done_r_reg_0),
        .I1(rd_data_offset_cal_done),
        .I2(ck_addr_cmd_delay_done),
        .O(calib_sel15_out));
  LUT6 #(
    .INIT(64'h0000000051551111)) 
    \calib_sel[1]_i_1 
       (.I0(\calib_sel_reg[1]_1 ),
        .I1(cmd_delay_start0),
        .I2(fine_adjust_done_r_reg_0),
        .I3(rd_data_offset_cal_done),
        .I4(ck_addr_cmd_delay_done),
        .I5(calib_sel0),
        .O(\gen_byte_sel_div2.byte_sel_cnt_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT5 #(
    .INIT(32'hFB7F2040)) 
    ck_po_stg2_f_en_i_1
       (.I0(Q),
        .I1(fine_adj_state_r[2]),
        .I2(fine_adj_state_r[1]),
        .I3(fine_adj_state_r[3]),
        .I4(ck_po_stg2_f_en),
        .O(ck_po_stg2_f_en_i_1_n_0));
  FDRE ck_po_stg2_f_en_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ck_po_stg2_f_en_i_1_n_0),
        .Q(ck_po_stg2_f_en),
        .R(ck_po_stg2_f_en_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT5 #(
    .INIT(32'hDB7F0040)) 
    ck_po_stg2_f_indec_i_1
       (.I0(Q),
        .I1(fine_adj_state_r[2]),
        .I2(fine_adj_state_r[1]),
        .I3(fine_adj_state_r[3]),
        .I4(ck_po_stg2_f_indec),
        .O(ck_po_stg2_f_indec_i_1_n_0));
  FDRE ck_po_stg2_f_indec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ck_po_stg2_f_indec_i_1_n_0),
        .Q(ck_po_stg2_f_indec),
        .R(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_pipe_plus.mc_data_offset[0]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [0]),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT5 #(
    .INIT(32'hDBFF2400)) 
    \ctl_lane_cnt[0]_i_1__0 
       (.I0(fine_adj_state_r[1]),
        .I1(fine_adj_state_r[3]),
        .I2(Q),
        .I3(fine_adj_state_r[2]),
        .I4(fine_adjust_lane_cnt),
        .O(\ctl_lane_cnt[0]_i_1__0_n_0 ));
  FDRE \ctl_lane_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\ctl_lane_cnt[0]_i_1__0_n_0 ),
        .Q(fine_adjust_lane_cnt),
        .R(ck_po_stg2_f_en_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF44F4)) 
    \dec_cnt[0]_i_1 
       (.I0(\dec_cnt_reg_n_0_[0] ),
        .I1(Q),
        .I2(\dec_cnt[4]_i_4_n_0 ),
        .I3(\first_fail_taps_reg_n_0_[1] ),
        .I4(\dec_cnt[0]_i_2_n_0 ),
        .I5(\dec_cnt[0]_i_3_n_0 ),
        .O(dec_cnt[0]));
  LUT6 #(
    .INIT(64'h0000000080800080)) 
    \dec_cnt[0]_i_2 
       (.I0(\dec_cnt_reg[2]_i_4_n_6 ),
        .I1(\dec_cnt[5]_i_9_n_0 ),
        .I2(first_fail_detect_reg_n_0),
        .I3(detect_pi_found_dqs),
        .I4(pi_dqs_found_all_bank),
        .I5(Q),
        .O(\dec_cnt[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h8000C080C0F0C0C0)) 
    \dec_cnt[0]_i_3 
       (.I0(\dec_cnt[0]_i_4_n_0 ),
        .I1(\dec_cnt_reg[2]_i_4_n_6 ),
        .I2(\dec_cnt[5]_i_5_n_0 ),
        .I3(\dec_cnt[0]_i_5_n_0 ),
        .I4(\inc_cnt_reg_n_0_[5] ),
        .I5(\inc_cnt_reg_n_0_[1] ),
        .O(\dec_cnt[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \dec_cnt[0]_i_4 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[2] ),
        .I2(\inc_cnt_reg_n_0_[4] ),
        .I3(\inc_cnt_reg_n_0_[3] ),
        .O(\dec_cnt[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAABFFFFFFF)) 
    \dec_cnt[0]_i_5 
       (.I0(first_fail_detect_reg_n_0),
        .I1(stable_pass_cnt_reg[3]),
        .I2(stable_pass_cnt_reg[1]),
        .I3(stable_pass_cnt_reg[2]),
        .I4(stable_pass_cnt_reg[4]),
        .I5(stable_pass_cnt_reg[5]),
        .O(\dec_cnt[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFEFEEEFEEEFEE)) 
    \dec_cnt[1]_i_1 
       (.I0(\dec_cnt[1]_i_2_n_0 ),
        .I1(\dec_cnt[1]_i_3_n_0 ),
        .I2(\first_fail_taps_reg_n_0_[2] ),
        .I3(\dec_cnt[4]_i_4_n_0 ),
        .I4(\dec_cnt_reg[2]_i_4_n_5 ),
        .I5(\dec_cnt[4]_i_6_n_0 ),
        .O(dec_cnt[1]));
  LUT3 #(
    .INIT(8'h82)) 
    \dec_cnt[1]_i_2 
       (.I0(Q),
        .I1(\dec_cnt_reg_n_0_[1] ),
        .I2(\dec_cnt_reg_n_0_[0] ),
        .O(\dec_cnt[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \dec_cnt[1]_i_3 
       (.I0(\dec_cnt[4]_i_7_n_0 ),
        .I1(\inc_cnt_reg_n_0_[2] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .O(\dec_cnt[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFEFEEEFEEEFEE)) 
    \dec_cnt[2]_i_1 
       (.I0(\dec_cnt[2]_i_2_n_0 ),
        .I1(\dec_cnt[2]_i_3_n_0 ),
        .I2(\first_fail_taps_reg_n_0_[3] ),
        .I3(\dec_cnt[4]_i_4_n_0 ),
        .I4(\dec_cnt_reg[2]_i_4_n_4 ),
        .I5(\dec_cnt[4]_i_6_n_0 ),
        .O(dec_cnt[2]));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT4 #(
    .INIT(16'h8882)) 
    \dec_cnt[2]_i_2 
       (.I0(Q),
        .I1(\dec_cnt_reg_n_0_[2] ),
        .I2(\dec_cnt_reg_n_0_[0] ),
        .I3(\dec_cnt_reg_n_0_[1] ),
        .O(\dec_cnt[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT4 #(
    .INIT(16'h2888)) 
    \dec_cnt[2]_i_3 
       (.I0(\dec_cnt[4]_i_7_n_0 ),
        .I1(\inc_cnt_reg_n_0_[3] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(\inc_cnt_reg_n_0_[2] ),
        .O(\dec_cnt[2]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[2]_i_5 
       (.I0(\inc_cnt_reg_n_0_[3] ),
        .I1(\first_fail_taps_reg_n_0_[3] ),
        .O(\dec_cnt[2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[2]_i_6 
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\first_fail_taps_reg_n_0_[2] ),
        .O(\dec_cnt[2]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[2]_i_7 
       (.I0(\inc_cnt_reg_n_0_[1] ),
        .I1(\first_fail_taps_reg_n_0_[1] ),
        .O(\dec_cnt[2]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[2]_i_8 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\first_fail_taps_reg_n_0_[0] ),
        .O(\dec_cnt[2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFEFEEEFEEEFEE)) 
    \dec_cnt[3]_i_1 
       (.I0(\dec_cnt[3]_i_2_n_0 ),
        .I1(\dec_cnt[3]_i_3_n_0 ),
        .I2(\first_fail_taps_reg_n_0_[4] ),
        .I3(\dec_cnt[4]_i_4_n_0 ),
        .I4(\dec_cnt_reg[4]_i_5_n_7 ),
        .I5(\dec_cnt[4]_i_6_n_0 ),
        .O(dec_cnt[3]));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT5 #(
    .INIT(32'h88888882)) 
    \dec_cnt[3]_i_2 
       (.I0(Q),
        .I1(\dec_cnt_reg_n_0_[3] ),
        .I2(\dec_cnt_reg_n_0_[1] ),
        .I3(\dec_cnt_reg_n_0_[0] ),
        .I4(\dec_cnt_reg_n_0_[2] ),
        .O(\dec_cnt[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT5 #(
    .INIT(32'h28888888)) 
    \dec_cnt[3]_i_3 
       (.I0(\dec_cnt[4]_i_7_n_0 ),
        .I1(\inc_cnt_reg_n_0_[4] ),
        .I2(\inc_cnt_reg_n_0_[2] ),
        .I3(\inc_cnt_reg_n_0_[1] ),
        .I4(\inc_cnt_reg_n_0_[3] ),
        .O(\dec_cnt[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFEFEEEFEEEFEE)) 
    \dec_cnt[4]_i_1 
       (.I0(\dec_cnt[4]_i_2_n_0 ),
        .I1(\dec_cnt[4]_i_3_n_0 ),
        .I2(\first_fail_taps_reg_n_0_[5] ),
        .I3(\dec_cnt[4]_i_4_n_0 ),
        .I4(\dec_cnt_reg[4]_i_5_n_6 ),
        .I5(\dec_cnt[4]_i_6_n_0 ),
        .O(dec_cnt[4]));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \dec_cnt[4]_i_10 
       (.I0(\first_fail_taps_reg_n_0_[2] ),
        .I1(\first_fail_taps_reg_n_0_[1] ),
        .I2(\first_fail_taps_reg_n_0_[4] ),
        .I3(\first_fail_taps_reg_n_0_[3] ),
        .O(\dec_cnt[4]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hA2AAAAAAFBFFFFFF)) 
    \dec_cnt[4]_i_11 
       (.I0(\dec_cnt[0]_i_5_n_0 ),
        .I1(\inc_cnt_reg_n_0_[3] ),
        .I2(\dec_cnt[4]_i_13_n_0 ),
        .I3(\inc_cnt_reg_n_0_[0] ),
        .I4(\inc_cnt_reg_n_0_[1] ),
        .I5(\inc_cnt_reg_n_0_[5] ),
        .O(\dec_cnt[4]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    \dec_cnt[4]_i_12 
       (.I0(\inc_cnt_reg_n_0_[3] ),
        .I1(\inc_cnt_reg_n_0_[4] ),
        .I2(\inc_cnt_reg_n_0_[2] ),
        .I3(\inc_cnt_reg_n_0_[0] ),
        .I4(\inc_cnt_reg_n_0_[1] ),
        .O(\dec_cnt[4]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \dec_cnt[4]_i_13 
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\inc_cnt_reg_n_0_[4] ),
        .O(\dec_cnt[4]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h8888888888888882)) 
    \dec_cnt[4]_i_2 
       (.I0(Q),
        .I1(\dec_cnt_reg_n_0_[4] ),
        .I2(\dec_cnt_reg_n_0_[2] ),
        .I3(\dec_cnt_reg_n_0_[0] ),
        .I4(\dec_cnt_reg_n_0_[1] ),
        .I5(\dec_cnt_reg_n_0_[3] ),
        .O(\dec_cnt[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h2888888888888888)) 
    \dec_cnt[4]_i_3 
       (.I0(\dec_cnt[4]_i_7_n_0 ),
        .I1(\inc_cnt_reg_n_0_[5] ),
        .I2(\inc_cnt_reg_n_0_[3] ),
        .I3(\inc_cnt_reg_n_0_[1] ),
        .I4(\inc_cnt_reg_n_0_[4] ),
        .I5(\inc_cnt_reg_n_0_[2] ),
        .O(\dec_cnt[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT5 #(
    .INIT(32'h00000004)) 
    \dec_cnt[4]_i_4 
       (.I0(\dec_cnt[5]_i_3_n_0 ),
        .I1(detect_pi_found_dqs),
        .I2(pi_dqs_found_all_bank),
        .I3(Q),
        .I4(first_fail_detect_i_1_n_0),
        .O(\dec_cnt[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h004F00CF004000C0)) 
    \dec_cnt[4]_i_6 
       (.I0(\dec_cnt[4]_i_10_n_0 ),
        .I1(first_fail_detect_reg_n_0),
        .I2(\first_fail_taps[5]_i_2_n_0 ),
        .I3(Q),
        .I4(\first_fail_taps_reg_n_0_[5] ),
        .I5(\dec_cnt[4]_i_11_n_0 ),
        .O(\dec_cnt[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0004000000000004)) 
    \dec_cnt[4]_i_7 
       (.I0(first_fail_detect_reg_n_0),
        .I1(\dec_cnt[5]_i_12_n_0 ),
        .I2(\first_fail_taps[5]_i_2_n_0 ),
        .I3(Q),
        .I4(\inc_cnt_reg_n_0_[5] ),
        .I5(\dec_cnt[4]_i_12_n_0 ),
        .O(\dec_cnt[4]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[4]_i_8 
       (.I0(\inc_cnt_reg_n_0_[5] ),
        .I1(\first_fail_taps_reg_n_0_[5] ),
        .O(\dec_cnt[4]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[4]_i_9 
       (.I0(\inc_cnt_reg_n_0_[4] ),
        .I1(\first_fail_taps_reg_n_0_[4] ),
        .O(\dec_cnt[4]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4F4F4F4F4F4F4)) 
    \dec_cnt[5]_i_1 
       (.I0(\dec_cnt[5]_i_3_n_0 ),
        .I1(stable_pass_cnt),
        .I2(\dec_cnt[5]_i_4_n_0 ),
        .I3(\dec_cnt[5]_i_5_n_0 ),
        .I4(\dec_cnt[5]_i_6_n_0 ),
        .I5(\dec_cnt[5]_i_7_n_0 ),
        .O(\dec_cnt[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h90FF909090909090)) 
    \dec_cnt[5]_i_10 
       (.I0(\dec_cnt[5]_i_13_n_0 ),
        .I1(\dec_cnt_reg_n_0_[5] ),
        .I2(Q),
        .I3(first_fail_detect_reg_n_0),
        .I4(\dec_cnt[5]_i_12_n_0 ),
        .I5(\dec_cnt[5]_i_14_n_0 ),
        .O(\dec_cnt[5]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \dec_cnt[5]_i_11 
       (.I0(Q),
        .I1(pi_dqs_found_all_bank),
        .I2(detect_pi_found_dqs),
        .I3(\dec_cnt[5]_i_3_n_0 ),
        .O(\dec_cnt[5]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT5 #(
    .INIT(32'hEAAAAAAA)) 
    \dec_cnt[5]_i_12 
       (.I0(stable_pass_cnt_reg[5]),
        .I1(stable_pass_cnt_reg[4]),
        .I2(stable_pass_cnt_reg[2]),
        .I3(stable_pass_cnt_reg[1]),
        .I4(stable_pass_cnt_reg[3]),
        .O(\dec_cnt[5]_i_12_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \dec_cnt[5]_i_13 
       (.I0(\dec_cnt_reg_n_0_[3] ),
        .I1(\dec_cnt_reg_n_0_[1] ),
        .I2(\dec_cnt_reg_n_0_[0] ),
        .I3(\dec_cnt_reg_n_0_[2] ),
        .I4(\dec_cnt_reg_n_0_[4] ),
        .O(\dec_cnt[5]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h0080000000000000)) 
    \dec_cnt[5]_i_14 
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\inc_cnt_reg_n_0_[4] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(Q),
        .I4(\inc_cnt_reg_n_0_[5] ),
        .I5(\inc_cnt_reg_n_0_[3] ),
        .O(\dec_cnt[5]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hFF2AFF2AFFFFFF2A)) 
    \dec_cnt[5]_i_2 
       (.I0(\dec_cnt[5]_i_8_n_0 ),
        .I1(first_fail_detect_reg_n_0),
        .I2(\dec_cnt[5]_i_9_n_0 ),
        .I3(\dec_cnt[5]_i_10_n_0 ),
        .I4(\dec_cnt[5]_i_11_n_0 ),
        .I5(\dec_cnt[5]_i_12_n_0 ),
        .O(dec_cnt[5]));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \dec_cnt[5]_i_3 
       (.I0(\inc_cnt_reg_n_0_[1] ),
        .I1(\inc_cnt_reg_n_0_[0] ),
        .I2(\inc_cnt_reg_n_0_[2] ),
        .I3(\inc_cnt_reg_n_0_[4] ),
        .I4(\inc_cnt_reg_n_0_[3] ),
        .I5(\inc_cnt_reg_n_0_[5] ),
        .O(\dec_cnt[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \dec_cnt[5]_i_4 
       (.I0(\FSM_sequential_fine_adj_state_r[0]_i_6_n_0 ),
        .I1(\dec_cnt[5]_i_6_n_0 ),
        .I2(Q),
        .I3(fine_adjust_lane_cnt),
        .I4(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ),
        .O(\dec_cnt[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \dec_cnt[5]_i_5 
       (.I0(detect_pi_found_dqs),
        .I1(pi_dqs_found_all_bank),
        .I2(Q),
        .O(\dec_cnt[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \dec_cnt[5]_i_6 
       (.I0(fine_adj_state_r[2]),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[3]),
        .O(\dec_cnt[5]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hE0)) 
    \dec_cnt[5]_i_7 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_9_n_0 ),
        .I1(first_fail_detect_reg_n_0),
        .I2(\dec_cnt[5]_i_12_n_0 ),
        .O(\dec_cnt[5]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT3 #(
    .INIT(8'h0D)) 
    \dec_cnt[5]_i_8 
       (.I0(detect_pi_found_dqs),
        .I1(pi_dqs_found_all_bank),
        .I2(Q),
        .O(\dec_cnt[5]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT5 #(
    .INIT(32'h0001FFFF)) 
    \dec_cnt[5]_i_9 
       (.I0(\first_fail_taps_reg_n_0_[3] ),
        .I1(\first_fail_taps_reg_n_0_[4] ),
        .I2(\first_fail_taps_reg_n_0_[1] ),
        .I3(\first_fail_taps_reg_n_0_[2] ),
        .I4(\first_fail_taps_reg_n_0_[5] ),
        .O(\dec_cnt[5]_i_9_n_0 ));
  FDRE \dec_cnt_reg[0] 
       (.C(CLK),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[0]),
        .Q(\dec_cnt_reg_n_0_[0] ),
        .R(ck_po_stg2_f_en_reg_0));
  FDRE \dec_cnt_reg[1] 
       (.C(CLK),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[1]),
        .Q(\dec_cnt_reg_n_0_[1] ),
        .R(ck_po_stg2_f_en_reg_0));
  FDRE \dec_cnt_reg[2] 
       (.C(CLK),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[2]),
        .Q(\dec_cnt_reg_n_0_[2] ),
        .R(ck_po_stg2_f_en_reg_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \dec_cnt_reg[2]_i_4 
       (.CI(1'b0),
        .CO({\dec_cnt_reg[2]_i_4_n_0 ,\dec_cnt_reg[2]_i_4_n_1 ,\dec_cnt_reg[2]_i_4_n_2 ,\dec_cnt_reg[2]_i_4_n_3 }),
        .CYINIT(1'b1),
        .DI({\inc_cnt_reg_n_0_[3] ,\inc_cnt_reg_n_0_[2] ,\inc_cnt_reg_n_0_[1] ,\inc_cnt_reg_n_0_[0] }),
        .O({\dec_cnt_reg[2]_i_4_n_4 ,\dec_cnt_reg[2]_i_4_n_5 ,\dec_cnt_reg[2]_i_4_n_6 ,\NLW_dec_cnt_reg[2]_i_4_O_UNCONNECTED [0]}),
        .S({\dec_cnt[2]_i_5_n_0 ,\dec_cnt[2]_i_6_n_0 ,\dec_cnt[2]_i_7_n_0 ,\dec_cnt[2]_i_8_n_0 }));
  FDRE \dec_cnt_reg[3] 
       (.C(CLK),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[3]),
        .Q(\dec_cnt_reg_n_0_[3] ),
        .R(ck_po_stg2_f_en_reg_0));
  FDRE \dec_cnt_reg[4] 
       (.C(CLK),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[4]),
        .Q(\dec_cnt_reg_n_0_[4] ),
        .R(ck_po_stg2_f_en_reg_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \dec_cnt_reg[4]_i_5 
       (.CI(\dec_cnt_reg[2]_i_4_n_0 ),
        .CO({\NLW_dec_cnt_reg[4]_i_5_CO_UNCONNECTED [3:1],\dec_cnt_reg[4]_i_5_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\inc_cnt_reg_n_0_[4] }),
        .O({\NLW_dec_cnt_reg[4]_i_5_O_UNCONNECTED [3:2],\dec_cnt_reg[4]_i_5_n_6 ,\dec_cnt_reg[4]_i_5_n_7 }),
        .S({1'b0,1'b0,\dec_cnt[4]_i_8_n_0 ,\dec_cnt[4]_i_9_n_0 }));
  FDRE \dec_cnt_reg[5] 
       (.C(CLK),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[5]),
        .Q(\dec_cnt_reg_n_0_[5] ),
        .R(ck_po_stg2_f_en_reg_0));
  LUT1 #(
    .INIT(2'h1)) 
    \detect_rd_cnt[0]_i_1 
       (.I0(detect_rd_cnt_reg[0]),
        .O(detect_rd_cnt0__0));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \detect_rd_cnt[1]_i_1 
       (.I0(detect_rd_cnt_reg[0]),
        .I1(detect_rd_cnt_reg[1]),
        .O(\detect_rd_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \detect_rd_cnt[2]_i_1 
       (.I0(detect_rd_cnt_reg[0]),
        .I1(detect_rd_cnt_reg[1]),
        .I2(detect_rd_cnt_reg[2]),
        .O(\detect_rd_cnt[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF0001)) 
    \detect_rd_cnt[3]_i_1 
       (.I0(detect_rd_cnt_reg[0]),
        .I1(detect_rd_cnt_reg[2]),
        .I2(detect_rd_cnt_reg[1]),
        .I3(detect_rd_cnt_reg[3]),
        .I4(\detect_rd_cnt_reg[2]_0 ),
        .O(\detect_rd_cnt[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF00FE00)) 
    \detect_rd_cnt[3]_i_2 
       (.I0(detect_rd_cnt_reg[2]),
        .I1(detect_rd_cnt_reg[1]),
        .I2(detect_rd_cnt_reg[3]),
        .I3(detect_pi_found_dqs),
        .I4(detect_rd_cnt_reg[0]),
        .O(detect_rd_cnt0));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \detect_rd_cnt[3]_i_3 
       (.I0(detect_rd_cnt_reg[0]),
        .I1(detect_rd_cnt_reg[1]),
        .I2(detect_rd_cnt_reg[2]),
        .I3(detect_rd_cnt_reg[3]),
        .O(\detect_rd_cnt[3]_i_3_n_0 ));
  FDSE \detect_rd_cnt_reg[0] 
       (.C(CLK),
        .CE(detect_rd_cnt0),
        .D(detect_rd_cnt0__0),
        .Q(detect_rd_cnt_reg[0]),
        .S(\detect_rd_cnt[3]_i_1_n_0 ));
  FDSE \detect_rd_cnt_reg[1] 
       (.C(CLK),
        .CE(detect_rd_cnt0),
        .D(\detect_rd_cnt[1]_i_1_n_0 ),
        .Q(detect_rd_cnt_reg[1]),
        .S(\detect_rd_cnt[3]_i_1_n_0 ));
  FDSE \detect_rd_cnt_reg[2] 
       (.C(CLK),
        .CE(detect_rd_cnt0),
        .D(\detect_rd_cnt[2]_i_1_n_0 ),
        .Q(detect_rd_cnt_reg[2]),
        .S(\detect_rd_cnt[3]_i_1_n_0 ));
  FDRE \detect_rd_cnt_reg[3] 
       (.C(CLK),
        .CE(detect_rd_cnt0),
        .D(\detect_rd_cnt[3]_i_3_n_0 ),
        .Q(detect_rd_cnt_reg[3]),
        .R(\detect_rd_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000001000000000)) 
    dqs_found_done_r_i_1
       (.I0(Q),
        .I1(fine_adj_state_r[3]),
        .I2(init_dqsfound_done_r1_reg_n_0),
        .I3(\rnk_cnt_r_reg_n_0_[1] ),
        .I4(\rnk_cnt_r_reg_n_0_[0] ),
        .I5(dqs_found_done_r_i_2_n_0),
        .O(dqs_found_done_r0));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT3 #(
    .INIT(8'h40)) 
    dqs_found_done_r_i_2
       (.I0(fine_adj_state_r[2]),
        .I1(fine_adj_state_r[1]),
        .I2(pi_dqs_found_all_bank),
        .O(dqs_found_done_r_i_2_n_0));
  FDRE dqs_found_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_found_done_r0),
        .Q(pi_dqs_found_done),
        .R(ck_po_stg2_f_en_reg_0));
  LUT6 #(
    .INIT(64'hAAAABFFFAAAA8000)) 
    dqs_found_prech_req_i_1
       (.I0(dqs_found_prech_req_i_2_n_0),
        .I1(dqs_found_prech_req_i_3_n_0),
        .I2(dqs_found_prech_req_i_4_n_0),
        .I3(prech_done),
        .I4(dqs_found_prech_req_i_5_n_0),
        .I5(dqs_found_prech_req),
        .O(dqs_found_prech_req_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFF080A0A0808)) 
    dqs_found_prech_req_i_2
       (.I0(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),
        .I1(first_fail_detect_reg_n_0),
        .I2(fine_adj_state_r[2]),
        .I3(first_fail_detect_i_1_n_0),
        .I4(\first_fail_taps[5]_i_2_n_0 ),
        .I5(dqs_found_prech_req_i_6_n_0),
        .O(dqs_found_prech_req_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT2 #(
    .INIT(4'h8)) 
    dqs_found_prech_req_i_3
       (.I0(fine_adj_state_r[1]),
        .I1(fine_adj_state_r[3]),
        .O(dqs_found_prech_req_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT2 #(
    .INIT(4'h8)) 
    dqs_found_prech_req_i_4
       (.I0(Q),
        .I1(fine_adj_state_r[2]),
        .O(dqs_found_prech_req_i_4_n_0));
  LUT6 #(
    .INIT(64'hFF3FAA0800000000)) 
    dqs_found_prech_req_i_5
       (.I0(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),
        .I1(first_fail_detect_reg_n_0),
        .I2(\dec_cnt[5]_i_12_n_0 ),
        .I3(pi_dqs_found_all_bank),
        .I4(\FSM_sequential_fine_adj_state_r[3]_i_7_n_0 ),
        .I5(stable_pass_cnt),
        .O(dqs_found_prech_req_i_5_n_0));
  LUT6 #(
    .INIT(64'h0000000000040000)) 
    dqs_found_prech_req_i_6
       (.I0(fine_adj_state_r[2]),
        .I1(dqs_found_prech_req_i_7_n_0),
        .I2(\inc_cnt_reg_n_0_[0] ),
        .I3(\inc_cnt_reg_n_0_[1] ),
        .I4(\inc_cnt_reg_n_0_[3] ),
        .I5(\inc_cnt_reg_n_0_[5] ),
        .O(dqs_found_prech_req_i_6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT2 #(
    .INIT(4'h6)) 
    dqs_found_prech_req_i_7
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\inc_cnt_reg_n_0_[4] ),
        .O(dqs_found_prech_req_i_7_n_0));
  FDRE dqs_found_prech_req_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_found_prech_req_i_1_n_0),
        .Q(dqs_found_prech_req),
        .R(ck_po_stg2_f_en_reg_0));
  FDRE dqs_found_start_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_found_start_r_reg_0),
        .Q(dqs_found_start_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00400000)) 
    final_dec_done_i_1
       (.I0(\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ),
        .I1(init_dec_done_i_2_n_0),
        .I2(fine_adj_state_r[3]),
        .I3(fine_adj_state_r[1]),
        .I4(init_dec_done_reg_n_0),
        .I5(final_dec_done_reg_n_0),
        .O(final_dec_done_i_1_n_0));
  FDRE final_dec_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(final_dec_done_i_1_n_0),
        .Q(final_dec_done_reg_n_0),
        .R(ck_po_stg2_f_en_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00001000)) 
    fine_adjust_done_r_i_1
       (.I0(fine_adj_state_r[3]),
        .I1(Q),
        .I2(pi_dqs_found_all_bank),
        .I3(fine_adj_state_r[1]),
        .I4(fine_adj_state_r[2]),
        .I5(fine_adjust_done_r_reg_0),
        .O(fine_adjust_done_r_i_1_n_0));
  FDRE fine_adjust_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(fine_adjust_done_r_i_1_n_0),
        .Q(fine_adjust_done_r_reg_0),
        .R(ck_po_stg2_f_en_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000002)) 
    fine_adjust_i_1
       (.I0(init_dqsfound_done_r5),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[3]),
        .I3(fine_adj_state_r[2]),
        .I4(Q),
        .I5(fine_adjust_reg_n_0),
        .O(fine_adjust_i_1_n_0));
  FDRE fine_adjust_reg
       (.C(CLK),
        .CE(1'b1),
        .D(fine_adjust_i_1_n_0),
        .Q(fine_adjust_reg_n_0),
        .R(ck_po_stg2_f_en_reg_0));
  LUT6 #(
    .INIT(64'h00007FFFFFFFFFFF)) 
    first_fail_detect_i_1
       (.I0(stable_pass_cnt_reg[3]),
        .I1(stable_pass_cnt_reg[1]),
        .I2(stable_pass_cnt_reg[2]),
        .I3(stable_pass_cnt_reg[4]),
        .I4(stable_pass_cnt_reg[5]),
        .I5(first_fail_detect_reg_n_0),
        .O(first_fail_detect_i_1_n_0));
  FDRE first_fail_detect_reg
       (.C(CLK),
        .CE(first_fail_detect),
        .D(first_fail_detect_i_1_n_0),
        .Q(first_fail_detect_reg_n_0),
        .R(in0));
  LUT6 #(
    .INIT(64'h0000004000000000)) 
    \first_fail_taps[5]_i_1 
       (.I0(fine_adj_state_r[2]),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[3]),
        .I3(\first_fail_taps[5]_i_2_n_0 ),
        .I4(Q),
        .I5(first_fail_detect_i_1_n_0),
        .O(first_fail_detect));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \first_fail_taps[5]_i_2 
       (.I0(pi_dqs_found_all_bank),
        .I1(detect_pi_found_dqs),
        .O(\first_fail_taps[5]_i_2_n_0 ));
  FDRE \first_fail_taps_reg[0] 
       (.C(CLK),
        .CE(first_fail_detect),
        .D(\inc_cnt_reg_n_0_[0] ),
        .Q(\first_fail_taps_reg_n_0_[0] ),
        .R(ck_po_stg2_f_en_reg_0));
  FDRE \first_fail_taps_reg[1] 
       (.C(CLK),
        .CE(first_fail_detect),
        .D(\inc_cnt_reg_n_0_[1] ),
        .Q(\first_fail_taps_reg_n_0_[1] ),
        .R(ck_po_stg2_f_en_reg_0));
  FDRE \first_fail_taps_reg[2] 
       (.C(CLK),
        .CE(first_fail_detect),
        .D(\inc_cnt_reg_n_0_[2] ),
        .Q(\first_fail_taps_reg_n_0_[2] ),
        .R(ck_po_stg2_f_en_reg_0));
  FDRE \first_fail_taps_reg[3] 
       (.C(CLK),
        .CE(first_fail_detect),
        .D(\inc_cnt_reg_n_0_[3] ),
        .Q(\first_fail_taps_reg_n_0_[3] ),
        .R(ck_po_stg2_f_en_reg_0));
  FDRE \first_fail_taps_reg[4] 
       (.C(CLK),
        .CE(first_fail_detect),
        .D(\inc_cnt_reg_n_0_[4] ),
        .Q(\first_fail_taps_reg_n_0_[4] ),
        .R(ck_po_stg2_f_en_reg_0));
  FDRE \first_fail_taps_reg[5] 
       (.C(CLK),
        .CE(first_fail_detect),
        .D(\inc_cnt_reg_n_0_[5] ),
        .Q(\first_fail_taps_reg_n_0_[5] ),
        .R(ck_po_stg2_f_en_reg_0));
  LUT6 #(
    .INIT(64'hFBFBFBFBBBFBFBFB)) 
    \gen_byte_sel_div2.byte_sel_cnt[1]_i_4 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ),
        .I1(cmd_delay_start0),
        .I2(ck_addr_cmd_delay_done),
        .I3(pi_calib_done),
        .I4(pi_dqs_found_done),
        .I5(byte_sel_cnt1),
        .O(RSTB));
  LUT2 #(
    .INIT(4'h2)) 
    \gen_byte_sel_div2.byte_sel_cnt[1]_i_5 
       (.I0(rd_data_offset_cal_done),
        .I1(fine_adjust_done_r_reg_0),
        .O(byte_sel_cnt1));
  LUT6 #(
    .INIT(64'hA2AAA2A2A200A2A2)) 
    \gen_byte_sel_div2.calib_in_common_i_2 
       (.I0(ck_addr_cmd_delay_done),
        .I1(pi_calib_done),
        .I2(\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .I3(fine_adjust_done_r_reg_0),
        .I4(rd_data_offset_cal_done),
        .I5(rst_stg1_cal),
        .O(calib_in_common4_out));
  LUT6 #(
    .INIT(64'hDFDFFFDFFFFFFFFF)) 
    \gen_byte_sel_div2.calib_in_common_i_3 
       (.I0(pi_dqs_found_done),
        .I1(\gen_byte_sel_div2.calib_in_common_reg_1 ),
        .I2(pi_calib_done),
        .I3(rd_data_offset_cal_done),
        .I4(fine_adjust_done_r_reg_0),
        .I5(ck_addr_cmd_delay_done),
        .O(dqs_found_done_r_reg_1));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    \gen_byte_sel_div2.ctl_lane_sel[0]_i_1 
       (.I0(fine_adjust_lane_cnt),
        .I1(rst_stg1_cal),
        .I2(ck_addr_cmd_delay_done),
        .I3(ctl_lane_cnt),
        .I4(ctl_lane_sel),
        .I5(\gen_byte_sel_div2.ctl_lane_sel_reg[0] ),
        .O(\ctl_lane_cnt_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT5 #(
    .INIT(32'h08088808)) 
    \gen_byte_sel_div2.ctl_lane_sel[0]_i_2 
       (.I0(\gen_byte_sel_div2.ctl_lane_sel_reg[0]_0 ),
        .I1(\gen_byte_sel_div2.ctl_lane_sel_reg[0]_1 ),
        .I2(ck_addr_cmd_delay_done),
        .I3(rd_data_offset_cal_done),
        .I4(fine_adjust_done_r_reg_0),
        .O(ctl_lane_sel));
  LUT2 #(
    .INIT(4'h8)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_6 
       (.I0(pi_dqs_found_done),
        .I1(D),
        .O(dqs_found_done_r_reg_0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b1),
        .O(n_0_0));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b1),
        .O(n_0_1));
  LUT6 #(
    .INIT(64'hFFFFFFFF45004400)) 
    ififo_rst_i_1
       (.I0(calib_zero_inputs),
        .I1(ofifo_rst_reg),
        .I2(ofifo_rst_reg_0),
        .I3(rst_stg1_cal),
        .I4(ofifo_rst_reg_1),
        .I5(phy_if_reset),
        .O(ififo_rst_reg0));
  LUT6 #(
    .INIT(64'hFFFFFFFF54440000)) 
    ififo_rst_i_1__0
       (.I0(calib_zero_inputs),
        .I1(ofifo_rst_reg),
        .I2(ofifo_rst_reg_1),
        .I3(ofifo_rst_reg_0),
        .I4(rst_stg1_cal),
        .I5(phy_if_reset),
        .O(ififo_rst_reg0_1));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \inc_cnt[0]_i_1 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \inc_cnt[1]_i_1 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \inc_cnt[2]_i_1 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[2] ),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \inc_cnt[3]_i_1 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[2] ),
        .I3(\inc_cnt_reg_n_0_[3] ),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \inc_cnt[4]_i_1 
       (.I0(\inc_cnt_reg_n_0_[1] ),
        .I1(\inc_cnt_reg_n_0_[2] ),
        .I2(\inc_cnt_reg_n_0_[0] ),
        .I3(\inc_cnt_reg_n_0_[3] ),
        .I4(\inc_cnt_reg_n_0_[4] ),
        .O(p_0_in__0[4]));
  LUT5 #(
    .INIT(32'h00080000)) 
    \inc_cnt[5]_i_1 
       (.I0(fine_adjust_lane_cnt),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[3]),
        .I3(Q),
        .I4(fine_adj_state_r[2]),
        .O(inc_cnt));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \inc_cnt[5]_i_2 
       (.I0(\inc_cnt_reg_n_0_[1] ),
        .I1(\inc_cnt_reg_n_0_[0] ),
        .I2(\inc_cnt_reg_n_0_[2] ),
        .I3(\inc_cnt_reg_n_0_[4] ),
        .I4(\inc_cnt_reg_n_0_[3] ),
        .I5(\inc_cnt_reg_n_0_[5] ),
        .O(\inc_cnt[5]_i_2_n_0 ));
  FDRE \inc_cnt_reg[0] 
       (.C(CLK),
        .CE(inc_cnt),
        .D(p_0_in__0[0]),
        .Q(\inc_cnt_reg_n_0_[0] ),
        .R(in0));
  FDRE \inc_cnt_reg[1] 
       (.C(CLK),
        .CE(inc_cnt),
        .D(p_0_in__0[1]),
        .Q(\inc_cnt_reg_n_0_[1] ),
        .R(in0));
  FDRE \inc_cnt_reg[2] 
       (.C(CLK),
        .CE(inc_cnt),
        .D(p_0_in__0[2]),
        .Q(\inc_cnt_reg_n_0_[2] ),
        .R(in0));
  FDRE \inc_cnt_reg[3] 
       (.C(CLK),
        .CE(inc_cnt),
        .D(p_0_in__0[3]),
        .Q(\inc_cnt_reg_n_0_[3] ),
        .R(in0));
  FDRE \inc_cnt_reg[4] 
       (.C(CLK),
        .CE(inc_cnt),
        .D(p_0_in__0[4]),
        .Q(\inc_cnt_reg_n_0_[4] ),
        .R(in0));
  FDRE \inc_cnt_reg[5] 
       (.C(CLK),
        .CE(inc_cnt),
        .D(\inc_cnt[5]_i_2_n_0 ),
        .Q(\inc_cnt_reg_n_0_[5] ),
        .R(in0));
  LUT1 #(
    .INIT(2'h1)) 
    \init_dec_cnt[0]_i_1 
       (.I0(init_dec_cnt_reg[0]),
        .O(init_dec_cnt0));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \init_dec_cnt[1]_i_1 
       (.I0(init_dec_cnt_reg[0]),
        .I1(init_dec_cnt_reg[1]),
        .O(\init_dec_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \init_dec_cnt[2]_i_1 
       (.I0(init_dec_cnt_reg[1]),
        .I1(init_dec_cnt_reg[0]),
        .I2(init_dec_cnt_reg[2]),
        .O(\init_dec_cnt[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \init_dec_cnt[3]_i_1 
       (.I0(init_dec_cnt_reg[2]),
        .I1(init_dec_cnt_reg[0]),
        .I2(init_dec_cnt_reg[1]),
        .I3(init_dec_cnt_reg[3]),
        .O(\init_dec_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \init_dec_cnt[4]_i_1 
       (.I0(init_dec_cnt_reg[3]),
        .I1(init_dec_cnt_reg[1]),
        .I2(init_dec_cnt_reg[0]),
        .I3(init_dec_cnt_reg[2]),
        .I4(init_dec_cnt_reg[4]),
        .O(\init_dec_cnt[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    \init_dec_cnt[5]_i_1 
       (.I0(fine_adj_state_r[2]),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[3]),
        .I3(Q),
        .I4(fine_adjust_lane_cnt),
        .I5(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ),
        .O(init_dec_cnt));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    \init_dec_cnt[5]_i_2 
       (.I0(init_dec_cnt_reg[4]),
        .I1(init_dec_cnt_reg[2]),
        .I2(init_dec_cnt_reg[0]),
        .I3(init_dec_cnt_reg[1]),
        .I4(init_dec_cnt_reg[3]),
        .I5(init_dec_cnt_reg[5]),
        .O(\init_dec_cnt[5]_i_2_n_0 ));
  FDSE \init_dec_cnt_reg[0] 
       (.C(CLK),
        .CE(init_dec_cnt),
        .D(init_dec_cnt0),
        .Q(init_dec_cnt_reg[0]),
        .S(in0));
  FDSE \init_dec_cnt_reg[1] 
       (.C(CLK),
        .CE(init_dec_cnt),
        .D(\init_dec_cnt[1]_i_1_n_0 ),
        .Q(init_dec_cnt_reg[1]),
        .S(in0));
  FDSE \init_dec_cnt_reg[2] 
       (.C(CLK),
        .CE(init_dec_cnt),
        .D(\init_dec_cnt[2]_i_1_n_0 ),
        .Q(init_dec_cnt_reg[2]),
        .S(in0));
  FDSE \init_dec_cnt_reg[3] 
       (.C(CLK),
        .CE(init_dec_cnt),
        .D(\init_dec_cnt[3]_i_1_n_0 ),
        .Q(init_dec_cnt_reg[3]),
        .S(in0));
  FDSE \init_dec_cnt_reg[4] 
       (.C(CLK),
        .CE(init_dec_cnt),
        .D(\init_dec_cnt[4]_i_1_n_0 ),
        .Q(init_dec_cnt_reg[4]),
        .S(in0));
  FDRE \init_dec_cnt_reg[5] 
       (.C(CLK),
        .CE(init_dec_cnt),
        .D(\init_dec_cnt[5]_i_2_n_0 ),
        .Q(init_dec_cnt_reg[5]),
        .R(in0));
  LUT6 #(
    .INIT(64'hCCCCCCCCCDCCCCCC)) 
    init_dec_done_i_1
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ),
        .I1(init_dec_done_reg_n_0),
        .I2(fine_adj_state_r[1]),
        .I3(fine_adj_state_r[3]),
        .I4(init_dec_done_i_2_n_0),
        .I5(\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ),
        .O(init_dec_done_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT2 #(
    .INIT(4'h2)) 
    init_dec_done_i_2
       (.I0(fine_adj_state_r[2]),
        .I1(Q),
        .O(init_dec_done_i_2_n_0));
  FDRE init_dec_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_dec_done_i_1_n_0),
        .Q(init_dec_done_reg_n_0),
        .R(ck_po_stg2_f_en_reg_0));
  FDRE init_dqsfound_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rd_data_offset_cal_done),
        .Q(init_dqsfound_done_r1_reg_n_0),
        .R(1'b0));
  FDRE init_dqsfound_done_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_dqsfound_done_r1_reg_n_0),
        .Q(init_dqsfound_done_r2),
        .R(1'b0));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r4_reg_srl2 " *) 
  SRL16E init_dqsfound_done_r4_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(init_dqsfound_done_r2),
        .Q(init_dqsfound_done_r4_reg_srl2_n_0));
  FDRE init_dqsfound_done_r5_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_dqsfound_done_r4_reg_srl2_n_0),
        .Q(init_dqsfound_done_r5),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0010001000101110)) 
    init_dqsfound_done_r_i_1
       (.I0(\pi_rst_stg1_cal_r_reg[0]_0 ),
        .I1(pi_rst_stg1_cal_r),
        .I2(rd_data_offset_cal_done),
        .I3(pi_dqs_found_all_bank),
        .I4(\rnk_cnt_r_reg_n_0_[0] ),
        .I5(\rnk_cnt_r_reg_n_0_[1] ),
        .O(init_dqsfound_done_r_i_1_n_0));
  FDRE init_dqsfound_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_dqsfound_done_r_i_1_n_0),
        .Q(rd_data_offset_cal_done),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF45004400)) 
    ofifo_rst_i_1
       (.I0(calib_zero_inputs),
        .I1(ofifo_rst_reg),
        .I2(ofifo_rst_reg_0),
        .I3(rst_stg1_cal),
        .I4(ofifo_rst_reg_1),
        .I5(A_rst_primitives),
        .O(ofifo_rst_reg0));
  LUT6 #(
    .INIT(64'hFFFFFFFF54440000)) 
    ofifo_rst_i_1__0
       (.I0(calib_zero_inputs),
        .I1(ofifo_rst_reg),
        .I2(ofifo_rst_reg_1),
        .I3(ofifo_rst_reg_0),
        .I4(rst_stg1_cal),
        .I5(A_rst_primitives),
        .O(ofifo_rst_reg0_2));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_5 
       (.I0(ofifo_rst_reg_1),
        .I1(rst_stg1_cal),
        .I2(ofifo_rst_reg_0),
        .I3(ofifo_rst_reg),
        .I4(calib_zero_inputs),
        .O(\calib_sel_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_5__0 
       (.I0(rst_stg1_cal),
        .I1(ofifo_rst_reg_0),
        .I2(ofifo_rst_reg_1),
        .I3(ofifo_rst_reg),
        .I4(calib_zero_inputs),
        .O(\pi_rst_stg1_cal_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h00000000FCFC00A8)) 
    phaser_out_i_3__0
       (.I0(ofifo_rst_reg_1),
        .I1(ck_po_stg2_f_indec),
        .I2(dqs_po_stg2_f_incdec),
        .I3(ofifo_rst_reg_0),
        .I4(ofifo_rst_reg),
        .I5(calib_zero_inputs),
        .O(\calib_sel_reg[1] ));
  LUT6 #(
    .INIT(64'h00000000EEEEE000)) 
    phaser_out_i_3__2
       (.I0(ck_po_stg2_f_indec),
        .I1(dqs_po_stg2_f_incdec),
        .I2(ofifo_rst_reg_0),
        .I3(ofifo_rst_reg_1),
        .I4(ofifo_rst_reg),
        .I5(calib_zero_inputs),
        .O(ck_po_stg2_f_indec_reg_0));
  LUT6 #(
    .INIT(64'h0000000000000054)) 
    phaser_out_i_4
       (.I0(ofifo_rst_reg),
        .I1(ck_po_stg2_f_indec),
        .I2(dqs_po_stg2_f_incdec),
        .I3(ofifo_rst_reg_0),
        .I4(ofifo_rst_reg_1),
        .I5(calib_zero_inputs),
        .O(\gen_byte_sel_div2.calib_in_common_reg ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \pi_dqs_found_all_bank[0]_i_1 
       (.I0(pi_dqs_found_lanes_r3[3]),
        .I1(pi_dqs_found_lanes_r3[2]),
        .I2(dqs_found_start_r_reg_0),
        .I3(pi_dqs_found_all_bank),
        .O(\pi_dqs_found_all_bank[0]_i_1_n_0 ));
  FDRE \pi_dqs_found_all_bank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_all_bank),
        .Q(pi_dqs_found_all_bank_r),
        .R(1'b0));
  FDRE \pi_dqs_found_all_bank_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_dqs_found_all_bank[0]_i_1_n_0 ),
        .Q(pi_dqs_found_all_bank),
        .R(ck_po_stg2_f_en_reg_0));
  LUT4 #(
    .INIT(16'hEFE0)) 
    \pi_dqs_found_any_bank[0]_i_1 
       (.I0(pi_dqs_found_lanes_r3[3]),
        .I1(pi_dqs_found_lanes_r3[2]),
        .I2(dqs_found_start_r_reg_0),
        .I3(pi_dqs_found_any_bank),
        .O(\pi_dqs_found_any_bank[0]_i_1_n_0 ));
  FDRE \pi_dqs_found_any_bank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_any_bank),
        .Q(pi_dqs_found_any_bank_r),
        .R(1'b0));
  FDRE \pi_dqs_found_any_bank_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_dqs_found_any_bank[0]_i_1_n_0 ),
        .Q(pi_dqs_found_any_bank),
        .R(ck_po_stg2_f_en_reg_0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(n_0_1),
        .Q(pi_dqs_found_lanes_r1[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(n_0_0),
        .Q(pi_dqs_found_lanes_r1[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes[0]),
        .Q(pi_dqs_found_lanes_r1[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes[1]),
        .Q(pi_dqs_found_lanes_r1[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[0]),
        .Q(pi_dqs_found_lanes_r2[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[1]),
        .Q(pi_dqs_found_lanes_r2[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[2]),
        .Q(pi_dqs_found_lanes_r2[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[3]),
        .Q(pi_dqs_found_lanes_r2[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[0]),
        .Q(pi_dqs_found_lanes_r3[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[1]),
        .Q(pi_dqs_found_lanes_r3[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[2]),
        .Q(pi_dqs_found_lanes_r3[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[3]),
        .Q(pi_dqs_found_lanes_r3[3]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \pi_rst_stg1_cal[0]_i_1 
       (.I0(pi_rst_stg1_cal_r),
        .I1(rst_dqs_find__0),
        .O(\pi_rst_stg1_cal[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1110111011101100)) 
    \pi_rst_stg1_cal_r1[0]_i_1 
       (.I0(\pi_rst_stg1_cal_r_reg[0]_0 ),
        .I1(fine_adjust_reg_n_0),
        .I2(\pi_rst_stg1_cal_r1_reg_n_0_[0] ),
        .I3(pi_rst_stg1_cal_r),
        .I4(pi_dqs_found_any_bank_r),
        .I5(pi_dqs_found_all_bank),
        .O(\pi_rst_stg1_cal_r1[0]_i_1_n_0 ));
  FDRE \pi_rst_stg1_cal_r1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal_r1[0]_i_1_n_0 ),
        .Q(\pi_rst_stg1_cal_r1_reg_n_0_[0] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0004)) 
    \pi_rst_stg1_cal_r[0]_i_1 
       (.I0(\pi_rst_stg1_cal_r1_reg_n_0_[0] ),
        .I1(\pi_rst_stg1_cal_r[0]_i_2_n_0 ),
        .I2(\pi_rst_stg1_cal_r_reg[0]_0 ),
        .I3(fine_adjust_reg_n_0),
        .O(\pi_rst_stg1_cal_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF2F22)) 
    \pi_rst_stg1_cal_r[0]_i_2 
       (.I0(dqs_found_start_r_reg_0),
        .I1(dqs_found_start_r),
        .I2(pi_dqs_found_all_bank),
        .I3(pi_dqs_found_any_bank_r),
        .I4(\rd_byte_data_offset[0][5]_i_4_n_0 ),
        .I5(pi_rst_stg1_cal_r),
        .O(\pi_rst_stg1_cal_r[0]_i_2_n_0 ));
  FDRE \pi_rst_stg1_cal_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal_r[0]_i_1_n_0 ),
        .Q(pi_rst_stg1_cal_r),
        .R(1'b0));
  FDRE \pi_rst_stg1_cal_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal[0]_i_1_n_0 ),
        .Q(rst_stg1_cal),
        .R(ck_po_stg2_f_en_reg_0));
  FDRE rank_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_rank_done),
        .Q(rank_done_r1),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0404040404040004)) 
    rank_done_r_i_1
       (.I0(\pi_rst_stg1_cal_r_reg[0]_0 ),
        .I1(pi_dqs_found_all_bank),
        .I2(pi_dqs_found_all_bank_r),
        .I3(rd_data_offset_cal_done),
        .I4(\rnk_cnt_r_reg_n_0_[0] ),
        .I5(\rnk_cnt_r_reg_n_0_[1] ),
        .O(rank_done_r_i_1_n_0));
  FDRE rank_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rank_done_r_i_1_n_0),
        .Q(pi_dqs_found_rank_done),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset[0][5]_i_1 
       (.I0(rd_data_offset_cal_done),
        .I1(init_dqsfound_done_r1_reg_n_0),
        .O(p_44_out));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1 
       (.I0(\rd_byte_data_offset_reg[0]_10 [0]),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1 
       (.I0(\rd_byte_data_offset_reg[0]_10 [1]),
        .I1(\rd_byte_data_offset_reg[0]_10 [0]),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1 
       (.I0(\rd_byte_data_offset_reg[0]_10 [1]),
        .I1(\rd_byte_data_offset_reg[0]_10 [0]),
        .I2(\rd_byte_data_offset_reg[0]_10 [2]),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1 
       (.I0(\rd_byte_data_offset_reg[0]_10 [0]),
        .I1(\rd_byte_data_offset_reg[0]_10 [1]),
        .I2(\rd_byte_data_offset_reg[0]_10 [2]),
        .I3(\rd_byte_data_offset_reg[0]_10 [3]),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1 
       (.I0(\rd_byte_data_offset_reg[0]_10 [0]),
        .I1(\rd_byte_data_offset_reg[0]_10 [2]),
        .I2(\rd_byte_data_offset_reg[0]_10 [1]),
        .I3(\rd_byte_data_offset_reg[0]_10 [3]),
        .I4(\rd_byte_data_offset_reg[0]_10 [4]),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h10)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1 
       (.I0(\detect_rd_cnt_reg[2]_0 ),
        .I1(init_dqsfound_done_r1_reg_n_0),
        .I2(rd_data_offset_cal_done),
        .O(final_data_offset_mc));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2 
       (.I0(\rd_byte_data_offset_reg[0]_10 [2]),
        .I1(\rd_byte_data_offset_reg[0]_10 [1]),
        .I2(\rd_byte_data_offset_reg[0]_10 [3]),
        .I3(\rd_byte_data_offset_reg[0]_10 [0]),
        .I4(\rd_byte_data_offset_reg[0]_10 [4]),
        .I5(\rd_byte_data_offset_reg[0]_10 [5]),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] 
       (.C(CLK),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [0]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][1] 
       (.C(CLK),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [1]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2] 
       (.C(CLK),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [2]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][3] 
       (.C(CLK),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [3]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] 
       (.C(CLK),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [4]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] 
       (.C(CLK),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [5]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][0] 
       (.C(CLK),
        .CE(p_44_out),
        .D(\rd_byte_data_offset_reg[0]_10 [0]),
        .Q(rd_data_offset_ranks_0[0]),
        .R(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]_0 ));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][1] 
       (.C(CLK),
        .CE(p_44_out),
        .D(\rd_byte_data_offset_reg[0]_10 [1]),
        .Q(rd_data_offset_ranks_0[1]),
        .R(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]_0 ));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2] 
       (.C(CLK),
        .CE(p_44_out),
        .D(\rd_byte_data_offset_reg[0]_10 [2]),
        .Q(rd_data_offset_ranks_0[2]),
        .R(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]_0 ));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] 
       (.C(CLK),
        .CE(p_44_out),
        .D(\rd_byte_data_offset_reg[0]_10 [3]),
        .Q(rd_data_offset_ranks_0[3]),
        .R(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]_0 ));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][4] 
       (.C(CLK),
        .CE(p_44_out),
        .D(\rd_byte_data_offset_reg[0]_10 [4]),
        .Q(rd_data_offset_ranks_0[4]),
        .R(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]_0 ));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5] 
       (.C(CLK),
        .CE(p_44_out),
        .D(\rd_byte_data_offset_reg[0]_10 [5]),
        .Q(rd_data_offset_ranks_0[5]),
        .R(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_byte_data_offset[0][1]_i_1 
       (.I0(\rd_byte_data_offset_reg[0]_10 [0]),
        .I1(\rd_byte_data_offset_reg[0]_10 [1]),
        .O(\rd_byte_data_offset[0][1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \rd_byte_data_offset[0][2]_i_1 
       (.I0(\rd_byte_data_offset_reg[0]_10 [1]),
        .I1(\rd_byte_data_offset_reg[0]_10 [0]),
        .I2(\rd_byte_data_offset_reg[0]_10 [2]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \rd_byte_data_offset[0][3]_i_1 
       (.I0(\rd_byte_data_offset_reg[0]_10 [2]),
        .I1(\rd_byte_data_offset_reg[0]_10 [0]),
        .I2(\rd_byte_data_offset_reg[0]_10 [1]),
        .I3(\rd_byte_data_offset_reg[0]_10 [3]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \rd_byte_data_offset[0][4]_i_1 
       (.I0(\rd_byte_data_offset_reg[0]_10 [0]),
        .I1(\rd_byte_data_offset_reg[0]_10 [1]),
        .I2(\rd_byte_data_offset_reg[0]_10 [2]),
        .I3(\rd_byte_data_offset_reg[0]_10 [3]),
        .I4(\rd_byte_data_offset_reg[0]_10 [4]),
        .O(p_0_in[4]));
  LUT6 #(
    .INIT(64'hAAAAAAFFAAAAAABA)) 
    \rd_byte_data_offset[0][5]_i_1 
       (.I0(\pi_rst_stg1_cal_r_reg[0]_0 ),
        .I1(rd_data_offset_cal_done),
        .I2(rank_done_r1),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(\rnk_cnt_r_reg_n_0_[1] ),
        .I5(\rd_byte_data_offset[0][5]_i_4_n_0 ),
        .O(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h01FF000000000000)) 
    \rd_byte_data_offset[0][5]_i_2 
       (.I0(\rd_byte_data_offset_reg[0]_10 [1]),
        .I1(\rd_byte_data_offset_reg[0]_10 [2]),
        .I2(\rd_byte_data_offset_reg[0]_10 [3]),
        .I3(\rd_byte_data_offset_reg[0]_10 [4]),
        .I4(\rd_byte_data_offset[0][5]_i_5_n_0 ),
        .I5(\rd_byte_data_offset[0][5]_i_6_n_0 ),
        .O(rd_byte_data_offset));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \rd_byte_data_offset[0][5]_i_3 
       (.I0(\rd_byte_data_offset_reg[0]_10 [0]),
        .I1(\rd_byte_data_offset_reg[0]_10 [1]),
        .I2(\rd_byte_data_offset_reg[0]_10 [4]),
        .I3(\rd_byte_data_offset_reg[0]_10 [3]),
        .I4(\rd_byte_data_offset_reg[0]_10 [2]),
        .I5(\rd_byte_data_offset_reg[0]_10 [5]),
        .O(p_0_in[5]));
  LUT5 #(
    .INIT(32'hFFFFAAA8)) 
    \rd_byte_data_offset[0][5]_i_4 
       (.I0(\rd_byte_data_offset_reg[0]_10 [4]),
        .I1(\rd_byte_data_offset_reg[0]_10 [2]),
        .I2(\rd_byte_data_offset_reg[0]_10 [1]),
        .I3(\rd_byte_data_offset_reg[0]_10 [3]),
        .I4(\rd_byte_data_offset_reg[0]_10 [5]),
        .O(\rd_byte_data_offset[0][5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \rd_byte_data_offset[0][5]_i_5 
       (.I0(\rnk_cnt_r_reg_n_0_[0] ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .I2(\first_fail_taps[5]_i_2_n_0 ),
        .I3(detect_rd_cnt_reg[3]),
        .I4(detect_rd_cnt_reg[1]),
        .I5(detect_rd_cnt_reg[2]),
        .O(\rd_byte_data_offset[0][5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000020)) 
    \rd_byte_data_offset[0][5]_i_6 
       (.I0(detect_rd_cnt_reg[0]),
        .I1(\rd_byte_data_offset_reg[0]_10 [5]),
        .I2(dqs_found_start_r),
        .I3(rank_done_r1),
        .I4(fine_adjust_reg_n_0),
        .I5(rd_data_offset_cal_done),
        .O(\rd_byte_data_offset[0][5]_i_6_n_0 ));
  FDSE \rd_byte_data_offset_reg[0][0] 
       (.C(CLK),
        .CE(rd_byte_data_offset),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ),
        .Q(\rd_byte_data_offset_reg[0]_10 [0]),
        .S(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDSE \rd_byte_data_offset_reg[0][1] 
       (.C(CLK),
        .CE(rd_byte_data_offset),
        .D(\rd_byte_data_offset[0][1]_i_1_n_0 ),
        .Q(\rd_byte_data_offset_reg[0]_10 [1]),
        .S(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][2] 
       (.C(CLK),
        .CE(rd_byte_data_offset),
        .D(p_0_in[2]),
        .Q(\rd_byte_data_offset_reg[0]_10 [2]),
        .R(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][3] 
       (.C(CLK),
        .CE(rd_byte_data_offset),
        .D(p_0_in[3]),
        .Q(\rd_byte_data_offset_reg[0]_10 [3]),
        .R(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][4] 
       (.C(CLK),
        .CE(rd_byte_data_offset),
        .D(p_0_in[4]),
        .Q(\rd_byte_data_offset_reg[0]_10 [4]),
        .R(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][5] 
       (.C(CLK),
        .CE(rd_byte_data_offset),
        .D(p_0_in[5]),
        .Q(\rd_byte_data_offset_reg[0]_10 [5]),
        .R(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rnk_cnt_r[0]_i_1 
       (.I0(rd_data_offset_cal_done),
        .I1(pi_dqs_found_rank_done),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .O(\rnk_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rnk_cnt_r[1]_i_1 
       (.I0(\rnk_cnt_r_reg_n_0_[0] ),
        .I1(pi_dqs_found_rank_done),
        .I2(rd_data_offset_cal_done),
        .I3(\rnk_cnt_r_reg_n_0_[1] ),
        .O(\rnk_cnt_r[1]_i_1_n_0 ));
  FDRE \rnk_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rnk_cnt_r[0]_i_1_n_0 ),
        .Q(\rnk_cnt_r_reg_n_0_[0] ),
        .R(ck_po_stg2_f_en_reg_0));
  FDRE \rnk_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rnk_cnt_r[1]_i_1_n_0 ),
        .Q(\rnk_cnt_r_reg_n_0_[1] ),
        .R(ck_po_stg2_f_en_reg_0));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAA8)) 
    rst_dqs_find_i_1
       (.I0(rst_dqs_find),
        .I1(rst_dqs_find_i_3_n_0),
        .I2(rst_dqs_find_i_4_n_0),
        .I3(rst_dqs_find_i_5_n_0),
        .I4(rst_dqs_find_i_6_n_0),
        .I5(rst_dqs_find__0),
        .O(rst_dqs_find_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000020)) 
    rst_dqs_find_i_10
       (.I0(rst_dqs_find_r2),
        .I1(pi_dqs_found_any_bank),
        .I2(Q),
        .I3(fine_adj_state_r[2]),
        .I4(fine_adj_state_r[3]),
        .I5(fine_adj_state_r[1]),
        .O(rst_dqs_find_i_10_n_0));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT5 #(
    .INIT(32'h00080000)) 
    rst_dqs_find_i_11
       (.I0(pi_dqs_found_all_bank),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[2]),
        .I3(Q),
        .I4(detect_pi_found_dqs),
        .O(rst_dqs_find_i_11_n_0));
  LUT6 #(
    .INIT(64'h3000202000002020)) 
    rst_dqs_find_i_12
       (.I0(\dec_cnt[5]_i_5_n_0 ),
        .I1(\dec_cnt[5]_i_12_n_0 ),
        .I2(dqs_found_prech_req_i_3_n_0),
        .I3(rst_dqs_find_i_4_0),
        .I4(\inc_cnt_reg_n_0_[1] ),
        .I5(rst_dqs_find_i_18_n_0),
        .O(rst_dqs_find_i_12_n_0));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT5 #(
    .INIT(32'h00000002)) 
    rst_dqs_find_i_13
       (.I0(init_dqsfound_done_r5),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[3]),
        .I3(fine_adj_state_r[2]),
        .I4(Q),
        .O(fine_adjust));
  LUT6 #(
    .INIT(64'h00000000BB00BF00)) 
    rst_dqs_find_i_14
       (.I0(rst_dqs_find_i_19_n_0),
        .I1(\inc_cnt_reg_n_0_[3] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(detect_pi_found_dqs),
        .I4(pi_dqs_found_all_bank),
        .I5(Q),
        .O(rst_dqs_find_i_14_n_0));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT5 #(
    .INIT(32'h00001000)) 
    rst_dqs_find_i_15
       (.I0(fine_adj_state_r[3]),
        .I1(Q),
        .I2(pi_dqs_found_all_bank),
        .I3(fine_adj_state_r[1]),
        .I4(fine_adj_state_r[2]),
        .O(fine_adjust_done_r));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT5 #(
    .INIT(32'hAA2FAAAA)) 
    rst_dqs_find_i_16
       (.I0(\dec_cnt[5]_i_3_n_0 ),
        .I1(\dec_cnt[5]_i_12_n_0 ),
        .I2(first_fail_detect_reg_n_0),
        .I3(pi_dqs_found_all_bank),
        .I4(detect_pi_found_dqs),
        .O(rst_dqs_find_i_16_n_0));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    rst_dqs_find_i_18
       (.I0(\inc_cnt_reg_n_0_[3] ),
        .I1(\inc_cnt_reg_n_0_[4] ),
        .I2(\inc_cnt_reg_n_0_[2] ),
        .I3(\inc_cnt_reg_n_0_[0] ),
        .I4(\inc_cnt_reg_n_0_[5] ),
        .O(rst_dqs_find_i_18_n_0));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT4 #(
    .INIT(16'h7F00)) 
    rst_dqs_find_i_19
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[2] ),
        .I2(\inc_cnt_reg_n_0_[4] ),
        .I3(\inc_cnt_reg_n_0_[1] ),
        .O(rst_dqs_find_i_19_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEAAA)) 
    rst_dqs_find_i_2
       (.I0(rst_dqs_find_i_7_n_0),
        .I1(prech_done),
        .I2(fine_adj_state_r[1]),
        .I3(fine_adj_state_r[2]),
        .I4(rst_dqs_find_i_8_n_0),
        .I5(rst_dqs_find_i_9_n_0),
        .O(rst_dqs_find));
  LUT6 #(
    .INIT(64'hBFEAEAFFAAAAAAAA)) 
    rst_dqs_find_i_3
       (.I0(rst_dqs_find_i_10_n_0),
        .I1(\inc_cnt_reg_n_0_[3] ),
        .I2(\inc_cnt_reg_n_0_[5] ),
        .I3(\inc_cnt_reg_n_0_[2] ),
        .I4(\inc_cnt_reg_n_0_[4] ),
        .I5(rst_dqs_find_i_11_n_0),
        .O(rst_dqs_find_i_3_n_0));
  LUT6 #(
    .INIT(64'hFEEEFEFEEEEEEEEE)) 
    rst_dqs_find_i_4
       (.I0(rst_dqs_find_i_12_n_0),
        .I1(fine_adjust),
        .I2(dqs_found_prech_req_i_3_n_0),
        .I3(prech_done),
        .I4(Q),
        .I5(fine_adj_state_r[2]),
        .O(rst_dqs_find_i_4_n_0));
  LUT6 #(
    .INIT(64'h000022F200002222)) 
    rst_dqs_find_i_5
       (.I0(rst_dqs_find_i_11_n_0),
        .I1(\inc_cnt_reg_n_0_[3] ),
        .I2(rst_dqs_find_i_14_n_0),
        .I3(first_fail_detect_reg_n_0),
        .I4(\inc_cnt_reg_n_0_[5] ),
        .I5(dqs_found_prech_req_i_3_n_0),
        .O(rst_dqs_find_i_5_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF60E0E0E0)) 
    rst_dqs_find_i_6
       (.I0(\inc_cnt_reg_n_0_[1] ),
        .I1(\inc_cnt_reg_n_0_[0] ),
        .I2(rst_dqs_find_i_11_n_0),
        .I3(\inc_cnt_reg_n_0_[4] ),
        .I4(\inc_cnt_reg_n_0_[2] ),
        .I5(fine_adjust_done_r),
        .O(rst_dqs_find_i_6_n_0));
  LUT6 #(
    .INIT(64'hF200220022002200)) 
    rst_dqs_find_i_7
       (.I0(\dec_cnt[5]_i_5_n_0 ),
        .I1(first_fail_detect_reg_n_0),
        .I2(rst_dqs_find_i_16_n_0),
        .I3(fine_adj_state_r[3]),
        .I4(fine_adj_state_r[1]),
        .I5(prech_done),
        .O(rst_dqs_find_i_7_n_0));
  LUT6 #(
    .INIT(64'h0000880800008888)) 
    rst_dqs_find_i_8
       (.I0(fine_adj_state_r[3]),
        .I1(\dec_cnt[5]_i_3_n_0 ),
        .I2(detect_pi_found_dqs),
        .I3(pi_dqs_found_all_bank),
        .I4(Q),
        .I5(\dec_cnt[5]_i_12_n_0 ),
        .O(rst_dqs_find_i_8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT4 #(
    .INIT(16'h0F02)) 
    rst_dqs_find_i_9
       (.I0(init_dqsfound_done_r5),
        .I1(fine_adj_state_r[1]),
        .I2(Q),
        .I3(fine_adj_state_r[2]),
        .O(rst_dqs_find_i_9_n_0));
  FDRE rst_dqs_find_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_dqs_find__0),
        .Q(rst_dqs_find_r1),
        .R(1'b0));
  FDRE rst_dqs_find_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_dqs_find_r1),
        .Q(rst_dqs_find_r2),
        .R(1'b0));
  FDRE rst_dqs_find_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rst_dqs_find_i_1_n_0),
        .Q(rst_dqs_find__0),
        .R(ck_po_stg2_f_en_reg_0));
  LUT2 #(
    .INIT(4'h2)) 
    \stable_pass_cnt[0]_i_1 
       (.I0(pi_dqs_found_all_bank),
        .I1(\stable_pass_cnt_reg_n_0_[0] ),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \stable_pass_cnt[1]_i_1 
       (.I0(pi_dqs_found_all_bank),
        .I1(stable_pass_cnt_reg[1]),
        .I2(\stable_pass_cnt_reg_n_0_[0] ),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT4 #(
    .INIT(16'h2888)) 
    \stable_pass_cnt[2]_i_1 
       (.I0(pi_dqs_found_all_bank),
        .I1(stable_pass_cnt_reg[2]),
        .I2(stable_pass_cnt_reg[1]),
        .I3(\stable_pass_cnt_reg_n_0_[0] ),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT5 #(
    .INIT(32'h28888888)) 
    \stable_pass_cnt[3]_i_1 
       (.I0(pi_dqs_found_all_bank),
        .I1(stable_pass_cnt_reg[3]),
        .I2(\stable_pass_cnt_reg_n_0_[0] ),
        .I3(stable_pass_cnt_reg[2]),
        .I4(stable_pass_cnt_reg[1]),
        .O(p_0_in__1[3]));
  LUT6 #(
    .INIT(64'h2888888888888888)) 
    \stable_pass_cnt[4]_i_1 
       (.I0(\first_fail_taps[5]_i_2_n_0 ),
        .I1(stable_pass_cnt_reg[4]),
        .I2(\stable_pass_cnt_reg_n_0_[0] ),
        .I3(stable_pass_cnt_reg[3]),
        .I4(stable_pass_cnt_reg[1]),
        .I5(stable_pass_cnt_reg[2]),
        .O(p_0_in__1[4]));
  LUT5 #(
    .INIT(32'h00004000)) 
    \stable_pass_cnt[5]_i_1 
       (.I0(Q),
        .I1(detect_pi_found_dqs),
        .I2(fine_adj_state_r[3]),
        .I3(fine_adj_state_r[1]),
        .I4(fine_adj_state_r[2]),
        .O(stable_pass_cnt));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT4 #(
    .INIT(16'h8828)) 
    \stable_pass_cnt[5]_i_2 
       (.I0(pi_dqs_found_all_bank),
        .I1(stable_pass_cnt_reg[5]),
        .I2(\stable_pass_cnt_reg_n_0_[0] ),
        .I3(\stable_pass_cnt[5]_i_3_n_0 ),
        .O(p_0_in__1[5]));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \stable_pass_cnt[5]_i_3 
       (.I0(stable_pass_cnt_reg[3]),
        .I1(stable_pass_cnt_reg[1]),
        .I2(stable_pass_cnt_reg[2]),
        .I3(stable_pass_cnt_reg[4]),
        .O(\stable_pass_cnt[5]_i_3_n_0 ));
  FDRE \stable_pass_cnt_reg[0] 
       (.C(CLK),
        .CE(stable_pass_cnt),
        .D(p_0_in__1[0]),
        .Q(\stable_pass_cnt_reg_n_0_[0] ),
        .R(in0));
  FDRE \stable_pass_cnt_reg[1] 
       (.C(CLK),
        .CE(stable_pass_cnt),
        .D(p_0_in__1[1]),
        .Q(stable_pass_cnt_reg[1]),
        .R(in0));
  FDRE \stable_pass_cnt_reg[2] 
       (.C(CLK),
        .CE(stable_pass_cnt),
        .D(p_0_in__1[2]),
        .Q(stable_pass_cnt_reg[2]),
        .R(in0));
  FDRE \stable_pass_cnt_reg[3] 
       (.C(CLK),
        .CE(stable_pass_cnt),
        .D(p_0_in__1[3]),
        .Q(stable_pass_cnt_reg[3]),
        .R(in0));
  FDRE \stable_pass_cnt_reg[4] 
       (.C(CLK),
        .CE(stable_pass_cnt),
        .D(p_0_in__1[4]),
        .Q(stable_pass_cnt_reg[4]),
        .R(in0));
  FDRE \stable_pass_cnt_reg[5] 
       (.C(CLK),
        .CE(stable_pass_cnt),
        .D(p_0_in__1[5]),
        .Q(stable_pass_cnt_reg[5]),
        .R(in0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_init
   (prech_done,
    out,
    prech_req_posedge_r_reg_0,
    wrlvl_done_r1,
    prbs_rdlvl_done_pulse_reg_0,
    pi_calib_done,
    wl_sm_start,
    wrcal_rd_wait,
    wrcal_sanity_chk,
    detect_pi_found_dqs,
    calib_complete,
    calib_ctl_wren_reg_0,
    pi_dqs_found_done_r1,
    calib_wrdata_en,
    \one_rank.stg1_wr_done_reg_0 ,
    wrlvl_final_if_rst,
    wr_lvl_start_reg_0,
    rdlvl_stg1_start_reg_0,
    phy_write_calib,
    phy_read_calib,
    first_rdlvl_pat_r,
    first_wrcal_pat_r,
    rdlvl_stg1_done_r1_reg_0,
    calib_ctl_wren_reg_1,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ,
    phy_dout,
    E,
    \my_empty_reg[3] ,
    \my_empty_reg[5] ,
    \my_empty_reg[3]_0 ,
    \my_empty_reg[5]_0 ,
    \my_empty_reg[3]_1 ,
    mem_init_done_r,
    \init_state_r_reg[2]_0 ,
    ddr3_lm_done_r,
    \write_buffer.wr_buf_out_data_reg[96] ,
    \write_buffer.wr_buf_out_data_reg[122] ,
    mux_wrdata_en,
    mux_cmd_wren,
    mux_reset_n,
    D0,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D9,
    D1,
    \write_buffer.wr_buf_out_data_reg[108] ,
    \write_buffer.wr_buf_out_data_reg[126] ,
    \write_buffer.wr_buf_out_data_reg[121] ,
    \write_buffer.wr_buf_out_data_reg[123] ,
    \write_buffer.wr_buf_out_data_reg[127] ,
    \write_buffer.wr_buf_out_data_reg[125] ,
    \write_buffer.wr_buf_out_data_reg[122]_0 ,
    detect_pi_found_dqs_reg_0,
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 ,
    \cmd_pipe_plus.mc_cas_n_reg[1] ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0 ,
    \cmd_pipe_plus.mc_cke_reg[3] ,
    \cmd_pipe_plus.mc_cas_n_reg[1]_0 ,
    \cmd_pipe_plus.mc_we_n_reg[1] ,
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_1 ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0 ,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0 ,
    wrcal_start_reg_0,
    pi_dqs_found_start_reg_0,
    mpr_rdlvl_start_reg_0,
    \calib_seq_reg[1]_0 ,
    CLK,
    pi_phase_locked_all_r1_reg_0,
    init_calib_complete_reg_0,
    wrlvl_done_r_reg_0,
    wrlvl_rank_done,
    prbs_rdlvl_done_pulse0,
    wrcal_resume_w,
    D,
    rdlvl_last_byte_done,
    \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ,
    pi_dqs_found_done,
    phy_ctl_wr_i1_reg,
    wr_lvl_start_reg_1,
    \init_state_r[2]_i_7_0 ,
    \init_state_r[2]_i_7_1 ,
    complex_row0_rd_done_reg_0,
    burst_addr_r_reg_0,
    \init_state_r[1]_i_3_0 ,
    wrlvl_byte_redo,
    wrcal_prech_req,
    \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ,
    \wr_ptr_timing_reg[0] ,
    \wr_ptr_timing_reg[0]_0 ,
    wr_en_inferred__0_i_1_0,
    \wr_ptr_timing_reg[0]_1 ,
    wr_en_inferred__0_i_1__0_0,
    \wr_ptr_timing_reg[0]_2 ,
    wr_en_inferred__0_i_1__1_0,
    \calib_data_offset_0_reg[3]_0 ,
    ck_addr_cmd_delay_done,
    Q,
    \num_refresh_reg[3]_0 ,
    rdlvl_pi_incdec,
    rdlvl_prech_req,
    dqs_found_prech_req,
    done_dqs_tap_inc,
    rdlvl_stg1_rank_done,
    \init_state_r[2]_i_6_0 ,
    \init_state_r[0]_i_7_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_1 ,
    \init_state_r[4]_i_4_0 ,
    \init_state_r_reg[0]_0 ,
    \init_state_r[4]_i_7_0 ,
    \init_state_r[2]_i_7_2 ,
    \init_state_r[2]_i_7_3 ,
    pi_dqs_found_rank_done,
    out_fifo,
    \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ,
    \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ,
    mc_wrdata_en,
    mc_cas_n,
    mc_ras_n,
    mc_odt,
    mc_cke,
    mc_we_n,
    \phy_ctl_wd_i1_reg[22] ,
    out_fifo_0,
    out_fifo_1,
    out_fifo_2,
    out_fifo_3,
    out_fifo_4,
    out_fifo_5,
    out_fifo_6,
    mc_address,
    rst_dqs_find_i_12,
    mc_bank,
    out_fifo_7,
    out_fifo_8,
    out_fifo_9,
    out_fifo_10,
    mem_out,
    out_fifo_11,
    \en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 ,
    \calib_data_offset_0_reg[5]_0 ,
    \calib_data_offset_0_reg[4]_0 ,
    \calib_data_offset_0_reg[2]_0 ,
    \calib_data_offset_0_reg[1]_0 ,
    \calib_data_offset_0_reg[0]_0 ,
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0 ,
    \cnt_pwron_ce_r_reg[9]_0 ,
    mc_cmd,
    \phy_ctl_wd_i1_reg[17] ,
    \phy_ctl_wd_i1_reg[18] ,
    \phy_ctl_wd_i1_reg[19] ,
    mc_data_offset,
    \phy_ctl_wd_i1_reg[21] ,
    \phy_ctl_wd_i1_reg[22]_0 );
  output prech_done;
  output out;
  output prech_req_posedge_r_reg_0;
  output wrlvl_done_r1;
  output prbs_rdlvl_done_pulse_reg_0;
  output pi_calib_done;
  output wl_sm_start;
  output wrcal_rd_wait;
  output wrcal_sanity_chk;
  output detect_pi_found_dqs;
  output calib_complete;
  output calib_ctl_wren_reg_0;
  output pi_dqs_found_done_r1;
  output calib_wrdata_en;
  output \one_rank.stg1_wr_done_reg_0 ;
  output wrlvl_final_if_rst;
  output wr_lvl_start_reg_0;
  output rdlvl_stg1_start_reg_0;
  output phy_write_calib;
  output phy_read_calib;
  output first_rdlvl_pat_r;
  output first_wrcal_pat_r;
  output rdlvl_stg1_done_r1_reg_0;
  output calib_ctl_wren_reg_1;
  output [32:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ;
  output [32:0]phy_dout;
  output [0:0]E;
  output \my_empty_reg[3] ;
  output [0:0]\my_empty_reg[5] ;
  output \my_empty_reg[3]_0 ;
  output [0:0]\my_empty_reg[5]_0 ;
  output \my_empty_reg[3]_1 ;
  output mem_init_done_r;
  output \init_state_r_reg[2]_0 ;
  output ddr3_lm_done_r;
  output [43:0]\write_buffer.wr_buf_out_data_reg[96] ;
  output [43:0]\write_buffer.wr_buf_out_data_reg[122] ;
  output mux_wrdata_en;
  output mux_cmd_wren;
  output mux_reset_n;
  output [5:0]D0;
  output [4:0]D2;
  output [4:0]D3;
  output [5:0]D4;
  output [5:0]D5;
  output [4:0]D6;
  output [4:0]D7;
  output [5:0]D9;
  output [5:0]D1;
  output [5:0]\write_buffer.wr_buf_out_data_reg[108] ;
  output [4:0]\write_buffer.wr_buf_out_data_reg[126] ;
  output [5:0]\write_buffer.wr_buf_out_data_reg[121] ;
  output [4:0]\write_buffer.wr_buf_out_data_reg[123] ;
  output [4:0]\write_buffer.wr_buf_out_data_reg[127] ;
  output [5:0]\write_buffer.wr_buf_out_data_reg[125] ;
  output [4:0]\write_buffer.wr_buf_out_data_reg[122]_0 ;
  output detect_pi_found_dqs_reg_0;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0 ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 ;
  output [0:0]\cmd_pipe_plus.mc_cas_n_reg[1] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0 ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0 ;
  output [7:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  output [1:0]\cmd_pipe_plus.mc_cas_n_reg[1]_0 ;
  output [0:0]\cmd_pipe_plus.mc_we_n_reg[1] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_1 ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0 ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0 ;
  output [7:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0 ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0 ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0 ;
  output wrcal_start_reg_0;
  output pi_dqs_found_start_reg_0;
  output mpr_rdlvl_start_reg_0;
  output [10:0]\calib_seq_reg[1]_0 ;
  input CLK;
  input pi_phase_locked_all_r1_reg_0;
  input init_calib_complete_reg_0;
  input wrlvl_done_r_reg_0;
  input wrlvl_rank_done;
  input prbs_rdlvl_done_pulse0;
  input wrcal_resume_w;
  input [4:0]D;
  input rdlvl_last_byte_done;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ;
  input pi_dqs_found_done;
  input phy_ctl_wr_i1_reg;
  input wr_lvl_start_reg_1;
  input \init_state_r[2]_i_7_0 ;
  input \init_state_r[2]_i_7_1 ;
  input complex_row0_rd_done_reg_0;
  input burst_addr_r_reg_0;
  input \init_state_r[1]_i_3_0 ;
  input wrlvl_byte_redo;
  input wrcal_prech_req;
  input \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ;
  input \wr_ptr_timing_reg[0] ;
  input \wr_ptr_timing_reg[0]_0 ;
  input wr_en_inferred__0_i_1_0;
  input \wr_ptr_timing_reg[0]_1 ;
  input wr_en_inferred__0_i_1__0_0;
  input \wr_ptr_timing_reg[0]_2 ;
  input wr_en_inferred__0_i_1__1_0;
  input \calib_data_offset_0_reg[3]_0 ;
  input ck_addr_cmd_delay_done;
  input [0:0]Q;
  input \num_refresh_reg[3]_0 ;
  input rdlvl_pi_incdec;
  input rdlvl_prech_req;
  input dqs_found_prech_req;
  input done_dqs_tap_inc;
  input rdlvl_stg1_rank_done;
  input \init_state_r[2]_i_6_0 ;
  input \init_state_r[0]_i_7_0 ;
  input \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_1 ;
  input \init_state_r[4]_i_4_0 ;
  input \init_state_r_reg[0]_0 ;
  input \init_state_r[4]_i_7_0 ;
  input \init_state_r[2]_i_7_2 ;
  input \init_state_r[2]_i_7_3 ;
  input pi_dqs_found_rank_done;
  input [87:0]out_fifo;
  input \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ;
  input \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ;
  input mc_wrdata_en;
  input [0:0]mc_cas_n;
  input [0:0]mc_ras_n;
  input [0:0]mc_odt;
  input [0:0]mc_cke;
  input [0:0]mc_we_n;
  input \phy_ctl_wd_i1_reg[22] ;
  input out_fifo_0;
  input [43:0]out_fifo_1;
  input out_fifo_2;
  input out_fifo_3;
  input out_fifo_4;
  input [43:0]out_fifo_5;
  input out_fifo_6;
  input [34:0]mc_address;
  input [0:0]rst_dqs_find_i_12;
  input [8:0]mc_bank;
  input out_fifo_7;
  input [35:0]out_fifo_8;
  input out_fifo_9;
  input out_fifo_10;
  input [35:0]mem_out;
  input out_fifo_11;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 ;
  input \calib_data_offset_0_reg[5]_0 ;
  input \calib_data_offset_0_reg[4]_0 ;
  input \calib_data_offset_0_reg[2]_0 ;
  input \calib_data_offset_0_reg[1]_0 ;
  input \calib_data_offset_0_reg[0]_0 ;
  input [0:0]\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0 ;
  input [3:0]\cnt_pwron_ce_r_reg[9]_0 ;
  input [1:0]mc_cmd;
  input \phy_ctl_wd_i1_reg[17] ;
  input \phy_ctl_wd_i1_reg[18] ;
  input \phy_ctl_wd_i1_reg[19] ;
  input [0:0]mc_data_offset;
  input \phy_ctl_wd_i1_reg[21] ;
  input \phy_ctl_wd_i1_reg[22]_0 ;

  wire CLK;
  wire [4:0]D;
  wire [5:0]D0;
  wire [5:0]D1;
  wire [4:0]D2;
  wire [4:0]D3;
  wire [5:0]D4;
  wire [5:0]D5;
  wire [4:0]D6;
  wire [4:0]D7;
  wire [5:0]D9;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_10_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_11_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_9_n_0 ;
  wire [0:0]E;
  wire [0:0]Q;
  wire [12:0]address_w;
  wire address_w173_out;
  wire \back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ;
  wire \back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ;
  wire [2:0]bank_w;
  wire burst_addr_r_i_1_n_0;
  wire burst_addr_r_i_2_n_0;
  wire burst_addr_r_reg_0;
  wire [3:3]calib_cke;
  wire [2:0]calib_cmd;
  wire \calib_cmd[0]_i_1_n_0 ;
  wire \calib_cmd[1]_i_1_n_0 ;
  wire \calib_cmd[2]_i_1_n_0 ;
  wire calib_complete;
  wire calib_ctl_wren_reg_0;
  wire calib_ctl_wren_reg_1;
  wire [5:0]calib_data_offset_0;
  wire \calib_data_offset_0[3]_i_1_n_0 ;
  wire \calib_data_offset_0[5]_i_1_n_0 ;
  wire \calib_data_offset_0_reg[0]_0 ;
  wire \calib_data_offset_0_reg[1]_0 ;
  wire \calib_data_offset_0_reg[2]_0 ;
  wire \calib_data_offset_0_reg[3]_0 ;
  wire \calib_data_offset_0_reg[4]_0 ;
  wire \calib_data_offset_0_reg[5]_0 ;
  wire [0:0]calib_odt;
  wire \calib_odt[0]_i_1_n_0 ;
  wire \calib_odt[0]_i_2_n_0 ;
  wire \calib_odt[0]_i_3_n_0 ;
  wire \calib_odt[0]_i_4_n_0 ;
  wire \calib_seq[0]_i_1_n_0 ;
  wire \calib_seq[1]_i_1_n_0 ;
  wire [10:0]\calib_seq_reg[1]_0 ;
  wire calib_wrdata_en;
  wire ck_addr_cmd_delay_done;
  wire clear;
  wire [0:0]\cmd_pipe_plus.mc_cas_n_reg[1] ;
  wire [1:0]\cmd_pipe_plus.mc_cas_n_reg[1]_0 ;
  wire [7:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  wire [7:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  wire [0:0]\cmd_pipe_plus.mc_we_n_reg[1] ;
  wire cnt_cmd_done_m7_r;
  wire cnt_cmd_done_m7_r_i_1_n_0;
  wire cnt_cmd_done_m7_r_i_2_n_0;
  wire cnt_cmd_done_r;
  wire cnt_cmd_done_r_i_1_n_0;
  wire \cnt_cmd_r[0]_i_1_n_0 ;
  wire \cnt_cmd_r[1]_i_1_n_0 ;
  wire \cnt_cmd_r[2]_i_1_n_0 ;
  wire \cnt_cmd_r[3]_i_1_n_0 ;
  wire \cnt_cmd_r[4]_i_1_n_0 ;
  wire \cnt_cmd_r[5]_i_1_n_0 ;
  wire \cnt_cmd_r[6]_i_1_n_0 ;
  wire \cnt_cmd_r[6]_i_2_n_0 ;
  wire \cnt_cmd_r[6]_i_3_n_0 ;
  wire \cnt_cmd_r[6]_i_4_n_0 ;
  wire \cnt_cmd_r[6]_i_5_n_0 ;
  wire \cnt_cmd_r_reg_n_0_[0] ;
  wire \cnt_cmd_r_reg_n_0_[1] ;
  wire \cnt_cmd_r_reg_n_0_[2] ;
  wire \cnt_cmd_r_reg_n_0_[3] ;
  wire \cnt_cmd_r_reg_n_0_[4] ;
  wire \cnt_cmd_r_reg_n_0_[5] ;
  wire \cnt_cmd_r_reg_n_0_[6] ;
  wire cnt_dllk_zqinit_done_r;
  wire cnt_dllk_zqinit_done_r_i_1_n_0;
  wire cnt_dllk_zqinit_r;
  wire [7:0]cnt_dllk_zqinit_r_reg;
  wire cnt_init_af_done_r;
  wire cnt_init_af_done_r_i_1_n_0;
  wire [1:0]cnt_init_af_r;
  wire \cnt_init_af_r[0]_i_1_n_0 ;
  wire \cnt_init_af_r[1]_i_1_n_0 ;
  wire cnt_init_mr_done_r;
  wire cnt_init_mr_done_r_i_1_n_0;
  wire [1:0]cnt_init_mr_r;
  wire cnt_init_mr_r1;
  wire \cnt_init_mr_r[0]_i_1_n_0 ;
  wire \cnt_init_mr_r[0]_i_2_n_0 ;
  wire \cnt_init_mr_r[0]_i_3_n_0 ;
  wire \cnt_init_mr_r[1]_i_1_n_0 ;
  wire \cnt_init_mr_r[1]_i_2_n_0 ;
  wire [9:0]cnt_pwron_ce_r_reg;
  wire [3:0]\cnt_pwron_ce_r_reg[9]_0 ;
  wire cnt_pwron_cke_done_r;
  wire cnt_pwron_cke_done_r_i_1_n_0;
  wire cnt_pwron_cke_done_r_i_2_n_0;
  wire cnt_pwron_cke_done_r_i_3_n_0;
  wire \cnt_pwron_r[8]_i_2_n_0 ;
  wire [8:0]cnt_pwron_r_reg;
  wire cnt_pwron_reset_done_r;
  wire cnt_pwron_reset_done_r_i_1_n_0;
  wire cnt_txpr_done_r;
  wire cnt_txpr_done_r_i_1_n_0;
  wire cnt_txpr_done_r_i_2_n_0;
  wire \cnt_txpr_r[7]_i_3_n_0 ;
  wire [7:0]cnt_txpr_r_reg;
  wire complex_address0;
  wire \complex_address[9]_i_2_n_0 ;
  wire \complex_address[9]_i_3_n_0 ;
  wire \complex_address[9]_i_4_n_0 ;
  wire \complex_address_reg_n_0_[0] ;
  wire \complex_address_reg_n_0_[1] ;
  wire \complex_address_reg_n_0_[2] ;
  wire \complex_address_reg_n_0_[3] ;
  wire \complex_address_reg_n_0_[4] ;
  wire \complex_address_reg_n_0_[5] ;
  wire \complex_address_reg_n_0_[6] ;
  wire \complex_address_reg_n_0_[7] ;
  wire \complex_address_reg_n_0_[8] ;
  wire \complex_address_reg_n_0_[9] ;
  wire complex_byte_rd_done;
  wire complex_byte_rd_done_i_1_n_0;
  wire complex_byte_rd_done_i_2_n_0;
  wire \complex_num_reads[0]_i_1_n_0 ;
  wire \complex_num_reads[1]_i_1_n_0 ;
  wire \complex_num_reads[1]_i_2_n_0 ;
  wire \complex_num_reads[1]_i_3_n_0 ;
  wire \complex_num_reads[1]_i_4_n_0 ;
  wire \complex_num_reads[1]_i_5_n_0 ;
  wire \complex_num_reads[2]_i_1_n_0 ;
  wire \complex_num_reads[2]_i_2_n_0 ;
  wire \complex_num_reads[3]_i_10_n_0 ;
  wire \complex_num_reads[3]_i_11_n_0 ;
  wire \complex_num_reads[3]_i_1_n_0 ;
  wire \complex_num_reads[3]_i_2_n_0 ;
  wire \complex_num_reads[3]_i_3_n_0 ;
  wire \complex_num_reads[3]_i_4_n_0 ;
  wire \complex_num_reads[3]_i_5_n_0 ;
  wire \complex_num_reads[3]_i_6_n_0 ;
  wire \complex_num_reads[3]_i_7_n_0 ;
  wire \complex_num_reads[3]_i_8_n_0 ;
  wire \complex_num_reads[3]_i_9_n_0 ;
  wire [3:0]complex_num_reads_dec;
  wire \complex_num_reads_dec[0]_i_1_n_0 ;
  wire \complex_num_reads_dec[1]_i_1_n_0 ;
  wire \complex_num_reads_dec[2]_i_1_n_0 ;
  wire \complex_num_reads_dec[3]_i_1_n_0 ;
  wire \complex_num_reads_dec[3]_i_2_n_0 ;
  wire \complex_num_reads_dec[3]_i_3_n_0 ;
  wire \complex_num_reads_dec[3]_i_4_n_0 ;
  wire \complex_num_reads_reg_n_0_[0] ;
  wire \complex_num_reads_reg_n_0_[1] ;
  wire \complex_num_reads_reg_n_0_[2] ;
  wire \complex_num_reads_reg_n_0_[3] ;
  wire \complex_num_writes[0]_i_1_n_0 ;
  wire \complex_num_writes[1]_i_1_n_0 ;
  wire \complex_num_writes[1]_i_2_n_0 ;
  wire \complex_num_writes[2]_i_10_n_0 ;
  wire \complex_num_writes[2]_i_1_n_0 ;
  wire \complex_num_writes[2]_i_2_n_0 ;
  wire \complex_num_writes[2]_i_3_n_0 ;
  wire \complex_num_writes[2]_i_4_n_0 ;
  wire \complex_num_writes[2]_i_5_n_0 ;
  wire \complex_num_writes[2]_i_6_n_0 ;
  wire \complex_num_writes[2]_i_7_n_0 ;
  wire \complex_num_writes[2]_i_8_n_0 ;
  wire \complex_num_writes[2]_i_9_n_0 ;
  wire \complex_num_writes[3]_i_1_n_0 ;
  wire \complex_num_writes[3]_i_2_n_0 ;
  wire \complex_num_writes[3]_i_3_n_0 ;
  wire \complex_num_writes[3]_i_4_n_0 ;
  wire \complex_num_writes[4]_i_10_n_0 ;
  wire \complex_num_writes[4]_i_11_n_0 ;
  wire \complex_num_writes[4]_i_12_n_0 ;
  wire \complex_num_writes[4]_i_13_n_0 ;
  wire \complex_num_writes[4]_i_14_n_0 ;
  wire \complex_num_writes[4]_i_15_n_0 ;
  wire \complex_num_writes[4]_i_16_n_0 ;
  wire \complex_num_writes[4]_i_17_n_0 ;
  wire \complex_num_writes[4]_i_18_n_0 ;
  wire \complex_num_writes[4]_i_19_n_0 ;
  wire \complex_num_writes[4]_i_1_n_0 ;
  wire \complex_num_writes[4]_i_20_n_0 ;
  wire \complex_num_writes[4]_i_2_n_0 ;
  wire \complex_num_writes[4]_i_3_n_0 ;
  wire \complex_num_writes[4]_i_4_n_0 ;
  wire \complex_num_writes[4]_i_5_n_0 ;
  wire \complex_num_writes[4]_i_6_n_0 ;
  wire \complex_num_writes[4]_i_7_n_0 ;
  wire \complex_num_writes[4]_i_8_n_0 ;
  wire \complex_num_writes[4]_i_9_n_0 ;
  wire \complex_num_writes_dec[4]_i_2_n_0 ;
  wire \complex_num_writes_dec[4]_i_4_n_0 ;
  wire \complex_num_writes_dec[4]_i_5_n_0 ;
  wire [4:0]complex_num_writes_dec_reg;
  wire \complex_num_writes_reg_n_0_[0] ;
  wire \complex_num_writes_reg_n_0_[1] ;
  wire \complex_num_writes_reg_n_0_[2] ;
  wire \complex_num_writes_reg_n_0_[3] ;
  wire \complex_num_writes_reg_n_0_[4] ;
  wire complex_ocal_odt_ext;
  wire complex_ocal_odt_ext_i_1_n_0;
  wire complex_ocal_odt_ext_i_2_n_0;
  wire complex_ocal_odt_ext_i_3_n_0;
  wire complex_ocal_reset_rd_addr;
  wire complex_ocal_reset_rd_addr0;
  wire complex_ocal_reset_rd_addr_i_2_n_0;
  wire complex_oclkdelay_calib_done_r1;
  wire complex_oclkdelay_calib_start_int;
  wire complex_oclkdelay_calib_start_int_i_1_n_0;
  wire complex_oclkdelay_calib_start_int_i_2_n_0;
  wire complex_oclkdelay_calib_start_r1;
  wire complex_odt_ext;
  wire complex_odt_ext_i_1_n_0;
  wire complex_row0_rd_done;
  wire complex_row0_rd_done1;
  wire complex_row0_rd_done_i_1_n_0;
  wire complex_row0_rd_done_reg_0;
  wire complex_row0_wr_done;
  wire complex_row0_wr_done0;
  wire [2:0]complex_row1_rd_cnt;
  wire \complex_row1_rd_cnt[0]_i_1_n_0 ;
  wire \complex_row1_rd_cnt[1]_i_1_n_0 ;
  wire \complex_row1_rd_cnt[2]_i_1_n_0 ;
  wire complex_row1_rd_done;
  wire complex_row1_rd_done_i_1_n_0;
  wire complex_row1_rd_done_i_2_n_0;
  wire complex_row1_rd_done_r1;
  wire complex_row1_wr_done;
  wire complex_row1_wr_done0;
  wire complex_row_cnt;
  wire complex_row_cnt_ocal;
  wire complex_row_cnt_ocal0;
  wire \complex_row_cnt_ocal[3]_i_4_n_0 ;
  wire \complex_row_cnt_ocal[3]_i_5_n_0 ;
  wire \complex_row_cnt_ocal[3]_i_6_n_0 ;
  wire \complex_row_cnt_ocal[3]_i_7_n_0 ;
  wire [3:0]complex_row_cnt_ocal_reg;
  wire complex_sample_cnt_inc0;
  wire complex_sample_cnt_inc_i_2_n_0;
  wire complex_sample_cnt_inc_r1;
  wire complex_sample_cnt_inc_r2;
  wire complex_sample_cnt_inc_reg_n_0;
  wire \complex_wait_cnt[3]_i_1_n_0 ;
  wire \complex_wait_cnt[3]_i_3_n_0 ;
  wire [3:0]complex_wait_cnt_reg;
  wire ddr2_pre_flag_r_i_1_n_0;
  wire ddr2_pre_flag_r_i_2_n_0;
  wire ddr2_pre_flag_r_reg_n_0;
  wire ddr2_refresh_flag_r;
  wire ddr2_refresh_flag_r_i_1_n_0;
  wire ddr2_refresh_flag_r_i_2_n_0;
  wire ddr2_refresh_flag_r_i_3_n_0;
  wire ddr3_lm_done_r;
  wire ddr3_lm_done_r_i_1_n_0;
  wire ddr3_lm_done_r_i_2_n_0;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ;
  wire detect_pi_found_dqs;
  wire detect_pi_found_dqs0;
  wire detect_pi_found_dqs_i_2_n_0;
  wire detect_pi_found_dqs_reg_0;
  wire done_dqs_tap_inc;
  wire [1:0]dqs_asrt_cnt;
  wire \dqs_asrt_cnt[0]_i_1_n_0 ;
  wire \dqs_asrt_cnt[1]_i_1_n_0 ;
  wire dqs_found_prech_req;
  wire \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 ;
  wire \en_cnt_div4.wrlvl_odt_i_1_n_0 ;
  wire \en_cnt_div4.wrlvl_odt_i_2_n_0 ;
  wire [4:0]enable_wrlvl_cnt;
  wire enable_wrlvl_cnt0;
  wire first_rdlvl_pat_r;
  wire first_rdlvl_pat_r_i_1_n_0;
  wire first_wrcal_pat_r;
  wire first_wrcal_pat_r_i_1_n_0;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_8_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_9_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ;
  wire [32:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_1 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_1 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0 ;
  wire \gen_rnk[0].mr1_r_reg_n_0_[0][0] ;
  wire init_calib_complete_reg_0;
  wire init_complete_r1;
  (* RTL_KEEP = "true" *) wire init_complete_r1_timing;
  wire init_complete_r2;
  wire init_complete_r_i_1_n_0;
  wire init_complete_r_reg_n_0;
  (* RTL_KEEP = "true" *) wire init_complete_r_timing;
  wire init_complete_r_timing_i_1_n_0;
  wire init_next_state199_out;
  wire [6:6]init_state_r;
  wire [6:0]init_state_r1;
  wire \init_state_r[0]_i_10_n_0 ;
  wire \init_state_r[0]_i_11_n_0 ;
  wire \init_state_r[0]_i_12_n_0 ;
  wire \init_state_r[0]_i_13_n_0 ;
  wire \init_state_r[0]_i_14_n_0 ;
  wire \init_state_r[0]_i_15_n_0 ;
  wire \init_state_r[0]_i_16_n_0 ;
  wire \init_state_r[0]_i_17_n_0 ;
  wire \init_state_r[0]_i_19_n_0 ;
  wire \init_state_r[0]_i_1_n_0 ;
  wire \init_state_r[0]_i_20_n_0 ;
  wire \init_state_r[0]_i_21_n_0 ;
  wire \init_state_r[0]_i_22_n_0 ;
  wire \init_state_r[0]_i_23_n_0 ;
  wire \init_state_r[0]_i_24_n_0 ;
  wire \init_state_r[0]_i_25_n_0 ;
  wire \init_state_r[0]_i_26_n_0 ;
  wire \init_state_r[0]_i_27_n_0 ;
  wire \init_state_r[0]_i_28_n_0 ;
  wire \init_state_r[0]_i_29_n_0 ;
  wire \init_state_r[0]_i_2_n_0 ;
  wire \init_state_r[0]_i_30_n_0 ;
  wire \init_state_r[0]_i_31_n_0 ;
  wire \init_state_r[0]_i_32_n_0 ;
  wire \init_state_r[0]_i_33_n_0 ;
  wire \init_state_r[0]_i_34_n_0 ;
  wire \init_state_r[0]_i_35_n_0 ;
  wire \init_state_r[0]_i_36_n_0 ;
  wire \init_state_r[0]_i_37_n_0 ;
  wire \init_state_r[0]_i_38_n_0 ;
  wire \init_state_r[0]_i_3_n_0 ;
  wire \init_state_r[0]_i_4_n_0 ;
  wire \init_state_r[0]_i_5_n_0 ;
  wire \init_state_r[0]_i_6_n_0 ;
  wire \init_state_r[0]_i_7_0 ;
  wire \init_state_r[0]_i_7_n_0 ;
  wire \init_state_r[0]_i_8_n_0 ;
  wire \init_state_r[0]_i_9_n_0 ;
  wire \init_state_r[1]_i_10_n_0 ;
  wire \init_state_r[1]_i_11_n_0 ;
  wire \init_state_r[1]_i_12_n_0 ;
  wire \init_state_r[1]_i_13_n_0 ;
  wire \init_state_r[1]_i_14_n_0 ;
  wire \init_state_r[1]_i_15_n_0 ;
  wire \init_state_r[1]_i_16_n_0 ;
  wire \init_state_r[1]_i_17_n_0 ;
  wire \init_state_r[1]_i_18_n_0 ;
  wire \init_state_r[1]_i_19_n_0 ;
  wire \init_state_r[1]_i_1_n_0 ;
  wire \init_state_r[1]_i_20_n_0 ;
  wire \init_state_r[1]_i_21_n_0 ;
  wire \init_state_r[1]_i_22_n_0 ;
  wire \init_state_r[1]_i_23_n_0 ;
  wire \init_state_r[1]_i_25_n_0 ;
  wire \init_state_r[1]_i_26_n_0 ;
  wire \init_state_r[1]_i_27_n_0 ;
  wire \init_state_r[1]_i_28_n_0 ;
  wire \init_state_r[1]_i_2_n_0 ;
  wire \init_state_r[1]_i_30_n_0 ;
  wire \init_state_r[1]_i_31_n_0 ;
  wire \init_state_r[1]_i_32_n_0 ;
  wire \init_state_r[1]_i_3_0 ;
  wire \init_state_r[1]_i_3_n_0 ;
  wire \init_state_r[1]_i_4_n_0 ;
  wire \init_state_r[1]_i_5_n_0 ;
  wire \init_state_r[1]_i_6_n_0 ;
  wire \init_state_r[1]_i_7_n_0 ;
  wire \init_state_r[1]_i_8_n_0 ;
  wire \init_state_r[1]_i_9_n_0 ;
  wire \init_state_r[2]_i_10_n_0 ;
  wire \init_state_r[2]_i_11_n_0 ;
  wire \init_state_r[2]_i_12_n_0 ;
  wire \init_state_r[2]_i_13_n_0 ;
  wire \init_state_r[2]_i_14_n_0 ;
  wire \init_state_r[2]_i_15_n_0 ;
  wire \init_state_r[2]_i_16_n_0 ;
  wire \init_state_r[2]_i_17_n_0 ;
  wire \init_state_r[2]_i_18_n_0 ;
  wire \init_state_r[2]_i_19_n_0 ;
  wire \init_state_r[2]_i_1_n_0 ;
  wire \init_state_r[2]_i_20_n_0 ;
  wire \init_state_r[2]_i_21_n_0 ;
  wire \init_state_r[2]_i_22_n_0 ;
  wire \init_state_r[2]_i_23_n_0 ;
  wire \init_state_r[2]_i_24_n_0 ;
  wire \init_state_r[2]_i_25_n_0 ;
  wire \init_state_r[2]_i_26_n_0 ;
  wire \init_state_r[2]_i_27_n_0 ;
  wire \init_state_r[2]_i_28_n_0 ;
  wire \init_state_r[2]_i_29_n_0 ;
  wire \init_state_r[2]_i_2_n_0 ;
  wire \init_state_r[2]_i_3_n_0 ;
  wire \init_state_r[2]_i_4_n_0 ;
  wire \init_state_r[2]_i_5_n_0 ;
  wire \init_state_r[2]_i_6_0 ;
  wire \init_state_r[2]_i_6_n_0 ;
  wire \init_state_r[2]_i_7_0 ;
  wire \init_state_r[2]_i_7_1 ;
  wire \init_state_r[2]_i_7_2 ;
  wire \init_state_r[2]_i_7_3 ;
  wire \init_state_r[2]_i_7_n_0 ;
  wire \init_state_r[2]_i_8_n_0 ;
  wire \init_state_r[2]_i_9_n_0 ;
  wire \init_state_r[3]_i_10_n_0 ;
  wire \init_state_r[3]_i_11_n_0 ;
  wire \init_state_r[3]_i_12_n_0 ;
  wire \init_state_r[3]_i_13_n_0 ;
  wire \init_state_r[3]_i_14_n_0 ;
  wire \init_state_r[3]_i_15_n_0 ;
  wire \init_state_r[3]_i_16_n_0 ;
  wire \init_state_r[3]_i_17_n_0 ;
  wire \init_state_r[3]_i_18_n_0 ;
  wire \init_state_r[3]_i_1_n_0 ;
  wire \init_state_r[3]_i_2_n_0 ;
  wire \init_state_r[3]_i_3_n_0 ;
  wire \init_state_r[3]_i_4_n_0 ;
  wire \init_state_r[3]_i_5_n_0 ;
  wire \init_state_r[3]_i_6_n_0 ;
  wire \init_state_r[3]_i_7_n_0 ;
  wire \init_state_r[3]_i_8_n_0 ;
  wire \init_state_r[3]_i_9_n_0 ;
  wire \init_state_r[4]_i_10_n_0 ;
  wire \init_state_r[4]_i_11_n_0 ;
  wire \init_state_r[4]_i_12_n_0 ;
  wire \init_state_r[4]_i_13_n_0 ;
  wire \init_state_r[4]_i_14_n_0 ;
  wire \init_state_r[4]_i_15_n_0 ;
  wire \init_state_r[4]_i_16_n_0 ;
  wire \init_state_r[4]_i_17_n_0 ;
  wire \init_state_r[4]_i_18_n_0 ;
  wire \init_state_r[4]_i_19_n_0 ;
  wire \init_state_r[4]_i_1_n_0 ;
  wire \init_state_r[4]_i_20_n_0 ;
  wire \init_state_r[4]_i_21_n_0 ;
  wire \init_state_r[4]_i_22_n_0 ;
  wire \init_state_r[4]_i_23_n_0 ;
  wire \init_state_r[4]_i_24_n_0 ;
  wire \init_state_r[4]_i_26_n_0 ;
  wire \init_state_r[4]_i_27_n_0 ;
  wire \init_state_r[4]_i_29_n_0 ;
  wire \init_state_r[4]_i_2_n_0 ;
  wire \init_state_r[4]_i_30_n_0 ;
  wire \init_state_r[4]_i_31_n_0 ;
  wire \init_state_r[4]_i_32_n_0 ;
  wire \init_state_r[4]_i_33_n_0 ;
  wire \init_state_r[4]_i_35_n_0 ;
  wire \init_state_r[4]_i_3_n_0 ;
  wire \init_state_r[4]_i_4_0 ;
  wire \init_state_r[4]_i_4_n_0 ;
  wire \init_state_r[4]_i_5_n_0 ;
  wire \init_state_r[4]_i_6_n_0 ;
  wire \init_state_r[4]_i_7_0 ;
  wire \init_state_r[4]_i_7_n_0 ;
  wire \init_state_r[4]_i_8_n_0 ;
  wire \init_state_r[4]_i_9_n_0 ;
  wire \init_state_r[5]_i_10_n_0 ;
  wire \init_state_r[5]_i_11_n_0 ;
  wire \init_state_r[5]_i_12_n_0 ;
  wire \init_state_r[5]_i_13_n_0 ;
  wire \init_state_r[5]_i_14_n_0 ;
  wire \init_state_r[5]_i_15_n_0 ;
  wire \init_state_r[5]_i_16_n_0 ;
  wire \init_state_r[5]_i_17_n_0 ;
  wire \init_state_r[5]_i_18_n_0 ;
  wire \init_state_r[5]_i_19_n_0 ;
  wire \init_state_r[5]_i_1_n_0 ;
  wire \init_state_r[5]_i_20_n_0 ;
  wire \init_state_r[5]_i_21_n_0 ;
  wire \init_state_r[5]_i_22_n_0 ;
  wire \init_state_r[5]_i_23_n_0 ;
  wire \init_state_r[5]_i_24_n_0 ;
  wire \init_state_r[5]_i_25_n_0 ;
  wire \init_state_r[5]_i_26_n_0 ;
  wire \init_state_r[5]_i_27_n_0 ;
  wire \init_state_r[5]_i_28_n_0 ;
  wire \init_state_r[5]_i_29_n_0 ;
  wire \init_state_r[5]_i_2_n_0 ;
  wire \init_state_r[5]_i_30_n_0 ;
  wire \init_state_r[5]_i_31_n_0 ;
  wire \init_state_r[5]_i_32_n_0 ;
  wire \init_state_r[5]_i_33_n_0 ;
  wire \init_state_r[5]_i_34_n_0 ;
  wire \init_state_r[5]_i_35_n_0 ;
  wire \init_state_r[5]_i_36_n_0 ;
  wire \init_state_r[5]_i_37_n_0 ;
  wire \init_state_r[5]_i_38_n_0 ;
  wire \init_state_r[5]_i_39_n_0 ;
  wire \init_state_r[5]_i_3_n_0 ;
  wire \init_state_r[5]_i_40_n_0 ;
  wire \init_state_r[5]_i_41_n_0 ;
  wire \init_state_r[5]_i_42_n_0 ;
  wire \init_state_r[5]_i_43_n_0 ;
  wire \init_state_r[5]_i_44_n_0 ;
  wire \init_state_r[5]_i_45_n_0 ;
  wire \init_state_r[5]_i_46_n_0 ;
  wire \init_state_r[5]_i_47_n_0 ;
  wire \init_state_r[5]_i_48_n_0 ;
  wire \init_state_r[5]_i_49_n_0 ;
  wire \init_state_r[5]_i_4_n_0 ;
  wire \init_state_r[5]_i_50_n_0 ;
  wire \init_state_r[5]_i_51_n_0 ;
  wire \init_state_r[5]_i_5_n_0 ;
  wire \init_state_r[5]_i_6_n_0 ;
  wire \init_state_r[5]_i_7_n_0 ;
  wire \init_state_r[5]_i_8_n_0 ;
  wire \init_state_r[5]_i_9_n_0 ;
  wire \init_state_r[6]_i_1_n_0 ;
  wire \init_state_r[6]_i_2_n_0 ;
  wire \init_state_r[6]_i_3_n_0 ;
  wire \init_state_r[6]_i_4_n_0 ;
  wire \init_state_r[6]_i_5_n_0 ;
  wire \init_state_r[6]_i_6_n_0 ;
  wire \init_state_r_reg[0]_0 ;
  wire \init_state_r_reg[2]_0 ;
  wire \init_state_r_reg_n_0_[0] ;
  wire \init_state_r_reg_n_0_[1] ;
  wire \init_state_r_reg_n_0_[2] ;
  wire \init_state_r_reg_n_0_[3] ;
  wire \init_state_r_reg_n_0_[4] ;
  wire \init_state_r_reg_n_0_[5] ;
  wire [34:0]mc_address;
  wire [8:0]mc_bank;
  wire [0:0]mc_cas_n;
  wire [0:0]mc_cke;
  wire [1:0]mc_cmd;
  wire [0:0]mc_data_offset;
  wire [0:0]mc_odt;
  wire [0:0]mc_ras_n;
  wire [0:0]mc_we_n;
  wire mc_wrdata_en;
  wire mem_init_done_r;
  wire mem_init_done_r_i_1_n_0;
  wire mem_init_done_r_i_2_n_0;
  wire [35:0]mem_out;
  wire mpr_rdlvl_start_i_1_n_0;
  wire mpr_rdlvl_start_reg_0;
  wire mux_cmd_wren;
  wire mux_reset_n;
  wire mux_wrdata_en;
  wire \my_empty_reg[3] ;
  wire \my_empty_reg[3]_0 ;
  wire \my_empty_reg[3]_1 ;
  wire [0:0]\my_empty_reg[5] ;
  wire [0:0]\my_empty_reg[5]_0 ;
  wire [1:0]num_reads;
  wire num_refresh0;
  wire \num_refresh[3]_i_1_n_0 ;
  wire \num_refresh[3]_i_4_n_0 ;
  wire \num_refresh[3]_i_5_n_0 ;
  wire \num_refresh[3]_i_6_n_0 ;
  wire \num_refresh[3]_i_7_n_0 ;
  wire \num_refresh[3]_i_8_n_0 ;
  wire [3:0]num_refresh_reg;
  wire \num_refresh_reg[3]_0 ;
  wire \ocal_act_wait_cnt[3]_i_1_n_0 ;
  wire \ocal_act_wait_cnt[3]_i_3_n_0 ;
  wire [3:0]ocal_act_wait_cnt_reg;
  wire [3:2]oclk_wr_cnt0;
  wire \oclk_wr_cnt[0]_i_1_n_0 ;
  wire \oclk_wr_cnt[1]_i_1_n_0 ;
  wire \oclk_wr_cnt[3]_i_1_n_0 ;
  wire \oclk_wr_cnt[3]_i_4_n_0 ;
  wire [3:0]oclk_wr_cnt_reg;
  wire \odd_cwl.phy_cas_n[1]_i_1_n_0 ;
  wire \odd_cwl.phy_ras_n[1]_i_1_n_0 ;
  wire \odd_cwl.phy_ras_n[1]_i_2_n_0 ;
  wire \odd_cwl.phy_we_n[1]_i_1_n_0 ;
  wire \one_rank.stg1_wr_done_i_1_n_0 ;
  wire \one_rank.stg1_wr_done_reg_0 ;
  wire [87:0]out_fifo;
  wire out_fifo_0;
  wire [43:0]out_fifo_1;
  wire out_fifo_10;
  wire out_fifo_11;
  wire out_fifo_2;
  wire out_fifo_3;
  wire out_fifo_4;
  wire [43:0]out_fifo_5;
  wire out_fifo_6;
  wire out_fifo_7;
  wire [35:0]out_fifo_8;
  wire out_fifo_9;
  wire p_0_in0_in;
  wire [9:0]p_0_in__0;
  wire [8:0]p_0_in__0__0;
  wire [7:0]p_0_in__1;
  wire [3:0]p_0_in__2;
  wire [7:0]p_0_in__3;
  wire [3:0]p_0_in__4;
  wire [3:0]p_0_in__5;
  wire [3:0]p_0_in__6;
  wire [4:0]p_0_in__7;
  wire [3:0]p_0_in__8;
  wire p_116_in;
  wire [3:3]p_15_in;
  wire [11:9]phy_bank;
  wire [1:1]phy_cas_n;
  wire [1:1]phy_cs_n;
  wire \phy_ctl_wd_i1_reg[17] ;
  wire \phy_ctl_wd_i1_reg[18] ;
  wire \phy_ctl_wd_i1_reg[19] ;
  wire \phy_ctl_wd_i1_reg[21] ;
  wire \phy_ctl_wd_i1_reg[22] ;
  wire \phy_ctl_wd_i1_reg[22]_0 ;
  wire phy_ctl_wr_i1_reg;
  wire [32:0]phy_dout;
  wire [1:1]phy_ras_n;
  wire phy_read_calib;
  wire phy_reset_n;
  wire [1:1]phy_we_n;
  wire [126:13]phy_wrdata;
  wire phy_wrdata_en;
  wire phy_write_calib;
  wire pi_calib_done;
  wire pi_calib_done_r;
  wire pi_calib_done_r_i_1_n_0;
  wire pi_calib_rank_done_r;
  wire pi_dqs_found_done;
  wire pi_dqs_found_done_r1;
  wire pi_dqs_found_rank_done;
  wire pi_dqs_found_start_i_1_n_0;
  wire pi_dqs_found_start_i_2_n_0;
  wire pi_dqs_found_start_reg_0;
  (* async_reg = "true" *) wire pi_phase_locked_all_r1;
  wire pi_phase_locked_all_r1_reg_0;
  (* async_reg = "true" *) wire pi_phase_locked_all_r2;
  (* async_reg = "true" *) wire pi_phase_locked_all_r3;
  (* async_reg = "true" *) wire pi_phase_locked_all_r4;
  wire prbs_rdlvl_done_pulse0;
  wire prbs_rdlvl_done_pulse_reg_0;
  wire prech_done;
  wire \prech_done_dly_r_reg[15]_srl16_n_0 ;
  wire prech_done_pre;
  wire prech_pending_r;
  wire prech_pending_r_i_1_n_0;
  wire prech_pending_r_i_2_n_0;
  wire prech_pending_r_i_3_n_0;
  wire prech_pending_r_i_4_n_0;
  wire prech_pending_r_i_5_n_0;
  wire prech_pending_r_i_6_n_0;
  wire prech_req;
  wire prech_req_posedge_r0;
  wire prech_req_posedge_r_i_2_n_0;
  wire prech_req_posedge_r_i_3_n_0;
  wire prech_req_posedge_r_reg_0;
  wire prech_req_r;
  wire pwron_ce_r;
  wire pwron_ce_r_i_1_n_0;
  wire pwron_ce_r_i_2_n_0;
  wire rdlvl_last_byte_done;
  wire rdlvl_last_byte_done_r;
  wire rdlvl_pi_incdec;
  wire rdlvl_prech_req;
  wire [14:14]rdlvl_start_dly0_r;
  wire \rdlvl_start_dly0_r_reg[13]_srl14_n_0 ;
  wire rdlvl_start_pre;
  wire rdlvl_start_pre_i_1_n_0;
  wire rdlvl_stg1_done_r1_reg_0;
  wire rdlvl_stg1_rank_done;
  wire rdlvl_stg1_start_i_1_n_0;
  wire rdlvl_stg1_start_reg_0;
  wire read_calib_i_1_n_0;
  wire read_calib_i_2_n_0;
  wire reg_ctrl_cnt_r;
  wire \reg_ctrl_cnt_r[3]_i_1_n_0 ;
  wire [3:0]reg_ctrl_cnt_r_reg;
  wire reset_rd_addr_r1;
  wire \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_9_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ;
  wire [0:0]rst_dqs_find_i_12;
  wire stg1_wr_done;
  wire \stg1_wr_rd_cnt[0]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[1]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[2]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[3]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[3]_i_2_n_0 ;
  wire \stg1_wr_rd_cnt[4]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[4]_i_2_n_0 ;
  wire \stg1_wr_rd_cnt[4]_i_3_n_0 ;
  wire \stg1_wr_rd_cnt[5]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[5]_i_2_n_0 ;
  wire \stg1_wr_rd_cnt[6]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[6]_i_2_n_0 ;
  wire \stg1_wr_rd_cnt[7]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_2_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_3_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_4_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_5_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_6_n_0 ;
  wire \stg1_wr_rd_cnt_reg_n_0_[0] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[1] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[2] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[3] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[4] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[5] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[6] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[7] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[8] ;
  wire wl_sm_start;
  wire \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ;
  wire \wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0 ;
  wire \wr_done_victim_rotate.complex_row0_wr_done_i_4_n_0 ;
  wire \wr_done_victim_rotate.complex_row0_wr_done_i_5_n_0 ;
  wire \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ;
  wire wr_en_inferred__0_i_1_0;
  wire wr_en_inferred__0_i_1__0_0;
  wire wr_en_inferred__0_i_1__1_0;
  wire wr_level_dqs_asrt;
  wire wr_level_dqs_asrt_i_1_n_0;
  wire wr_level_dqs_asrt_r1;
  wire wr_lvl_start_i_1_n_0;
  wire wr_lvl_start_reg_0;
  wire wr_lvl_start_reg_1;
  wire \wr_ptr_timing_reg[0] ;
  wire \wr_ptr_timing_reg[0]_0 ;
  wire \wr_ptr_timing_reg[0]_1 ;
  wire \wr_ptr_timing_reg[0]_2 ;
  wire wr_victim_inc;
  wire wr_victim_inc_i_1_n_0;
  wire wr_victim_inc_i_2_n_0;
  wire wrcal_final_chk;
  wire wrcal_final_chk_i_10_n_0;
  wire wrcal_final_chk_i_11_n_0;
  wire wrcal_final_chk_i_12_n_0;
  wire wrcal_final_chk_i_13_n_0;
  wire wrcal_final_chk_i_14_n_0;
  wire wrcal_final_chk_i_15_n_0;
  wire wrcal_final_chk_i_16_n_0;
  wire wrcal_final_chk_i_17_n_0;
  wire wrcal_final_chk_i_18_n_0;
  wire wrcal_final_chk_i_19_n_0;
  wire wrcal_final_chk_i_1_n_0;
  wire wrcal_final_chk_i_20_n_0;
  wire wrcal_final_chk_i_21_n_0;
  wire wrcal_final_chk_i_22_n_0;
  wire wrcal_final_chk_i_23_n_0;
  wire wrcal_final_chk_i_24_n_0;
  wire wrcal_final_chk_i_2_n_0;
  wire wrcal_final_chk_i_3_n_0;
  wire wrcal_final_chk_i_4_n_0;
  wire wrcal_final_chk_i_5_n_0;
  wire wrcal_final_chk_i_6_n_0;
  wire wrcal_final_chk_i_7_n_0;
  wire wrcal_final_chk_i_8_n_0;
  wire wrcal_final_chk_i_9_n_0;
  wire wrcal_prech_req;
  wire wrcal_rd_wait;
  wire wrcal_rd_wait_i_1_n_0;
  wire wrcal_reads;
  wire wrcal_reads0;
  wire wrcal_reads05_out;
  wire \wrcal_reads[0]_i_1_n_0 ;
  wire \wrcal_reads[1]_i_1_n_0 ;
  wire \wrcal_reads[2]_i_1_n_0 ;
  wire \wrcal_reads[3]_i_1_n_0 ;
  wire \wrcal_reads[4]_i_1_n_0 ;
  wire \wrcal_reads[5]_i_1_n_0 ;
  wire \wrcal_reads[6]_i_1_n_0 ;
  wire \wrcal_reads[7]_i_2_n_0 ;
  wire \wrcal_reads[7]_i_3_n_0 ;
  wire \wrcal_reads[7]_i_4_n_0 ;
  wire \wrcal_reads[7]_i_5_n_0 ;
  wire \wrcal_reads[7]_i_7_n_0 ;
  wire \wrcal_reads[7]_i_8_n_0 ;
  wire \wrcal_reads_reg_n_0_[0] ;
  wire \wrcal_reads_reg_n_0_[1] ;
  wire \wrcal_reads_reg_n_0_[2] ;
  wire \wrcal_reads_reg_n_0_[3] ;
  wire \wrcal_reads_reg_n_0_[4] ;
  wire \wrcal_reads_reg_n_0_[5] ;
  wire \wrcal_reads_reg_n_0_[6] ;
  wire \wrcal_reads_reg_n_0_[7] ;
  wire wrcal_resume_r;
  wire wrcal_resume_w;
  wire wrcal_sanity_chk;
  wire [5:5]wrcal_start_dly_r;
  wire \wrcal_start_dly_r_reg[4]_srl5_n_0 ;
  wire wrcal_start_i_1_n_0;
  wire wrcal_start_pre;
  wire wrcal_start_reg_0;
  wire [3:2]wrcal_wr_cnt0;
  wire \wrcal_wr_cnt[0]_i_1_n_0 ;
  wire \wrcal_wr_cnt[1]_i_1_n_0 ;
  wire \wrcal_wr_cnt[3]_i_1_n_0 ;
  wire \wrcal_wr_cnt[3]_i_2_n_0 ;
  wire \wrcal_wr_cnt[3]_i_4_n_0 ;
  wire \wrcal_wr_cnt[3]_i_5_n_0 ;
  wire [3:0]wrcal_wr_cnt_reg;
  wire \wrdq_div2_4to1_rdlvl_first.phy_wrdata[121]_i_1_n_0 ;
  wire \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_2_n_0 ;
  wire \wrdq_div2_4to1_rdlvl_first.phy_wrdata[25]_i_1_n_0 ;
  wire [0:0]\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0 ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[108] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[121] ;
  wire [43:0]\write_buffer.wr_buf_out_data_reg[122] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[122]_0 ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[123] ;
  wire [5:0]\write_buffer.wr_buf_out_data_reg[125] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[126] ;
  wire [4:0]\write_buffer.wr_buf_out_data_reg[127] ;
  wire [43:0]\write_buffer.wr_buf_out_data_reg[96] ;
  wire write_calib_i_1_n_0;
  wire wrlvl_active;
  wire wrlvl_active_i_1_n_0;
  wire wrlvl_active_r1;
  wire wrlvl_byte_redo;
  wire wrlvl_done_r;
  wire wrlvl_done_r1;
  wire wrlvl_done_r_reg_0;
  wire wrlvl_final_if_rst;
  wire wrlvl_final_if_rst_i_1_n_0;
  wire wrlvl_final_if_rst_i_2_n_0;
  wire wrlvl_odt;
  wire wrlvl_odt_ctl;
  wire wrlvl_odt_ctl_i_1_n_0;
  wire wrlvl_odt_ctl_i_2_n_0;
  wire wrlvl_rank_done;
  wire wrlvl_rank_done_r1;
  wire wrlvl_rank_done_r6_reg_srl5_n_0;
  wire wrlvl_rank_done_r7;

  assign out = init_complete_r1_timing;
  LUT6 #(
    .INIT(64'h22F2000000000000)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_1 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .I1(phy_wrdata_en),
        .I2(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .I3(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ),
        .I4(\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ),
        .I5(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8FAFFAFFFFCFFF8F)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_10 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I1(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair323" *) 
  LUT4 #(
    .INIT(16'h0020)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_11 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_2 
       (.I0(address_w[12]),
        .I1(\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ),
        .I2(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I3(read_calib_i_2_n_0),
        .I4(\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair374" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_3 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair295" *) 
  LUT5 #(
    .INIT(32'hFFFEFFFF)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_4 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(init_state_r),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFFFEEF)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_5 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\DDR3_1rank.phy_int_cs_n[1]_i_9_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_6 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_10_n_0 ),
        .I1(\num_refresh[3]_i_4_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_7 
       (.I0(pi_dqs_found_start_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0F001F1F0F001F11)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_8 
       (.I0(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I1(ddr3_lm_done_r_i_2_n_0),
        .I2(rdlvl_pi_incdec),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ),
        .I4(\wrcal_reads[7]_i_4_n_0 ),
        .I5(\DDR3_1rank.phy_int_cs_n[1]_i_11_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000001000C0C010)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_9 
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\wrcal_reads[7]_i_4_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_9_n_0 ));
  FDSE \DDR3_1rank.phy_int_cs_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ),
        .Q(phy_cs_n),
        .S(init_calib_complete_reg_0));
  LUT6 #(
    .INIT(64'h0000000044444054)) 
    \back_to_back_reads_4_1.num_reads[0]_i_1 
       (.I0(num_reads[0]),
        .I1(num_reads[1]),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(prech_req_posedge_r_i_2_n_0),
        .I5(\num_refresh_reg[3]_0 ),
        .O(\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000088888098)) 
    \back_to_back_reads_4_1.num_reads[1]_i_1 
       (.I0(num_reads[0]),
        .I1(num_reads[1]),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(prech_req_posedge_r_i_2_n_0),
        .I5(\num_refresh_reg[3]_0 ),
        .O(\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ));
  FDRE \back_to_back_reads_4_1.num_reads_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ),
        .Q(num_reads[0]),
        .R(1'b0));
  FDRE \back_to_back_reads_4_1.num_reads_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ),
        .Q(num_reads[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000000BABB)) 
    burst_addr_r_i_1
       (.I0(burst_addr_r_i_2_n_0),
        .I1(p_15_in),
        .I2(phy_wrdata_en),
        .I3(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .I4(burst_addr_r_reg_0),
        .I5(\num_refresh_reg[3]_0 ),
        .O(burst_addr_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h1100000000111131)) 
    burst_addr_r_i_2
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r[5]_i_25_n_0 ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(burst_addr_r_i_2_n_0));
  FDRE burst_addr_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(burst_addr_r_i_1_n_0),
        .Q(p_15_in),
        .R(1'b0));
  FDRE \calib_cke_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_pwron_cke_done_r),
        .Q(calib_cke),
        .R(init_calib_complete_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair355" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \calib_cmd[0]_i_1 
       (.I0(wr_level_dqs_asrt),
        .I1(phy_wrdata_en),
        .I2(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .O(\calib_cmd[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair354" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \calib_cmd[1]_i_1 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .I1(phy_wrdata_en),
        .I2(wr_level_dqs_asrt),
        .O(\calib_cmd[1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \calib_cmd[2]_i_1 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .I1(phy_wrdata_en),
        .I2(wr_level_dqs_asrt),
        .O(\calib_cmd[2]_i_1_n_0 ));
  FDRE \calib_cmd_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_cmd[0]_i_1_n_0 ),
        .Q(calib_cmd[0]),
        .R(1'b0));
  FDRE \calib_cmd_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_cmd[1]_i_1_n_0 ),
        .Q(calib_cmd[1]),
        .R(1'b0));
  FDRE \calib_cmd_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_cmd[2]_i_1_n_0 ),
        .Q(calib_cmd[2]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair319" *) 
  LUT2 #(
    .INIT(4'h8)) 
    calib_ctl_wren_i_1
       (.I0(cnt_pwron_cke_done_r),
        .I1(Q),
        .O(p_116_in));
  FDRE calib_ctl_wren_reg
       (.C(CLK),
        .CE(1'b1),
        .D(p_116_in),
        .Q(calib_ctl_wren_reg_0),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair354" *) 
  LUT4 #(
    .INIT(16'hEFEE)) 
    \calib_data_offset_0[3]_i_1 
       (.I0(phy_wrdata_en),
        .I1(wr_level_dqs_asrt),
        .I2(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .I3(\calib_data_offset_0_reg[3]_0 ),
        .O(\calib_data_offset_0[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \calib_data_offset_0[5]_i_1 
       (.I0(pi_calib_done),
        .I1(wr_level_dqs_asrt),
        .I2(phy_wrdata_en),
        .I3(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .O(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_data_offset_0_reg[0]_0 ),
        .Q(calib_data_offset_0[0]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_data_offset_0_reg[1]_0 ),
        .Q(calib_data_offset_0[1]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_data_offset_0_reg[2]_0 ),
        .Q(calib_data_offset_0[2]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_data_offset_0[3]_i_1_n_0 ),
        .Q(calib_data_offset_0[3]),
        .R(1'b0));
  FDRE \calib_data_offset_0_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_data_offset_0_reg[4]_0 ),
        .Q(calib_data_offset_0[4]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_data_offset_0_reg[5]_0 ),
        .Q(calib_data_offset_0[5]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0000FE00)) 
    \calib_odt[0]_i_1 
       (.I0(\calib_odt[0]_i_2_n_0 ),
        .I1(\calib_odt[0]_i_3_n_0 ),
        .I2(phy_wrdata_en),
        .I3(\gen_rnk[0].mr1_r_reg_n_0_[0][0] ),
        .I4(\num_refresh_reg[3]_0 ),
        .O(\calib_odt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF04)) 
    \calib_odt[0]_i_2 
       (.I0(ddr3_lm_done_r_i_2_n_0),
        .I1(wrlvl_odt),
        .I2(\calib_odt[0]_i_4_n_0 ),
        .I3(complex_ocal_odt_ext),
        .I4(complex_odt_ext),
        .I5(stg1_wr_done),
        .O(\calib_odt[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0020000000000014)) 
    \calib_odt[0]_i_3 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r[5]_i_25_n_0 ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\calib_odt[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair322" *) 
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    \calib_odt[0]_i_4 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .O(\calib_odt[0]_i_4_n_0 ));
  FDRE \calib_odt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_odt[0]_i_1_n_0 ),
        .Q(calib_odt),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair387" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \calib_seq[0]_i_1 
       (.I0(Q),
        .I1(cnt_pwron_cke_done_r),
        .I2(\calib_seq_reg[1]_0 [9]),
        .O(\calib_seq[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair387" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \calib_seq[1]_i_1 
       (.I0(\calib_seq_reg[1]_0 [9]),
        .I1(cnt_pwron_cke_done_r),
        .I2(Q),
        .I3(\calib_seq_reg[1]_0 [10]),
        .O(\calib_seq[1]_i_1_n_0 ));
  FDRE \calib_seq_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq[0]_i_1_n_0 ),
        .Q(\calib_seq_reg[1]_0 [9]),
        .R(init_calib_complete_reg_0));
  FDRE \calib_seq_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\calib_seq[1]_i_1_n_0 ),
        .Q(\calib_seq_reg[1]_0 [10]),
        .R(init_calib_complete_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF01FFFF)) 
    calib_wrdata_en_i_1
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ),
        .I3(p_0_in0_in),
        .I4(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I5(\wrcal_wr_cnt[3]_i_2_n_0 ),
        .O(phy_wrdata_en));
  FDRE calib_wrdata_en_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_wrdata_en),
        .Q(calib_wrdata_en),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00000010)) 
    cnt_cmd_done_m7_r_i_1
       (.I0(cnt_cmd_done_m7_r_i_2_n_0),
        .I1(\cnt_cmd_r_reg_n_0_[2] ),
        .I2(\cnt_cmd_r_reg_n_0_[6] ),
        .I3(\cnt_cmd_r_reg_n_0_[0] ),
        .I4(\cnt_cmd_r_reg_n_0_[1] ),
        .O(cnt_cmd_done_m7_r_i_1_n_0));
  LUT3 #(
    .INIT(8'h7F)) 
    cnt_cmd_done_m7_r_i_2
       (.I0(\cnt_cmd_r_reg_n_0_[4] ),
        .I1(\cnt_cmd_r_reg_n_0_[3] ),
        .I2(\cnt_cmd_r_reg_n_0_[5] ),
        .O(cnt_cmd_done_m7_r_i_2_n_0));
  FDRE cnt_cmd_done_m7_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_cmd_done_m7_r_i_1_n_0),
        .Q(cnt_cmd_done_m7_r),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    cnt_cmd_done_r_i_1
       (.I0(\cnt_cmd_r_reg_n_0_[6] ),
        .I1(\cnt_cmd_r[6]_i_5_n_0 ),
        .O(cnt_cmd_done_r_i_1_n_0));
  FDRE cnt_cmd_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_cmd_done_r_i_1_n_0),
        .Q(cnt_cmd_done_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_cmd_r[0]_i_1 
       (.I0(\cnt_cmd_r_reg_n_0_[0] ),
        .O(\cnt_cmd_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair404" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_cmd_r[1]_i_1 
       (.I0(\cnt_cmd_r_reg_n_0_[1] ),
        .I1(\cnt_cmd_r_reg_n_0_[0] ),
        .O(\cnt_cmd_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair404" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_cmd_r[2]_i_1 
       (.I0(\cnt_cmd_r_reg_n_0_[2] ),
        .I1(\cnt_cmd_r_reg_n_0_[1] ),
        .I2(\cnt_cmd_r_reg_n_0_[0] ),
        .O(\cnt_cmd_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair346" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_cmd_r[3]_i_1 
       (.I0(\cnt_cmd_r_reg_n_0_[3] ),
        .I1(\cnt_cmd_r_reg_n_0_[2] ),
        .I2(\cnt_cmd_r_reg_n_0_[0] ),
        .I3(\cnt_cmd_r_reg_n_0_[1] ),
        .O(\cnt_cmd_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair346" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_cmd_r[4]_i_1 
       (.I0(\cnt_cmd_r_reg_n_0_[4] ),
        .I1(\cnt_cmd_r_reg_n_0_[3] ),
        .I2(\cnt_cmd_r_reg_n_0_[1] ),
        .I3(\cnt_cmd_r_reg_n_0_[0] ),
        .I4(\cnt_cmd_r_reg_n_0_[2] ),
        .O(\cnt_cmd_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_cmd_r[5]_i_1 
       (.I0(\cnt_cmd_r_reg_n_0_[5] ),
        .I1(\cnt_cmd_r_reg_n_0_[4] ),
        .I2(\cnt_cmd_r_reg_n_0_[2] ),
        .I3(\cnt_cmd_r_reg_n_0_[0] ),
        .I4(\cnt_cmd_r_reg_n_0_[1] ),
        .I5(\cnt_cmd_r_reg_n_0_[3] ),
        .O(\cnt_cmd_r[5]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \cnt_cmd_r[6]_i_1 
       (.I0(\cnt_cmd_r[6]_i_3_n_0 ),
        .I1(\cnt_cmd_r[6]_i_4_n_0 ),
        .I2(init_state_r),
        .O(\cnt_cmd_r[6]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_cmd_r[6]_i_2 
       (.I0(\cnt_cmd_r_reg_n_0_[6] ),
        .I1(\cnt_cmd_r[6]_i_5_n_0 ),
        .O(\cnt_cmd_r[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h5444554111115111)) 
    \cnt_cmd_r[6]_i_3 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\cnt_cmd_r[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAAA88A8AAA22AA02)) 
    \cnt_cmd_r[6]_i_4 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\cnt_cmd_r[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \cnt_cmd_r[6]_i_5 
       (.I0(\cnt_cmd_r_reg_n_0_[5] ),
        .I1(\cnt_cmd_r_reg_n_0_[3] ),
        .I2(\cnt_cmd_r_reg_n_0_[4] ),
        .I3(\cnt_cmd_r_reg_n_0_[2] ),
        .I4(\cnt_cmd_r_reg_n_0_[0] ),
        .I5(\cnt_cmd_r_reg_n_0_[1] ),
        .O(\cnt_cmd_r[6]_i_5_n_0 ));
  FDRE \cnt_cmd_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[0]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[0] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  FDRE \cnt_cmd_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[1]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[1] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  FDRE \cnt_cmd_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[2]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[2] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  FDRE \cnt_cmd_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[3]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[3] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  FDRE \cnt_cmd_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[4]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[4] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  FDRE \cnt_cmd_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[5]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[5] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  FDRE \cnt_cmd_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_cmd_r[6]_i_2_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[6] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair384" *) 
  LUT4 #(
    .INIT(16'hEAAA)) 
    cnt_dllk_zqinit_done_r_i_1
       (.I0(cnt_dllk_zqinit_done_r),
        .I1(cnt_dllk_zqinit_r_reg[6]),
        .I2(mem_init_done_r_i_2_n_0),
        .I3(cnt_dllk_zqinit_r_reg[7]),
        .O(cnt_dllk_zqinit_done_r_i_1_n_0));
  FDRE cnt_dllk_zqinit_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_dllk_zqinit_done_r_i_1_n_0),
        .Q(cnt_dllk_zqinit_done_r),
        .R(cnt_dllk_zqinit_r));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_dllk_zqinit_r[0]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[0]),
        .O(p_0_in__3[0]));
  (* SOFT_HLUTNM = "soft_lutpair405" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_dllk_zqinit_r[1]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[0]),
        .I1(cnt_dllk_zqinit_r_reg[1]),
        .O(p_0_in__3[1]));
  (* SOFT_HLUTNM = "soft_lutpair405" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_dllk_zqinit_r[2]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[2]),
        .I1(cnt_dllk_zqinit_r_reg[1]),
        .I2(cnt_dllk_zqinit_r_reg[0]),
        .O(p_0_in__3[2]));
  (* SOFT_HLUTNM = "soft_lutpair347" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_dllk_zqinit_r[3]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[3]),
        .I1(cnt_dllk_zqinit_r_reg[0]),
        .I2(cnt_dllk_zqinit_r_reg[1]),
        .I3(cnt_dllk_zqinit_r_reg[2]),
        .O(p_0_in__3[3]));
  (* SOFT_HLUTNM = "soft_lutpair347" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_dllk_zqinit_r[4]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[4]),
        .I1(cnt_dllk_zqinit_r_reg[2]),
        .I2(cnt_dllk_zqinit_r_reg[1]),
        .I3(cnt_dllk_zqinit_r_reg[0]),
        .I4(cnt_dllk_zqinit_r_reg[3]),
        .O(p_0_in__3[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_dllk_zqinit_r[5]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[5]),
        .I1(cnt_dllk_zqinit_r_reg[3]),
        .I2(cnt_dllk_zqinit_r_reg[0]),
        .I3(cnt_dllk_zqinit_r_reg[1]),
        .I4(cnt_dllk_zqinit_r_reg[2]),
        .I5(cnt_dllk_zqinit_r_reg[4]),
        .O(p_0_in__3[5]));
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_dllk_zqinit_r[6]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[6]),
        .I1(mem_init_done_r_i_2_n_0),
        .O(p_0_in__3[6]));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \cnt_dllk_zqinit_r[7]_i_1 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(cnt_dllk_zqinit_r));
  (* SOFT_HLUTNM = "soft_lutpair384" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_dllk_zqinit_r[7]_i_2 
       (.I0(cnt_dllk_zqinit_r_reg[7]),
        .I1(mem_init_done_r_i_2_n_0),
        .I2(cnt_dllk_zqinit_r_reg[6]),
        .O(p_0_in__3[7]));
  FDRE \cnt_dllk_zqinit_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[0]),
        .Q(cnt_dllk_zqinit_r_reg[0]),
        .R(cnt_dllk_zqinit_r));
  FDRE \cnt_dllk_zqinit_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[1]),
        .Q(cnt_dllk_zqinit_r_reg[1]),
        .R(cnt_dllk_zqinit_r));
  FDRE \cnt_dllk_zqinit_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[2]),
        .Q(cnt_dllk_zqinit_r_reg[2]),
        .R(cnt_dllk_zqinit_r));
  FDRE \cnt_dllk_zqinit_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[3]),
        .Q(cnt_dllk_zqinit_r_reg[3]),
        .R(cnt_dllk_zqinit_r));
  FDRE \cnt_dllk_zqinit_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[4]),
        .Q(cnt_dllk_zqinit_r_reg[4]),
        .R(cnt_dllk_zqinit_r));
  FDRE \cnt_dllk_zqinit_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[5]),
        .Q(cnt_dllk_zqinit_r_reg[5]),
        .R(cnt_dllk_zqinit_r));
  FDRE \cnt_dllk_zqinit_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[6]),
        .Q(cnt_dllk_zqinit_r_reg[6]),
        .R(cnt_dllk_zqinit_r));
  FDRE \cnt_dllk_zqinit_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__3[7]),
        .Q(cnt_dllk_zqinit_r_reg[7]),
        .R(cnt_dllk_zqinit_r));
  (* SOFT_HLUTNM = "soft_lutpair309" *) 
  LUT5 #(
    .INIT(32'h0000E222)) 
    cnt_init_af_done_r_i_1
       (.I0(cnt_init_af_done_r),
        .I1(cnt_init_mr_r1),
        .I2(cnt_init_af_r[1]),
        .I3(cnt_init_af_r[0]),
        .I4(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .O(cnt_init_af_done_r_i_1_n_0));
  FDRE cnt_init_af_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_init_af_done_r_i_1_n_0),
        .Q(cnt_init_af_done_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h06)) 
    \cnt_init_af_r[0]_i_1 
       (.I0(cnt_init_af_r[0]),
        .I1(cnt_init_mr_r1),
        .I2(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .O(\cnt_init_af_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair309" *) 
  LUT4 #(
    .INIT(16'h006A)) 
    \cnt_init_af_r[1]_i_1 
       (.I0(cnt_init_af_r[1]),
        .I1(cnt_init_mr_r1),
        .I2(cnt_init_af_r[0]),
        .I3(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .O(\cnt_init_af_r[1]_i_1_n_0 ));
  FDRE \cnt_init_af_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_init_af_r[0]_i_1_n_0 ),
        .Q(cnt_init_af_r[0]),
        .R(1'b0));
  FDRE \cnt_init_af_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_init_af_r[1]_i_1_n_0 ),
        .Q(cnt_init_af_r[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000000E222)) 
    cnt_init_mr_done_r_i_1
       (.I0(cnt_init_mr_done_r),
        .I1(\cnt_init_mr_r[1]_i_2_n_0 ),
        .I2(cnt_init_mr_r[1]),
        .I3(cnt_init_mr_r[0]),
        .I4(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .I5(cnt_init_mr_r1),
        .O(cnt_init_mr_done_r_i_1_n_0));
  FDRE cnt_init_mr_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_init_mr_done_r_i_1_n_0),
        .Q(cnt_init_mr_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000AAAAA9A8)) 
    \cnt_init_mr_r[0]_i_1 
       (.I0(cnt_init_mr_r[0]),
        .I1(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I2(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(cnt_init_mr_r1),
        .O(\cnt_init_mr_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair389" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \cnt_init_mr_r[0]_i_2 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[5] ),
        .O(\cnt_init_mr_r[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair369" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \cnt_init_mr_r[0]_i_3 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(\cnt_init_mr_r[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0000006A)) 
    \cnt_init_mr_r[1]_i_1 
       (.I0(cnt_init_mr_r[1]),
        .I1(\cnt_init_mr_r[1]_i_2_n_0 ),
        .I2(cnt_init_mr_r[0]),
        .I3(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .I4(cnt_init_mr_r1),
        .O(\cnt_init_mr_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \cnt_init_mr_r[1]_i_2 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(prech_req_posedge_r_i_3_n_0),
        .O(\cnt_init_mr_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \cnt_init_mr_r[1]_i_3 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\num_refresh[3]_i_5_n_0 ),
        .I4(pi_dqs_found_start_i_2_n_0),
        .I5(mem_init_done_r),
        .O(cnt_init_mr_r1));
  FDRE \cnt_init_mr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_init_mr_r[0]_i_1_n_0 ),
        .Q(cnt_init_mr_r[0]),
        .R(1'b0));
  FDRE \cnt_init_mr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cnt_init_mr_r[1]_i_1_n_0 ),
        .Q(cnt_init_mr_r[1]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair424" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_pwron_ce_r[0]_i_1 
       (.I0(cnt_pwron_ce_r_reg[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair424" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_pwron_ce_r[1]_i_1 
       (.I0(cnt_pwron_ce_r_reg[0]),
        .I1(cnt_pwron_ce_r_reg[1]),
        .O(p_0_in__0[1]));
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_pwron_ce_r[2]_i_1 
       (.I0(cnt_pwron_ce_r_reg[2]),
        .I1(cnt_pwron_ce_r_reg[1]),
        .I2(cnt_pwron_ce_r_reg[0]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair348" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_pwron_ce_r[3]_i_1 
       (.I0(cnt_pwron_ce_r_reg[3]),
        .I1(cnt_pwron_ce_r_reg[0]),
        .I2(cnt_pwron_ce_r_reg[1]),
        .I3(cnt_pwron_ce_r_reg[2]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair348" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_pwron_ce_r[4]_i_1 
       (.I0(cnt_pwron_ce_r_reg[4]),
        .I1(cnt_pwron_ce_r_reg[2]),
        .I2(cnt_pwron_ce_r_reg[1]),
        .I3(cnt_pwron_ce_r_reg[0]),
        .I4(cnt_pwron_ce_r_reg[3]),
        .O(p_0_in__0[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_pwron_ce_r[5]_i_1 
       (.I0(cnt_pwron_ce_r_reg[5]),
        .I1(cnt_pwron_ce_r_reg[3]),
        .I2(cnt_pwron_ce_r_reg[0]),
        .I3(cnt_pwron_ce_r_reg[1]),
        .I4(cnt_pwron_ce_r_reg[2]),
        .I5(cnt_pwron_ce_r_reg[4]),
        .O(p_0_in__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair402" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_pwron_ce_r[6]_i_1 
       (.I0(cnt_pwron_ce_r_reg[6]),
        .I1(pwron_ce_r_i_2_n_0),
        .O(p_0_in__0[6]));
  (* SOFT_HLUTNM = "soft_lutpair402" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_pwron_ce_r[7]_i_1 
       (.I0(cnt_pwron_ce_r_reg[7]),
        .I1(pwron_ce_r_i_2_n_0),
        .I2(cnt_pwron_ce_r_reg[6]),
        .O(p_0_in__0[7]));
  (* SOFT_HLUTNM = "soft_lutpair345" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_pwron_ce_r[8]_i_1 
       (.I0(cnt_pwron_ce_r_reg[8]),
        .I1(cnt_pwron_ce_r_reg[6]),
        .I2(pwron_ce_r_i_2_n_0),
        .I3(cnt_pwron_ce_r_reg[7]),
        .O(p_0_in__0[8]));
  (* SOFT_HLUTNM = "soft_lutpair345" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_pwron_ce_r[9]_i_1 
       (.I0(cnt_pwron_ce_r_reg[9]),
        .I1(cnt_pwron_ce_r_reg[7]),
        .I2(pwron_ce_r_i_2_n_0),
        .I3(cnt_pwron_ce_r_reg[6]),
        .I4(cnt_pwron_ce_r_reg[8]),
        .O(p_0_in__0[9]));
  FDRE \cnt_pwron_ce_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(cnt_pwron_ce_r_reg[0]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [0]));
  FDRE \cnt_pwron_ce_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(cnt_pwron_ce_r_reg[1]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [0]));
  FDRE \cnt_pwron_ce_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(cnt_pwron_ce_r_reg[2]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [1]));
  FDRE \cnt_pwron_ce_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(cnt_pwron_ce_r_reg[3]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [1]));
  FDRE \cnt_pwron_ce_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[4]),
        .Q(cnt_pwron_ce_r_reg[4]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [1]));
  FDRE \cnt_pwron_ce_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[5]),
        .Q(cnt_pwron_ce_r_reg[5]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [2]));
  FDRE \cnt_pwron_ce_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[6]),
        .Q(cnt_pwron_ce_r_reg[6]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [3]));
  FDRE \cnt_pwron_ce_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[7]),
        .Q(cnt_pwron_ce_r_reg[7]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [3]));
  FDRE \cnt_pwron_ce_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[8]),
        .Q(cnt_pwron_ce_r_reg[8]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [3]));
  FDRE \cnt_pwron_ce_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[9]),
        .Q(cnt_pwron_ce_r_reg[9]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [3]));
  LUT6 #(
    .INIT(64'h00000000FF800000)) 
    cnt_pwron_cke_done_r_i_1
       (.I0(cnt_pwron_cke_done_r_i_2_n_0),
        .I1(cnt_pwron_r_reg[5]),
        .I2(cnt_pwron_r_reg[3]),
        .I3(cnt_pwron_cke_done_r),
        .I4(Q),
        .I5(\num_refresh_reg[3]_0 ),
        .O(cnt_pwron_cke_done_r_i_1_n_0));
  LUT4 #(
    .INIT(16'h0004)) 
    cnt_pwron_cke_done_r_i_2
       (.I0(cnt_pwron_r_reg[8]),
        .I1(cnt_pwron_r_reg[4]),
        .I2(cnt_pwron_r_reg[7]),
        .I3(cnt_pwron_cke_done_r_i_3_n_0),
        .O(cnt_pwron_cke_done_r_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair380" *) 
  LUT4 #(
    .INIT(16'hFFFD)) 
    cnt_pwron_cke_done_r_i_3
       (.I0(cnt_pwron_r_reg[0]),
        .I1(cnt_pwron_r_reg[1]),
        .I2(cnt_pwron_r_reg[6]),
        .I3(cnt_pwron_r_reg[2]),
        .O(cnt_pwron_cke_done_r_i_3_n_0));
  FDRE cnt_pwron_cke_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_pwron_cke_done_r_i_1_n_0),
        .Q(cnt_pwron_cke_done_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair425" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_pwron_r[0]_i_1 
       (.I0(cnt_pwron_r_reg[0]),
        .O(p_0_in__0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair425" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_pwron_r[1]_i_1 
       (.I0(cnt_pwron_r_reg[0]),
        .I1(cnt_pwron_r_reg[1]),
        .O(p_0_in__0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair380" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_pwron_r[2]_i_1 
       (.I0(cnt_pwron_r_reg[2]),
        .I1(cnt_pwron_r_reg[1]),
        .I2(cnt_pwron_r_reg[0]),
        .O(p_0_in__0__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair349" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_pwron_r[3]_i_1 
       (.I0(cnt_pwron_r_reg[3]),
        .I1(cnt_pwron_r_reg[0]),
        .I2(cnt_pwron_r_reg[1]),
        .I3(cnt_pwron_r_reg[2]),
        .O(p_0_in__0__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair349" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_pwron_r[4]_i_1 
       (.I0(cnt_pwron_r_reg[4]),
        .I1(cnt_pwron_r_reg[2]),
        .I2(cnt_pwron_r_reg[1]),
        .I3(cnt_pwron_r_reg[0]),
        .I4(cnt_pwron_r_reg[3]),
        .O(p_0_in__0__0[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_pwron_r[5]_i_1 
       (.I0(cnt_pwron_r_reg[5]),
        .I1(cnt_pwron_r_reg[3]),
        .I2(cnt_pwron_r_reg[0]),
        .I3(cnt_pwron_r_reg[1]),
        .I4(cnt_pwron_r_reg[2]),
        .I5(cnt_pwron_r_reg[4]),
        .O(p_0_in__0__0[5]));
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_pwron_r[6]_i_1 
       (.I0(cnt_pwron_r_reg[6]),
        .I1(\cnt_pwron_r[8]_i_2_n_0 ),
        .O(p_0_in__0__0[6]));
  (* SOFT_HLUTNM = "soft_lutpair382" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_pwron_r[7]_i_1 
       (.I0(cnt_pwron_r_reg[7]),
        .I1(\cnt_pwron_r[8]_i_2_n_0 ),
        .I2(cnt_pwron_r_reg[6]),
        .O(p_0_in__0__0[7]));
  (* SOFT_HLUTNM = "soft_lutpair382" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_pwron_r[8]_i_1 
       (.I0(cnt_pwron_r_reg[8]),
        .I1(cnt_pwron_r_reg[7]),
        .I2(cnt_pwron_r_reg[6]),
        .I3(\cnt_pwron_r[8]_i_2_n_0 ),
        .O(p_0_in__0__0[8]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \cnt_pwron_r[8]_i_2 
       (.I0(cnt_pwron_r_reg[5]),
        .I1(cnt_pwron_r_reg[3]),
        .I2(cnt_pwron_r_reg[0]),
        .I3(cnt_pwron_r_reg[1]),
        .I4(cnt_pwron_r_reg[2]),
        .I5(cnt_pwron_r_reg[4]),
        .O(\cnt_pwron_r[8]_i_2_n_0 ));
  FDRE \cnt_pwron_r_reg[0] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[0]),
        .Q(cnt_pwron_r_reg[0]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [0]));
  FDRE \cnt_pwron_r_reg[1] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[1]),
        .Q(cnt_pwron_r_reg[1]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [0]));
  FDRE \cnt_pwron_r_reg[2] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[2]),
        .Q(cnt_pwron_r_reg[2]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [0]));
  FDRE \cnt_pwron_r_reg[3] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[3]),
        .Q(cnt_pwron_r_reg[3]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [0]));
  FDRE \cnt_pwron_r_reg[4] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[4]),
        .Q(cnt_pwron_r_reg[4]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [0]));
  FDRE \cnt_pwron_r_reg[5] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[5]),
        .Q(cnt_pwron_r_reg[5]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [0]));
  FDRE \cnt_pwron_r_reg[6] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[6]),
        .Q(cnt_pwron_r_reg[6]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [0]));
  FDRE \cnt_pwron_r_reg[7] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[7]),
        .Q(cnt_pwron_r_reg[7]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [0]));
  FDRE \cnt_pwron_r_reg[8] 
       (.C(CLK),
        .CE(pwron_ce_r),
        .D(p_0_in__0__0[8]),
        .Q(cnt_pwron_r_reg[8]),
        .R(\cnt_pwron_ce_r_reg[9]_0 [0]));
  LUT6 #(
    .INIT(64'h00000000FF020000)) 
    cnt_pwron_reset_done_r_i_1
       (.I0(cnt_pwron_cke_done_r_i_2_n_0),
        .I1(cnt_pwron_r_reg[5]),
        .I2(cnt_pwron_r_reg[3]),
        .I3(cnt_pwron_reset_done_r),
        .I4(Q),
        .I5(\num_refresh_reg[3]_0 ),
        .O(cnt_pwron_reset_done_r_i_1_n_0));
  FDRE cnt_pwron_reset_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_pwron_reset_done_r_i_1_n_0),
        .Q(cnt_pwron_reset_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAABAA)) 
    cnt_txpr_done_r_i_1
       (.I0(cnt_txpr_done_r),
        .I1(cnt_txpr_done_r_i_2_n_0),
        .I2(cnt_txpr_r_reg[6]),
        .I3(cnt_txpr_r_reg[4]),
        .I4(cnt_txpr_r_reg[5]),
        .I5(cnt_txpr_r_reg[2]),
        .O(cnt_txpr_done_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair383" *) 
  LUT4 #(
    .INIT(16'hFFEF)) 
    cnt_txpr_done_r_i_2
       (.I0(cnt_txpr_r_reg[1]),
        .I1(cnt_txpr_r_reg[0]),
        .I2(cnt_txpr_r_reg[3]),
        .I3(cnt_txpr_r_reg[7]),
        .O(cnt_txpr_done_r_i_2_n_0));
  FDRE cnt_txpr_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cnt_txpr_done_r_i_1_n_0),
        .Q(cnt_txpr_done_r),
        .R(clear));
  (* SOFT_HLUTNM = "soft_lutpair426" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_txpr_r[0]_i_1 
       (.I0(cnt_txpr_r_reg[0]),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair426" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_txpr_r[1]_i_1 
       (.I0(cnt_txpr_r_reg[0]),
        .I1(cnt_txpr_r_reg[1]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair383" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_txpr_r[2]_i_1 
       (.I0(cnt_txpr_r_reg[2]),
        .I1(cnt_txpr_r_reg[1]),
        .I2(cnt_txpr_r_reg[0]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair350" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_txpr_r[3]_i_1 
       (.I0(cnt_txpr_r_reg[3]),
        .I1(cnt_txpr_r_reg[0]),
        .I2(cnt_txpr_r_reg[1]),
        .I3(cnt_txpr_r_reg[2]),
        .O(p_0_in__1[3]));
  (* SOFT_HLUTNM = "soft_lutpair350" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_txpr_r[4]_i_1 
       (.I0(cnt_txpr_r_reg[4]),
        .I1(cnt_txpr_r_reg[2]),
        .I2(cnt_txpr_r_reg[1]),
        .I3(cnt_txpr_r_reg[0]),
        .I4(cnt_txpr_r_reg[3]),
        .O(p_0_in__1[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_txpr_r[5]_i_1 
       (.I0(cnt_txpr_r_reg[5]),
        .I1(cnt_txpr_r_reg[3]),
        .I2(cnt_txpr_r_reg[0]),
        .I3(cnt_txpr_r_reg[1]),
        .I4(cnt_txpr_r_reg[2]),
        .I5(cnt_txpr_r_reg[4]),
        .O(p_0_in__1[5]));
  (* SOFT_HLUTNM = "soft_lutpair403" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_txpr_r[6]_i_1 
       (.I0(cnt_txpr_r_reg[6]),
        .I1(\cnt_txpr_r[7]_i_3_n_0 ),
        .O(p_0_in__1[6]));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_txpr_r[7]_i_1 
       (.I0(cnt_pwron_cke_done_r),
        .O(clear));
  (* SOFT_HLUTNM = "soft_lutpair403" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_txpr_r[7]_i_2 
       (.I0(cnt_txpr_r_reg[7]),
        .I1(\cnt_txpr_r[7]_i_3_n_0 ),
        .I2(cnt_txpr_r_reg[6]),
        .O(p_0_in__1[7]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \cnt_txpr_r[7]_i_3 
       (.I0(cnt_txpr_r_reg[5]),
        .I1(cnt_txpr_r_reg[3]),
        .I2(cnt_txpr_r_reg[0]),
        .I3(cnt_txpr_r_reg[1]),
        .I4(cnt_txpr_r_reg[2]),
        .I5(cnt_txpr_r_reg[4]),
        .O(\cnt_txpr_r[7]_i_3_n_0 ));
  FDRE \cnt_txpr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[0]),
        .Q(cnt_txpr_r_reg[0]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[1]),
        .Q(cnt_txpr_r_reg[1]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[2]),
        .Q(cnt_txpr_r_reg[2]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[3]),
        .Q(cnt_txpr_r_reg[3]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[4]),
        .Q(cnt_txpr_r_reg[4]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[5]),
        .Q(cnt_txpr_r_reg[5]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[6]),
        .Q(cnt_txpr_r_reg[6]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__1[7]),
        .Q(cnt_txpr_r_reg[7]),
        .R(clear));
  LUT6 #(
    .INIT(64'hFFFFBFFFAAAAAA2A)) 
    \complex_address[9]_i_1 
       (.I0(\complex_address[9]_i_2_n_0 ),
        .I1(init_state_r1[5]),
        .I2(init_state_r1[0]),
        .I3(init_state_r1[2]),
        .I4(\complex_address[9]_i_3_n_0 ),
        .I5(\complex_address[9]_i_4_n_0 ),
        .O(complex_address0));
  LUT6 #(
    .INIT(64'h0000100000000000)) 
    \complex_address[9]_i_2 
       (.I0(pi_dqs_found_start_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\complex_address[9]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair294" *) 
  LUT4 #(
    .INIT(16'hFFBF)) 
    \complex_address[9]_i_3 
       (.I0(init_state_r1[1]),
        .I1(init_state_r1[3]),
        .I2(init_state_r1[4]),
        .I3(init_state_r1[6]),
        .O(\complex_address[9]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000400000000000)) 
    \complex_address[9]_i_4 
       (.I0(pi_dqs_found_start_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\complex_address[9]_i_4_n_0 ));
  FDRE \complex_address_reg[0] 
       (.C(CLK),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .Q(\complex_address_reg_n_0_[0] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[1] 
       (.C(CLK),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .Q(\complex_address_reg_n_0_[1] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[2] 
       (.C(CLK),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .Q(\complex_address_reg_n_0_[2] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[3] 
       (.C(CLK),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .Q(\complex_address_reg_n_0_[3] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[4] 
       (.C(CLK),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .Q(\complex_address_reg_n_0_[4] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[5] 
       (.C(CLK),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .Q(\complex_address_reg_n_0_[5] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[6] 
       (.C(CLK),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .Q(\complex_address_reg_n_0_[6] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[7] 
       (.C(CLK),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .Q(\complex_address_reg_n_0_[7] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[8] 
       (.C(CLK),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .Q(\complex_address_reg_n_0_[8] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[9] 
       (.C(CLK),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .Q(\complex_address_reg_n_0_[9] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  LUT5 #(
    .INIT(32'h02020200)) 
    complex_byte_rd_done_i_1
       (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I1(\num_refresh_reg[3]_0 ),
        .I2(prbs_rdlvl_done_pulse_reg_0),
        .I3(complex_byte_rd_done_i_2_n_0),
        .I4(complex_byte_rd_done),
        .O(complex_byte_rd_done_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    complex_byte_rd_done_i_2
       (.I0(complex_row1_rd_cnt[0]),
        .I1(complex_row1_rd_cnt[1]),
        .I2(complex_row1_rd_cnt[2]),
        .I3(complex_row1_rd_done),
        .I4(complex_row1_rd_done_r1),
        .I5(D[3]),
        .O(complex_byte_rd_done_i_2_n_0));
  FDRE complex_byte_rd_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_byte_rd_done_i_1_n_0),
        .Q(complex_byte_rd_done),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF26EEEE)) 
    \complex_num_reads[0]_i_1 
       (.I0(\complex_num_reads_reg_n_0_[0] ),
        .I1(\complex_num_reads[3]_i_2_n_0 ),
        .I2(\complex_num_writes[4]_i_6_n_0 ),
        .I3(\complex_num_reads[3]_i_4_n_0 ),
        .I4(\complex_num_reads[3]_i_5_n_0 ),
        .I5(\complex_num_reads[3]_i_6_n_0 ),
        .O(\complex_num_reads[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0002)) 
    \complex_num_reads[1]_i_1 
       (.I0(\complex_num_reads_reg_n_0_[1] ),
        .I1(\complex_num_reads[1]_i_2_n_0 ),
        .I2(\complex_num_reads[3]_i_2_n_0 ),
        .I3(\complex_num_reads[1]_i_3_n_0 ),
        .I4(\complex_num_reads[1]_i_4_n_0 ),
        .I5(\complex_num_reads[1]_i_5_n_0 ),
        .O(\complex_num_reads[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair416" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \complex_num_reads[1]_i_2 
       (.I0(\complex_num_reads[3]_i_4_n_0 ),
        .I1(\complex_num_reads[3]_i_5_n_0 ),
        .O(\complex_num_reads[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair417" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \complex_num_reads[1]_i_3 
       (.I0(\complex_num_writes[2]_i_5_n_0 ),
        .I1(\complex_num_reads[3]_i_5_n_0 ),
        .O(\complex_num_reads[1]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0028AAAA)) 
    \complex_num_reads[1]_i_4 
       (.I0(\complex_num_reads[3]_i_5_n_0 ),
        .I1(\complex_num_reads_reg_n_0_[0] ),
        .I2(\complex_num_reads_reg_n_0_[1] ),
        .I3(\complex_num_writes[4]_i_6_n_0 ),
        .I4(\complex_num_writes[4]_i_9_n_0 ),
        .O(\complex_num_reads[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hEAEAEAEAEAAAAAAA)) 
    \complex_num_reads[1]_i_5 
       (.I0(wr_lvl_start_reg_1),
        .I1(\complex_num_reads[3]_i_5_n_0 ),
        .I2(\complex_num_writes[4]_i_13_n_0 ),
        .I3(\complex_num_reads_reg_n_0_[1] ),
        .I4(\complex_num_reads_reg_n_0_[2] ),
        .I5(\complex_num_reads_reg_n_0_[3] ),
        .O(\complex_num_reads[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h000000000222FE22)) 
    \complex_num_reads[2]_i_1 
       (.I0(\complex_num_reads_reg_n_0_[2] ),
        .I1(\complex_num_reads[3]_i_2_n_0 ),
        .I2(\complex_num_reads[3]_i_4_n_0 ),
        .I3(\complex_num_reads[3]_i_5_n_0 ),
        .I4(\complex_num_reads[2]_i_2_n_0 ),
        .I5(\complex_num_reads[3]_i_6_n_0 ),
        .O(\complex_num_reads[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h802A)) 
    \complex_num_reads[2]_i_2 
       (.I0(\complex_num_writes[2]_i_7_n_0 ),
        .I1(\complex_num_reads_reg_n_0_[1] ),
        .I2(\complex_num_reads_reg_n_0_[0] ),
        .I3(\complex_num_reads_reg_n_0_[2] ),
        .O(\complex_num_reads[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000002E2222)) 
    \complex_num_reads[3]_i_1 
       (.I0(\complex_num_reads_reg_n_0_[3] ),
        .I1(\complex_num_reads[3]_i_2_n_0 ),
        .I2(\complex_num_reads[3]_i_3_n_0 ),
        .I3(\complex_num_reads[3]_i_4_n_0 ),
        .I4(\complex_num_reads[3]_i_5_n_0 ),
        .I5(\complex_num_reads[3]_i_6_n_0 ),
        .O(\complex_num_reads[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair305" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \complex_num_reads[3]_i_10 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .O(\complex_num_reads[3]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair303" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \complex_num_reads[3]_i_11 
       (.I0(\complex_num_reads_reg_n_0_[1] ),
        .I1(\complex_num_reads_reg_n_0_[2] ),
        .O(\complex_num_reads[3]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hFACAFAFA)) 
    \complex_num_reads[3]_i_2 
       (.I0(\complex_num_reads_dec[3]_i_4_n_0 ),
        .I1(\complex_num_reads[3]_i_7_n_0 ),
        .I2(\complex_num_reads[3]_i_5_n_0 ),
        .I3(\complex_num_writes[4]_i_13_n_0 ),
        .I4(\complex_num_reads[3]_i_8_n_0 ),
        .O(\complex_num_reads[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0000807F)) 
    \complex_num_reads[3]_i_3 
       (.I0(\complex_num_reads_reg_n_0_[2] ),
        .I1(\complex_num_reads_reg_n_0_[1] ),
        .I2(\complex_num_reads_reg_n_0_[0] ),
        .I3(\complex_num_reads_reg_n_0_[3] ),
        .I4(\complex_num_writes[4]_i_6_n_0 ),
        .O(\complex_num_reads[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \complex_num_reads[3]_i_4 
       (.I0(\complex_num_reads[3]_i_9_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I5(\complex_num_reads[3]_i_10_n_0 ),
        .O(\complex_num_reads[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \complex_num_reads[3]_i_5 
       (.I0(\complex_address[9]_i_2_n_0 ),
        .I1(complex_wait_cnt_reg[3]),
        .I2(complex_wait_cnt_reg[2]),
        .I3(complex_wait_cnt_reg[1]),
        .I4(complex_wait_cnt_reg[0]),
        .I5(complex_row0_rd_done),
        .O(\complex_num_reads[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF00FFE0FF00)) 
    \complex_num_reads[3]_i_6 
       (.I0(\complex_num_reads_reg_n_0_[3] ),
        .I1(\complex_num_reads[3]_i_11_n_0 ),
        .I2(\complex_num_writes[4]_i_13_n_0 ),
        .I3(wr_lvl_start_reg_1),
        .I4(\complex_num_reads[3]_i_5_n_0 ),
        .I5(\complex_num_writes[2]_i_5_n_0 ),
        .O(\complex_num_reads[3]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h11155555)) 
    \complex_num_reads[3]_i_7 
       (.I0(\complex_num_reads_reg_n_0_[3] ),
        .I1(\complex_num_reads_reg_n_0_[2] ),
        .I2(\complex_num_reads_reg_n_0_[0] ),
        .I3(\complex_num_reads_reg_n_0_[1] ),
        .I4(\complex_num_writes[4]_i_18_n_0 ),
        .O(\complex_num_reads[3]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair303" *) 
  LUT5 #(
    .INIT(32'hBBBABAAA)) 
    \complex_num_reads[3]_i_8 
       (.I0(\complex_num_writes[4]_i_18_n_0 ),
        .I1(\complex_num_writes[4]_i_6_n_0 ),
        .I2(\complex_num_reads_reg_n_0_[2] ),
        .I3(\complex_num_reads_reg_n_0_[1] ),
        .I4(\complex_num_writes[4]_i_17_n_0 ),
        .O(\complex_num_reads[3]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair304" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \complex_num_reads[3]_i_9 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .O(\complex_num_reads[3]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'h74)) 
    \complex_num_reads_dec[0]_i_1 
       (.I0(complex_num_reads_dec[0]),
        .I1(\complex_num_reads_dec[3]_i_3_n_0 ),
        .I2(\complex_num_reads_reg_n_0_[0] ),
        .O(\complex_num_reads_dec[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h9F90)) 
    \complex_num_reads_dec[1]_i_1 
       (.I0(complex_num_reads_dec[0]),
        .I1(complex_num_reads_dec[1]),
        .I2(\complex_num_reads_dec[3]_i_3_n_0 ),
        .I3(\complex_num_reads_reg_n_0_[1] ),
        .O(\complex_num_reads_dec[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hA9FFA900)) 
    \complex_num_reads_dec[2]_i_1 
       (.I0(complex_num_reads_dec[2]),
        .I1(complex_num_reads_dec[1]),
        .I2(complex_num_reads_dec[0]),
        .I3(\complex_num_reads_dec[3]_i_3_n_0 ),
        .I4(\complex_num_reads_reg_n_0_[2] ),
        .O(\complex_num_reads_dec[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAA8FFFFFFFF)) 
    \complex_num_reads_dec[3]_i_1 
       (.I0(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I1(complex_num_reads_dec[1]),
        .I2(complex_num_reads_dec[0]),
        .I3(complex_num_reads_dec[3]),
        .I4(complex_num_reads_dec[2]),
        .I5(\complex_num_reads_dec[3]_i_3_n_0 ),
        .O(\complex_num_reads_dec[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAA9FFFFAAA90000)) 
    \complex_num_reads_dec[3]_i_2 
       (.I0(complex_num_reads_dec[3]),
        .I1(complex_num_reads_dec[2]),
        .I2(complex_num_reads_dec[0]),
        .I3(complex_num_reads_dec[1]),
        .I4(\complex_num_reads_dec[3]_i_3_n_0 ),
        .I5(\complex_num_reads_reg_n_0_[3] ),
        .O(\complex_num_reads_dec[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555555554)) 
    \complex_num_reads_dec[3]_i_3 
       (.I0(\complex_num_reads_dec[3]_i_4_n_0 ),
        .I1(complex_row0_rd_done),
        .I2(\init_state_r[4]_i_9_n_0 ),
        .I3(pi_dqs_found_start_i_2_n_0),
        .I4(\num_refresh[3]_i_5_n_0 ),
        .I5(complex_oclkdelay_calib_start_int_i_2_n_0),
        .O(\complex_num_reads_dec[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0010000F00100000)) 
    \complex_num_reads_dec[3]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I1(ddr3_lm_done_r_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r[6]_i_2_n_0 ),
        .O(\complex_num_reads_dec[3]_i_4_n_0 ));
  FDSE \complex_num_reads_dec_reg[0] 
       (.C(CLK),
        .CE(\complex_num_reads_dec[3]_i_1_n_0 ),
        .D(\complex_num_reads_dec[0]_i_1_n_0 ),
        .Q(complex_num_reads_dec[0]),
        .S(init_calib_complete_reg_0));
  FDRE \complex_num_reads_dec_reg[1] 
       (.C(CLK),
        .CE(\complex_num_reads_dec[3]_i_1_n_0 ),
        .D(\complex_num_reads_dec[1]_i_1_n_0 ),
        .Q(complex_num_reads_dec[1]),
        .R(init_calib_complete_reg_0));
  FDRE \complex_num_reads_dec_reg[2] 
       (.C(CLK),
        .CE(\complex_num_reads_dec[3]_i_1_n_0 ),
        .D(\complex_num_reads_dec[2]_i_1_n_0 ),
        .Q(complex_num_reads_dec[2]),
        .R(init_calib_complete_reg_0));
  FDRE \complex_num_reads_dec_reg[3] 
       (.C(CLK),
        .CE(\complex_num_reads_dec[3]_i_1_n_0 ),
        .D(\complex_num_reads_dec[3]_i_2_n_0 ),
        .Q(complex_num_reads_dec[3]),
        .R(init_calib_complete_reg_0));
  FDRE \complex_num_reads_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_num_reads[0]_i_1_n_0 ),
        .Q(\complex_num_reads_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \complex_num_reads_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_num_reads[1]_i_1_n_0 ),
        .Q(\complex_num_reads_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \complex_num_reads_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_num_reads[2]_i_1_n_0 ),
        .Q(\complex_num_reads_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \complex_num_reads_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_num_reads[3]_i_1_n_0 ),
        .Q(\complex_num_reads_reg_n_0_[3] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h02620E6EFFFFFFFF)) 
    \complex_num_writes[0]_i_1 
       (.I0(\complex_num_writes_reg_n_0_[0] ),
        .I1(\complex_num_writes[4]_i_4_n_0 ),
        .I2(\complex_num_writes[4]_i_5_n_0 ),
        .I3(\complex_num_writes[4]_i_6_n_0 ),
        .I4(\complex_num_writes[3]_i_4_n_0 ),
        .I5(\complex_num_writes[4]_i_2_n_0 ),
        .O(\complex_num_writes[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFEEE022200000000)) 
    \complex_num_writes[1]_i_1 
       (.I0(\complex_num_writes_reg_n_0_[1] ),
        .I1(\complex_num_writes[2]_i_4_n_0 ),
        .I2(\complex_num_writes[4]_i_5_n_0 ),
        .I3(\complex_num_writes[2]_i_5_n_0 ),
        .I4(\complex_num_writes[1]_i_2_n_0 ),
        .I5(\complex_num_writes[2]_i_2_n_0 ),
        .O(\complex_num_writes[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBBBFBFBBAAAAAAAA)) 
    \complex_num_writes[1]_i_2 
       (.I0(\complex_num_writes[3]_i_4_n_0 ),
        .I1(\complex_num_writes[4]_i_9_n_0 ),
        .I2(\complex_num_writes[4]_i_6_n_0 ),
        .I3(\complex_num_writes_reg_n_0_[1] ),
        .I4(\complex_num_writes_reg_n_0_[0] ),
        .I5(\complex_num_writes[4]_i_5_n_0 ),
        .O(\complex_num_writes[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00008A808A808A80)) 
    \complex_num_writes[2]_i_1 
       (.I0(\complex_num_writes[2]_i_2_n_0 ),
        .I1(\complex_num_writes[2]_i_3_n_0 ),
        .I2(\complex_num_writes[2]_i_4_n_0 ),
        .I3(\complex_num_writes_reg_n_0_[2] ),
        .I4(\complex_num_writes[4]_i_5_n_0 ),
        .I5(\complex_num_writes[2]_i_5_n_0 ),
        .O(\complex_num_writes[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair340" *) 
  LUT5 #(
    .INIT(32'hEFFFFFFF)) 
    \complex_num_writes[2]_i_10 
       (.I0(complex_row0_wr_done),
        .I1(complex_wait_cnt_reg[0]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[2]),
        .I4(complex_wait_cnt_reg[3]),
        .O(\complex_num_writes[2]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0222AAAAAAAAAAAA)) 
    \complex_num_writes[2]_i_2 
       (.I0(complex_row0_rd_done_reg_0),
        .I1(\complex_num_writes[2]_i_6_n_0 ),
        .I2(\complex_num_writes_reg_n_0_[1] ),
        .I3(\complex_num_writes_reg_n_0_[2] ),
        .I4(\complex_num_writes[4]_i_13_n_0 ),
        .I5(\complex_num_writes[4]_i_7_n_0 ),
        .O(\complex_num_writes[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF2A80AAAA)) 
    \complex_num_writes[2]_i_3 
       (.I0(\complex_num_writes[4]_i_5_n_0 ),
        .I1(\complex_num_writes_reg_n_0_[1] ),
        .I2(\complex_num_writes_reg_n_0_[0] ),
        .I3(\complex_num_writes_reg_n_0_[2] ),
        .I4(\complex_num_writes[2]_i_7_n_0 ),
        .I5(\complex_num_writes[3]_i_4_n_0 ),
        .O(\complex_num_writes[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000EFFF0000FFFF)) 
    \complex_num_writes[2]_i_4 
       (.I0(\complex_num_writes[4]_i_13_n_0 ),
        .I1(\complex_num_writes[4]_i_12_n_0 ),
        .I2(\complex_num_writes[4]_i_5_n_0 ),
        .I3(\complex_num_writes[4]_i_11_n_0 ),
        .I4(\complex_num_writes[2]_i_8_n_0 ),
        .I5(\complex_num_writes[2]_i_7_n_0 ),
        .O(\complex_num_writes[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000020000000000)) 
    \complex_num_writes[2]_i_5 
       (.I0(\complex_num_writes[2]_i_9_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .O(\complex_num_writes[2]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair306" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \complex_num_writes[2]_i_6 
       (.I0(\complex_num_writes_reg_n_0_[3] ),
        .I1(\complex_num_writes_reg_n_0_[4] ),
        .O(\complex_num_writes[2]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair416" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \complex_num_writes[2]_i_7 
       (.I0(\complex_num_reads[3]_i_4_n_0 ),
        .I1(\complex_num_writes[4]_i_6_n_0 ),
        .O(\complex_num_writes[2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFB3FFFFF)) 
    \complex_num_writes[2]_i_8 
       (.I0(\complex_num_writes[2]_i_10_n_0 ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(complex_oclkdelay_calib_start_int_i_2_n_0),
        .O(\complex_num_writes[2]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair357" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \complex_num_writes[2]_i_9 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(\complex_num_writes[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFEFEFE0200000000)) 
    \complex_num_writes[3]_i_1 
       (.I0(\complex_num_writes_reg_n_0_[3] ),
        .I1(\complex_num_writes[4]_i_4_n_0 ),
        .I2(\complex_num_writes[3]_i_2_n_0 ),
        .I3(\complex_num_writes[3]_i_3_n_0 ),
        .I4(\complex_num_writes[3]_i_4_n_0 ),
        .I5(\complex_num_writes[4]_i_2_n_0 ),
        .O(\complex_num_writes[3]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \complex_num_writes[3]_i_2 
       (.I0(\complex_num_writes[4]_i_5_n_0 ),
        .I1(\complex_num_writes[4]_i_6_n_0 ),
        .O(\complex_num_writes[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h8AA8A8A8A8A8A8A8)) 
    \complex_num_writes[3]_i_3 
       (.I0(\complex_num_writes[4]_i_7_n_0 ),
        .I1(\complex_num_writes[4]_i_6_n_0 ),
        .I2(\complex_num_writes_reg_n_0_[3] ),
        .I3(\complex_num_writes_reg_n_0_[0] ),
        .I4(\complex_num_writes_reg_n_0_[1] ),
        .I5(\complex_num_writes_reg_n_0_[2] ),
        .O(\complex_num_writes[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000002000000000)) 
    \complex_num_writes[3]_i_4 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I4(ddr3_lm_done_r_i_2_n_0),
        .I5(complex_row0_wr_done),
        .O(\complex_num_writes[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00008A808A808A80)) 
    \complex_num_writes[4]_i_1 
       (.I0(\complex_num_writes[4]_i_2_n_0 ),
        .I1(\complex_num_writes[4]_i_3_n_0 ),
        .I2(\complex_num_writes[4]_i_4_n_0 ),
        .I3(\complex_num_writes_reg_n_0_[4] ),
        .I4(\complex_num_writes[4]_i_5_n_0 ),
        .I5(\complex_num_writes[4]_i_6_n_0 ),
        .O(\complex_num_writes[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair364" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \complex_num_writes[4]_i_10 
       (.I0(\complex_num_writes_reg_n_0_[1] ),
        .I1(\complex_num_writes_reg_n_0_[2] ),
        .O(\complex_num_writes[4]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFE080)) 
    \complex_num_writes[4]_i_11 
       (.I0(\complex_num_writes_reg_n_0_[2] ),
        .I1(\complex_num_writes_reg_n_0_[1] ),
        .I2(\complex_num_writes_reg_n_0_[3] ),
        .I3(\complex_num_writes[4]_i_17_n_0 ),
        .I4(\complex_num_writes[4]_i_18_n_0 ),
        .I5(\complex_num_writes_reg_n_0_[4] ),
        .O(\complex_num_writes[4]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000222A)) 
    \complex_num_writes[4]_i_12 
       (.I0(\complex_num_writes[4]_i_18_n_0 ),
        .I1(\complex_num_writes_reg_n_0_[2] ),
        .I2(\complex_num_writes_reg_n_0_[0] ),
        .I3(\complex_num_writes_reg_n_0_[1] ),
        .I4(\complex_num_writes_reg_n_0_[3] ),
        .I5(\complex_num_writes_reg_n_0_[4] ),
        .O(\complex_num_writes[4]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBAAAAFFAAAAAA)) 
    \complex_num_writes[4]_i_13 
       (.I0(\complex_num_reads[3]_i_10_n_0 ),
        .I1(\complex_num_writes[4]_i_19_n_0 ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .O(\complex_num_writes[4]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    \complex_num_writes[4]_i_14 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\complex_num_writes[4]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair316" *) 
  LUT4 #(
    .INIT(16'hFF7F)) 
    \complex_num_writes[4]_i_15 
       (.I0(complex_wait_cnt_reg[3]),
        .I1(complex_wait_cnt_reg[2]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[0]),
        .O(\complex_num_writes[4]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair305" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \complex_num_writes[4]_i_16 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .O(\complex_num_writes[4]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFEFFFEFFFC)) 
    \complex_num_writes[4]_i_17 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .O(\complex_num_writes[4]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'hFCDCFCDCFCDCDCDC)) 
    \complex_num_writes[4]_i_18 
       (.I0(\complex_num_writes[4]_i_20_n_0 ),
        .I1(\complex_num_reads[3]_i_10_n_0 ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(\complex_num_writes[4]_i_18_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair357" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \complex_num_writes[4]_i_19 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(\complex_num_writes[4]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'h000D0000000D000D)) 
    \complex_num_writes[4]_i_2 
       (.I0(\complex_num_writes[4]_i_7_n_0 ),
        .I1(\complex_num_writes[4]_i_8_n_0 ),
        .I2(wr_lvl_start_reg_1),
        .I3(prbs_rdlvl_done_pulse_reg_0),
        .I4(\complex_num_writes[4]_i_9_n_0 ),
        .I5(\complex_num_writes[4]_i_5_n_0 ),
        .O(\complex_num_writes[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair356" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \complex_num_writes[4]_i_20 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .O(\complex_num_writes[4]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hCEECECECECECECEC)) 
    \complex_num_writes[4]_i_3 
       (.I0(\complex_num_writes[4]_i_5_n_0 ),
        .I1(\complex_num_writes[3]_i_4_n_0 ),
        .I2(\complex_num_writes_reg_n_0_[4] ),
        .I3(\complex_num_writes[4]_i_10_n_0 ),
        .I4(\complex_num_writes_reg_n_0_[0] ),
        .I5(\complex_num_writes_reg_n_0_[3] ),
        .O(\complex_num_writes[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF7FFF7FFF70000)) 
    \complex_num_writes[4]_i_4 
       (.I0(\complex_num_writes[4]_i_11_n_0 ),
        .I1(\complex_num_writes[4]_i_5_n_0 ),
        .I2(\complex_num_writes[4]_i_12_n_0 ),
        .I3(\complex_num_writes[4]_i_13_n_0 ),
        .I4(\complex_num_writes[4]_i_7_n_0 ),
        .I5(\complex_num_writes[4]_i_14_n_0 ),
        .O(\complex_num_writes[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \complex_num_writes[4]_i_5 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r[5]_i_12_n_0 ),
        .I3(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I4(\complex_num_writes[4]_i_15_n_0 ),
        .I5(complex_row0_wr_done),
        .O(\complex_num_writes[4]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair304" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \complex_num_writes[4]_i_6 
       (.I0(\complex_num_writes[4]_i_16_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .O(\complex_num_writes[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \complex_num_writes[4]_i_7 
       (.I0(\complex_address[9]_i_4_n_0 ),
        .I1(complex_wait_cnt_reg[3]),
        .I2(complex_wait_cnt_reg[2]),
        .I3(complex_wait_cnt_reg[1]),
        .I4(complex_wait_cnt_reg[0]),
        .I5(complex_row0_wr_done),
        .O(\complex_num_writes[4]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair306" *) 
  LUT5 #(
    .INIT(32'h0111FFFF)) 
    \complex_num_writes[4]_i_8 
       (.I0(\complex_num_writes_reg_n_0_[3] ),
        .I1(\complex_num_writes_reg_n_0_[4] ),
        .I2(\complex_num_writes_reg_n_0_[1] ),
        .I3(\complex_num_writes_reg_n_0_[2] ),
        .I4(\complex_num_writes[4]_i_13_n_0 ),
        .O(\complex_num_writes[4]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair417" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \complex_num_writes[4]_i_9 
       (.I0(\complex_num_writes[2]_i_5_n_0 ),
        .I1(\complex_num_reads[3]_i_4_n_0 ),
        .O(\complex_num_writes[4]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'h74)) 
    \complex_num_writes_dec[0]_i_1 
       (.I0(complex_num_writes_dec_reg[0]),
        .I1(\complex_num_writes_dec[4]_i_5_n_0 ),
        .I2(\complex_num_writes_reg_n_0_[0] ),
        .O(p_0_in__7[0]));
  (* SOFT_HLUTNM = "soft_lutpair364" *) 
  LUT4 #(
    .INIT(16'h9F90)) 
    \complex_num_writes_dec[1]_i_1 
       (.I0(complex_num_writes_dec_reg[0]),
        .I1(complex_num_writes_dec_reg[1]),
        .I2(\complex_num_writes_dec[4]_i_5_n_0 ),
        .I3(\complex_num_writes_reg_n_0_[1] ),
        .O(p_0_in__7[1]));
  (* SOFT_HLUTNM = "soft_lutpair312" *) 
  LUT5 #(
    .INIT(32'hA9FFA900)) 
    \complex_num_writes_dec[2]_i_1 
       (.I0(complex_num_writes_dec_reg[2]),
        .I1(complex_num_writes_dec_reg[1]),
        .I2(complex_num_writes_dec_reg[0]),
        .I3(\complex_num_writes_dec[4]_i_5_n_0 ),
        .I4(\complex_num_writes_reg_n_0_[2] ),
        .O(p_0_in__7[2]));
  LUT6 #(
    .INIT(64'hAAA9FFFFAAA90000)) 
    \complex_num_writes_dec[3]_i_1 
       (.I0(complex_num_writes_dec_reg[3]),
        .I1(complex_num_writes_dec_reg[2]),
        .I2(complex_num_writes_dec_reg[0]),
        .I3(complex_num_writes_dec_reg[1]),
        .I4(\complex_num_writes_dec[4]_i_5_n_0 ),
        .I5(\complex_num_writes_reg_n_0_[3] ),
        .O(p_0_in__7[3]));
  LUT2 #(
    .INIT(4'hE)) 
    \complex_num_writes_dec[4]_i_1 
       (.I0(prbs_rdlvl_done_pulse_reg_0),
        .I1(wr_lvl_start_reg_1),
        .O(complex_row0_rd_done1));
  LUT5 #(
    .INIT(32'h00FDFFFF)) 
    \complex_num_writes_dec[4]_i_2 
       (.I0(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I1(complex_num_writes_dec_reg[3]),
        .I2(complex_num_writes_dec_reg[4]),
        .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I4(\complex_num_writes_dec[4]_i_5_n_0 ),
        .O(\complex_num_writes_dec[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h9AFF9A00)) 
    \complex_num_writes_dec[4]_i_3 
       (.I0(complex_num_writes_dec_reg[4]),
        .I1(complex_num_writes_dec_reg[3]),
        .I2(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I3(\complex_num_writes_dec[4]_i_5_n_0 ),
        .I4(\complex_num_writes_reg_n_0_[4] ),
        .O(p_0_in__7[4]));
  (* SOFT_HLUTNM = "soft_lutpair312" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \complex_num_writes_dec[4]_i_4 
       (.I0(complex_num_writes_dec_reg[1]),
        .I1(complex_num_writes_dec_reg[0]),
        .I2(complex_num_writes_dec_reg[2]),
        .O(\complex_num_writes_dec[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555555554)) 
    \complex_num_writes_dec[4]_i_5 
       (.I0(\complex_num_reads_dec[3]_i_4_n_0 ),
        .I1(complex_row0_rd_done),
        .I2(\init_state_r[4]_i_9_n_0 ),
        .I3(pi_dqs_found_start_i_2_n_0),
        .I4(\init_state_r[5]_i_12_n_0 ),
        .I5(complex_oclkdelay_calib_start_int_i_2_n_0),
        .O(\complex_num_writes_dec[4]_i_5_n_0 ));
  FDSE \complex_num_writes_dec_reg[0] 
       (.C(CLK),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(p_0_in__7[0]),
        .Q(complex_num_writes_dec_reg[0]),
        .S(complex_row0_rd_done1));
  FDRE \complex_num_writes_dec_reg[1] 
       (.C(CLK),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(p_0_in__7[1]),
        .Q(complex_num_writes_dec_reg[1]),
        .R(complex_row0_rd_done1));
  FDRE \complex_num_writes_dec_reg[2] 
       (.C(CLK),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(p_0_in__7[2]),
        .Q(complex_num_writes_dec_reg[2]),
        .R(complex_row0_rd_done1));
  FDRE \complex_num_writes_dec_reg[3] 
       (.C(CLK),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(p_0_in__7[3]),
        .Q(complex_num_writes_dec_reg[3]),
        .R(complex_row0_rd_done1));
  FDRE \complex_num_writes_dec_reg[4] 
       (.C(CLK),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(p_0_in__7[4]),
        .Q(complex_num_writes_dec_reg[4]),
        .R(complex_row0_rd_done1));
  FDRE \complex_num_writes_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_num_writes[0]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \complex_num_writes_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_num_writes[1]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \complex_num_writes_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_num_writes[2]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \complex_num_writes_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_num_writes[3]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \complex_num_writes_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_num_writes[4]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFFFFBF)) 
    complex_ocal_odt_ext_i_1
       (.I0(ddr3_lm_done_r_i_2_n_0),
        .I1(cnt_cmd_done_m7_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(detect_pi_found_dqs_i_2_n_0),
        .I4(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I5(complex_ocal_odt_ext_i_2_n_0),
        .O(complex_ocal_odt_ext_i_1_n_0));
  LUT6 #(
    .INIT(64'hF3F3F2F2F3FFF2F2)) 
    complex_ocal_odt_ext_i_2
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ),
        .I1(complex_ocal_odt_ext),
        .I2(wr_lvl_start_reg_1),
        .I3(complex_ocal_odt_ext_i_3_n_0),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(complex_ocal_odt_ext_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair299" *) 
  LUT5 #(
    .INIT(32'hFFEFFFFF)) 
    complex_ocal_odt_ext_i_3
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[5] ),
        .O(complex_ocal_odt_ext_i_3_n_0));
  FDRE complex_ocal_odt_ext_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_ocal_odt_ext_i_1_n_0),
        .Q(complex_ocal_odt_ext),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAAEAAAAAAAAAA)) 
    complex_ocal_reset_rd_addr_i_1
       (.I0(prbs_rdlvl_done_pulse0),
        .I1(complex_wait_cnt_reg[0]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[3]),
        .I4(complex_wait_cnt_reg[2]),
        .I5(complex_ocal_reset_rd_addr_i_2_n_0),
        .O(complex_ocal_reset_rd_addr0));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    complex_ocal_reset_rd_addr_i_2
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(complex_ocal_reset_rd_addr_i_2_n_0));
  FDRE complex_ocal_reset_rd_addr_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_ocal_reset_rd_addr0),
        .Q(complex_ocal_reset_rd_addr),
        .R(1'b0));
  FDRE complex_oclkdelay_calib_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(complex_oclkdelay_calib_done_r1),
        .R(init_calib_complete_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00080000)) 
    complex_oclkdelay_calib_start_int_i_1
       (.I0(rdlvl_stg1_done_r1_reg_0),
        .I1(prech_req_posedge_r_i_3_n_0),
        .I2(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(complex_oclkdelay_calib_start_int),
        .O(complex_oclkdelay_calib_start_int_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair343" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    complex_oclkdelay_calib_start_int_i_2
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .O(complex_oclkdelay_calib_start_int_i_2_n_0));
  FDRE complex_oclkdelay_calib_start_int_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_oclkdelay_calib_start_int_i_1_n_0),
        .Q(complex_oclkdelay_calib_start_int),
        .R(init_calib_complete_reg_0));
  FDRE complex_oclkdelay_calib_start_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_oclkdelay_calib_start_int),
        .Q(complex_oclkdelay_calib_start_r1),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000AAAA0020)) 
    complex_odt_ext_i_1
       (.I0(complex_row1_rd_done_i_2_n_0),
        .I1(complex_sample_cnt_inc_i_2_n_0),
        .I2(rdlvl_stg1_done_r1_reg_0),
        .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I4(complex_odt_ext),
        .I5(\num_refresh_reg[3]_0 ),
        .O(complex_odt_ext_i_1_n_0));
  FDRE complex_odt_ext_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_odt_ext_i_1_n_0),
        .Q(complex_odt_ext),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000AAAA8000)) 
    complex_row0_rd_done_i_1
       (.I0(complex_row0_rd_done_reg_0),
        .I1(complex_row1_wr_done),
        .I2(complex_oclkdelay_calib_start_int),
        .I3(complex_row1_wr_done0),
        .I4(complex_row0_rd_done),
        .I5(complex_sample_cnt_inc_reg_n_0),
        .O(complex_row0_rd_done_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair332" *) 
  LUT5 #(
    .INIT(32'h00000800)) 
    complex_row0_rd_done_i_3
       (.I0(complex_row0_wr_done),
        .I1(wr_victim_inc_i_2_n_0),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .O(complex_row1_wr_done0));
  FDRE complex_row0_rd_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_row0_rd_done_i_1_n_0),
        .Q(complex_row0_rd_done),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h000000A6)) 
    \complex_row1_rd_cnt[0]_i_1 
       (.I0(complex_row1_rd_cnt[0]),
        .I1(complex_row1_rd_done),
        .I2(complex_row1_rd_done_r1),
        .I3(\num_refresh_reg[3]_0 ),
        .I4(prbs_rdlvl_done_pulse_reg_0),
        .O(\complex_row1_rd_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000009AAA)) 
    \complex_row1_rd_cnt[1]_i_1 
       (.I0(complex_row1_rd_cnt[1]),
        .I1(complex_row1_rd_done_r1),
        .I2(complex_row1_rd_done),
        .I3(complex_row1_rd_cnt[0]),
        .I4(\num_refresh_reg[3]_0 ),
        .I5(prbs_rdlvl_done_pulse_reg_0),
        .O(\complex_row1_rd_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000009AAAAAAA)) 
    \complex_row1_rd_cnt[2]_i_1 
       (.I0(complex_row1_rd_cnt[2]),
        .I1(complex_row1_rd_done_r1),
        .I2(complex_row1_rd_done),
        .I3(complex_row1_rd_cnt[0]),
        .I4(complex_row1_rd_cnt[1]),
        .I5(complex_row0_rd_done1),
        .O(\complex_row1_rd_cnt[2]_i_1_n_0 ));
  FDRE \complex_row1_rd_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_row1_rd_cnt[0]_i_1_n_0 ),
        .Q(complex_row1_rd_cnt[0]),
        .R(1'b0));
  FDRE \complex_row1_rd_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_row1_rd_cnt[1]_i_1_n_0 ),
        .Q(complex_row1_rd_cnt[1]),
        .R(1'b0));
  FDRE \complex_row1_rd_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\complex_row1_rd_cnt[2]_i_1_n_0 ),
        .Q(complex_row1_rd_cnt[2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0202020200020000)) 
    complex_row1_rd_done_i_1
       (.I0(complex_row1_rd_done_i_2_n_0),
        .I1(\num_refresh_reg[3]_0 ),
        .I2(prbs_rdlvl_done_pulse_reg_0),
        .I3(\wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0 ),
        .I4(complex_row0_rd_done),
        .I5(complex_row1_rd_done),
        .O(complex_row1_rd_done_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair331" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFB)) 
    complex_row1_rd_done_i_2
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(complex_row1_rd_done_i_2_n_0));
  FDRE complex_row1_rd_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_row1_rd_done),
        .Q(complex_row1_rd_done_r1),
        .R(1'b0));
  FDRE complex_row1_rd_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_row1_rd_done_i_1_n_0),
        .Q(complex_row1_rd_done),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \complex_row_cnt_ocal[0]_i_1 
       (.I0(complex_row_cnt_ocal_reg[0]),
        .O(p_0_in__4[0]));
  (* SOFT_HLUTNM = "soft_lutpair406" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \complex_row_cnt_ocal[1]_i_1 
       (.I0(complex_row_cnt_ocal_reg[0]),
        .I1(complex_row_cnt_ocal_reg[1]),
        .O(p_0_in__4[1]));
  (* SOFT_HLUTNM = "soft_lutpair406" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \complex_row_cnt_ocal[2]_i_1 
       (.I0(complex_row_cnt_ocal_reg[2]),
        .I1(complex_row_cnt_ocal_reg[1]),
        .I2(complex_row_cnt_ocal_reg[0]),
        .O(p_0_in__4[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF8F)) 
    \complex_row_cnt_ocal[3]_i_1 
       (.I0(wr_victim_inc),
        .I1(\complex_row_cnt_ocal[3]_i_4_n_0 ),
        .I2(rdlvl_stg1_done_r1_reg_0),
        .I3(complex_byte_rd_done),
        .I4(prbs_rdlvl_done_pulse_reg_0),
        .I5(wr_lvl_start_reg_1),
        .O(complex_row_cnt_ocal0));
  LUT6 #(
    .INIT(64'h00000000FFF10000)) 
    \complex_row_cnt_ocal[3]_i_2 
       (.I0(\complex_row_cnt_ocal[3]_i_5_n_0 ),
        .I1(\complex_row_cnt_ocal[3]_i_6_n_0 ),
        .I2(wr_victim_inc),
        .I3(complex_sample_cnt_inc_r2),
        .I4(D[3]),
        .I5(\complex_row_cnt_ocal[3]_i_4_n_0 ),
        .O(complex_row_cnt_ocal));
  (* SOFT_HLUTNM = "soft_lutpair376" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \complex_row_cnt_ocal[3]_i_3 
       (.I0(complex_row_cnt_ocal_reg[3]),
        .I1(complex_row_cnt_ocal_reg[0]),
        .I2(complex_row_cnt_ocal_reg[1]),
        .I3(complex_row_cnt_ocal_reg[2]),
        .O(p_0_in__4[3]));
  (* SOFT_HLUTNM = "soft_lutpair376" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \complex_row_cnt_ocal[3]_i_4 
       (.I0(complex_row_cnt_ocal_reg[3]),
        .I1(complex_row_cnt_ocal_reg[0]),
        .I2(complex_row_cnt_ocal_reg[1]),
        .I3(complex_row_cnt_ocal_reg[2]),
        .O(\complex_row_cnt_ocal[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFBFF)) 
    \complex_row_cnt_ocal[3]_i_5 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\complex_row_cnt_ocal[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFDFFFFFFFFFFF)) 
    \complex_row_cnt_ocal[3]_i_6 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I4(\complex_row_cnt_ocal[3]_i_7_n_0 ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .O(\complex_row_cnt_ocal[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair356" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \complex_row_cnt_ocal[3]_i_7 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .O(\complex_row_cnt_ocal[3]_i_7_n_0 ));
  FDRE \complex_row_cnt_ocal_reg[0] 
       (.C(CLK),
        .CE(complex_row_cnt_ocal),
        .D(p_0_in__4[0]),
        .Q(complex_row_cnt_ocal_reg[0]),
        .R(complex_row_cnt_ocal0));
  FDRE \complex_row_cnt_ocal_reg[1] 
       (.C(CLK),
        .CE(complex_row_cnt_ocal),
        .D(p_0_in__4[1]),
        .Q(complex_row_cnt_ocal_reg[1]),
        .R(complex_row_cnt_ocal0));
  FDRE \complex_row_cnt_ocal_reg[2] 
       (.C(CLK),
        .CE(complex_row_cnt_ocal),
        .D(p_0_in__4[2]),
        .Q(complex_row_cnt_ocal_reg[2]),
        .R(complex_row_cnt_ocal0));
  FDRE \complex_row_cnt_ocal_reg[3] 
       (.C(CLK),
        .CE(complex_row_cnt_ocal),
        .D(p_0_in__4[3]),
        .Q(complex_row_cnt_ocal_reg[3]),
        .R(complex_row_cnt_ocal0));
  LUT2 #(
    .INIT(4'h2)) 
    complex_sample_cnt_inc_i_1
       (.I0(complex_row1_rd_done),
        .I1(complex_sample_cnt_inc_i_2_n_0),
        .O(complex_sample_cnt_inc0));
  (* SOFT_HLUTNM = "soft_lutpair292" *) 
  LUT4 #(
    .INIT(16'hFBFF)) 
    complex_sample_cnt_inc_i_2
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I3(wr_victim_inc_i_2_n_0),
        .O(complex_sample_cnt_inc_i_2_n_0));
  FDRE complex_sample_cnt_inc_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_sample_cnt_inc_reg_n_0),
        .Q(complex_sample_cnt_inc_r1),
        .R(1'b0));
  FDRE complex_sample_cnt_inc_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_sample_cnt_inc_r1),
        .Q(complex_sample_cnt_inc_r2),
        .R(1'b0));
  FDRE complex_sample_cnt_inc_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_sample_cnt_inc0),
        .Q(complex_sample_cnt_inc_reg_n_0),
        .R(init_calib_complete_reg_0));
  LUT1 #(
    .INIT(2'h1)) 
    \complex_wait_cnt[0]_i_1 
       (.I0(complex_wait_cnt_reg[0]),
        .O(p_0_in__6[0]));
  (* SOFT_HLUTNM = "soft_lutpair340" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \complex_wait_cnt[1]_i_1 
       (.I0(complex_wait_cnt_reg[0]),
        .I1(complex_wait_cnt_reg[1]),
        .O(p_0_in__6[1]));
  (* SOFT_HLUTNM = "soft_lutpair335" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \complex_wait_cnt[2]_i_1 
       (.I0(complex_wait_cnt_reg[0]),
        .I1(complex_wait_cnt_reg[1]),
        .I2(complex_wait_cnt_reg[2]),
        .O(p_0_in__6[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFA93F)) 
    \complex_wait_cnt[3]_i_1 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I5(\complex_wait_cnt[3]_i_3_n_0 ),
        .O(\complex_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair325" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \complex_wait_cnt[3]_i_2 
       (.I0(complex_wait_cnt_reg[3]),
        .I1(complex_wait_cnt_reg[0]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[2]),
        .O(p_0_in__6[3]));
  (* SOFT_HLUTNM = "soft_lutpair296" *) 
  LUT5 #(
    .INIT(32'hEAAAAAAA)) 
    \complex_wait_cnt[3]_i_3 
       (.I0(wr_lvl_start_reg_1),
        .I1(complex_wait_cnt_reg[0]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[2]),
        .I4(complex_wait_cnt_reg[3]),
        .O(\complex_wait_cnt[3]_i_3_n_0 ));
  FDRE \complex_wait_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__6[0]),
        .Q(complex_wait_cnt_reg[0]),
        .R(\complex_wait_cnt[3]_i_1_n_0 ));
  FDRE \complex_wait_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__6[1]),
        .Q(complex_wait_cnt_reg[1]),
        .R(\complex_wait_cnt[3]_i_1_n_0 ));
  FDRE \complex_wait_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__6[2]),
        .Q(complex_wait_cnt_reg[2]),
        .R(\complex_wait_cnt[3]_i_1_n_0 ));
  FDRE \complex_wait_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__6[3]),
        .Q(complex_wait_cnt_reg[3]),
        .R(\complex_wait_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h2222222222222F20)) 
    ddr2_pre_flag_r_i_1
       (.I0(ddr2_pre_flag_r_reg_n_0),
        .I1(ddr2_pre_flag_r_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I5(\cnt_init_mr_r[0]_i_2_n_0 ),
        .O(ddr2_pre_flag_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h0010000000000000)) 
    ddr2_pre_flag_r_i_2
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I2(cnt_cmd_done_r),
        .I3(ddr3_lm_done_r_i_2_n_0),
        .I4(cnt_init_mr_done_r),
        .I5(ddr2_refresh_flag_r),
        .O(ddr2_pre_flag_r_i_2_n_0));
  FDRE ddr2_pre_flag_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ddr2_pre_flag_r_i_1_n_0),
        .Q(ddr2_pre_flag_r_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000FF70FFF0FFF0)) 
    ddr2_refresh_flag_r_i_1
       (.I0(ddr2_refresh_flag_r_i_2_n_0),
        .I1(cnt_init_mr_done_r),
        .I2(ddr2_refresh_flag_r),
        .I3(cnt_init_mr_r1),
        .I4(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .I5(ddr2_refresh_flag_r_i_3_n_0),
        .O(ddr2_refresh_flag_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair401" *) 
  LUT3 #(
    .INIT(8'h80)) 
    ddr2_refresh_flag_r_i_2
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .O(ddr2_refresh_flag_r_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair343" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    ddr2_refresh_flag_r_i_3
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[4] ),
        .O(ddr2_refresh_flag_r_i_3_n_0));
  FDRE ddr2_refresh_flag_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ddr2_refresh_flag_r_i_1_n_0),
        .Q(ddr2_refresh_flag_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000004)) 
    ddr3_lm_done_r_i_1
       (.I0(ddr3_lm_done_r_i_2_n_0),
        .I1(burst_addr_r_reg_0),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I5(ddr3_lm_done_r),
        .O(ddr3_lm_done_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair396" *) 
  LUT2 #(
    .INIT(4'h7)) 
    ddr3_lm_done_r_i_2
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .O(ddr3_lm_done_r_i_2_n_0));
  FDRE ddr3_lm_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ddr3_lm_done_r_i_1_n_0),
        .Q(ddr3_lm_done_r),
        .R(init_calib_complete_reg_0));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_12 
       (.I0(mc_cas_n),
        .I1(out_fifo_7),
        .I2(phy_cs_n),
        .I3(out_fifo_8[8]),
        .I4(out_fifo_9),
        .O(\cmd_pipe_plus.mc_cas_n_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair358" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_14 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I1(out_fifo_7),
        .I2(out_fifo_8[12]),
        .I3(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_15 
       (.I0(mc_address[26]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(out_fifo_7),
        .I3(out_fifo_8[11]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_16 
       (.I0(mc_address[15]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(out_fifo_7),
        .I3(out_fifo_8[10]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_17 
       (.I0(mc_address[3]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(out_fifo_7),
        .I3(out_fifo_8[9]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[3]_0 [0]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_18 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I1(out_fifo_0),
        .I2(out_fifo_8[16]),
        .I3(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_19 
       (.I0(mc_address[34]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I2(out_fifo_7),
        .I3(out_fifo_8[15]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0 [2]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_2 
       (.I0(phy_bank[11]),
        .I1(out_fifo_7),
        .I2(out_fifo_8[3]),
        .I3(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_20 
       (.I0(mc_ras_n),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I2(out_fifo_7),
        .I3(out_fifo_8[14]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_21 
       (.I0(mc_address[11]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I2(out_fifo_7),
        .I3(out_fifo_8[13]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[12]_0 [0]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_22 
       (.I0(mc_cke),
        .I1(out_fifo_0),
        .I2(calib_cke),
        .I3(out_fifo_8[24]),
        .I4(out_fifo_9),
        .O(\cmd_pipe_plus.mc_cke_reg[3] [7]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_23 
       (.I0(mc_cke),
        .I1(out_fifo_0),
        .I2(calib_cke),
        .I3(out_fifo_8[23]),
        .I4(out_fifo_9),
        .O(\cmd_pipe_plus.mc_cke_reg[3] [6]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_24 
       (.I0(mc_cke),
        .I1(out_fifo_0),
        .I2(calib_cke),
        .I3(out_fifo_8[22]),
        .I4(out_fifo_9),
        .O(\cmd_pipe_plus.mc_cke_reg[3] [5]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_25 
       (.I0(mc_cke),
        .I1(out_fifo_0),
        .I2(calib_cke),
        .I3(out_fifo_8[21]),
        .I4(out_fifo_9),
        .O(\cmd_pipe_plus.mc_cke_reg[3] [4]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_26 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I1(out_fifo_0),
        .I2(out_fifo_8[20]),
        .I3(out_fifo_9),
        .O(\cmd_pipe_plus.mc_cke_reg[3] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_27 
       (.I0(mc_address[23]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I2(out_fifo_0),
        .I3(out_fifo_8[19]),
        .I4(out_fifo_9),
        .O(\cmd_pipe_plus.mc_cke_reg[3] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_28 
       (.I0(mc_address[12]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I2(out_fifo_0),
        .I3(out_fifo_8[18]),
        .I4(out_fifo_9),
        .O(\cmd_pipe_plus.mc_cke_reg[3] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_29 
       (.I0(mc_address[0]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I2(out_fifo_0),
        .I3(out_fifo_8[17]),
        .I4(out_fifo_9),
        .O(\cmd_pipe_plus.mc_cke_reg[3] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_3 
       (.I0(mc_bank[8]),
        .I1(phy_bank[11]),
        .I2(out_fifo_7),
        .I3(out_fifo_8[2]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0 [2]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_32 
       (.I0(mc_cas_n),
        .I1(out_fifo_0),
        .I2(phy_cas_n),
        .I3(out_fifo_8[26]),
        .I4(out_fifo_9),
        .O(\cmd_pipe_plus.mc_cas_n_reg[1]_0 [1]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_36 
       (.I0(mc_ras_n),
        .I1(out_fifo_0),
        .I2(phy_ras_n),
        .I3(out_fifo_8[25]),
        .I4(out_fifo_9),
        .O(\cmd_pipe_plus.mc_cas_n_reg[1]_0 [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_4 
       (.I0(mc_bank[5]),
        .I1(phy_bank[11]),
        .I2(out_fifo_7),
        .I3(out_fifo_8[1]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0 [1]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_40 
       (.I0(mc_we_n),
        .I1(out_fifo_0),
        .I2(phy_we_n),
        .I3(out_fifo_8[27]),
        .I4(out_fifo_9),
        .O(\cmd_pipe_plus.mc_we_n_reg[1] ));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_42 
       (.I0(phy_bank[9]),
        .I1(out_fifo_0),
        .I2(out_fifo_8[31]),
        .I3(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_43 
       (.I0(mc_bank[6]),
        .I1(phy_bank[9]),
        .I2(out_fifo_0),
        .I3(out_fifo_8[30]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_44 
       (.I0(mc_bank[3]),
        .I1(phy_bank[9]),
        .I2(out_fifo_0),
        .I3(out_fifo_8[29]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_45 
       (.I0(mc_bank[0]),
        .I1(phy_bank[9]),
        .I2(out_fifo_0),
        .I3(out_fifo_8[28]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 [0]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_46 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I1(out_fifo_0),
        .I2(out_fifo_8[35]),
        .I3(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_1 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_47 
       (.I0(mc_address[33]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I2(out_fifo_0),
        .I3(out_fifo_8[34]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_1 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_48 
       (.I0(mc_address[22]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I2(out_fifo_0),
        .I3(out_fifo_8[33]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_1 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_49 
       (.I0(mc_address[10]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I2(out_fifo_0),
        .I3(out_fifo_8[32]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_1 [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_5 
       (.I0(mc_bank[2]),
        .I1(phy_bank[11]),
        .I2(out_fifo_7),
        .I3(out_fifo_8[0]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2]_0 [0]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_6 
       (.I0(phy_bank[10]),
        .I1(out_fifo_7),
        .I2(out_fifo_8[7]),
        .I3(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_7 
       (.I0(mc_bank[7]),
        .I1(phy_bank[10]),
        .I2(out_fifo_7),
        .I3(out_fifo_8[6]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_8 
       (.I0(mc_bank[4]),
        .I1(phy_bank[10]),
        .I2(out_fifo_7),
        .I3(out_fifo_8[5]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_9 
       (.I0(mc_bank[1]),
        .I1(phy_bank[10]),
        .I2(out_fifo_7),
        .I3(out_fifo_8[4]),
        .I4(out_fifo_9),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 [0]));
  LUT6 #(
    .INIT(64'h0000000000000200)) 
    detect_pi_found_dqs_i_1
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(detect_pi_found_dqs_i_2_n_0),
        .I2(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I3(prech_req_posedge_r_i_3_n_0),
        .I4(\cnt_cmd_r[6]_i_5_n_0 ),
        .I5(\cnt_cmd_r_reg_n_0_[6] ),
        .O(detect_pi_found_dqs0));
  (* SOFT_HLUTNM = "soft_lutpair415" *) 
  LUT2 #(
    .INIT(4'hE)) 
    detect_pi_found_dqs_i_2
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .O(detect_pi_found_dqs_i_2_n_0));
  FDRE detect_pi_found_dqs_reg
       (.C(CLK),
        .CE(1'b1),
        .D(detect_pi_found_dqs0),
        .Q(detect_pi_found_dqs),
        .R(init_calib_complete_reg_0));
  LUT6 #(
    .INIT(64'h00000000E6E600E6)) 
    \dqs_asrt_cnt[0]_i_1 
       (.I0(dqs_asrt_cnt[0]),
        .I1(wr_level_dqs_asrt),
        .I2(dqs_asrt_cnt[1]),
        .I3(wrlvl_done_r),
        .I4(wrlvl_done_r1),
        .I5(\num_refresh_reg[3]_0 ),
        .O(\dqs_asrt_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EAEA00EA)) 
    \dqs_asrt_cnt[1]_i_1 
       (.I0(dqs_asrt_cnt[1]),
        .I1(dqs_asrt_cnt[0]),
        .I2(wr_level_dqs_asrt),
        .I3(wrlvl_done_r),
        .I4(wrlvl_done_r1),
        .I5(\num_refresh_reg[3]_0 ),
        .O(\dqs_asrt_cnt[1]_i_1_n_0 ));
  FDRE \dqs_asrt_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqs_asrt_cnt[0]_i_1_n_0 ),
        .Q(dqs_asrt_cnt[0]),
        .R(1'b0));
  FDRE \dqs_asrt_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqs_asrt_cnt[1]_i_1_n_0 ),
        .Q(dqs_asrt_cnt[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000055555554)) 
    \en_cnt_div4.enable_wrlvl_cnt[0]_i_1 
       (.I0(enable_wrlvl_cnt[0]),
        .I1(enable_wrlvl_cnt[1]),
        .I2(enable_wrlvl_cnt[4]),
        .I3(enable_wrlvl_cnt[3]),
        .I4(enable_wrlvl_cnt[2]),
        .I5(\en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 ),
        .O(\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF0000FE)) 
    \en_cnt_div4.enable_wrlvl_cnt[1]_i_1 
       (.I0(enable_wrlvl_cnt[2]),
        .I1(enable_wrlvl_cnt[3]),
        .I2(enable_wrlvl_cnt[4]),
        .I3(enable_wrlvl_cnt[1]),
        .I4(enable_wrlvl_cnt[0]),
        .I5(\en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 ),
        .O(\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAAA54)) 
    \en_cnt_div4.enable_wrlvl_cnt[2]_i_1 
       (.I0(enable_wrlvl_cnt[2]),
        .I1(enable_wrlvl_cnt[3]),
        .I2(enable_wrlvl_cnt[4]),
        .I3(enable_wrlvl_cnt[1]),
        .I4(enable_wrlvl_cnt[0]),
        .I5(\init_state_r_reg[2]_0 ),
        .O(\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFCCCCCC98)) 
    \en_cnt_div4.enable_wrlvl_cnt[3]_i_1 
       (.I0(enable_wrlvl_cnt[2]),
        .I1(enable_wrlvl_cnt[3]),
        .I2(enable_wrlvl_cnt[4]),
        .I3(enable_wrlvl_cnt[1]),
        .I4(enable_wrlvl_cnt[0]),
        .I5(\init_state_r_reg[2]_0 ),
        .O(\en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0400FFFF04000400)) 
    \en_cnt_div4.enable_wrlvl_cnt[3]_i_2 
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(prech_req_posedge_r_i_3_n_0),
        .I4(enable_wrlvl_cnt0),
        .I5(wrlvl_odt),
        .O(\init_state_r_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair341" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \en_cnt_div4.enable_wrlvl_cnt[3]_i_3 
       (.I0(enable_wrlvl_cnt[0]),
        .I1(enable_wrlvl_cnt[1]),
        .I2(enable_wrlvl_cnt[4]),
        .I3(enable_wrlvl_cnt[3]),
        .I4(enable_wrlvl_cnt[2]),
        .O(enable_wrlvl_cnt0));
  LUT6 #(
    .INIT(64'h00000000F0F0F0E0)) 
    \en_cnt_div4.enable_wrlvl_cnt[4]_i_1 
       (.I0(enable_wrlvl_cnt[2]),
        .I1(enable_wrlvl_cnt[3]),
        .I2(enable_wrlvl_cnt[4]),
        .I3(enable_wrlvl_cnt[1]),
        .I4(enable_wrlvl_cnt[0]),
        .I5(\en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 ),
        .O(\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ),
        .Q(enable_wrlvl_cnt[0]),
        .R(1'b0));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ),
        .Q(enable_wrlvl_cnt[1]),
        .R(1'b0));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ),
        .Q(enable_wrlvl_cnt[2]),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0 ),
        .Q(enable_wrlvl_cnt[3]),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ),
        .Q(enable_wrlvl_cnt[4]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0054)) 
    \en_cnt_div4.wrlvl_odt_i_1 
       (.I0(wr_lvl_start_reg_1),
        .I1(\en_cnt_div4.wrlvl_odt_i_2_n_0 ),
        .I2(wrlvl_odt),
        .I3(wrlvl_odt_ctl),
        .O(\en_cnt_div4.wrlvl_odt_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair341" *) 
  LUT5 #(
    .INIT(32'h00000100)) 
    \en_cnt_div4.wrlvl_odt_i_2 
       (.I0(enable_wrlvl_cnt[4]),
        .I1(enable_wrlvl_cnt[3]),
        .I2(enable_wrlvl_cnt[2]),
        .I3(enable_wrlvl_cnt[0]),
        .I4(enable_wrlvl_cnt[1]),
        .O(\en_cnt_div4.wrlvl_odt_i_2_n_0 ));
  FDRE \en_cnt_div4.wrlvl_odt_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\en_cnt_div4.wrlvl_odt_i_1_n_0 ),
        .Q(wrlvl_odt),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFF8)) 
    first_rdlvl_pat_r_i_1
       (.I0(first_rdlvl_pat_r),
        .I1(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I2(rdlvl_stg1_rank_done),
        .I3(\num_refresh_reg[3]_0 ),
        .O(first_rdlvl_pat_r_i_1_n_0));
  FDRE first_rdlvl_pat_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(first_rdlvl_pat_r_i_1_n_0),
        .Q(first_rdlvl_pat_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFBAAAB)) 
    first_wrcal_pat_r_i_1
       (.I0(wr_lvl_start_reg_1),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\wrcal_wr_cnt[3]_i_4_n_0 ),
        .I4(first_wrcal_pat_r),
        .I5(wrcal_resume_w),
        .O(first_wrcal_pat_r_i_1_n_0));
  FDRE first_wrcal_pat_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(first_wrcal_pat_r_i_1_n_0),
        .Q(first_wrcal_pat_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF20000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ),
        .O(address_w[0]));
  (* SOFT_HLUTNM = "soft_lutpair361" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I1(D[3]),
        .I2(complex_row_cnt_ocal_reg[0]),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair290" *) 
  LUT5 #(
    .INIT(32'hAAAA2000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3 
       (.I0(\complex_address_reg_n_0_[0] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair377" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4 
       (.I0(reg_ctrl_cnt_r),
        .I1(reg_ctrl_cnt_r_reg[0]),
        .I2(reg_ctrl_cnt_r_reg[3]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000001090001)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .O(address_w173_out));
  (* SOFT_HLUTNM = "soft_lutpair324" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000003050)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I1(\wrcal_reads[7]_i_4_n_0 ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(address_w[12]));
  (* SOFT_HLUTNM = "soft_lutpair389" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF54545554)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ),
        .O(address_w[1]));
  (* SOFT_HLUTNM = "soft_lutpair390" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2 
       (.I0(address_w173_out),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_7_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hAAAA2000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3 
       (.I0(\complex_address_reg_n_0_[1] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair362" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I1(D[3]),
        .I2(complex_row_cnt_ocal_reg[1]),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h55555555D5555555)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ),
        .I4(reg_ctrl_cnt_r_reg[1]),
        .I5(reg_ctrl_cnt_r_reg[3]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFDFFFFFFFFFFDDD)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF20000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ),
        .O(address_w[2]));
  LUT4 #(
    .INIT(16'h00E2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I1(D[3]),
        .I2(complex_row_cnt_ocal_reg[2]),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hAAAA2000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3 
       (.I0(\complex_address_reg_n_0_[2] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ),
        .I1(\gen_rnk[0].mr1_r_reg_n_0_[0][0] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFEFFFEFFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5 
       (.I0(address_w[12]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),
        .I4(D[3]),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair337" *) 
  LUT5 #(
    .INIT(32'hAFFAFEFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6 
       (.I0(init_state_r),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_8_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'hFFDFAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ),
        .I1(reg_ctrl_cnt_r_reg[1]),
        .I2(reg_ctrl_cnt_r_reg[2]),
        .I3(reg_ctrl_cnt_r_reg[3]),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair311" *) 
  LUT4 #(
    .INIT(16'hFF8F)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8 
       (.I0(D[3]),
        .I1(pi_dqs_found_done),
        .I2(cnt_init_mr_r[1]),
        .I3(cnt_init_mr_r[0]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFABAAAAAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ),
        .O(address_w[3]));
  (* SOFT_HLUTNM = "soft_lutpair310" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2 
       (.I0(reg_ctrl_cnt_r),
        .I1(reg_ctrl_cnt_r_reg[0]),
        .I2(reg_ctrl_cnt_r_reg[1]),
        .I3(reg_ctrl_cnt_r_reg[3]),
        .I4(reg_ctrl_cnt_r_reg[2]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFE200E2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I1(D[3]),
        .I2(complex_row_cnt_ocal_reg[3]),
        .I3(address_w[12]),
        .I4(p_15_in),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0000FF40)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),
        .I4(\complex_address_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFF0FFFEFFFFFFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5 
       (.I0(read_calib_i_2_n_0),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ),
        .I4(D[3]),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFBFBFFFFFFFF3)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6 
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFBBFBAAAAAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ),
        .O(address_w[4]));
  LUT6 #(
    .INIT(64'h99999999F9FFFFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2 
       (.I0(\complex_address_reg_n_0_[4] ),
        .I1(\complex_address_reg_n_0_[3] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair358" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair419" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AEEEEAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ),
        .O(address_w[5]));
  LUT5 #(
    .INIT(32'hFFF2F2F2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4544)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ),
        .I1(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ),
        .I3(init_state_r1[3]),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hDDDDDD5D5D5DDD5D)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair381" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5 
       (.I0(\complex_address_reg_n_0_[5] ),
        .I1(\complex_address_reg_n_0_[4] ),
        .I2(\complex_address_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000001011)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6 
       (.I0(address_w[12]),
        .I1(D[3]),
        .I2(\wrcal_wr_cnt[3]_i_4_n_0 ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF7)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7 
       (.I0(init_state_r1[2]),
        .I1(init_state_r1[1]),
        .I2(init_state_r1[5]),
        .I3(init_state_r1[0]),
        .I4(init_state_r1[4]),
        .I5(init_state_r1[6]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'h95)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAA20AA20AA20AAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ),
        .O(address_w[6]));
  (* SOFT_HLUTNM = "soft_lutpair298" *) 
  LUT5 #(
    .INIT(32'h0000000D)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ),
        .I1(init_state_r),
        .I2(address_w173_out),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_7_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair381" *) 
  LUT4 #(
    .INIT(16'h9555)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3 
       (.I0(\complex_address_reg_n_0_[6] ),
        .I1(\complex_address_reg_n_0_[5] ),
        .I2(\complex_address_reg_n_0_[3] ),
        .I3(\complex_address_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair419" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair344" *) 
  LUT4 #(
    .INIT(16'h9555)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000F4F4F4FF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ),
        .O(address_w[7]));
  (* SOFT_HLUTNM = "soft_lutpair322" *) 
  LUT5 #(
    .INIT(32'hFFDFFFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFBFFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair342" *) 
  LUT5 #(
    .INIT(32'h95555555)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2 
       (.I0(\complex_address_reg_n_0_[7] ),
        .I1(\complex_address_reg_n_0_[6] ),
        .I2(\complex_address_reg_n_0_[4] ),
        .I3(\complex_address_reg_n_0_[3] ),
        .I4(\complex_address_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair390" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_7_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair344" *) 
  LUT5 #(
    .INIT(32'h95555555)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair298" *) 
  LUT4 #(
    .INIT(16'hFFAE)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ),
        .I2(init_state_r),
        .I3(address_w173_out),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFD)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),
        .I4(D[3]),
        .I5(address_w[12]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair337" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7 
       (.I0(init_state_r),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_8_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFF0FCA0AFF0FC000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ),
        .I1(\init_state_r[3]_i_4_n_0 ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(prech_req_posedge_r_i_2_n_0),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000020)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFF28FF28FFFFFF28)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I1(\complex_address_reg_n_0_[8] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .O(address_w[8]));
  (* SOFT_HLUTNM = "soft_lutpair342" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2 
       (.I0(\complex_address_reg_n_0_[6] ),
        .I1(\complex_address_reg_n_0_[4] ),
        .I2(\complex_address_reg_n_0_[3] ),
        .I3(\complex_address_reg_n_0_[5] ),
        .I4(\complex_address_reg_n_0_[7] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000020000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_1 ),
        .I2(cnt_init_mr_r[0]),
        .I3(cnt_init_mr_r[1]),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_7_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_8_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000800E)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair324" *) 
  LUT5 #(
    .INIT(32'h0800002A)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_7 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_9_n_0 ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFDFFFFFF77EFF7F)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_8 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair331" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_9 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0909FF09)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),
        .O(address_w[9]));
  LUT6 #(
    .INIT(64'hFEFFFFFFFEFF0000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10 
       (.I0(oclk_wr_cnt_reg[0]),
        .I1(oclk_wr_cnt_reg[1]),
        .I2(oclk_wr_cnt_reg[3]),
        .I3(oclk_wr_cnt_reg[2]),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h2000000020002000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11 
       (.I0(prech_req_posedge_r_i_3_n_0),
        .I1(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ),
        .I5(init_state_r1[3]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF1FFF1F1F)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12 
       (.I0(\complex_row_cnt_ocal[3]_i_6_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ),
        .I2(D[3]),
        .I3(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I4(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ));
  LUT5 #(
    .INIT(32'h20202000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ),
        .I4(\complex_row_cnt_ocal[3]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair294" *) 
  LUT5 #(
    .INIT(32'hFFFFEFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14 
       (.I0(init_state_r1[2]),
        .I1(init_state_r1[6]),
        .I2(init_state_r1[4]),
        .I3(init_state_r1[3]),
        .I4(init_state_r1[1]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h5504)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15 
       (.I0(complex_row0_rd_done),
        .I1(init_state_r1[3]),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ),
        .I3(\one_rank.stg1_wr_done_reg_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair292" *) 
  LUT5 #(
    .INIT(32'h00000020)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16 
       (.I0(wr_victim_inc_i_2_n_0),
        .I1(D[3]),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17 
       (.I0(\complex_num_writes[2]_i_9_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h0000000200000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h0C0C0CFF0C0C5D5D)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ),
        .I1(\init_state_r[6]_i_2_n_0 ),
        .I2(\wrcal_reads[7]_i_4_n_0 ),
        .I3(complex_ocal_odt_ext_i_3_n_0),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h4444444444444044)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20 
       (.I0(\wrcal_wr_cnt[3]_i_4_n_0 ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(wrcal_wr_cnt_reg[3]),
        .I3(wrcal_wr_cnt_reg[2]),
        .I4(wrcal_wr_cnt_reg[1]),
        .I5(wrcal_wr_cnt_reg[0]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'h000000020808080A)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21 
       (.I0(D[3]),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I4(\num_refresh[3]_i_5_n_0 ),
        .I5(\init_state_r[3]_i_4_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'h007F007F007F0000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair290" *) 
  LUT4 #(
    .INIT(16'hAAEA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'h95)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5 
       (.I0(\complex_address_reg_n_0_[9] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ),
        .I2(\complex_address_reg_n_0_[8] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair311" *) 
  LUT5 #(
    .INIT(32'hAA808080)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6 
       (.I0(\cnt_init_mr_r[1]_i_2_n_0 ),
        .I1(cnt_init_mr_r[0]),
        .I2(cnt_init_mr_r[1]),
        .I3(pi_dqs_found_done),
        .I4(D[3]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h04FF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),
        .I1(init_state_r1[5]),
        .I2(init_state_r1[0]),
        .I3(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h000E)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_9_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'h55555455)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9 
       (.I0(D[3]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ),
        .I2(read_calib_i_2_n_0),
        .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I4(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(address_w[0]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(address_w173_out),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(address_w[12]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(address_w[1]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(address_w[2]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(address_w[3]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(address_w[4]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(address_w[5]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(address_w[6]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(address_w[7]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(address_w[8]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(address_w[9]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000FF04)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_1 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),
        .O(bank_w[0]));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF3F3EFE00000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h55404055)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(pi_dqs_found_done),
        .I2(D[3]),
        .I3(cnt_init_mr_r[0]),
        .I4(cnt_init_mr_r[1]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair379" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(init_state_r),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ),
        .O(bank_w[1]));
  LUT6 #(
    .INIT(64'hF67FF67FF67FF67E)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_1 ),
        .I5(cnt_init_mr_r[1]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair377" *) 
  LUT4 #(
    .INIT(16'h0800)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1 
       (.I0(reg_ctrl_cnt_r),
        .I1(reg_ctrl_cnt_r_reg[2]),
        .I2(reg_ctrl_cnt_r_reg[3]),
        .I3(reg_ctrl_cnt_r_reg[1]),
        .O(bank_w[2]));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_w[0]),
        .Q(phy_bank[9]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_w[1]),
        .Q(phy_bank[10]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_w[2]),
        .Q(phy_bank[11]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair422" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \gen_reset_obuf.u_reset_obuf_i_1 
       (.I0(phy_ctl_wr_i1_reg),
        .I1(phy_reset_n),
        .O(mux_reset_n));
  FDRE \gen_rnk[0].mr1_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b1),
        .Q(\gen_rnk[0].mr1_r_reg_n_0_[0][0] ),
        .R(init_calib_complete_reg_0));
  FDRE init_calib_complete_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r2),
        .Q(calib_complete),
        .R(init_calib_complete_reg_0));
  FDRE init_complete_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r_reg_n_0),
        .Q(init_complete_r1),
        .R(init_calib_complete_reg_0));
  (* KEEP = "yes" *) 
  FDRE init_complete_r1_timing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r_timing),
        .Q(init_complete_r1_timing),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE init_complete_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r1),
        .Q(init_complete_r2),
        .R(init_calib_complete_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000020)) 
    init_complete_r_i_1
       (.I0(prech_req_posedge_r_i_3_n_0),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(init_complete_r_reg_n_0),
        .O(init_complete_r_i_1_n_0));
  FDRE init_complete_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r_i_1_n_0),
        .Q(init_complete_r_reg_n_0),
        .R(init_calib_complete_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000020)) 
    init_complete_r_timing_i_1
       (.I0(prech_req_posedge_r_i_3_n_0),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(init_complete_r_timing),
        .O(init_complete_r_timing_i_1_n_0));
  (* KEEP = "yes" *) 
  FDRE init_complete_r_timing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_complete_r_timing_i_1_n_0),
        .Q(init_complete_r_timing),
        .R(init_calib_complete_reg_0));
  FDRE \init_state_r1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[0] ),
        .Q(init_state_r1[0]),
        .R(init_calib_complete_reg_0));
  FDRE \init_state_r1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[1] ),
        .Q(init_state_r1[1]),
        .R(init_calib_complete_reg_0));
  FDRE \init_state_r1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[2] ),
        .Q(init_state_r1[2]),
        .R(init_calib_complete_reg_0));
  FDRE \init_state_r1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[3] ),
        .Q(init_state_r1[3]),
        .R(init_calib_complete_reg_0));
  FDRE \init_state_r1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[4] ),
        .Q(init_state_r1[4]),
        .R(init_calib_complete_reg_0));
  FDRE \init_state_r1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[5] ),
        .Q(init_state_r1[5]),
        .R(init_calib_complete_reg_0));
  FDRE \init_state_r1_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(init_state_r),
        .Q(init_state_r1[6]),
        .R(init_calib_complete_reg_0));
  LUT6 #(
    .INIT(64'hAEAEAEAEFFAEFFFF)) 
    \init_state_r[0]_i_1 
       (.I0(\init_state_r[0]_i_2_n_0 ),
        .I1(\init_state_r[0]_i_3_n_0 ),
        .I2(\init_state_r[0]_i_4_n_0 ),
        .I3(\init_state_r[0]_i_5_n_0 ),
        .I4(\init_state_r[0]_i_6_n_0 ),
        .I5(\init_state_r[0]_i_7_n_0 ),
        .O(\init_state_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair314" *) 
  LUT4 #(
    .INIT(16'h0400)) 
    \init_state_r[0]_i_10 
       (.I0(rdlvl_stg1_done_r1_reg_0),
        .I1(D[3]),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[0]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFBABB0000)) 
    \init_state_r[0]_i_11 
       (.I0(\init_state_r[5]_i_24_n_0 ),
        .I1(\init_state_r[0]_i_25_n_0 ),
        .I2(\complex_num_reads[3]_i_9_n_0 ),
        .I3(wr_victim_inc_i_2_n_0),
        .I4(\init_state_r[0]_i_26_n_0 ),
        .I5(\init_state_r[0]_i_27_n_0 ),
        .O(\init_state_r[0]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h1500151555555555)) 
    \init_state_r[0]_i_12 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I1(\init_state_r[0]_i_28_n_0 ),
        .I2(\init_state_r[0]_i_29_n_0 ),
        .I3(\init_state_r[0]_i_30_n_0 ),
        .I4(\init_state_r[0]_i_31_n_0 ),
        .I5(\init_state_r[0]_i_25_n_0 ),
        .O(\init_state_r[0]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hC5FFC5FFC5FFC500)) 
    \init_state_r[0]_i_13 
       (.I0(cnt_cmd_done_r),
        .I1(p_15_in),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r[0]_i_32_n_0 ),
        .I5(\init_state_r[0]_i_33_n_0 ),
        .O(\init_state_r[0]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF8F8C0000)) 
    \init_state_r[0]_i_14 
       (.I0(\init_state_r[5]_i_45_n_0 ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[0]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FF02)) 
    \init_state_r[0]_i_15 
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\init_state_r[5]_i_47_n_0 ),
        .I2(\init_state_r[5]_i_48_n_0 ),
        .I3(pi_dqs_found_start_i_2_n_0),
        .I4(\init_state_r[2]_i_23_n_0 ),
        .I5(\init_state_r[0]_i_34_n_0 ),
        .O(\init_state_r[0]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h4544454545454545)) 
    \init_state_r[0]_i_16 
       (.I0(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I1(\init_state_r[0]_i_35_n_0 ),
        .I2(\init_state_r[1]_i_26_n_0 ),
        .I3(num_reads[1]),
        .I4(num_reads[0]),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[0]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h00000E0AFFFFFFFF)) 
    \init_state_r[0]_i_17 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r[0]_i_36_n_0 ),
        .I4(\init_state_r[5]_i_12_n_0 ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[0]_i_17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair420" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \init_state_r[0]_i_19 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(cnt_cmd_done_r),
        .O(\init_state_r[0]_i_19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair339" *) 
  LUT5 #(
    .INIT(32'hF0F00070)) 
    \init_state_r[0]_i_2 
       (.I0(\init_state_r[0]_i_8_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000FFFEEEE)) 
    \init_state_r[0]_i_20 
       (.I0(\init_state_r[0]_i_37_n_0 ),
        .I1(\init_state_r[0]_i_38_n_0 ),
        .I2(\init_state_r[6]_i_6_n_0 ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[0]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAFFBFBFBF)) 
    \init_state_r[0]_i_21 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(wrlvl_done_r1),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\num_refresh[3]_i_5_n_0 ),
        .O(\init_state_r[0]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'h0000C0F0AFFFAFFF)) 
    \init_state_r[0]_i_22 
       (.I0(\init_state_r[0]_i_7_0 ),
        .I1(rdlvl_stg1_done_r1_reg_0),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(cnt_cmd_done_r),
        .I4(reset_rd_addr_r1),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[0]_i_22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair395" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \init_state_r[0]_i_23 
       (.I0(complex_row0_rd_done),
        .I1(complex_num_reads_dec[3]),
        .I2(complex_num_reads_dec[2]),
        .O(\init_state_r[0]_i_23_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair359" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \init_state_r[0]_i_24 
       (.I0(prech_req_posedge_r_reg_0),
        .I1(rdlvl_stg1_done_r1_reg_0),
        .I2(D[3]),
        .O(\init_state_r[0]_i_24_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair316" *) 
  LUT5 #(
    .INIT(32'hD5555555)) 
    \init_state_r[0]_i_25 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(complex_wait_cnt_reg[0]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[2]),
        .I4(complex_wait_cnt_reg[3]),
        .O(\init_state_r[0]_i_25_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair323" *) 
  LUT5 #(
    .INIT(32'h08008888)) 
    \init_state_r[0]_i_26 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(D[3]),
        .I4(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[0]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'h0002000EFFFFFFFF)) 
    \init_state_r[0]_i_27 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[0]_i_27_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF7FFFFFFFFFFF)) 
    \init_state_r[0]_i_28 
       (.I0(complex_wait_cnt_reg[3]),
        .I1(complex_wait_cnt_reg[2]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[0]),
        .I4(\one_rank.stg1_wr_done_reg_0 ),
        .I5(complex_row1_wr_done),
        .O(\init_state_r[0]_i_28_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair334" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \init_state_r[0]_i_29 
       (.I0(prech_req_posedge_r_reg_0),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[0]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF00F1)) 
    \init_state_r[0]_i_3 
       (.I0(\init_state_r[0]_i_9_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r[0]_i_10_n_0 ),
        .I3(\num_refresh[3]_i_5_n_0 ),
        .I4(\init_state_r[0]_i_11_n_0 ),
        .I5(\init_state_r[0]_i_12_n_0 ),
        .O(\init_state_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h8000800080000000)) 
    \init_state_r[0]_i_30 
       (.I0(complex_wait_cnt_reg[0]),
        .I1(complex_wait_cnt_reg[1]),
        .I2(complex_wait_cnt_reg[2]),
        .I3(complex_wait_cnt_reg[3]),
        .I4(rdlvl_stg1_done_r1_reg_0),
        .I5(D[3]),
        .O(\init_state_r[0]_i_30_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair302" *) 
  LUT4 #(
    .INIT(16'h2022)) 
    \init_state_r[0]_i_31 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(rdlvl_stg1_done_r1_reg_0),
        .I3(D[3]),
        .O(\init_state_r[0]_i_31_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair328" *) 
  LUT5 #(
    .INIT(32'h00000020)) 
    \init_state_r[0]_i_32 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(wrcal_wr_cnt_reg[1]),
        .I2(wrcal_wr_cnt_reg[0]),
        .I3(wrcal_wr_cnt_reg[3]),
        .I4(wrcal_wr_cnt_reg[2]),
        .O(\init_state_r[0]_i_32_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair330" *) 
  LUT5 #(
    .INIT(32'h00001101)) 
    \init_state_r[0]_i_33 
       (.I0(prech_req_posedge_r_reg_0),
        .I1(burst_addr_r_reg_0),
        .I2(cnt_cmd_done_r),
        .I3(wrcal_prech_req),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[0]_i_33_n_0 ));
  LUT4 #(
    .INIT(16'h0040)) 
    \init_state_r[0]_i_34 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(pi_phase_locked_all_r3),
        .I3(pi_phase_locked_all_r4),
        .O(\init_state_r[0]_i_34_n_0 ));
  LUT6 #(
    .INIT(64'h0000AAAAAAAAAAA8)) 
    \init_state_r[0]_i_35 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(prech_req_posedge_r_reg_0),
        .I2(pi_dqs_found_rank_done),
        .I3(pi_dqs_found_done),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(cnt_cmd_done_r),
        .O(\init_state_r[0]_i_35_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair310" *) 
  LUT4 #(
    .INIT(16'hFFEF)) 
    \init_state_r[0]_i_36 
       (.I0(reg_ctrl_cnt_r_reg[1]),
        .I1(reg_ctrl_cnt_r_reg[0]),
        .I2(reg_ctrl_cnt_r_reg[3]),
        .I3(reg_ctrl_cnt_r_reg[2]),
        .O(\init_state_r[0]_i_36_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair378" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    \init_state_r[0]_i_37 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[0]_i_37_n_0 ));
  LUT6 #(
    .INIT(64'h000000800000FF80)) 
    \init_state_r[0]_i_38 
       (.I0(ck_addr_cmd_delay_done),
        .I1(cnt_pwron_cke_done_r),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(cnt_txpr_done_r),
        .O(\init_state_r[0]_i_38_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAFFFEAAAAFAFE)) 
    \init_state_r[0]_i_4 
       (.I0(\init_state_r[5]_i_25_n_0 ),
        .I1(\init_state_r[0]_i_13_n_0 ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r[0]_i_14_n_0 ),
        .I5(\init_state_r[0]_i_15_n_0 ),
        .O(\init_state_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hEEEFEEEEEEEFEEEF)) 
    \init_state_r[0]_i_5 
       (.I0(\init_state_r[0]_i_16_n_0 ),
        .I1(\init_state_r[0]_i_17_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg[0]_0 ),
        .I5(\init_state_r[0]_i_19_n_0 ),
        .O(\init_state_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFEEEFFEFFFEFFFEF)) 
    \init_state_r[0]_i_6 
       (.I0(\num_refresh[3]_i_5_n_0 ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r[4]_i_21_n_0 ),
        .I4(ddr2_pre_flag_r_reg_n_0),
        .I5(cnt_cmd_done_r),
        .O(\init_state_r[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hABAAABABABAAABAA)) 
    \init_state_r[0]_i_7 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r[0]_i_20_n_0 ),
        .I2(\init_state_r[0]_i_21_n_0 ),
        .I3(\init_state_r[5]_i_12_n_0 ),
        .I4(\init_state_r[0]_i_22_n_0 ),
        .I5(\init_state_r[2]_i_16_n_0 ),
        .O(\init_state_r[0]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair317" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \init_state_r[0]_i_8 
       (.I0(ocal_act_wait_cnt_reg[2]),
        .I1(ocal_act_wait_cnt_reg[0]),
        .I2(ocal_act_wait_cnt_reg[1]),
        .I3(ocal_act_wait_cnt_reg[3]),
        .O(\init_state_r[0]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hD000D0D0D000D000)) 
    \init_state_r[0]_i_9 
       (.I0(\init_state_r[0]_i_23_n_0 ),
        .I1(\init_state_r[1]_i_32_n_0 ),
        .I2(\init_state_r[0]_i_24_n_0 ),
        .I3(\init_state_r[0]_i_25_n_0 ),
        .I4(\complex_num_reads[3]_i_9_n_0 ),
        .I5(wr_victim_inc_i_2_n_0),
        .O(\init_state_r[0]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEAEAEFFAEFFFF)) 
    \init_state_r[1]_i_1 
       (.I0(\init_state_r[1]_i_2_n_0 ),
        .I1(\init_state_r[1]_i_3_n_0 ),
        .I2(\init_state_r[1]_i_4_n_0 ),
        .I3(\init_state_r[1]_i_5_n_0 ),
        .I4(\init_state_r[1]_i_6_n_0 ),
        .I5(\init_state_r[1]_i_7_n_0 ),
        .O(\init_state_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000510055550000)) 
    \init_state_r[1]_i_10 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I1(\init_state_r[2]_i_7_0 ),
        .I2(\init_state_r[2]_i_7_1 ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[1]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h76000000FFFFFFFF)) 
    \init_state_r[1]_i_11 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[1]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h4444444445554545)) 
    \init_state_r[1]_i_12 
       (.I0(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I1(\init_state_r[1]_i_25_n_0 ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(num_reads[1]),
        .I4(num_reads[0]),
        .I5(\init_state_r[1]_i_26_n_0 ),
        .O(\init_state_r[1]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hEE000FFF00000FFF)) 
    \init_state_r[1]_i_13 
       (.I0(cnt_init_mr_done_r),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_1 ),
        .I2(cnt_txpr_done_r),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(cnt_cmd_done_r),
        .O(\init_state_r[1]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hCFDCCFDCCFDCCCDC)) 
    \init_state_r[1]_i_14 
       (.I0(\init_state_r[1]_i_27_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r[0]_i_19_n_0 ),
        .O(\init_state_r[1]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'hAAAA8A80)) 
    \init_state_r[1]_i_15 
       (.I0(\init_state_r[6]_i_2_n_0 ),
        .I1(rdlvl_stg1_done_r1_reg_0),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(reset_rd_addr_r1),
        .O(\init_state_r[1]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAFBFBFBFBFB)) 
    \init_state_r[1]_i_16 
       (.I0(\init_state_r[5]_i_12_n_0 ),
        .I1(\init_state_r[1]_i_28_n_0 ),
        .I2(\init_state_r[0]_i_7_0 ),
        .I3(\init_state_r[5]_i_37_n_0 ),
        .I4(\init_state_r[5]_i_36_n_0 ),
        .I5(prech_req_posedge_r_i_3_n_0),
        .O(\init_state_r[1]_i_16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair336" *) 
  LUT5 #(
    .INIT(32'hAAEBAAAB)) 
    \init_state_r[1]_i_17 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(cnt_cmd_done_r),
        .O(\init_state_r[1]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF00DFF0)) 
    \init_state_r[1]_i_18 
       (.I0(\one_rank.stg1_wr_done_reg_0 ),
        .I1(prech_req_posedge_r_reg_0),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r[4]_i_9_n_0 ),
        .I5(\init_state_r[1]_i_30_n_0 ),
        .O(\init_state_r[1]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h3A0A3F3F3A0A3A0A)) 
    \init_state_r[1]_i_19 
       (.I0(prech_req_posedge_r_reg_0),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r[4]_i_9_n_0 ),
        .I4(rdlvl_stg1_done_r1_reg_0),
        .I5(D[3]),
        .O(\init_state_r[1]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hFF55004000000000)) 
    \init_state_r[1]_i_2 
       (.I0(\init_state_r[5]_i_9_n_0 ),
        .I1(prech_req_posedge_r_reg_0),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(init_state_r),
        .O(\init_state_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFDDDDDDDF)) 
    \init_state_r[1]_i_20 
       (.I0(wr_victim_inc_i_2_n_0),
        .I1(\complex_num_reads[3]_i_9_n_0 ),
        .I2(\init_state_r[1]_i_31_n_0 ),
        .I3(complex_row0_rd_done),
        .I4(\init_state_r[1]_i_32_n_0 ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[1]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEEEFFFFFFFC)) 
    \init_state_r[1]_i_21 
       (.I0(wrcal_final_chk),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(wrlvl_byte_redo),
        .I3(prech_req_posedge_r_reg_0),
        .I4(burst_addr_r_reg_0),
        .I5(wrcal_resume_r),
        .O(\init_state_r[1]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFAAAABEBEAAAA)) 
    \init_state_r[1]_i_22 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r[4]_i_23_n_0 ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[1]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF4F44)) 
    \init_state_r[1]_i_23 
       (.I0(\init_state_r[5]_i_41_n_0 ),
        .I1(\init_state_r[4]_i_24_n_0 ),
        .I2(ddr3_lm_done_r_i_2_n_0),
        .I3(p_15_in),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[1]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'h44444440CCCCCCCC)) 
    \init_state_r[1]_i_25 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(prech_req_posedge_r_reg_0),
        .I3(pi_dqs_found_rank_done),
        .I4(pi_dqs_found_done),
        .I5(cnt_cmd_done_r),
        .O(\init_state_r[1]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF01000101)) 
    \init_state_r[1]_i_26 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(rdlvl_stg1_rank_done),
        .I2(prech_req_posedge_r_reg_0),
        .I3(rdlvl_stg1_done_r1_reg_0),
        .I4(D[3]),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[1]_i_26_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair321" *) 
  LUT5 #(
    .INIT(32'hFB0B0F0F)) 
    \init_state_r[1]_i_27 
       (.I0(mem_init_done_r),
        .I1(cnt_dllk_zqinit_done_r),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(wrlvl_rank_done_r7),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[1]_i_27_n_0 ));
  LUT6 #(
    .INIT(64'h0000002020202020)) 
    \init_state_r[1]_i_28 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(D[3]),
        .I4(\one_rank.stg1_wr_done_reg_0 ),
        .I5(pi_calib_done),
        .O(\init_state_r[1]_i_28_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF0D)) 
    \init_state_r[1]_i_3 
       (.I0(\init_state_r[1]_i_8_n_0 ),
        .I1(\init_state_r[1]_i_9_n_0 ),
        .I2(\num_refresh[3]_i_5_n_0 ),
        .I3(\init_state_r[1]_i_10_n_0 ),
        .I4(\init_state_r[1]_i_11_n_0 ),
        .I5(\init_state_r[1]_i_12_n_0 ),
        .O(\init_state_r[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair314" *) 
  LUT5 #(
    .INIT(32'h0040FFFF)) 
    \init_state_r[1]_i_30 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(D[3]),
        .I3(rdlvl_stg1_done_r1_reg_0),
        .I4(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[1]_i_30_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair395" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \init_state_r[1]_i_31 
       (.I0(complex_num_reads_dec[2]),
        .I1(complex_num_reads_dec[3]),
        .O(\init_state_r[1]_i_31_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair374" *) 
  LUT4 #(
    .INIT(16'hFFEF)) 
    \init_state_r[1]_i_32 
       (.I0(D[3]),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(complex_num_reads_dec[0]),
        .I3(complex_num_reads_dec[1]),
        .O(\init_state_r[1]_i_32_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAFEAAAAAAAA)) 
    \init_state_r[1]_i_4 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r[1]_i_13_n_0 ),
        .I2(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I3(\init_state_r[1]_i_14_n_0 ),
        .I4(\init_state_r[1]_i_15_n_0 ),
        .I5(\init_state_r[1]_i_16_n_0 ),
        .O(\init_state_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4FFF4F4F4FFF4FFF)) 
    \init_state_r[1]_i_5 
       (.I0(\init_state_r[1]_i_17_n_0 ),
        .I1(\init_state_r[1]_i_18_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\num_refresh[3]_i_5_n_0 ),
        .I4(\init_state_r[1]_i_19_n_0 ),
        .I5(\init_state_r[1]_i_20_n_0 ),
        .O(\init_state_r[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h7777F7FF77777777)) 
    \init_state_r[1]_i_6 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(complex_sample_cnt_inc_i_2_n_0),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r[5]_i_24_n_0 ),
        .I5(\init_state_r[4]_i_9_n_0 ),
        .O(\init_state_r[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAFEFFAAAAAAAA)) 
    \init_state_r[1]_i_7 
       (.I0(\init_state_r[5]_i_25_n_0 ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I3(\init_state_r[1]_i_21_n_0 ),
        .I4(\init_state_r[1]_i_22_n_0 ),
        .I5(\init_state_r[1]_i_23_n_0 ),
        .O(\init_state_r[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h45454500FFFFFFFF)) 
    \init_state_r[1]_i_8 
       (.I0(\init_state_r[4]_i_33_n_0 ),
        .I1(\init_state_r[4]_i_31_n_0 ),
        .I2(\init_state_r[4]_i_32_n_0 ),
        .I3(\init_state_r[4]_i_35_n_0 ),
        .I4(\init_state_r[1]_i_3_0 ),
        .I5(prech_req_posedge_r_i_3_n_0),
        .O(\init_state_r[1]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair378" *) 
  LUT4 #(
    .INIT(16'h00F4)) 
    \init_state_r[1]_i_9 
       (.I0(ddr2_pre_flag_r_reg_n_0),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[1]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h54FF54FFFFFF54FF)) 
    \init_state_r[2]_i_1 
       (.I0(\init_state_r[2]_i_2_n_0 ),
        .I1(\init_state_r[2]_i_3_n_0 ),
        .I2(\init_state_r[2]_i_4_n_0 ),
        .I3(\init_state_r[2]_i_5_n_0 ),
        .I4(\init_state_r[2]_i_6_n_0 ),
        .I5(\init_state_r[2]_i_7_n_0 ),
        .O(\init_state_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0003333311113333)) 
    \init_state_r[2]_i_10 
       (.I0(prbs_rdlvl_done_pulse0),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I2(prech_req_posedge_r_reg_0),
        .I3(\init_state_r[2]_i_24_n_0 ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[2]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair302" *) 
  LUT5 #(
    .INIT(32'h0000F200)) 
    \init_state_r[2]_i_11 
       (.I0(D[3]),
        .I1(rdlvl_stg1_done_r1_reg_0),
        .I2(\init_state_r[4]_i_9_n_0 ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[2]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h10000000FFFFFFFF)) 
    \init_state_r[2]_i_12 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[2]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair351" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \init_state_r[2]_i_13 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(D[3]),
        .O(\init_state_r[2]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0020)) 
    \init_state_r[2]_i_14 
       (.I0(\init_state_r[2]_i_25_n_0 ),
        .I1(ddr3_lm_done_r_i_2_n_0),
        .I2(cnt_cmd_done_r),
        .I3(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I4(\init_state_r[2]_i_26_n_0 ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[2]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h000000000FFFBFBF)) 
    \init_state_r[2]_i_15 
       (.I0(mem_init_done_r),
        .I1(cnt_dllk_zqinit_done_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(wrlvl_rank_done_r7),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .O(\init_state_r[2]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hFBFBFB00FFFFFFFF)) 
    \init_state_r[2]_i_16 
       (.I0(rdlvl_stg1_done_r1_reg_0),
        .I1(wr_victim_inc_i_2_n_0),
        .I2(\complex_num_reads[3]_i_9_n_0 ),
        .I3(\init_state_r[5]_i_36_n_0 ),
        .I4(\init_state_r[5]_i_37_n_0 ),
        .I5(prech_req_posedge_r_i_3_n_0),
        .O(\init_state_r[2]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h8F888F8F8F8F8F8F)) 
    \init_state_r[2]_i_17 
       (.I0(\init_state_r[2]_i_27_n_0 ),
        .I1(\init_state_r[2]_i_28_n_0 ),
        .I2(\init_state_r[2]_i_29_n_0 ),
        .I3(\init_state_r[2]_i_6_0 ),
        .I4(\init_state_r[0]_i_19_n_0 ),
        .I5(pi_calib_done),
        .O(\init_state_r[2]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h4444404444444444)) 
    \init_state_r[2]_i_18 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I5(wr_victim_inc_i_2_n_0),
        .O(\init_state_r[2]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h00000000F4FF0000)) 
    \init_state_r[2]_i_19 
       (.I0(\init_state_r[2]_i_7_0 ),
        .I1(ddr3_lm_done_r),
        .I2(\init_state_r[2]_i_7_1 ),
        .I3(\init_state_r[0]_i_19_n_0 ),
        .I4(ddr3_lm_done_r_i_2_n_0),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .O(\init_state_r[2]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hDDDFDDDFDDDFDDDD)) 
    \init_state_r[2]_i_2 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r[2]_i_8_n_0 ),
        .I3(\init_state_r[2]_i_9_n_0 ),
        .I4(\init_state_r[5]_i_12_n_0 ),
        .I5(\init_state_r[4]_i_13_n_0 ),
        .O(\init_state_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h5F5DD5D5D5D555D5)) 
    \init_state_r[2]_i_20 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[2]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hC0FFC000EAFFEAFF)) 
    \init_state_r[2]_i_21 
       (.I0(cnt_init_af_done_r),
        .I1(\init_state_r[4]_i_31_n_0 ),
        .I2(\init_state_r[2]_i_7_2 ),
        .I3(\init_state_r[4]_i_35_n_0 ),
        .I4(\init_state_r[2]_i_7_3 ),
        .I5(mem_init_done_r),
        .O(\init_state_r[2]_i_21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair338" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \init_state_r[2]_i_22 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[2]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'h1111111111111110)) 
    \init_state_r[2]_i_23 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(wrlvl_byte_redo),
        .I3(prech_req_posedge_r_reg_0),
        .I4(burst_addr_r_reg_0),
        .I5(wrcal_resume_r),
        .O(\init_state_r[2]_i_23_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair325" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \init_state_r[2]_i_24 
       (.I0(\one_rank.stg1_wr_done_reg_0 ),
        .I1(complex_wait_cnt_reg[0]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[2]),
        .I4(complex_wait_cnt_reg[3]),
        .O(\init_state_r[2]_i_24_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair370" *) 
  LUT4 #(
    .INIT(16'hFBBB)) 
    \init_state_r[2]_i_25 
       (.I0(cnt_init_mr_done_r),
        .I1(cnt_cmd_done_r),
        .I2(pi_dqs_found_done),
        .I3(D[3]),
        .O(\init_state_r[2]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \init_state_r[2]_i_26 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(cnt_cmd_done_r),
        .I5(wrlvl_done_r1),
        .O(\init_state_r[2]_i_26_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair421" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \init_state_r[2]_i_27 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(cnt_cmd_done_r),
        .O(\init_state_r[2]_i_27_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair394" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \init_state_r[2]_i_28 
       (.I0(reset_rd_addr_r1),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[2]_i_28_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair336" *) 
  LUT4 #(
    .INIT(16'hAABA)) 
    \init_state_r[2]_i_29 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[2]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAABAAA)) 
    \init_state_r[2]_i_3 
       (.I0(\init_state_r[2]_i_10_n_0 ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r[2]_i_11_n_0 ),
        .I5(\init_state_r[2]_i_12_n_0 ),
        .O(\init_state_r[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair297" *) 
  LUT5 #(
    .INIT(32'h08088808)) 
    \init_state_r[2]_i_4 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r[4]_i_10_n_0 ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r[2]_i_13_n_0 ),
        .O(\init_state_r[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair421" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \init_state_r[2]_i_5 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(init_state_r),
        .O(\init_state_r[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEEEFFFFFFEF)) 
    \init_state_r[2]_i_6 
       (.I0(\init_state_r[2]_i_14_n_0 ),
        .I1(\init_state_r[2]_i_15_n_0 ),
        .I2(\init_state_r[2]_i_16_n_0 ),
        .I3(\init_state_r[2]_i_17_n_0 ),
        .I4(\init_state_r[2]_i_18_n_0 ),
        .I5(\init_state_r[5]_i_12_n_0 ),
        .O(\init_state_r[2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hABAAABABABABABAB)) 
    \init_state_r[2]_i_7 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r[2]_i_19_n_0 ),
        .I2(\init_state_r[2]_i_20_n_0 ),
        .I3(\init_state_r[2]_i_21_n_0 ),
        .I4(\init_state_r[2]_i_22_n_0 ),
        .I5(cnt_cmd_done_r),
        .O(\init_state_r[2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000015151115)) 
    \init_state_r[2]_i_8 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(pi_phase_locked_all_r3),
        .I4(pi_phase_locked_all_r4),
        .I5(\init_state_r[2]_i_23_n_0 ),
        .O(\init_state_r[2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0E000000)) 
    \init_state_r[2]_i_9 
       (.I0(p_15_in),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFDDDF)) 
    \init_state_r[3]_i_1 
       (.I0(\init_state_r[3]_i_2_n_0 ),
        .I1(\init_state_r[3]_i_3_n_0 ),
        .I2(\init_state_r[3]_i_4_n_0 ),
        .I3(\init_state_r[3]_i_5_n_0 ),
        .I4(\init_state_r[3]_i_6_n_0 ),
        .I5(\init_state_r[3]_i_7_n_0 ),
        .O(\init_state_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h3373337F3F7F337F)) 
    \init_state_r[3]_i_10 
       (.I0(wrlvl_rank_done_r7),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(cnt_dllk_zqinit_done_r),
        .I5(mem_init_done_r),
        .O(\init_state_r[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF4FFFFFFFFF)) 
    \init_state_r[3]_i_11 
       (.I0(rdlvl_last_byte_done),
        .I1(\one_rank.stg1_wr_done_reg_0 ),
        .I2(pi_dqs_found_done),
        .I3(D[3]),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(pi_calib_done),
        .O(\init_state_r[3]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0000005D00000000)) 
    \init_state_r[3]_i_12 
       (.I0(prech_req_posedge_r_i_3_n_0),
        .I1(\init_state_r[4]_i_9_n_0 ),
        .I2(prbs_rdlvl_done_pulse0),
        .I3(\init_state_r[3]_i_15_n_0 ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFF3AAF300F3AAF3)) 
    \init_state_r[3]_i_13 
       (.I0(\init_state_r[3]_i_16_n_0 ),
        .I1(\init_state_r[3]_i_17_n_0 ),
        .I2(\init_state_r[4]_i_9_n_0 ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r[2]_i_13_n_0 ),
        .O(\init_state_r[3]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h0000000080CCFFFF)) 
    \init_state_r[3]_i_14 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r[4]_i_23_n_0 ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r[3]_i_18_n_0 ),
        .O(\init_state_r[3]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair367" *) 
  LUT4 #(
    .INIT(16'h5504)) 
    \init_state_r[3]_i_15 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(D[3]),
        .I2(rdlvl_stg1_done_r1_reg_0),
        .I3(prech_req_posedge_r_reg_0),
        .O(\init_state_r[3]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair329" *) 
  LUT4 #(
    .INIT(16'hAA08)) 
    \init_state_r[3]_i_16 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(D[3]),
        .I2(complex_oclkdelay_calib_done_r1),
        .I3(prech_req_posedge_r_reg_0),
        .O(\init_state_r[3]_i_16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair367" *) 
  LUT4 #(
    .INIT(16'h7040)) 
    \init_state_r[3]_i_17 
       (.I0(prech_req_posedge_r_reg_0),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(rdlvl_stg1_done_r1_reg_0),
        .O(\init_state_r[3]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'hBAEAAAEABAAAAAAA)) 
    \init_state_r[3]_i_18 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[3]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBFFFBFFFBF)) 
    \init_state_r[3]_i_2 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r[3]_i_8_n_0 ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r[3]_i_9_n_0 ),
        .O(\init_state_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000046024646)) 
    \init_state_r[3]_i_3 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r[3]_i_10_n_0 ),
        .I3(ddr3_lm_done_r_i_2_n_0),
        .I4(cnt_cmd_done_r),
        .I5(\cnt_init_mr_r[0]_i_2_n_0 ),
        .O(\init_state_r[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair295" *) 
  LUT5 #(
    .INIT(32'hFEFFFFFF)) 
    \init_state_r[3]_i_4 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h2A0000002A000800)) 
    \init_state_r[3]_i_5 
       (.I0(\init_state_r[3]_i_11_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(reset_rd_addr_r1),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFF004E0000000000)) 
    \init_state_r[3]_i_6 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r[5]_i_8_n_0 ),
        .I2(\init_state_r[5]_i_9_n_0 ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(init_state_r),
        .O(\init_state_r[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000BBFB)) 
    \init_state_r[3]_i_7 
       (.I0(\init_state_r[3]_i_12_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r[3]_i_13_n_0 ),
        .I4(\init_state_r[3]_i_14_n_0 ),
        .I5(\init_state_r[5]_i_25_n_0 ),
        .O(\init_state_r[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hF3F3A3AFF3F3AFAF)) 
    \init_state_r[3]_i_8 
       (.I0(\init_state_r[4]_i_27_n_0 ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg[0]_0 ),
        .O(\init_state_r[3]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h00CF00EE00FFFFFF)) 
    \init_state_r[3]_i_9 
       (.I0(ddr2_pre_flag_r_reg_n_0),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r[4]_i_33_n_0 ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(cnt_cmd_done_r),
        .O(\init_state_r[3]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEAEAEFFAEFFFF)) 
    \init_state_r[4]_i_1 
       (.I0(\init_state_r[4]_i_2_n_0 ),
        .I1(\init_state_r[4]_i_3_n_0 ),
        .I2(\init_state_r[4]_i_4_n_0 ),
        .I3(\init_state_r[4]_i_5_n_0 ),
        .I4(\init_state_r[4]_i_6_n_0 ),
        .I5(\init_state_r[4]_i_7_n_0 ),
        .O(\init_state_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF04000000)) 
    \init_state_r[4]_i_10 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I3(wr_victim_inc_i_2_n_0),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r[5]_i_24_n_0 ),
        .O(\init_state_r[4]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h50500000F0D00000)) 
    \init_state_r[4]_i_11 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(D[3]),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[4]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAAABAAAAAAAAAAAA)) 
    \init_state_r[4]_i_12 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\one_rank.stg1_wr_done_reg_0 ),
        .I2(\init_state_r[4]_i_9_n_0 ),
        .I3(prech_req_posedge_r_reg_0),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[4]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair368" *) 
  LUT4 #(
    .INIT(16'hD313)) 
    \init_state_r[4]_i_13 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r[4]_i_23_n_0 ),
        .O(\init_state_r[4]_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair338" *) 
  LUT5 #(
    .INIT(32'hAAAAAAAB)) 
    \init_state_r[4]_i_14 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r[4]_i_24_n_0 ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[4]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF0FFBBBB)) 
    \init_state_r[4]_i_15 
       (.I0(wrcal_resume_r),
        .I1(\init_state_r[4]_i_4_0 ),
        .I2(pi_phase_locked_all_r4),
        .I3(pi_phase_locked_all_r3),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[4]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h0044004000000040)) 
    \init_state_r[4]_i_16 
       (.I0(ddr3_lm_done_r_i_2_n_0),
        .I1(cnt_cmd_done_r),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_1 ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(wrlvl_done_r1),
        .O(\init_state_r[4]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h00020F0F00000000)) 
    \init_state_r[4]_i_17 
       (.I0(\one_rank.stg1_wr_done_reg_0 ),
        .I1(rdlvl_last_byte_done),
        .I2(\init_state_r[4]_i_26_n_0 ),
        .I3(D[3]),
        .I4(pi_dqs_found_done),
        .I5(pi_calib_done),
        .O(\init_state_r[4]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h0000040000000000)) 
    \init_state_r[4]_i_18 
       (.I0(\init_state_r[5]_i_36_n_0 ),
        .I1(rdlvl_stg1_done_r1_reg_0),
        .I2(complex_row0_wr_done),
        .I3(D[3]),
        .I4(complex_num_writes_dec_reg[1]),
        .I5(complex_num_writes_dec_reg[0]),
        .O(\init_state_r[4]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h0808080800888888)) 
    \init_state_r[4]_i_19 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r[4]_i_27_n_0 ),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[4]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF02000000)) 
    \init_state_r[4]_i_2 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r[5]_i_9_n_0 ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r[4]_i_8_n_0 ),
        .O(\init_state_r[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000FFFE)) 
    \init_state_r[4]_i_20 
       (.I0(\init_state_r[2]_i_7_0 ),
        .I1(ddr3_lm_done_r),
        .I2(pi_dqs_found_start_i_2_n_0),
        .I3(\init_state_r[2]_i_7_1 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I5(\init_state_r[4]_i_29_n_0 ),
        .O(\init_state_r[4]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hFF02FF02FF02FFFF)) 
    \init_state_r[4]_i_21 
       (.I0(\init_state_r[4]_i_30_n_0 ),
        .I1(\init_state_r[4]_i_31_n_0 ),
        .I2(\init_state_r[4]_i_32_n_0 ),
        .I3(\init_state_r[4]_i_33_n_0 ),
        .I4(\init_state_r[4]_i_7_0 ),
        .I5(\init_state_r[4]_i_35_n_0 ),
        .O(\init_state_r[4]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'hDDDDDDDDDDDDDFFF)) 
    \init_state_r[4]_i_22 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(cnt_cmd_done_r),
        .I3(ddr2_pre_flag_r_reg_n_0),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[4]_i_22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair327" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \init_state_r[4]_i_23 
       (.I0(oclk_wr_cnt_reg[3]),
        .I1(oclk_wr_cnt_reg[2]),
        .I2(oclk_wr_cnt_reg[0]),
        .I3(oclk_wr_cnt_reg[1]),
        .O(\init_state_r[4]_i_23_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair330" *) 
  LUT5 #(
    .INIT(32'hF2F2F2FF)) 
    \init_state_r[4]_i_24 
       (.I0(cnt_cmd_done_r),
        .I1(wrcal_prech_req),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(prech_req_posedge_r_reg_0),
        .I4(burst_addr_r_reg_0),
        .O(\init_state_r[4]_i_24_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair320" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \init_state_r[4]_i_26 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(cnt_cmd_done_r),
        .O(\init_state_r[4]_i_26_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair318" *) 
  LUT5 #(
    .INIT(32'h00000010)) 
    \init_state_r[4]_i_27 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(reg_ctrl_cnt_r_reg[2]),
        .I2(reg_ctrl_cnt_r_reg[3]),
        .I3(reg_ctrl_cnt_r_reg[0]),
        .I4(reg_ctrl_cnt_r_reg[1]),
        .O(\init_state_r[4]_i_27_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair369" *) 
  LUT4 #(
    .INIT(16'h577F)) 
    \init_state_r[4]_i_29 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[4]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'hE0FFFFFFFFFFFFFF)) 
    \init_state_r[4]_i_3 
       (.I0(\init_state_r[4]_i_9_n_0 ),
        .I1(\init_state_r[4]_i_10_n_0 ),
        .I2(\init_state_r[4]_i_11_n_0 ),
        .I3(\init_state_r[4]_i_12_n_0 ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair370" *) 
  LUT3 #(
    .INIT(8'h2F)) 
    \init_state_r[4]_i_30 
       (.I0(wrlvl_done_r1),
        .I1(D[3]),
        .I2(pi_dqs_found_done),
        .O(\init_state_r[4]_i_30_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair375" *) 
  LUT4 #(
    .INIT(16'hFFFD)) 
    \init_state_r[4]_i_31 
       (.I0(num_refresh_reg[3]),
        .I1(num_refresh_reg[2]),
        .I2(num_refresh_reg[1]),
        .I3(num_refresh_reg[0]),
        .O(\init_state_r[4]_i_31_n_0 ));
  LUT4 #(
    .INIT(16'h2000)) 
    \init_state_r[4]_i_32 
       (.I0(mem_init_done_r),
        .I1(D[3]),
        .I2(rdlvl_stg1_done_r1_reg_0),
        .I3(pi_dqs_found_done),
        .O(\init_state_r[4]_i_32_n_0 ));
  LUT6 #(
    .INIT(64'h5D5D5D5D5DFF5D5D)) 
    \init_state_r[4]_i_33 
       (.I0(cnt_cmd_done_r),
        .I1(cnt_init_af_done_r),
        .I2(mem_init_done_r),
        .I3(wrlvl_done_r1),
        .I4(pi_dqs_found_done),
        .I5(wrlvl_byte_redo),
        .O(\init_state_r[4]_i_33_n_0 ));
  LUT6 #(
    .INIT(64'h00FF0FFFFFFF8FFF)) 
    \init_state_r[4]_i_35 
       (.I0(rdlvl_stg1_done_r1_reg_0),
        .I1(mem_init_done_r),
        .I2(wrlvl_byte_redo),
        .I3(pi_dqs_found_done),
        .I4(wrlvl_done_r1),
        .I5(D[3]),
        .O(\init_state_r[4]_i_35_n_0 ));
  LUT6 #(
    .INIT(64'hAAAABFFFAAAAAFEF)) 
    \init_state_r[4]_i_4 
       (.I0(\init_state_r[5]_i_25_n_0 ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r[4]_i_13_n_0 ),
        .I4(\init_state_r[4]_i_14_n_0 ),
        .I5(\init_state_r[4]_i_15_n_0 ),
        .O(\init_state_r[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFEAEEEAEA)) 
    \init_state_r[4]_i_5 
       (.I0(\init_state_r[4]_i_16_n_0 ),
        .I1(\init_state_r[6]_i_2_n_0 ),
        .I2(reset_rd_addr_r1),
        .I3(rdlvl_stg1_done_r1_reg_0),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hABAAABABBBBBBBBB)) 
    \init_state_r[4]_i_6 
       (.I0(\init_state_r[5]_i_12_n_0 ),
        .I1(\init_state_r[4]_i_17_n_0 ),
        .I2(\init_state_r[4]_i_18_n_0 ),
        .I3(complex_sample_cnt_inc_i_2_n_0),
        .I4(rdlvl_stg1_done_r1_reg_0),
        .I5(prech_req_posedge_r_i_3_n_0),
        .O(\init_state_r[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hABABABABABAAAAAA)) 
    \init_state_r[4]_i_7 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r[4]_i_19_n_0 ),
        .I2(\init_state_r[4]_i_20_n_0 ),
        .I3(prech_req_posedge_r_i_3_n_0),
        .I4(\init_state_r[4]_i_21_n_0 ),
        .I5(\init_state_r[4]_i_22_n_0 ),
        .O(\init_state_r[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hC000C000C0C8C000)) 
    \init_state_r[4]_i_8 
       (.I0(prech_req_posedge_r_reg_0),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[4]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair296" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \init_state_r[4]_i_9 
       (.I0(complex_wait_cnt_reg[3]),
        .I1(complex_wait_cnt_reg[2]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[0]),
        .O(\init_state_r[4]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEEEFFFEFFFF)) 
    \init_state_r[5]_i_1 
       (.I0(\init_state_r[5]_i_2_n_0 ),
        .I1(\init_state_r[5]_i_3_n_0 ),
        .I2(\init_state_r[5]_i_4_n_0 ),
        .I3(\init_state_r[5]_i_5_n_0 ),
        .I4(\init_state_r[5]_i_6_n_0 ),
        .I5(\init_state_r[5]_i_7_n_0 ),
        .O(\init_state_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000400011005100)) 
    \init_state_r[5]_i_10 
       (.I0(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r[5]_i_30_n_0 ),
        .O(\init_state_r[5]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF2F2FFF2)) 
    \init_state_r[5]_i_11 
       (.I0(\init_state_r[6]_i_2_n_0 ),
        .I1(\init_state_r[5]_i_31_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r[5]_i_32_n_0 ),
        .I4(\init_state_r[6]_i_6_n_0 ),
        .I5(\init_state_r[5]_i_33_n_0 ),
        .O(\init_state_r[5]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair418" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \init_state_r[5]_i_12 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[5]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFEEEFEFEEEEEEEEE)) 
    \init_state_r[5]_i_13 
       (.I0(\init_state_r[5]_i_34_n_0 ),
        .I1(\init_state_r[5]_i_35_n_0 ),
        .I2(prech_req_posedge_r_i_3_n_0),
        .I3(\complex_num_reads[3]_i_9_n_0 ),
        .I4(wr_victim_inc_i_2_n_0),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\init_state_r[5]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hEE0EEEEEFFFFFFFF)) 
    \init_state_r[5]_i_14 
       (.I0(\init_state_r[5]_i_36_n_0 ),
        .I1(\init_state_r[5]_i_37_n_0 ),
        .I2(wr_victim_inc_i_2_n_0),
        .I3(\complex_num_reads[3]_i_9_n_0 ),
        .I4(rdlvl_stg1_done_r1_reg_0),
        .I5(prech_req_posedge_r_i_3_n_0),
        .O(\init_state_r[5]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFA822AAAA)) 
    \init_state_r[5]_i_15 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r[5]_i_38_n_0 ),
        .I3(\init_state_r[5]_i_39_n_0 ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(detect_pi_found_dqs_i_2_n_0),
        .O(\init_state_r[5]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair360" *) 
  LUT4 #(
    .INIT(16'hB0BB)) 
    \init_state_r[5]_i_16 
       (.I0(rdlvl_stg1_done_r1_reg_0),
        .I1(D[3]),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r[4]_i_9_n_0 ),
        .O(\init_state_r[5]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h77777777F7FFF777)) 
    \init_state_r[5]_i_17 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r[4]_i_9_n_0 ),
        .I4(\one_rank.stg1_wr_done_reg_0 ),
        .I5(prech_req_posedge_r_reg_0),
        .O(\init_state_r[5]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h10005554FFFFFFFF)) 
    \init_state_r[5]_i_18 
       (.I0(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[5]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \init_state_r[5]_i_19 
       (.I0(complex_num_reads_dec[2]),
        .I1(complex_num_reads_dec[3]),
        .I2(complex_row0_rd_done),
        .I3(complex_num_reads_dec[1]),
        .I4(complex_num_reads_dec[0]),
        .I5(\init_state_r[2]_i_13_n_0 ),
        .O(\init_state_r[5]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'h8A008800AA00A800)) 
    \init_state_r[5]_i_2 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r[5]_i_8_n_0 ),
        .I5(\init_state_r[5]_i_9_n_0 ),
        .O(\init_state_r[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair363" *) 
  LUT4 #(
    .INIT(16'hEFEE)) 
    \init_state_r[5]_i_20 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r[4]_i_9_n_0 ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hDDDDDDDDFDFFFDFD)) 
    \init_state_r[5]_i_21 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(prech_req_posedge_r_reg_0),
        .I3(rdlvl_stg1_done_r1_reg_0),
        .I4(D[3]),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[5]_i_21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair363" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    \init_state_r[5]_i_22 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(D[3]),
        .I3(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair335" *) 
  LUT5 #(
    .INIT(32'hD5555555)) 
    \init_state_r[5]_i_23 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(complex_wait_cnt_reg[0]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[2]),
        .I4(complex_wait_cnt_reg[3]),
        .O(\init_state_r[5]_i_23_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair329" *) 
  LUT5 #(
    .INIT(32'hEFEEAAAA)) 
    \init_state_r[5]_i_24 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(prech_req_posedge_r_reg_0),
        .I2(complex_oclkdelay_calib_done_r1),
        .I3(D[3]),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_24_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair415" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \init_state_r[5]_i_25 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .O(\init_state_r[5]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FFF4)) 
    \init_state_r[5]_i_26 
       (.I0(wrcal_prech_req),
        .I1(\init_state_r[5]_i_40_n_0 ),
        .I2(\init_state_r[5]_i_41_n_0 ),
        .I3(\init_state_r[5]_i_42_n_0 ),
        .I4(\init_state_r[5]_i_43_n_0 ),
        .I5(\cnt_init_mr_r[0]_i_3_n_0 ),
        .O(\init_state_r[5]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF10111111)) 
    \init_state_r[5]_i_27 
       (.I0(\init_state_r[5]_i_12_n_0 ),
        .I1(\init_state_r[5]_i_44_n_0 ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r[5]_i_45_n_0 ),
        .I5(\init_state_r[5]_i_46_n_0 ),
        .O(\init_state_r[5]_i_27_n_0 ));
  LUT5 #(
    .INIT(32'hFF008A00)) 
    \init_state_r[5]_i_28 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(pi_phase_locked_all_r4),
        .I2(pi_phase_locked_all_r3),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_28_n_0 ));
  LUT6 #(
    .INIT(64'hFD00FFFFFD00FD00)) 
    \init_state_r[5]_i_29 
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\init_state_r[5]_i_47_n_0 ),
        .I2(\init_state_r[5]_i_48_n_0 ),
        .I3(\init_state_r[5]_i_49_n_0 ),
        .I4(\init_state_r[5]_i_50_n_0 ),
        .I5(\init_state_r[5]_i_51_n_0 ),
        .O(\init_state_r[5]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EFEEEFEF)) 
    \init_state_r[5]_i_3 
       (.I0(\init_state_r[5]_i_10_n_0 ),
        .I1(\init_state_r[5]_i_11_n_0 ),
        .I2(\init_state_r[5]_i_12_n_0 ),
        .I3(\init_state_r[5]_i_13_n_0 ),
        .I4(\init_state_r[5]_i_14_n_0 ),
        .I5(\init_state_r[5]_i_15_n_0 ),
        .O(\init_state_r[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair319" *) 
  LUT5 #(
    .INIT(32'hB8888888)) 
    \init_state_r[5]_i_30 
       (.I0(cnt_txpr_done_r),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(ck_addr_cmd_delay_done),
        .I3(cnt_pwron_cke_done_r),
        .I4(Q),
        .O(\init_state_r[5]_i_30_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair397" *) 
  LUT3 #(
    .INIT(8'h0D)) 
    \init_state_r[5]_i_31 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(cnt_cmd_done_r),
        .I2(reset_rd_addr_r1),
        .O(\init_state_r[5]_i_31_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair315" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    \init_state_r[5]_i_32 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_32_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair315" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \init_state_r[5]_i_33 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_33_n_0 ));
  LUT6 #(
    .INIT(64'h0000D50000000000)) 
    \init_state_r[5]_i_34 
       (.I0(pi_calib_done),
        .I1(pi_dqs_found_done),
        .I2(D[3]),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_34_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair326" *) 
  LUT4 #(
    .INIT(16'h0020)) 
    \init_state_r[5]_i_35 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(cnt_cmd_done_r),
        .O(\init_state_r[5]_i_35_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \init_state_r[5]_i_36 
       (.I0(complex_num_writes_dec_reg[2]),
        .I1(complex_num_writes_dec_reg[3]),
        .I2(complex_num_writes_dec_reg[4]),
        .O(\init_state_r[5]_i_36_n_0 ));
  LUT5 #(
    .INIT(32'hFFDFFFFF)) 
    \init_state_r[5]_i_37 
       (.I0(complex_num_writes_dec_reg[0]),
        .I1(complex_num_writes_dec_reg[1]),
        .I2(D[3]),
        .I3(complex_row0_wr_done),
        .I4(rdlvl_stg1_done_r1_reg_0),
        .O(\init_state_r[5]_i_37_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair397" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \init_state_r[5]_i_38 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .O(\init_state_r[5]_i_38_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair339" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \init_state_r[5]_i_39 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[5]_i_39_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF22200000)) 
    \init_state_r[5]_i_4 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r[5]_i_16_n_0 ),
        .I3(pi_dqs_found_start_i_2_n_0),
        .I4(\init_state_r[5]_i_17_n_0 ),
        .I5(\init_state_r[5]_i_18_n_0 ),
        .O(\init_state_r[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair401" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \init_state_r[5]_i_40 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_40_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAABAAAAAAAAAA)) 
    \init_state_r[5]_i_41 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(wrcal_wr_cnt_reg[2]),
        .I2(wrcal_wr_cnt_reg[3]),
        .I3(wrcal_wr_cnt_reg[0]),
        .I4(wrcal_wr_cnt_reg[1]),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_41_n_0 ));
  LUT6 #(
    .INIT(64'hF1FFF1F100000000)) 
    \init_state_r[5]_i_42 
       (.I0(burst_addr_r_reg_0),
        .I1(prech_req_posedge_r_reg_0),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(wrcal_prech_req),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\init_state_r[5]_i_42_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair326" *) 
  LUT5 #(
    .INIT(32'h00400444)) 
    \init_state_r[5]_i_43 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(p_15_in),
        .I4(cnt_cmd_done_r),
        .O(\init_state_r[5]_i_43_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair368" *) 
  LUT3 #(
    .INIT(8'h07)) 
    \init_state_r[5]_i_44 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_44_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair327" *) 
  LUT5 #(
    .INIT(32'hAAAAAA8A)) 
    \init_state_r[5]_i_45 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(oclk_wr_cnt_reg[1]),
        .I2(oclk_wr_cnt_reg[0]),
        .I3(oclk_wr_cnt_reg[2]),
        .I4(oclk_wr_cnt_reg[3]),
        .O(\init_state_r[5]_i_45_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAFFFEAAAAAAAA)) 
    \init_state_r[5]_i_46 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[5]_i_46_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \init_state_r[5]_i_47 
       (.I0(\wrcal_reads_reg_n_0_[4] ),
        .I1(\wrcal_reads_reg_n_0_[7] ),
        .I2(\wrcal_reads_reg_n_0_[2] ),
        .O(\init_state_r[5]_i_47_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair372" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \init_state_r[5]_i_48 
       (.I0(\wrcal_reads_reg_n_0_[6] ),
        .I1(\wrcal_reads_reg_n_0_[5] ),
        .I2(\wrcal_reads_reg_n_0_[1] ),
        .I3(\wrcal_reads_reg_n_0_[3] ),
        .O(\init_state_r[5]_i_48_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair420" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \init_state_r[5]_i_49 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .O(\init_state_r[5]_i_49_n_0 ));
  LUT6 #(
    .INIT(64'h00EF00EF000000EF)) 
    \init_state_r[5]_i_5 
       (.I0(\init_state_r[5]_i_19_n_0 ),
        .I1(\init_state_r[5]_i_20_n_0 ),
        .I2(complex_sample_cnt_inc_i_2_n_0),
        .I3(\init_state_r[5]_i_21_n_0 ),
        .I4(prech_req_posedge_r_i_3_n_0),
        .I5(\init_state_r[5]_i_16_n_0 ),
        .O(\init_state_r[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair396" *) 
  LUT3 #(
    .INIT(8'h54)) 
    \init_state_r[5]_i_50 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(wrcal_resume_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .O(\init_state_r[5]_i_50_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFD)) 
    \init_state_r[5]_i_51 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(burst_addr_r_reg_0),
        .I3(prech_req_posedge_r_reg_0),
        .I4(wrlvl_byte_redo),
        .O(\init_state_r[5]_i_51_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBBBBABAAAA)) 
    \init_state_r[5]_i_6 
       (.I0(\init_state_r[5]_i_12_n_0 ),
        .I1(\init_state_r[5]_i_22_n_0 ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(complex_sample_cnt_inc_i_2_n_0),
        .I4(\init_state_r[5]_i_23_n_0 ),
        .I5(\init_state_r[5]_i_24_n_0 ),
        .O(\init_state_r[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hABAAABABABAAABAA)) 
    \init_state_r[5]_i_7 
       (.I0(\init_state_r[5]_i_25_n_0 ),
        .I1(\init_state_r[5]_i_26_n_0 ),
        .I2(\init_state_r[5]_i_27_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I4(\init_state_r[5]_i_28_n_0 ),
        .I5(\init_state_r[5]_i_29_n_0 ),
        .O(\init_state_r[5]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair391" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \init_state_r[5]_i_8 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(prech_req_posedge_r_reg_0),
        .O(\init_state_r[5]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair317" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    \init_state_r[5]_i_9 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(ocal_act_wait_cnt_reg[3]),
        .I2(ocal_act_wait_cnt_reg[1]),
        .I3(ocal_act_wait_cnt_reg[0]),
        .I4(ocal_act_wait_cnt_reg[2]),
        .O(\init_state_r[5]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h3A3A303030303033)) 
    \init_state_r[6]_i_1 
       (.I0(\init_state_r[6]_i_2_n_0 ),
        .I1(\init_state_r[6]_i_3_n_0 ),
        .I2(init_state_r),
        .I3(\init_state_r[6]_i_4_n_0 ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair301" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \init_state_r[6]_i_2 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair334" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \init_state_r[6]_i_3 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(prech_req_posedge_r_reg_0),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(init_state_r),
        .O(\init_state_r[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hE0EEEEEEEEEEEEEE)) 
    \init_state_r[6]_i_4 
       (.I0(\init_state_r[6]_i_5_n_0 ),
        .I1(\init_state_r[6]_i_6_n_0 ),
        .I2(reset_rd_addr_r1),
        .I3(rdlvl_stg1_done_r1_reg_0),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r[6]_i_2_n_0 ),
        .O(\init_state_r[6]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair373" *) 
  LUT4 #(
    .INIT(16'hDFFF)) 
    \init_state_r[6]_i_5 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[6]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair321" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \init_state_r[6]_i_6 
       (.I0(wrlvl_rank_done_r7),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(cnt_dllk_zqinit_done_r),
        .O(\init_state_r[6]_i_6_n_0 ));
  FDRE \init_state_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[0]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[0] ),
        .R(init_calib_complete_reg_0));
  FDRE \init_state_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[1]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[1] ),
        .R(init_calib_complete_reg_0));
  FDRE \init_state_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[2]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[2] ),
        .R(init_calib_complete_reg_0));
  FDRE \init_state_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[3]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[3] ),
        .R(init_calib_complete_reg_0));
  FDRE \init_state_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[4]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[4] ),
        .R(init_calib_complete_reg_0));
  FDRE \init_state_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[5]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[5] ),
        .R(init_calib_complete_reg_0));
  FDRE \init_state_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\init_state_r[6]_i_1_n_0 ),
        .Q(init_state_r),
        .R(init_calib_complete_reg_0));
  LUT5 #(
    .INIT(32'hFFFF4000)) 
    mem_init_done_r_i_1
       (.I0(cnt_dllk_zqinit_done_r),
        .I1(cnt_dllk_zqinit_r_reg[7]),
        .I2(mem_init_done_r_i_2_n_0),
        .I3(cnt_dllk_zqinit_r_reg[6]),
        .I4(mem_init_done_r),
        .O(mem_init_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    mem_init_done_r_i_2
       (.I0(cnt_dllk_zqinit_r_reg[5]),
        .I1(cnt_dllk_zqinit_r_reg[3]),
        .I2(cnt_dllk_zqinit_r_reg[0]),
        .I3(cnt_dllk_zqinit_r_reg[1]),
        .I4(cnt_dllk_zqinit_r_reg[2]),
        .I5(cnt_dllk_zqinit_r_reg[4]),
        .O(mem_init_done_r_i_2_n_0));
  FDRE mem_init_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mem_init_done_r_i_1_n_0),
        .Q(mem_init_done_r),
        .R(init_calib_complete_reg_0));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_0_5_i_1__0
       (.I0(mc_address[14]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_0_5_i_1__1
       (.I0(mc_bank[5]),
        .I1(phy_bank[11]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_0_5_i_2
       (.I0(mc_address[2]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_0_5_i_2__0
       (.I0(mc_bank[2]),
        .I1(phy_bank[11]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_0_5_i_2__1
       (.I0(out_fifo[10]),
        .I1(phy_wrdata[46]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [0]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_0_5_i_3__0
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(phy_dout[3]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_0_5_i_3__1
       (.I0(phy_bank[11]),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_0_5_i_4
       (.I0(mc_address[25]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_0_5_i_4__0
       (.I0(mc_bank[8]),
        .I1(phy_bank[11]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_0_5_i_4__1
       (.I0(out_fifo[31]),
        .I1(phy_wrdata[121]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_0_5_i_5
       (.I0(out_fifo[19]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_0_5_i_6
       (.I0(out_fifo[51]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_0_5_i_7
       (.I0(out_fifo[42]),
        .I1(phy_wrdata[121]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_1
       (.I0(mc_address[20]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[5]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_1__1
       (.I0(out_fifo[54]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [4]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_1__2
       (.I0(mc_cas_n),
        .I1(phy_ctl_wr_i1_reg),
        .I2(phy_cs_n),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [8]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_2
       (.I0(mc_address[8]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_2__0
       (.I0(out_fifo[3]),
        .I1(phy_wrdata[121]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_2__1
       (.I0(out_fifo[44]),
        .I1(phy_wrdata[121]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_4
       (.I0(out_fifo[68]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [5]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_5
       (.I0(out_fifo[14]),
        .I1(phy_wrdata[46]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_1__0
       (.I0(out_fifo[37]),
        .I1(phy_wrdata[121]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [8]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_18_23_i_1__1
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(phy_dout[7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_2
       (.I0(mc_address[31]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_2__0
       (.I0(out_fifo[20]),
        .I1(phy_wrdata[46]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_2__1
       (.I0(out_fifo[25]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_3
       (.I0(out_fifo[53]),
        .I1(phy_wrdata[123]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [8]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_3__0
       (.I0(out_fifo[57]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_4__0
       (.I0(out_fifo[46]),
        .I1(phy_wrdata[121]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_5
       (.I0(out_fifo[80]),
        .I1(phy_wrdata[126]),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_6
       (.I0(out_fifo[66]),
        .I1(phy_wrdata[123]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_6__0
       (.I0(out_fifo[72]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [11]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_1__0
       (.I0(mc_address[15]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_2
       (.I0(mc_address[3]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_2__2
       (.I0(out_fifo[7]),
        .I1(phy_wrdata[121]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [12]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_3
       (.I0(out_fifo[30]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [12]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_24_29_i_3__1
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [12]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_4
       (.I0(mc_address[26]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [11]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_4__0
       (.I0(out_fifo[18]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [11]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_4__1
       (.I0(out_fifo[26]),
        .I1(phy_wrdata[46]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_5__0
       (.I0(out_fifo[59]),
        .I1(phy_wrdata[123]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_6
       (.I0(out_fifo[41]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1
       (.I0(mc_address[13]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1__0
       (.I0(mc_ras_n),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1__1
       (.I0(out_fifo[78]),
        .I1(phy_wrdata[123]),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [15]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1__2
       (.I0(out_fifo[86]),
        .I1(phy_wrdata[126]),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2
       (.I0(mc_address[1]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[8]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2__0
       (.I0(mc_address[11]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2__1
       (.I0(out_fifo[63]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2__2
       (.I0(out_fifo[74]),
        .I1(phy_wrdata[123]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [15]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_3
       (.I0(out_fifo[9]),
        .I1(phy_wrdata[25]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [17]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_3__0
       (.I0(out_fifo[13]),
        .I1(phy_wrdata[25]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [18]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_30_35_i_3__1
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(phy_dout[11]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_30_35_i_3__2
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4
       (.I0(mc_address[24]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4__0
       (.I0(mc_address[34]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [15]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4__1
       (.I0(out_fifo[0]),
        .I1(phy_wrdata[13]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4__2
       (.I0(out_fifo[4]),
        .I1(phy_wrdata[13]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [17]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_5
       (.I0(out_fifo[29]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [18]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_5__0
       (.I0(out_fifo[35]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_1
       (.I0(mc_address[12]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [18]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_1__0
       (.I0(mc_address[18]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_1__1
       (.I0(out_fifo[49]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_1__2
       (.I0(out_fifo[55]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [20]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_2
       (.I0(mc_address[0]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [17]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_2__0
       (.I0(mc_address[6]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[12]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_3
       (.I0(out_fifo[76]),
        .I1(phy_wrdata[121]),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [21]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_3__0
       (.I0(out_fifo[82]),
        .I1(phy_wrdata[121]),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_4
       (.I0(out_fifo[61]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [20]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_4__0
       (.I0(out_fifo[69]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [21]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_5
       (.I0(out_fifo[11]),
        .I1(phy_wrdata[25]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [23]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_6
       (.I0(out_fifo[2]),
        .I1(phy_wrdata[13]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_1
       (.I0(out_fifo[32]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [24]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_1__0
       (.I0(out_fifo[36]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [24]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_42_47_i_1__1
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [20]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_42_47_i_1__2
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(phy_dout[15]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_2
       (.I0(mc_address[23]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_2__0
       (.I0(mc_address[29]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_2__2
       (.I0(out_fifo[24]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [23]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_3
       (.I0(out_fifo[52]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [25]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_3__1
       (.I0(mc_cke),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_cke),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [21]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_4__0
       (.I0(out_fifo[45]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [25]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_5
       (.I0(out_fifo[79]),
        .I1(phy_wrdata[121]),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [27]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_5__0
       (.I0(out_fifo[84]),
        .I1(phy_wrdata[123]),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [27]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_6
       (.I0(out_fifo[65]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [26]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_6__0
       (.I0(out_fifo[71]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [26]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_1
       (.I0(mc_address[21]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[17]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_1__2
       (.I0(mc_ras_n),
        .I1(phy_ctl_wr_i1_reg),
        .I2(phy_ras_n),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_2
       (.I0(mc_address[9]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_2__0
       (.I0(out_fifo[1]),
        .I1(phy_wrdata[121]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [28]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_3__0
       (.I0(out_fifo[39]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [29]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_3__1
       (.I0(mc_cas_n),
        .I1(phy_ctl_wr_i1_reg),
        .I2(phy_cas_n),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [23]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_48_53_i_3__2
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(phy_dout[19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_4
       (.I0(mc_address[32]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[18]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_4__0
       (.I0(out_fifo[17]),
        .I1(phy_wrdata[46]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [29]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_4__1
       (.I0(out_fifo[27]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [28]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_5
       (.I0(out_fifo[50]),
        .I1(phy_wrdata[123]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [30]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_5__1
       (.I0(mc_odt),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_odt),
        .O(phy_dout[20]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_6__0
       (.I0(out_fifo[47]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [30]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_1
       (.I0(mc_address[19]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_1__0
       (.I0(out_fifo[77]),
        .I1(phy_wrdata[126]),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [32]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_1__1
       (.I0(out_fifo[87]),
        .I1(phy_wrdata[123]),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [32]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_2
       (.I0(mc_address[7]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[21]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_2__0
       (.I0(out_fifo[62]),
        .I1(phy_wrdata[123]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [31]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_2__1
       (.I0(out_fifo[75]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [31]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_2__2
       (.I0(mc_we_n),
        .I1(\phy_ctl_wd_i1_reg[22] ),
        .I2(phy_we_n),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [24]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_3__0
       (.I0(out_fifo[15]),
        .I1(phy_wrdata[25]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [34]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_54_59_i_3__1
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(phy_dout[24]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_4
       (.I0(mc_address[30]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[23]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_4__1
       (.I0(out_fifo[6]),
        .I1(phy_wrdata[13]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [33]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_5
       (.I0(out_fifo[33]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [34]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_5__0
       (.I0(out_fifo[38]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [35]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_6
       (.I0(out_fifo[21]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [33]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_1
       (.I0(mc_address[17]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[26]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_1__0
       (.I0(mc_bank[3]),
        .I1(phy_bank[9]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [26]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_1__2
       (.I0(out_fifo[58]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [36]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_2
       (.I0(mc_address[5]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[25]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_2__0
       (.I0(mc_bank[0]),
        .I1(phy_bank[9]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [25]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_2__1
       (.I0(out_fifo[43]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [35]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_3
       (.I0(out_fifo[81]),
        .I1(phy_wrdata[123]),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [37]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_3__0
       (.I0(out_fifo[85]),
        .I1(phy_wrdata[121]),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [38]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_4
       (.I0(out_fifo[67]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [36]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_4__0
       (.I0(out_fifo[73]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [37]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_66_71_i_1
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(phy_dout[28]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_66_71_i_1__0
       (.I0(phy_bank[9]),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [28]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_2
       (.I0(mc_address[28]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[27]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_2__0
       (.I0(mc_bank[6]),
        .I1(phy_bank[9]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [27]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_1__1
       (.I0(mc_bank[4]),
        .I1(phy_bank[10]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [5]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_2__0
       (.I0(mc_bank[1]),
        .I1(phy_bank[10]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_2__1
       (.I0(out_fifo[12]),
        .I1(phy_wrdata[46]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_2__2
       (.I0(out_fifo[64]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [5]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_6_11_i_3__1
       (.I0(phy_bank[10]),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_4
       (.I0(mc_bank[7]),
        .I1(phy_bank[10]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_4__0
       (.I0(out_fifo[34]),
        .I1(phy_wrdata[121]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_5
       (.I0(out_fifo[22]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_1
       (.I0(mc_address[16]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[30]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_1__0
       (.I0(mc_address[22]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [30]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_1__1
       (.I0(out_fifo[8]),
        .I1(phy_wrdata[46]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [38]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_2
       (.I0(mc_address[4]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[29]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_2__0
       (.I0(mc_address[10]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [29]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_2__2
       (.I0(out_fifo[5]),
        .I1(phy_wrdata[121]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [39]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_3
       (.I0(out_fifo[28]),
        .I1(phy_wrdata[121]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [40]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_72_77_i_3__1
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(phy_dout[32]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_72_77_i_3__2
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_30_35 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [32]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4
       (.I0(mc_address[27]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(phy_dout[31]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4__0
       (.I0(mc_address[33]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 [31]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4__1
       (.I0(out_fifo[16]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [39]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4__2
       (.I0(out_fifo[23]),
        .I1(phy_wrdata[46]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [40]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_5
       (.I0(out_fifo[48]),
        .I1(phy_wrdata[109]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [42]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_5__0
       (.I0(out_fifo[56]),
        .I1(phy_wrdata[123]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [41]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_6
       (.I0(out_fifo[40]),
        .I1(phy_wrdata[121]),
        .I2(\ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_72_77 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [41]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_1__0
       (.I0(out_fifo[83]),
        .I1(phy_wrdata[126]),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [43]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_2
       (.I0(out_fifo[60]),
        .I1(phy_wrdata[111]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[96] [43]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_2__0
       (.I0(out_fifo[70]),
        .I1(phy_wrdata[123]),
        .I2(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_54_59 ),
        .O(\write_buffer.wr_buf_out_data_reg[122] [42]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000200)) 
    mpr_rdlvl_start_i_1
       (.I0(pi_dqs_found_done),
        .I1(pi_dqs_found_start_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\wrcal_reads[7]_i_4_n_0 ),
        .I5(mpr_rdlvl_start_reg_0),
        .O(mpr_rdlvl_start_i_1_n_0));
  FDRE mpr_rdlvl_start_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mpr_rdlvl_start_i_1_n_0),
        .Q(mpr_rdlvl_start_reg_0),
        .R(init_calib_complete_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair400" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \my_empty[7]_i_2__0 
       (.I0(mc_wrdata_en),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_wrdata_en),
        .O(mux_wrdata_en));
  (* SOFT_HLUTNM = "soft_lutpair400" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \my_empty[7]_i_2__1 
       (.I0(phy_ctl_wr_i1_reg),
        .I1(calib_ctl_wren_reg_0),
        .O(mux_cmd_wren));
  LUT1 #(
    .INIT(2'h1)) 
    \num_refresh[0]_i_1 
       (.I0(num_refresh_reg[0]),
        .O(p_0_in__5[0]));
  (* SOFT_HLUTNM = "soft_lutpair409" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \num_refresh[1]_i_1 
       (.I0(num_refresh_reg[0]),
        .I1(num_refresh_reg[1]),
        .O(p_0_in__5[1]));
  (* SOFT_HLUTNM = "soft_lutpair409" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \num_refresh[2]_i_1 
       (.I0(num_refresh_reg[2]),
        .I1(num_refresh_reg[1]),
        .I2(num_refresh_reg[0]),
        .O(p_0_in__5[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFEEEFEEEE)) 
    \num_refresh[3]_i_1 
       (.I0(\num_refresh[3]_i_4_n_0 ),
        .I1(\num_refresh_reg[3]_0 ),
        .I2(\num_refresh[3]_i_5_n_0 ),
        .I3(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I4(prech_req_posedge_r_i_3_n_0),
        .I5(\num_refresh[3]_i_6_n_0 ),
        .O(\num_refresh[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2A22)) 
    \num_refresh[3]_i_2 
       (.I0(\num_refresh[3]_i_7_n_0 ),
        .I1(pi_dqs_found_done),
        .I2(D[3]),
        .I3(wrlvl_done_r1),
        .O(num_refresh0));
  (* SOFT_HLUTNM = "soft_lutpair375" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \num_refresh[3]_i_3 
       (.I0(num_refresh_reg[3]),
        .I1(num_refresh_reg[0]),
        .I2(num_refresh_reg[1]),
        .I3(num_refresh_reg[2]),
        .O(p_0_in__5[3]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00100013)) 
    \num_refresh[3]_i_4 
       (.I0(\wrcal_reads[7]_i_4_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r[5]_i_12_n_0 ),
        .I4(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I5(\num_refresh[3]_i_8_n_0 ),
        .O(\num_refresh[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair373" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \num_refresh[3]_i_5 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .O(\num_refresh[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h4010000000000000)) 
    \num_refresh[3]_i_6 
       (.I0(\init_state_r[5]_i_25_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\num_refresh[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    \num_refresh[3]_i_7 
       (.I0(pi_dqs_found_start_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(init_state_r),
        .O(\num_refresh[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000100000000000)) 
    \num_refresh[3]_i_8 
       (.I0(ddr3_lm_done_r_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\num_refresh[3]_i_8_n_0 ));
  FDRE \num_refresh_reg[0] 
       (.C(CLK),
        .CE(num_refresh0),
        .D(p_0_in__5[0]),
        .Q(num_refresh_reg[0]),
        .R(\num_refresh[3]_i_1_n_0 ));
  FDRE \num_refresh_reg[1] 
       (.C(CLK),
        .CE(num_refresh0),
        .D(p_0_in__5[1]),
        .Q(num_refresh_reg[1]),
        .R(\num_refresh[3]_i_1_n_0 ));
  FDRE \num_refresh_reg[2] 
       (.C(CLK),
        .CE(num_refresh0),
        .D(p_0_in__5[2]),
        .Q(num_refresh_reg[2]),
        .R(\num_refresh[3]_i_1_n_0 ));
  FDRE \num_refresh_reg[3] 
       (.C(CLK),
        .CE(num_refresh0),
        .D(p_0_in__5[3]),
        .Q(num_refresh_reg[3]),
        .R(\num_refresh[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair427" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \ocal_act_wait_cnt[0]_i_1 
       (.I0(ocal_act_wait_cnt_reg[0]),
        .O(p_0_in__8[0]));
  (* SOFT_HLUTNM = "soft_lutpair427" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \ocal_act_wait_cnt[1]_i_1 
       (.I0(ocal_act_wait_cnt_reg[0]),
        .I1(ocal_act_wait_cnt_reg[1]),
        .O(p_0_in__8[1]));
  (* SOFT_HLUTNM = "soft_lutpair385" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \ocal_act_wait_cnt[2]_i_1 
       (.I0(ocal_act_wait_cnt_reg[2]),
        .I1(ocal_act_wait_cnt_reg[0]),
        .I2(ocal_act_wait_cnt_reg[1]),
        .O(p_0_in__8[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    \ocal_act_wait_cnt[3]_i_1 
       (.I0(\ocal_act_wait_cnt[3]_i_3_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I4(init_state_r),
        .I5(wr_lvl_start_reg_1),
        .O(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair385" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \ocal_act_wait_cnt[3]_i_2 
       (.I0(ocal_act_wait_cnt_reg[3]),
        .I1(ocal_act_wait_cnt_reg[1]),
        .I2(ocal_act_wait_cnt_reg[0]),
        .I3(ocal_act_wait_cnt_reg[2]),
        .O(p_0_in__8[3]));
  LUT6 #(
    .INIT(64'hFBBBBBBBBBBBBBBB)) 
    \ocal_act_wait_cnt[3]_i_3 
       (.I0(\init_state_r_reg_n_0_[0] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(ocal_act_wait_cnt_reg[3]),
        .I3(ocal_act_wait_cnt_reg[1]),
        .I4(ocal_act_wait_cnt_reg[0]),
        .I5(ocal_act_wait_cnt_reg[2]),
        .O(\ocal_act_wait_cnt[3]_i_3_n_0 ));
  FDRE \ocal_act_wait_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__8[0]),
        .Q(ocal_act_wait_cnt_reg[0]),
        .R(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  FDRE \ocal_act_wait_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__8[1]),
        .Q(ocal_act_wait_cnt_reg[1]),
        .R(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  FDRE \ocal_act_wait_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__8[2]),
        .Q(ocal_act_wait_cnt_reg[2]),
        .R(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  FDRE \ocal_act_wait_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__8[3]),
        .Q(ocal_act_wait_cnt_reg[3]),
        .R(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \oclk_wr_cnt[0]_i_1 
       (.I0(oclk_wr_cnt_reg[0]),
        .O(\oclk_wr_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair386" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \oclk_wr_cnt[1]_i_1 
       (.I0(oclk_wr_cnt_reg[1]),
        .I1(oclk_wr_cnt_reg[0]),
        .O(\oclk_wr_cnt[1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hA9)) 
    \oclk_wr_cnt[2]_i_1 
       (.I0(oclk_wr_cnt_reg[2]),
        .I1(oclk_wr_cnt_reg[0]),
        .I2(oclk_wr_cnt_reg[1]),
        .O(oclk_wr_cnt0[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAAAAB)) 
    \oclk_wr_cnt[3]_i_1 
       (.I0(\oclk_wr_cnt[3]_i_4_n_0 ),
        .I1(oclk_wr_cnt_reg[0]),
        .I2(oclk_wr_cnt_reg[1]),
        .I3(oclk_wr_cnt_reg[3]),
        .I4(oclk_wr_cnt_reg[2]),
        .I5(wr_lvl_start_reg_1),
        .O(\oclk_wr_cnt[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00008000)) 
    \oclk_wr_cnt[3]_i_2 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\wrcal_reads[7]_i_4_n_0 ),
        .O(p_0_in0_in));
  (* SOFT_HLUTNM = "soft_lutpair386" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \oclk_wr_cnt[3]_i_3 
       (.I0(oclk_wr_cnt_reg[3]),
        .I1(oclk_wr_cnt_reg[2]),
        .I2(oclk_wr_cnt_reg[1]),
        .I3(oclk_wr_cnt_reg[0]),
        .O(oclk_wr_cnt0[3]));
  LUT6 #(
    .INIT(64'h0000000000000800)) 
    \oclk_wr_cnt[3]_i_4 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\oclk_wr_cnt[3]_i_4_n_0 ));
  FDRE \oclk_wr_cnt_reg[0] 
       (.C(CLK),
        .CE(p_0_in0_in),
        .D(\oclk_wr_cnt[0]_i_1_n_0 ),
        .Q(oclk_wr_cnt_reg[0]),
        .R(\oclk_wr_cnt[3]_i_1_n_0 ));
  FDRE \oclk_wr_cnt_reg[1] 
       (.C(CLK),
        .CE(p_0_in0_in),
        .D(\oclk_wr_cnt[1]_i_1_n_0 ),
        .Q(oclk_wr_cnt_reg[1]),
        .R(\oclk_wr_cnt[3]_i_1_n_0 ));
  FDSE \oclk_wr_cnt_reg[2] 
       (.C(CLK),
        .CE(p_0_in0_in),
        .D(oclk_wr_cnt0[2]),
        .Q(oclk_wr_cnt_reg[2]),
        .S(\oclk_wr_cnt[3]_i_1_n_0 ));
  FDRE \oclk_wr_cnt_reg[3] 
       (.C(CLK),
        .CE(p_0_in0_in),
        .D(oclk_wr_cnt0[3]),
        .Q(oclk_wr_cnt_reg[3]),
        .R(\oclk_wr_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair355" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    \odd_cwl.phy_cas_n[1]_i_1 
       (.I0(phy_wrdata_en),
        .I1(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .I2(\odd_cwl.phy_ras_n[1]_i_2_n_0 ),
        .I3(\num_refresh[3]_i_7_n_0 ),
        .O(\odd_cwl.phy_cas_n[1]_i_1_n_0 ));
  FDRE \odd_cwl.phy_cas_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\odd_cwl.phy_cas_n[1]_i_1_n_0 ),
        .Q(phy_cas_n),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair388" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \odd_cwl.phy_ras_n[1]_i_1 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ),
        .I1(\odd_cwl.phy_ras_n[1]_i_2_n_0 ),
        .O(\odd_cwl.phy_ras_n[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0101010101010001)) 
    \odd_cwl.phy_ras_n[1]_i_2 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_9_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ),
        .I2(reg_ctrl_cnt_r),
        .I3(prech_req_posedge_r_i_3_n_0),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I5(\cnt_init_mr_r[0]_i_2_n_0 ),
        .O(\odd_cwl.phy_ras_n[1]_i_2_n_0 ));
  FDRE \odd_cwl.phy_ras_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\odd_cwl.phy_ras_n[1]_i_1_n_0 ),
        .Q(phy_ras_n),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair388" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \odd_cwl.phy_we_n[1]_i_1 
       (.I0(\odd_cwl.phy_ras_n[1]_i_2_n_0 ),
        .I1(phy_wrdata_en),
        .I2(address_w173_out),
        .O(\odd_cwl.phy_we_n[1]_i_1_n_0 ));
  FDRE \odd_cwl.phy_we_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\odd_cwl.phy_we_n[1]_i_1_n_0 ),
        .Q(phy_we_n),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_10 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I1(out_fifo_10),
        .I2(mem_out[7]),
        .I3(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_11 
       (.I0(mc_address[31]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I2(out_fifo_10),
        .I3(mem_out[6]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_12 
       (.I0(mc_address[20]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I2(out_fifo_10),
        .I3(mem_out[5]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_13 
       (.I0(mc_address[8]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I2(out_fifo_10),
        .I3(mem_out[4]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 [0]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_18 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I1(out_fifo_7),
        .I2(mem_out[11]),
        .I3(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_19 
       (.I0(mc_address[24]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I2(out_fifo_10),
        .I3(mem_out[10]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0 [2]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I1(out_fifo_10),
        .I2(mem_out[3]),
        .I3(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_20 
       (.I0(mc_address[13]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I2(out_fifo_10),
        .I3(mem_out[9]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_21 
       (.I0(mc_address[1]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I2(out_fifo_10),
        .I3(mem_out[8]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[1]_0 [0]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_22 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I1(out_fifo_7),
        .I2(mem_out[15]),
        .I3(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_23 
       (.I0(mc_address[29]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(out_fifo_7),
        .I3(mem_out[14]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_24 
       (.I0(mc_address[18]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(out_fifo_7),
        .I3(mem_out[13]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_25 
       (.I0(mc_address[6]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(out_fifo_7),
        .I3(mem_out[12]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[6]_0 [0]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_26 
       (.I0(mc_odt),
        .I1(out_fifo_7),
        .I2(calib_odt),
        .I3(mem_out[23]),
        .I4(out_fifo_11),
        .O(\cmd_pipe_plus.mc_odt_reg[0] [7]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_27 
       (.I0(mc_odt),
        .I1(out_fifo_7),
        .I2(calib_odt),
        .I3(mem_out[22]),
        .I4(out_fifo_11),
        .O(\cmd_pipe_plus.mc_odt_reg[0] [6]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_28 
       (.I0(mc_odt),
        .I1(out_fifo_7),
        .I2(calib_odt),
        .I3(mem_out[21]),
        .I4(out_fifo_11),
        .O(\cmd_pipe_plus.mc_odt_reg[0] [5]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_29 
       (.I0(mc_odt),
        .I1(out_fifo_7),
        .I2(calib_odt),
        .I3(mem_out[20]),
        .I4(out_fifo_11),
        .O(\cmd_pipe_plus.mc_odt_reg[0] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_3 
       (.I0(mc_address[25]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I2(out_fifo_10),
        .I3(mem_out[2]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 [2]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_30 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I1(out_fifo_7),
        .I2(mem_out[19]),
        .I3(out_fifo_11),
        .O(\cmd_pipe_plus.mc_odt_reg[0] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_31 
       (.I0(mc_address[32]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I2(out_fifo_7),
        .I3(mem_out[18]),
        .I4(out_fifo_11),
        .O(\cmd_pipe_plus.mc_odt_reg[0] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_32 
       (.I0(mc_address[21]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I2(out_fifo_7),
        .I3(mem_out[17]),
        .I4(out_fifo_11),
        .O(\cmd_pipe_plus.mc_odt_reg[0] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_33 
       (.I0(mc_address[9]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I2(out_fifo_7),
        .I3(mem_out[16]),
        .I4(out_fifo_11),
        .O(\cmd_pipe_plus.mc_odt_reg[0] [0]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_34 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I1(out_fifo_7),
        .I2(mem_out[27]),
        .I3(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_35 
       (.I0(mc_address[30]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(out_fifo_7),
        .I3(mem_out[26]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_36 
       (.I0(mc_address[19]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(out_fifo_7),
        .I3(mem_out[25]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_37 
       (.I0(mc_address[7]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(out_fifo_7),
        .I3(mem_out[24]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[7]_0 [0]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_38 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I1(out_fifo_7),
        .I2(mem_out[31]),
        .I3(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_39 
       (.I0(mc_address[28]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(out_fifo_7),
        .I3(mem_out[30]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_4 
       (.I0(mc_address[14]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I2(out_fifo_10),
        .I3(mem_out[1]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_40 
       (.I0(mc_address[17]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(out_fifo_7),
        .I3(mem_out[29]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_41 
       (.I0(mc_address[5]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(out_fifo_7),
        .I3(mem_out[28]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[5]_0 [0]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_42 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I1(out_fifo_7),
        .I2(mem_out[35]),
        .I3(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_43 
       (.I0(mc_address[27]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I2(out_fifo_7),
        .I3(mem_out[34]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_44 
       (.I0(mc_address[16]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I2(out_fifo_7),
        .I3(mem_out[33]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_45 
       (.I0(mc_address[4]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I2(out_fifo_7),
        .I3(mem_out[32]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[4]_0 [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    \of_pre_fifo_gen.u_ddr_of_pre_fifo/out_fifo_i_5 
       (.I0(mc_address[2]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I2(out_fifo_10),
        .I3(mem_out[0]),
        .I4(out_fifo_11),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 [0]));
  LUT6 #(
    .INIT(64'h0000000001010100)) 
    \one_rank.stg1_wr_done_i_1 
       (.I0(prbs_rdlvl_done_pulse_reg_0),
        .I1(rdlvl_last_byte_done),
        .I2(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .I3(stg1_wr_done),
        .I4(\one_rank.stg1_wr_done_reg_0 ),
        .I5(complex_byte_rd_done),
        .O(\one_rank.stg1_wr_done_i_1_n_0 ));
  FDRE \one_rank.stg1_wr_done_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\one_rank.stg1_wr_done_i_1_n_0 ),
        .Q(\one_rank.stg1_wr_done_reg_0 ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_10
       (.I0(out_fifo[80]),
        .I1(phy_wrdata[126]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[10]),
        .I4(out_fifo_2),
        .O(D2[4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_11
       (.I0(out_fifo[66]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[9]),
        .I4(out_fifo_2),
        .O(D2[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_11__0
       (.I0(out_fifo[72]),
        .I1(phy_wrdata[111]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[11]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[108] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_12
       (.I0(out_fifo[53]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[8]),
        .I4(out_fifo_2),
        .O(D2[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_12__0
       (.I0(out_fifo[57]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[10]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[108] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_13__0
       (.I0(out_fifo[46]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[9]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[108] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_14__0
       (.I0(out_fifo[37]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[8]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[108] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_15
       (.I0(out_fifo[20]),
        .I1(phy_wrdata[46]),
        .I2(out_fifo_0),
        .I3(out_fifo_1[7]),
        .I4(out_fifo_2),
        .O(D2[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_15__0
       (.I0(out_fifo[25]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[7]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[108] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_16__0
       (.I0(out_fifo[14]),
        .I1(phy_wrdata[46]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[6]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[108] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_17
       (.I0(out_fifo[3]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_0),
        .I3(out_fifo_1[6]),
        .I4(out_fifo_2),
        .O(D2[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_18
       (.I0(out_fifo[78]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[15]),
        .I4(out_fifo_2),
        .O(D3[4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_18__0
       (.I0(out_fifo[86]),
        .I1(phy_wrdata[126]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[16]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[126] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_19
       (.I0(out_fifo[63]),
        .I1(phy_wrdata[111]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[14]),
        .I4(out_fifo_2),
        .O(D3[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_19__0
       (.I0(out_fifo[74]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[15]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[126] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_20__0
       (.I0(out_fifo[59]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[14]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[126] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_21
       (.I0(out_fifo[41]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[13]),
        .I4(out_fifo_2),
        .O(D3[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_22
       (.I0(out_fifo[30]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[12]),
        .I4(out_fifo_2),
        .O(D3[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_23
       (.I0(out_fifo[18]),
        .I1(phy_wrdata[111]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[11]),
        .I4(out_fifo_2),
        .O(D3[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_23__0
       (.I0(out_fifo[26]),
        .I1(phy_wrdata[46]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[13]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[126] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_25__0
       (.I0(out_fifo[7]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[12]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[126] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_26
       (.I0(out_fifo[76]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[21]),
        .I4(out_fifo_2),
        .O(D4[5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_26__0
       (.I0(out_fifo[82]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[22]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[121] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_27
       (.I0(out_fifo[61]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[20]),
        .I4(out_fifo_2),
        .O(D4[4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_27__0
       (.I0(out_fifo[69]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[21]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[121] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_28
       (.I0(out_fifo[49]),
        .I1(phy_wrdata[111]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[19]),
        .I4(out_fifo_2),
        .O(D4[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_28__0
       (.I0(out_fifo[55]),
        .I1(phy_wrdata[111]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[20]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[121] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_3
       (.I0(out_fifo[64]),
        .I1(phy_wrdata[111]),
        .I2(out_fifo_0),
        .I3(out_fifo_1[5]),
        .I4(out_fifo_2),
        .O(D0[5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_30
       (.I0(out_fifo[29]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[18]),
        .I4(out_fifo_2),
        .O(D4[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_30__0
       (.I0(out_fifo[35]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[19]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[121] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_32
       (.I0(out_fifo[9]),
        .I1(phy_wrdata[25]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[17]),
        .I4(out_fifo_2),
        .O(D4[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_32__0
       (.I0(out_fifo[13]),
        .I1(phy_wrdata[25]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[18]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[121] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_33
       (.I0(out_fifo[0]),
        .I1(phy_wrdata[13]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[16]),
        .I4(out_fifo_2),
        .O(D4[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_33__0
       (.I0(out_fifo[4]),
        .I1(phy_wrdata[13]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[17]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[121] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_34
       (.I0(out_fifo[79]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[27]),
        .I4(out_fifo_2),
        .O(D5[5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_34__0
       (.I0(out_fifo[84]),
        .I1(phy_wrdata[123]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[27]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[123] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_35
       (.I0(out_fifo[65]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[26]),
        .I4(out_fifo_2),
        .O(D5[4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_35__0
       (.I0(out_fifo[71]),
        .I1(phy_wrdata[111]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[26]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[123] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_36
       (.I0(out_fifo[52]),
        .I1(phy_wrdata[111]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[25]),
        .I4(out_fifo_2),
        .O(D5[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_37__0
       (.I0(out_fifo[45]),
        .I1(phy_wrdata[109]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[25]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[123] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_38
       (.I0(out_fifo[32]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[24]),
        .I4(out_fifo_2),
        .O(D5[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_38__0
       (.I0(out_fifo[36]),
        .I1(phy_wrdata[109]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[24]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[123] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_39__0
       (.I0(out_fifo[24]),
        .I1(phy_wrdata[111]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[23]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[123] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_3__0
       (.I0(out_fifo[68]),
        .I1(phy_wrdata[111]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[5]),
        .I4(out_fifo_6),
        .O(D1[5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_4
       (.I0(out_fifo[51]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_0),
        .I3(out_fifo_1[4]),
        .I4(out_fifo_2),
        .O(D0[4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_40
       (.I0(out_fifo[11]),
        .I1(phy_wrdata[25]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[23]),
        .I4(out_fifo_2),
        .O(D5[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_41
       (.I0(out_fifo[2]),
        .I1(phy_wrdata[13]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[22]),
        .I4(out_fifo_2),
        .O(D5[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_42
       (.I0(out_fifo[77]),
        .I1(phy_wrdata[126]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[32]),
        .I4(out_fifo_2),
        .O(D6[4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_42__0
       (.I0(out_fifo[87]),
        .I1(phy_wrdata[123]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[32]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[127] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_43
       (.I0(out_fifo[62]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[31]),
        .I4(out_fifo_2),
        .O(D6[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_43__0
       (.I0(out_fifo[75]),
        .I1(phy_wrdata[111]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[31]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[127] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_44
       (.I0(out_fifo[50]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[30]),
        .I4(out_fifo_2),
        .O(D6[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_45__0
       (.I0(out_fifo[47]),
        .I1(phy_wrdata[109]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[30]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[127] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_46__0
       (.I0(out_fifo[39]),
        .I1(phy_wrdata[109]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[29]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[127] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_47
       (.I0(out_fifo[17]),
        .I1(phy_wrdata[46]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[29]),
        .I4(out_fifo_2),
        .O(D6[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_47__0
       (.I0(out_fifo[27]),
        .I1(phy_wrdata[111]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[28]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[127] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_49
       (.I0(out_fifo[1]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[28]),
        .I4(out_fifo_2),
        .O(D6[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_4__0
       (.I0(out_fifo[54]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[4]),
        .I4(out_fifo_6),
        .O(D1[4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_5
       (.I0(out_fifo[42]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_0),
        .I3(out_fifo_1[3]),
        .I4(out_fifo_2),
        .O(D0[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_50
       (.I0(out_fifo[81]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[37]),
        .I4(out_fifo_2),
        .O(D7[4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_50__0
       (.I0(out_fifo[85]),
        .I1(phy_wrdata[121]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[38]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[125] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_51
       (.I0(out_fifo[67]),
        .I1(phy_wrdata[111]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[36]),
        .I4(out_fifo_2),
        .O(D7[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_51__0
       (.I0(out_fifo[73]),
        .I1(phy_wrdata[109]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[37]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[125] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_52__0
       (.I0(out_fifo[58]),
        .I1(phy_wrdata[111]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[36]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[125] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_53
       (.I0(out_fifo[43]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[35]),
        .I4(out_fifo_2),
        .O(D7[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_54
       (.I0(out_fifo[33]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[34]),
        .I4(out_fifo_2),
        .O(D7[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_54__0
       (.I0(out_fifo[38]),
        .I1(phy_wrdata[109]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[35]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[125] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_55
       (.I0(out_fifo[21]),
        .I1(phy_wrdata[111]),
        .I2(out_fifo_3),
        .I3(out_fifo_1[33]),
        .I4(out_fifo_2),
        .O(D7[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_56__0
       (.I0(out_fifo[15]),
        .I1(phy_wrdata[25]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[34]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[125] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_57__0
       (.I0(out_fifo[6]),
        .I1(phy_wrdata[13]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[33]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[125] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_5__0
       (.I0(out_fifo[44]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[3]),
        .I4(out_fifo_6),
        .O(D1[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_6
       (.I0(out_fifo[31]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_0),
        .I3(out_fifo_1[2]),
        .I4(out_fifo_2),
        .O(D0[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_66__0
       (.I0(out_fifo[83]),
        .I1(phy_wrdata[126]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[43]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[122]_0 [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_67
       (.I0(out_fifo[60]),
        .I1(phy_wrdata[111]),
        .I2(out_fifo_4),
        .I3(out_fifo_1[43]),
        .I4(out_fifo_2),
        .O(D9[5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_67__0
       (.I0(out_fifo[70]),
        .I1(phy_wrdata[123]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[42]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[122]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_68
       (.I0(out_fifo[48]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_4),
        .I3(out_fifo_1[42]),
        .I4(out_fifo_2),
        .O(D9[4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_68__0
       (.I0(out_fifo[56]),
        .I1(phy_wrdata[123]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[41]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[122]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_69
       (.I0(out_fifo[40]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_4),
        .I3(out_fifo_1[41]),
        .I4(out_fifo_2),
        .O(D9[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_6__0
       (.I0(out_fifo[34]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[2]),
        .I4(out_fifo_6),
        .O(D1[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_7
       (.I0(out_fifo[19]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_0),
        .I3(out_fifo_1[1]),
        .I4(out_fifo_2),
        .O(D0[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_70
       (.I0(out_fifo[28]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_4),
        .I3(out_fifo_1[40]),
        .I4(out_fifo_2),
        .O(D9[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_71
       (.I0(out_fifo[16]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_4),
        .I3(out_fifo_1[39]),
        .I4(out_fifo_2),
        .O(D9[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_71__0
       (.I0(out_fifo[23]),
        .I1(phy_wrdata[46]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[40]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[122]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_72
       (.I0(out_fifo[8]),
        .I1(phy_wrdata[46]),
        .I2(out_fifo_4),
        .I3(out_fifo_1[38]),
        .I4(out_fifo_2),
        .O(D9[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_73__0
       (.I0(out_fifo[5]),
        .I1(phy_wrdata[121]),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_5[39]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[122]_0 [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_7__0
       (.I0(out_fifo[22]),
        .I1(phy_wrdata[109]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[1]),
        .I4(out_fifo_6),
        .O(D1[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_8
       (.I0(out_fifo[10]),
        .I1(phy_wrdata[46]),
        .I2(out_fifo_0),
        .I3(out_fifo_1[0]),
        .I4(out_fifo_2),
        .O(D0[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_8__0
       (.I0(out_fifo[12]),
        .I1(phy_wrdata[46]),
        .I2(out_fifo_4),
        .I3(out_fifo_5[0]),
        .I4(out_fifo_6),
        .O(D1[0]));
  (* SOFT_HLUTNM = "soft_lutpair410" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[0]_i_1 
       (.I0(mc_cmd[0]),
        .I1(calib_cmd[0]),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\calib_seq_reg[1]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair411" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[17]_i_1 
       (.I0(\phy_ctl_wd_i1_reg[17] ),
        .I1(calib_data_offset_0[0]),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\calib_seq_reg[1]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair412" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[18]_i_1 
       (.I0(\phy_ctl_wd_i1_reg[18] ),
        .I1(calib_data_offset_0[1]),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\calib_seq_reg[1]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair412" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[19]_i_1 
       (.I0(\phy_ctl_wd_i1_reg[19] ),
        .I1(calib_data_offset_0[2]),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\calib_seq_reg[1]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair410" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[1]_i_1 
       (.I0(mc_cmd[1]),
        .I1(calib_cmd[1]),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\calib_seq_reg[1]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair413" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[20]_i_1 
       (.I0(mc_data_offset),
        .I1(calib_data_offset_0[3]),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\calib_seq_reg[1]_0 [6]));
  (* SOFT_HLUTNM = "soft_lutpair413" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[21]_i_1 
       (.I0(\phy_ctl_wd_i1_reg[21] ),
        .I1(calib_data_offset_0[4]),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\calib_seq_reg[1]_0 [7]));
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[22]_i_1 
       (.I0(\phy_ctl_wd_i1_reg[22]_0 ),
        .I1(calib_data_offset_0[5]),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\calib_seq_reg[1]_0 [8]));
  (* SOFT_HLUTNM = "soft_lutpair411" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[2]_i_1 
       (.I0(mc_cas_n),
        .I1(calib_cmd[2]),
        .I2(\phy_ctl_wd_i1_reg[22] ),
        .O(\calib_seq_reg[1]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair422" *) 
  LUT2 #(
    .INIT(4'hE)) 
    phy_ctl_wr_i1_i_1
       (.I0(calib_ctl_wren_reg_0),
        .I1(phy_ctl_wr_i1_reg),
        .O(calib_ctl_wren_reg_1));
  FDCE phy_reset_n_reg
       (.C(CLK),
        .CE(1'b1),
        .CLR(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ),
        .D(cnt_pwron_reset_done_r),
        .Q(phy_reset_n));
  FDRE pi_calib_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_calib_done_r),
        .Q(pi_calib_done),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    pi_calib_done_r_i_1
       (.I0(pi_calib_rank_done_r),
        .I1(pi_calib_done_r),
        .O(pi_calib_done_r_i_1_n_0));
  FDRE pi_calib_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_calib_done_r_i_1_n_0),
        .Q(pi_calib_done_r),
        .R(init_calib_complete_reg_0));
  LUT2 #(
    .INIT(4'h2)) 
    pi_calib_rank_done_r_i_1
       (.I0(pi_phase_locked_all_r3),
        .I1(pi_phase_locked_all_r4),
        .O(init_next_state199_out));
  FDRE pi_calib_rank_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(init_next_state199_out),
        .Q(pi_calib_rank_done_r),
        .R(init_calib_complete_reg_0));
  FDRE pi_dqs_found_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_done),
        .Q(pi_dqs_found_done_r1),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  LUT6 #(
    .INIT(64'h000000000000AAAB)) 
    pi_dqs_found_start_i_1
       (.I0(pi_dqs_found_start_reg_0),
        .I1(prech_req_posedge_r_i_2_n_0),
        .I2(pi_dqs_found_start_i_2_n_0),
        .I3(pi_dqs_found_done),
        .I4(wrlvl_byte_redo),
        .I5(\num_refresh_reg[3]_0 ),
        .O(pi_dqs_found_start_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair394" *) 
  LUT2 #(
    .INIT(4'hB)) 
    pi_dqs_found_start_i_2
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .O(pi_dqs_found_start_i_2_n_0));
  FDRE pi_dqs_found_start_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_dqs_found_start_i_1_n_0),
        .Q(pi_dqs_found_start_reg_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pi_phase_locked_all_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_phase_locked_all_r1_reg_0),
        .Q(pi_phase_locked_all_r1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pi_phase_locked_all_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_phase_locked_all_r1),
        .Q(pi_phase_locked_all_r2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pi_phase_locked_all_r3_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_phase_locked_all_r2),
        .Q(pi_phase_locked_all_r3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pi_phase_locked_all_r4_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_phase_locked_all_r3),
        .Q(pi_phase_locked_all_r4),
        .R(1'b0));
  FDRE prbs_rdlvl_done_pulse_reg
       (.C(CLK),
        .CE(1'b1),
        .D(prbs_rdlvl_done_pulse0),
        .Q(prbs_rdlvl_done_pulse_reg_0),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg[15]_srl16 " *) 
  SRL16E \prech_done_dly_r_reg[15]_srl16 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(CLK),
        .D(prech_done_pre),
        .Q(\prech_done_dly_r_reg[15]_srl16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair366" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \prech_done_dly_r_reg[15]_srl16_i_1 
       (.I0(prech_pending_r_i_2_n_0),
        .I1(prech_req_posedge_r_reg_0),
        .O(prech_done_pre));
  FDRE prech_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(\prech_done_dly_r_reg[15]_srl16_n_0 ),
        .Q(prech_done),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair391" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    prech_pending_r_i_1
       (.I0(prech_req_posedge_r_reg_0),
        .I1(prech_pending_r_i_2_n_0),
        .I2(prech_pending_r),
        .O(prech_pending_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hA8A8AAA8AAAAAAAA)) 
    prech_pending_r_i_2
       (.I0(prech_pending_r),
        .I1(prech_pending_r_i_3_n_0),
        .I2(\num_refresh[3]_i_6_n_0 ),
        .I3(rdlvl_stg1_done_r1_reg_0),
        .I4(\complex_row_cnt_ocal[3]_i_5_n_0 ),
        .I5(prech_pending_r_i_4_n_0),
        .O(prech_pending_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h1111101011101010)) 
    prech_pending_r_i_3
       (.I0(\init_state_r[3]_i_4_n_0 ),
        .I1(pi_dqs_found_start_i_2_n_0),
        .I2(dqs_found_prech_req),
        .I3(rdlvl_stg1_done_r1_reg_0),
        .I4(cnt_cmd_done_r),
        .I5(rdlvl_last_byte_done_r),
        .O(prech_pending_r_i_3_n_0));
  LUT6 #(
    .INIT(64'h0000000000000DDD)) 
    prech_pending_r_i_4
       (.I0(cnt_cmd_done_r),
        .I1(prech_pending_r_i_5_n_0),
        .I2(complex_oclkdelay_calib_start_r1),
        .I3(prech_pending_r_i_6_n_0),
        .I4(stg1_wr_done),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_18_n_0 ),
        .O(prech_pending_r_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair293" *) 
  LUT5 #(
    .INIT(32'hFFFFF7FE)) 
    prech_pending_r_i_5
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\wrcal_reads[7]_i_4_n_0 ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .O(prech_pending_r_i_5_n_0));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    prech_pending_r_i_6
       (.I0(prech_req_posedge_r_i_3_n_0),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(prech_pending_r_i_6_n_0));
  FDRE prech_pending_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(prech_pending_r_i_1_n_0),
        .Q(prech_pending_r),
        .R(init_calib_complete_reg_0));
  LUT6 #(
    .INIT(64'h5454555454545454)) 
    prech_req_posedge_r_i_1
       (.I0(prech_req_r),
        .I1(wrcal_prech_req),
        .I2(rdlvl_prech_req),
        .I3(dqs_found_prech_req),
        .I4(prech_req_posedge_r_i_2_n_0),
        .I5(prech_req_posedge_r_i_3_n_0),
        .O(prech_req_posedge_r0));
  (* SOFT_HLUTNM = "soft_lutpair299" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFD)) 
    prech_req_posedge_r_i_2
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .O(prech_req_posedge_r_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair371" *) 
  LUT2 #(
    .INIT(4'h2)) 
    prech_req_posedge_r_i_3
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .O(prech_req_posedge_r_i_3_n_0));
  FDRE prech_req_posedge_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(prech_req_posedge_r0),
        .Q(prech_req_posedge_r_reg_0),
        .R(init_calib_complete_reg_0));
  LUT6 #(
    .INIT(64'hEEEEEEEEEEFEEEEE)) 
    prech_req_r_i_1
       (.I0(wrcal_prech_req),
        .I1(rdlvl_prech_req),
        .I2(dqs_found_prech_req),
        .I3(prech_req_posedge_r_i_2_n_0),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(prech_req));
  FDRE prech_req_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(prech_req),
        .Q(prech_req_r),
        .R(init_calib_complete_reg_0));
  LUT5 #(
    .INIT(32'h80000000)) 
    pwron_ce_r_i_1
       (.I0(cnt_pwron_ce_r_reg[9]),
        .I1(cnt_pwron_ce_r_reg[7]),
        .I2(pwron_ce_r_i_2_n_0),
        .I3(cnt_pwron_ce_r_reg[6]),
        .I4(cnt_pwron_ce_r_reg[8]),
        .O(pwron_ce_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    pwron_ce_r_i_2
       (.I0(cnt_pwron_ce_r_reg[5]),
        .I1(cnt_pwron_ce_r_reg[3]),
        .I2(cnt_pwron_ce_r_reg[0]),
        .I3(cnt_pwron_ce_r_reg[1]),
        .I4(cnt_pwron_ce_r_reg[2]),
        .I5(cnt_pwron_ce_r_reg[4]),
        .O(pwron_ce_r_i_2_n_0));
  FDRE pwron_ce_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pwron_ce_r_i_1_n_0),
        .Q(pwron_ce_r),
        .R(init_calib_complete_reg_0));
  FDRE rdlvl_last_byte_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_last_byte_done),
        .Q(rdlvl_last_byte_done_r),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[13]_srl14 " *) 
  SRL16E \rdlvl_start_dly0_r_reg[13]_srl14 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(CLK),
        .D(rdlvl_start_pre),
        .Q(\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ));
  FDRE \rdlvl_start_dly0_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ),
        .Q(rdlvl_start_dly0_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00080000)) 
    rdlvl_start_pre_i_1
       (.I0(pi_dqs_found_done),
        .I1(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .I2(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I3(detect_pi_found_dqs_i_2_n_0),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(rdlvl_start_pre),
        .O(rdlvl_start_pre_i_1_n_0));
  FDRE rdlvl_start_pre_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_start_pre_i_1_n_0),
        .Q(rdlvl_start_pre),
        .R(init_calib_complete_reg_0));
  FDRE rdlvl_stg1_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(D[3]),
        .Q(rdlvl_stg1_done_r1_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    rdlvl_stg1_start_i_1
       (.I0(rdlvl_start_dly0_r),
        .I1(prech_req_posedge_r_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(pi_dqs_found_done),
        .I5(rdlvl_stg1_start_reg_0),
        .O(rdlvl_stg1_start_i_1_n_0));
  FDRE rdlvl_stg1_start_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_stg1_start_i_1_n_0),
        .Q(rdlvl_stg1_start_reg_0),
        .R(init_calib_complete_reg_0));
  LUT4 #(
    .INIT(16'h0054)) 
    read_calib_i_1
       (.I0(wr_lvl_start_reg_1),
        .I1(read_calib_i_2_n_0),
        .I2(phy_read_calib),
        .I3(pi_calib_done),
        .O(read_calib_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000020000)) 
    read_calib_i_2
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(init_state_r),
        .O(read_calib_i_2_n_0));
  FDRE read_calib_reg
       (.C(CLK),
        .CE(1'b1),
        .D(read_calib_i_1_n_0),
        .Q(phy_read_calib),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \reg_ctrl_cnt_r[0]_i_1 
       (.I0(reg_ctrl_cnt_r_reg[0]),
        .O(p_0_in__2[0]));
  (* SOFT_HLUTNM = "soft_lutpair408" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \reg_ctrl_cnt_r[1]_i_1 
       (.I0(reg_ctrl_cnt_r_reg[0]),
        .I1(reg_ctrl_cnt_r_reg[1]),
        .O(p_0_in__2[1]));
  (* SOFT_HLUTNM = "soft_lutpair408" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \reg_ctrl_cnt_r[2]_i_1 
       (.I0(reg_ctrl_cnt_r_reg[2]),
        .I1(reg_ctrl_cnt_r_reg[1]),
        .I2(reg_ctrl_cnt_r_reg[0]),
        .O(p_0_in__2[2]));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \reg_ctrl_cnt_r[3]_i_1 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .O(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    \reg_ctrl_cnt_r[3]_i_2 
       (.I0(ddr3_lm_done_r_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(init_state_r),
        .O(reg_ctrl_cnt_r));
  (* SOFT_HLUTNM = "soft_lutpair318" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \reg_ctrl_cnt_r[3]_i_3 
       (.I0(reg_ctrl_cnt_r_reg[3]),
        .I1(reg_ctrl_cnt_r_reg[2]),
        .I2(reg_ctrl_cnt_r_reg[0]),
        .I3(reg_ctrl_cnt_r_reg[1]),
        .O(p_0_in__2[3]));
  FDRE \reg_ctrl_cnt_r_reg[0] 
       (.C(CLK),
        .CE(reg_ctrl_cnt_r),
        .D(p_0_in__2[0]),
        .Q(reg_ctrl_cnt_r_reg[0]),
        .R(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  FDRE \reg_ctrl_cnt_r_reg[1] 
       (.C(CLK),
        .CE(reg_ctrl_cnt_r),
        .D(p_0_in__2[1]),
        .Q(reg_ctrl_cnt_r_reg[1]),
        .R(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  FDRE \reg_ctrl_cnt_r_reg[2] 
       (.C(CLK),
        .CE(reg_ctrl_cnt_r),
        .D(p_0_in__2[2]),
        .Q(reg_ctrl_cnt_r_reg[2]),
        .R(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  FDRE \reg_ctrl_cnt_r_reg[3] 
       (.C(CLK),
        .CE(reg_ctrl_cnt_r),
        .D(p_0_in__2[3]),
        .Q(reg_ctrl_cnt_r_reg[3]),
        .R(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  FDRE reset_rd_addr_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(complex_ocal_reset_rd_addr),
        .Q(reset_rd_addr_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair333" *) 
  LUT4 #(
    .INIT(16'h0455)) 
    \row_cnt_victim_rotate.complex_row_cnt[0]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),
        .I2(\one_rank.stg1_wr_done_reg_0 ),
        .I3(complex_sample_cnt_inc_r2),
        .O(\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair333" *) 
  LUT5 #(
    .INIT(32'h00606666)) 
    \row_cnt_victim_rotate.complex_row_cnt[1]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),
        .I3(\one_rank.stg1_wr_done_reg_0 ),
        .I4(complex_sample_cnt_inc_r2),
        .O(\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000780078787878)) 
    \row_cnt_victim_rotate.complex_row_cnt[2]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),
        .I4(\one_rank.stg1_wr_done_reg_0 ),
        .I5(complex_sample_cnt_inc_r2),
        .O(\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair313" *) 
  LUT5 #(
    .INIT(32'h00007F80)) 
    \row_cnt_victim_rotate.complex_row_cnt[3]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h8A)) 
    \row_cnt_victim_rotate.complex_row_cnt[3]_i_2 
       (.I0(complex_sample_cnt_inc_r2),
        .I1(\one_rank.stg1_wr_done_reg_0 ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAEEEFAAAA)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ),
        .I1(reset_rd_addr_r1),
        .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),
        .I3(complex_sample_cnt_inc_r2),
        .I4(\one_rank.stg1_wr_done_reg_0 ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h0E)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),
        .I1(\one_rank.stg1_wr_done_reg_0 ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ),
        .O(complex_row_cnt));
  LUT6 #(
    .INIT(64'h1555555540000000)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_3 
       (.I0(complex_sample_cnt_inc_r2),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair359" *) 
  LUT4 #(
    .INIT(16'hFFFB)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_4 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ),
        .I1(rdlvl_stg1_done_r1_reg_0),
        .I2(wr_lvl_start_reg_1),
        .I3(D[3]),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_5 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000000000FB)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_6 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),
        .I1(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_9_n_0 ),
        .I3(wr_victim_inc),
        .I4(complex_sample_cnt_inc_r2),
        .I5(reset_rd_addr_r1),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000008)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_7 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),
        .I1(wr_victim_inc),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair300" *) 
  LUT5 #(
    .INIT(32'hFFFFDFFF)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_8 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFBFFFFFF)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_9 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I5(\complex_row_cnt_ocal[3]_i_7_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h0000000022226AAA)) 
    \row_cnt_victim_rotate.complex_row_cnt[5]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .I1(complex_row_cnt),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),
        .I4(complex_sample_cnt_inc_r2),
        .I5(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair313" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \row_cnt_victim_rotate.complex_row_cnt[5]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0000262A)) 
    \row_cnt_victim_rotate.complex_row_cnt[6]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .I1(complex_row_cnt),
        .I2(complex_sample_cnt_inc_r2),
        .I3(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000022226AAA)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .I1(complex_row_cnt),
        .I2(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .I4(complex_sample_cnt_inc_r2),
        .I5(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAFFFBAAAA)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_3 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),
        .I2(reset_rd_addr_r1),
        .I3(complex_sample_cnt_inc_r2),
        .I4(\one_rank.stg1_wr_done_reg_0 ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[0] 
       (.C(CLK),
        .CE(complex_row_cnt),
        .D(\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[1] 
       (.C(CLK),
        .CE(complex_row_cnt),
        .D(\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[2] 
       (.C(CLK),
        .CE(complex_row_cnt),
        .D(\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[3] 
       (.C(CLK),
        .CE(complex_row_cnt),
        .D(\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[4] 
       (.C(CLK),
        .CE(complex_row_cnt),
        .D(\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    rst_dqs_find_i_17
       (.I0(detect_pi_found_dqs),
        .I1(rst_dqs_find_i_12),
        .O(detect_pi_found_dqs_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair353" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \stg1_wr_rd_cnt[0]_i_1 
       (.I0(\stg1_wr_rd_cnt[6]_i_2_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0D00000D0D0D0D0D)) 
    \stg1_wr_rd_cnt[1]_i_1 
       (.I0(stg1_wr_done),
        .I1(D[3]),
        .I2(wr_lvl_start_reg_1),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I5(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \stg1_wr_rd_cnt[1]_i_2 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(detect_pi_found_dqs_i_2_n_0),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(stg1_wr_done));
  (* SOFT_HLUTNM = "soft_lutpair352" *) 
  LUT4 #(
    .INIT(16'hFD57)) 
    \stg1_wr_rd_cnt[2]_i_1 
       (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(\stg1_wr_rd_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00A8AAA8AAA800A8)) 
    \stg1_wr_rd_cnt[3]_i_1 
       (.I0(\stg1_wr_rd_cnt[4]_i_2_n_0 ),
        .I1(\stg1_wr_rd_cnt[3]_i_2_n_0 ),
        .I2(D[3]),
        .I3(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .I4(\stg1_wr_rd_cnt[5]_i_2_n_0 ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .O(\stg1_wr_rd_cnt[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFD0FF)) 
    \stg1_wr_rd_cnt[3]_i_2 
       (.I0(complex_row0_rd_done),
        .I1(complex_row1_rd_done),
        .I2(complex_row1_wr_done),
        .I3(complex_row0_wr_done),
        .I4(wr_victim_inc),
        .O(\stg1_wr_rd_cnt[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h8288AAAA)) 
    \stg1_wr_rd_cnt[4]_i_1 
       (.I0(\stg1_wr_rd_cnt[4]_i_2_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I3(\stg1_wr_rd_cnt[5]_i_2_n_0 ),
        .I4(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555555545)) 
    \stg1_wr_rd_cnt[4]_i_2 
       (.I0(wr_lvl_start_reg_1),
        .I1(D[3]),
        .I2(\init_state_r[6]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\stg1_wr_rd_cnt[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAA2AAA)) 
    \stg1_wr_rd_cnt[4]_i_3 
       (.I0(complex_sample_cnt_inc_i_2_n_0),
        .I1(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I5(rdlvl_last_byte_done),
        .O(\stg1_wr_rd_cnt[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEBEAAAAAAAA)) 
    \stg1_wr_rd_cnt[5]_i_1 
       (.I0(\stg1_wr_rd_cnt[6]_i_2_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I2(\stg1_wr_rd_cnt[5]_i_2_n_0 ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I5(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair352" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \stg1_wr_rd_cnt[5]_i_2 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .O(\stg1_wr_rd_cnt[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair353" *) 
  LUT4 #(
    .INIT(16'hBEAA)) 
    \stg1_wr_rd_cnt[6]_i_1 
       (.I0(\stg1_wr_rd_cnt[6]_i_2_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I2(\stg1_wr_rd_cnt[8]_i_6_n_0 ),
        .I3(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00002022)) 
    \stg1_wr_rd_cnt[6]_i_2 
       (.I0(\stg1_wr_rd_cnt[3]_i_2_n_0 ),
        .I1(wr_lvl_start_reg_1),
        .I2(D[3]),
        .I3(stg1_wr_done),
        .I4(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair291" *) 
  LUT4 #(
    .INIT(16'hA208)) 
    \stg1_wr_rd_cnt[7]_i_1 
       (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I1(\stg1_wr_rd_cnt[8]_i_6_n_0 ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .O(\stg1_wr_rd_cnt[7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hD5FF)) 
    \stg1_wr_rd_cnt[8]_i_1 
       (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I1(D[3]),
        .I2(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .O(\stg1_wr_rd_cnt[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair291" *) 
  LUT5 #(
    .INIT(32'hA8AA0200)) 
    \stg1_wr_rd_cnt[8]_i_2 
       (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I3(\stg1_wr_rd_cnt[8]_i_6_n_0 ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .O(\stg1_wr_rd_cnt[8]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair351" *) 
  LUT4 #(
    .INIT(16'h0D00)) 
    \stg1_wr_rd_cnt[8]_i_3 
       (.I0(stg1_wr_done),
        .I1(D[3]),
        .I2(\num_refresh_reg[3]_0 ),
        .I3(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    \stg1_wr_rd_cnt[8]_i_4 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\stg1_wr_rd_cnt[8]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFF7FFFFFFFF)) 
    \stg1_wr_rd_cnt[8]_i_5 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(prech_req_posedge_r_i_3_n_0),
        .O(\stg1_wr_rd_cnt[8]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \stg1_wr_rd_cnt[8]_i_6 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .O(\stg1_wr_rd_cnt[8]_i_6_n_0 ));
  FDRE \stg1_wr_rd_cnt_reg[0] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[0]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[1] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[1]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[2] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[2]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[3] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[3]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[4] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[4]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[5] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[5]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[6] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[6]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[7] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[7]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[8] 
       (.C(CLK),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[8]_i_2_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .R(1'b0));
  FDRE wl_sm_start_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_dqs_asrt_r1),
        .Q(wl_sm_start),
        .R(init_calib_complete_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair365" *) 
  LUT4 #(
    .INIT(16'h00AE)) 
    \wr_done_victim_rotate.complex_row0_wr_done_i_1 
       (.I0(complex_row0_wr_done),
        .I1(rdlvl_stg1_done_r1_reg_0),
        .I2(\wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0 ),
        .I3(complex_row0_wr_done0),
        .O(\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair332" *) 
  LUT4 #(
    .INIT(16'hFBFF)) 
    \wr_done_victim_rotate.complex_row0_wr_done_i_2 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I3(wr_victim_inc_i_2_n_0),
        .O(\wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0011F011)) 
    \wr_done_victim_rotate.complex_row0_wr_done_i_3 
       (.I0(\wr_done_victim_rotate.complex_row0_wr_done_i_4_n_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),
        .I2(wr_victim_inc),
        .I3(D[3]),
        .I4(\complex_row_cnt_ocal[3]_i_4_n_0 ),
        .I5(\wr_done_victim_rotate.complex_row0_wr_done_i_5_n_0 ),
        .O(complex_row0_wr_done0));
  LUT5 #(
    .INIT(32'hFFFEFFFF)) 
    \wr_done_victim_rotate.complex_row0_wr_done_i_4 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I4(wr_victim_inc),
        .O(\wr_done_victim_rotate.complex_row0_wr_done_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \wr_done_victim_rotate.complex_row0_wr_done_i_5 
       (.I0(complex_byte_rd_done),
        .I1(prbs_rdlvl_done_pulse_reg_0),
        .I2(wr_lvl_start_reg_1),
        .O(\wr_done_victim_rotate.complex_row0_wr_done_i_5_n_0 ));
  FDRE \wr_done_victim_rotate.complex_row0_wr_done_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ),
        .Q(complex_row0_wr_done),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair365" *) 
  LUT4 #(
    .INIT(16'h00AE)) 
    \wr_done_victim_rotate.complex_row1_wr_done_i_1 
       (.I0(complex_row1_wr_done),
        .I1(complex_row0_wr_done),
        .I2(\wr_done_victim_rotate.complex_row0_wr_done_i_2_n_0 ),
        .I3(complex_row0_wr_done0),
        .O(\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ));
  FDRE \wr_done_victim_rotate.complex_row1_wr_done_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ),
        .Q(complex_row1_wr_done),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair399" *) 
  LUT3 #(
    .INIT(8'h54)) 
    wr_en_inferred__0_i_1
       (.I0(wr_en_inferred__0_i_1_0),
        .I1(calib_ctl_wren_reg_0),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\my_empty_reg[3] ));
  (* SOFT_HLUTNM = "soft_lutpair414" *) 
  LUT3 #(
    .INIT(8'h54)) 
    wr_en_inferred__0_i_1__0
       (.I0(wr_en_inferred__0_i_1__0_0),
        .I1(calib_ctl_wren_reg_0),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\my_empty_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair414" *) 
  LUT3 #(
    .INIT(8'h54)) 
    wr_en_inferred__0_i_1__1
       (.I0(wr_en_inferred__0_i_1__1_0),
        .I1(calib_ctl_wren_reg_0),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\my_empty_reg[3]_1 ));
  LUT4 #(
    .INIT(16'h00A8)) 
    wr_level_dqs_asrt_i_1
       (.I0(\en_cnt_div4.wrlvl_odt_i_2_n_0 ),
        .I1(wrlvl_active_r1),
        .I2(wr_level_dqs_asrt),
        .I3(wr_lvl_start_reg_1),
        .O(wr_level_dqs_asrt_i_1_n_0));
  FDRE wr_level_dqs_asrt_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_dqs_asrt),
        .Q(wr_level_dqs_asrt_r1),
        .R(1'b0));
  FDRE wr_level_dqs_asrt_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_dqs_asrt_i_1_n_0),
        .Q(wr_level_dqs_asrt),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000EA00)) 
    wr_lvl_start_i_1
       (.I0(wr_lvl_start_reg_0),
        .I1(dqs_asrt_cnt[1]),
        .I2(dqs_asrt_cnt[0]),
        .I3(wrlvl_active),
        .I4(wr_lvl_start_reg_1),
        .O(wr_lvl_start_i_1_n_0));
  FDRE wr_lvl_start_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_lvl_start_i_1_n_0),
        .Q(wr_lvl_start_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair398" *) 
  LUT3 #(
    .INIT(8'h54)) 
    \wr_ptr[2]_i_1__3 
       (.I0(\wr_ptr_timing_reg[0] ),
        .I1(calib_ctl_wren_reg_0),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(E));
  (* SOFT_HLUTNM = "soft_lutpair398" *) 
  LUT3 #(
    .INIT(8'h54)) 
    \wr_ptr[2]_i_1__4 
       (.I0(\wr_ptr_timing_reg[0]_1 ),
        .I1(calib_ctl_wren_reg_0),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\my_empty_reg[5] ));
  (* SOFT_HLUTNM = "soft_lutpair399" *) 
  LUT3 #(
    .INIT(8'h54)) 
    \wr_ptr[2]_i_1__5 
       (.I0(\wr_ptr_timing_reg[0]_2 ),
        .I1(calib_ctl_wren_reg_0),
        .I2(\wr_ptr_timing_reg[0]_0 ),
        .O(\my_empty_reg[5]_0 ));
  LUT6 #(
    .INIT(64'h0000040000000000)) 
    wr_victim_inc_i_1
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I3(wr_victim_inc_i_2_n_0),
        .I4(\one_rank.stg1_wr_done_reg_0 ),
        .I5(complex_row0_wr_done),
        .O(wr_victim_inc_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    wr_victim_inc_i_2
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .O(wr_victim_inc_i_2_n_0));
  FDRE wr_victim_inc_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_victim_inc_i_1_n_0),
        .Q(wr_victim_inc),
        .R(init_calib_complete_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00008000)) 
    wrcal_final_chk_i_1
       (.I0(\init_state_r[1]_i_1_n_0 ),
        .I1(\init_state_r[0]_i_1_n_0 ),
        .I2(\init_state_r[2]_i_1_n_0 ),
        .I3(wrcal_final_chk_i_2_n_0),
        .I4(\init_state_r[5]_i_1_n_0 ),
        .I5(wrcal_final_chk),
        .O(wrcal_final_chk_i_1_n_0));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAA2000)) 
    wrcal_final_chk_i_10
       (.I0(\init_state_r[4]_i_11_n_0 ),
        .I1(\complex_num_reads[3]_i_9_n_0 ),
        .I2(wr_victim_inc_i_2_n_0),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r[5]_i_24_n_0 ),
        .I5(\init_state_r[4]_i_9_n_0 ),
        .O(wrcal_final_chk_i_10_n_0));
  LUT6 #(
    .INIT(64'h77777777FFFFFF7F)) 
    wrcal_final_chk_i_11
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r[0]_i_29_n_0 ),
        .I3(\init_state_r[4]_i_9_n_0 ),
        .I4(\one_rank.stg1_wr_done_reg_0 ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(wrcal_final_chk_i_11_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    wrcal_final_chk_i_12
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .O(wrcal_final_chk_i_12_n_0));
  (* SOFT_HLUTNM = "soft_lutpair301" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    wrcal_final_chk_i_13
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(complex_oclkdelay_calib_start_int_i_2_n_0),
        .O(wrcal_final_chk_i_13_n_0));
  LUT6 #(
    .INIT(64'hBBABBBABBBBBBBAB)) 
    wrcal_final_chk_i_14
       (.I0(\init_state_r[5]_i_25_n_0 ),
        .I1(\init_state_r[3]_i_18_n_0 ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(wrcal_final_chk_i_21_n_0),
        .I4(\init_state_r[4]_i_23_n_0 ),
        .I5(\init_state_r[5]_i_39_n_0 ),
        .O(wrcal_final_chk_i_14_n_0));
  LUT6 #(
    .INIT(64'h888A8888AAAAAAAA)) 
    wrcal_final_chk_i_15
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(wrcal_final_chk_i_22_n_0),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r[4]_i_9_n_0 ),
        .I4(\init_state_r[3]_i_17_n_0 ),
        .I5(wrcal_final_chk_i_23_n_0),
        .O(wrcal_final_chk_i_15_n_0));
  LUT6 #(
    .INIT(64'h10005555FFFFFFFF)) 
    wrcal_final_chk_i_16
       (.I0(\init_state_r[5]_i_21_n_0 ),
        .I1(prbs_rdlvl_done_pulse0),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r[4]_i_9_n_0 ),
        .I4(prech_req_posedge_r_i_3_n_0),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(wrcal_final_chk_i_16_n_0));
  LUT6 #(
    .INIT(64'h1010111010101010)) 
    wrcal_final_chk_i_17
       (.I0(\init_state_r[5]_i_12_n_0 ),
        .I1(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I2(wrcal_final_chk_i_24_n_0),
        .I3(\init_state_r[2]_i_6_0 ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(pi_calib_done),
        .O(wrcal_final_chk_i_17_n_0));
  LUT6 #(
    .INIT(64'h0004000000000000)) 
    wrcal_final_chk_i_18
       (.I0(oclk_wr_cnt_reg[1]),
        .I1(oclk_wr_cnt_reg[0]),
        .I2(oclk_wr_cnt_reg[2]),
        .I3(oclk_wr_cnt_reg[3]),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[0] ),
        .O(wrcal_final_chk_i_18_n_0));
  (* SOFT_HLUTNM = "soft_lutpair297" *) 
  LUT3 #(
    .INIT(8'h01)) 
    wrcal_final_chk_i_19
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .O(wrcal_final_chk_i_19_n_0));
  LUT6 #(
    .INIT(64'h00F400F4000000F4)) 
    wrcal_final_chk_i_2
       (.I0(\init_state_r[4]_i_7_n_0 ),
        .I1(wrcal_final_chk_i_3_n_0),
        .I2(wrcal_final_chk_i_4_n_0),
        .I3(wrcal_final_chk_i_5_n_0),
        .I4(\init_state_r[3]_i_2_n_0 ),
        .I5(wrcal_final_chk_i_6_n_0),
        .O(wrcal_final_chk_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair366" *) 
  LUT4 #(
    .INIT(16'hAAAB)) 
    wrcal_final_chk_i_20
       (.I0(wrcal_resume_r),
        .I1(burst_addr_r_reg_0),
        .I2(prech_req_posedge_r_reg_0),
        .I3(wrlvl_byte_redo),
        .O(wrcal_final_chk_i_20_n_0));
  (* SOFT_HLUTNM = "soft_lutpair418" *) 
  LUT2 #(
    .INIT(4'h2)) 
    wrcal_final_chk_i_21
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .O(wrcal_final_chk_i_21_n_0));
  (* SOFT_HLUTNM = "soft_lutpair371" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    wrcal_final_chk_i_22
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(D[3]),
        .I3(\init_state_r_reg_n_0_[0] ),
        .O(wrcal_final_chk_i_22_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFBA00FFFF)) 
    wrcal_final_chk_i_23
       (.I0(prech_req_posedge_r_reg_0),
        .I1(complex_oclkdelay_calib_done_r1),
        .I2(D[3]),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(wrcal_final_chk_i_23_n_0));
  (* SOFT_HLUTNM = "soft_lutpair320" *) 
  LUT5 #(
    .INIT(32'hFF2F3F3F)) 
    wrcal_final_chk_i_24
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[0] ),
        .I3(reset_rd_addr_r1),
        .I4(\init_state_r_reg_n_0_[1] ),
        .O(wrcal_final_chk_i_24_n_0));
  LUT6 #(
    .INIT(64'hFFEFEEEEEEEEEEEE)) 
    wrcal_final_chk_i_3
       (.I0(wrcal_final_chk_i_7_n_0),
        .I1(\init_state_r[4]_i_16_n_0 ),
        .I2(\init_state_r[5]_i_14_n_0 ),
        .I3(\init_state_r[4]_i_17_n_0 ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(wrcal_final_chk_i_3_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF45454500)) 
    wrcal_final_chk_i_4
       (.I0(\init_state_r[5]_i_25_n_0 ),
        .I1(wrcal_final_chk_i_8_n_0),
        .I2(wrcal_final_chk_i_9_n_0),
        .I3(wrcal_final_chk_i_10_n_0),
        .I4(wrcal_final_chk_i_11_n_0),
        .I5(\init_state_r[4]_i_2_n_0 ),
        .O(wrcal_final_chk_i_4_n_0));
  LUT6 #(
    .INIT(64'hFFFF00F1FFFFFFFF)) 
    wrcal_final_chk_i_5
       (.I0(wrcal_final_chk_i_12_n_0),
        .I1(\init_state_r[6]_i_4_n_0 ),
        .I2(init_state_r),
        .I3(\init_state_r[6]_i_3_n_0 ),
        .I4(wrcal_final_chk_i_13_n_0),
        .I5(burst_addr_r_reg_0),
        .O(wrcal_final_chk_i_5_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF54)) 
    wrcal_final_chk_i_6
       (.I0(wrcal_final_chk_i_14_n_0),
        .I1(wrcal_final_chk_i_15_n_0),
        .I2(wrcal_final_chk_i_16_n_0),
        .I3(\init_state_r[3]_i_6_n_0 ),
        .I4(wrcal_final_chk_i_17_n_0),
        .I5(\init_state_r[3]_i_3_n_0 ),
        .O(wrcal_final_chk_i_6_n_0));
  LUT5 #(
    .INIT(32'hFFAEAAAA)) 
    wrcal_final_chk_i_7
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(cnt_cmd_done_r),
        .I2(rdlvl_stg1_done_r1_reg_0),
        .I3(reset_rd_addr_r1),
        .I4(\init_state_r[6]_i_2_n_0 ),
        .O(wrcal_final_chk_i_7_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF5454FF54)) 
    wrcal_final_chk_i_8
       (.I0(\init_state_r[5]_i_12_n_0 ),
        .I1(\init_state_r[5]_i_44_n_0 ),
        .I2(wrcal_final_chk_i_18_n_0),
        .I3(wrcal_final_chk_i_19_n_0),
        .I4(\init_state_r[4]_i_24_n_0 ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(wrcal_final_chk_i_8_n_0));
  LUT6 #(
    .INIT(64'hFFFFEFFFFEFEEEFE)) 
    wrcal_final_chk_i_9
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(pi_phase_locked_all_r3),
        .I4(pi_phase_locked_all_r4),
        .I5(wrcal_final_chk_i_20_n_0),
        .O(wrcal_final_chk_i_9_n_0));
  FDRE wrcal_final_chk_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_final_chk_i_1_n_0),
        .Q(wrcal_final_chk),
        .R(init_calib_complete_reg_0));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    wrcal_rd_wait_i_1
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(init_state_r),
        .O(wrcal_rd_wait_i_1_n_0));
  FDRE wrcal_rd_wait_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_rd_wait_i_1_n_0),
        .Q(wrcal_rd_wait),
        .R(init_calib_complete_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair392" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \wrcal_reads[0]_i_1 
       (.I0(wrcal_reads),
        .I1(\wrcal_reads_reg_n_0_[0] ),
        .O(\wrcal_reads[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair393" *) 
  LUT3 #(
    .INIT(8'hF9)) 
    \wrcal_reads[1]_i_1 
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\wrcal_reads_reg_n_0_[1] ),
        .I2(wrcal_reads),
        .O(\wrcal_reads[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair308" *) 
  LUT4 #(
    .INIT(16'hFFE1)) 
    \wrcal_reads[2]_i_1 
       (.I0(\wrcal_reads_reg_n_0_[1] ),
        .I1(\wrcal_reads_reg_n_0_[0] ),
        .I2(\wrcal_reads_reg_n_0_[2] ),
        .I3(wrcal_reads),
        .O(\wrcal_reads[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair308" *) 
  LUT5 #(
    .INIT(32'hFFFFFE01)) 
    \wrcal_reads[3]_i_1 
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\wrcal_reads_reg_n_0_[1] ),
        .I2(\wrcal_reads_reg_n_0_[2] ),
        .I3(\wrcal_reads_reg_n_0_[3] ),
        .I4(wrcal_reads),
        .O(\wrcal_reads[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFE0001)) 
    \wrcal_reads[4]_i_1 
       (.I0(\wrcal_reads_reg_n_0_[2] ),
        .I1(\wrcal_reads_reg_n_0_[1] ),
        .I2(\wrcal_reads_reg_n_0_[0] ),
        .I3(\wrcal_reads_reg_n_0_[3] ),
        .I4(\wrcal_reads_reg_n_0_[4] ),
        .I5(wrcal_reads),
        .O(\wrcal_reads[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair392" *) 
  LUT3 #(
    .INIT(8'hF6)) 
    \wrcal_reads[5]_i_1 
       (.I0(\wrcal_reads[7]_i_7_n_0 ),
        .I1(\wrcal_reads_reg_n_0_[5] ),
        .I2(wrcal_reads),
        .O(\wrcal_reads[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair307" *) 
  LUT4 #(
    .INIT(16'hFFD2)) 
    \wrcal_reads[6]_i_1 
       (.I0(\wrcal_reads[7]_i_7_n_0 ),
        .I1(\wrcal_reads_reg_n_0_[5] ),
        .I2(\wrcal_reads_reg_n_0_[6] ),
        .I3(wrcal_reads),
        .O(\wrcal_reads[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAABAA)) 
    \wrcal_reads[7]_i_1 
       (.I0(wr_lvl_start_reg_1),
        .I1(\wrcal_reads[7]_i_4_n_0 ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[0] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(wrcal_reads05_out));
  LUT3 #(
    .INIT(8'hFE)) 
    \wrcal_reads[7]_i_2 
       (.I0(\wrcal_reads[7]_i_5_n_0 ),
        .I1(\wrcal_reads_reg_n_0_[0] ),
        .I2(wrcal_reads),
        .O(\wrcal_reads[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair307" *) 
  LUT5 #(
    .INIT(32'hFFFFFD02)) 
    \wrcal_reads[7]_i_3 
       (.I0(\wrcal_reads[7]_i_7_n_0 ),
        .I1(\wrcal_reads_reg_n_0_[6] ),
        .I2(\wrcal_reads_reg_n_0_[5] ),
        .I3(\wrcal_reads_reg_n_0_[7] ),
        .I4(wrcal_reads),
        .O(\wrcal_reads[7]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair379" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \wrcal_reads[7]_i_4 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .O(\wrcal_reads[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \wrcal_reads[7]_i_5 
       (.I0(\wrcal_reads_reg_n_0_[3] ),
        .I1(\wrcal_reads_reg_n_0_[1] ),
        .I2(\wrcal_reads[7]_i_8_n_0 ),
        .I3(\wrcal_reads_reg_n_0_[2] ),
        .I4(\wrcal_reads_reg_n_0_[7] ),
        .I5(\wrcal_reads_reg_n_0_[4] ),
        .O(\wrcal_reads[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \wrcal_reads[7]_i_6 
       (.I0(\wrcal_reads[7]_i_4_n_0 ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(wrcal_reads0),
        .O(wrcal_reads));
  LUT5 #(
    .INIT(32'h00000001)) 
    \wrcal_reads[7]_i_7 
       (.I0(\wrcal_reads_reg_n_0_[3] ),
        .I1(\wrcal_reads_reg_n_0_[0] ),
        .I2(\wrcal_reads_reg_n_0_[1] ),
        .I3(\wrcal_reads_reg_n_0_[2] ),
        .I4(\wrcal_reads_reg_n_0_[4] ),
        .O(\wrcal_reads[7]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair372" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \wrcal_reads[7]_i_8 
       (.I0(\wrcal_reads_reg_n_0_[5] ),
        .I1(\wrcal_reads_reg_n_0_[6] ),
        .O(\wrcal_reads[7]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair393" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \wrcal_reads[7]_i_9 
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\wrcal_reads[7]_i_5_n_0 ),
        .O(wrcal_reads0));
  FDRE \wrcal_reads_reg[0] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[0]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[0] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[1] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[1]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[1] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[2] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[2]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[2] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[3] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[3]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[3] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[4] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[4]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[4] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[5] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[5]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[5] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[6] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[6]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[6] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[7] 
       (.C(CLK),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[7]_i_3_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[7] ),
        .R(wrcal_reads05_out));
  FDRE wrcal_resume_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_resume_w),
        .Q(wrcal_resume_r),
        .R(1'b0));
  FDRE wrcal_sanity_chk_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_final_chk),
        .Q(wrcal_sanity_chk),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[4]_srl5 " *) 
  SRL16E \wrcal_start_dly_r_reg[4]_srl5 
       (.A0(1'b0),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(wrcal_start_pre),
        .Q(\wrcal_start_dly_r_reg[4]_srl5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair293" *) 
  LUT5 #(
    .INIT(32'h01000200)) 
    \wrcal_start_dly_r_reg[4]_srl5_i_1 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\wrcal_reads[7]_i_4_n_0 ),
        .I3(\init_state_r_reg_n_0_[0] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .O(wrcal_start_pre));
  FDRE \wrcal_start_dly_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrcal_start_dly_r_reg[4]_srl5_n_0 ),
        .Q(wrcal_start_dly_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h000E)) 
    wrcal_start_i_1
       (.I0(wrcal_start_reg_0),
        .I1(wrcal_start_dly_r),
        .I2(wrlvl_byte_redo),
        .I3(\num_refresh_reg[3]_0 ),
        .O(wrcal_start_i_1_n_0));
  FDRE wrcal_start_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_start_i_1_n_0),
        .Q(wrcal_start_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair423" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wrcal_wr_cnt[0]_i_1 
       (.I0(wrcal_wr_cnt_reg[0]),
        .O(\wrcal_wr_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair423" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wrcal_wr_cnt[1]_i_1 
       (.I0(wrcal_wr_cnt_reg[1]),
        .I1(wrcal_wr_cnt_reg[0]),
        .O(\wrcal_wr_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair407" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wrcal_wr_cnt[2]_i_1 
       (.I0(wrcal_wr_cnt_reg[2]),
        .I1(wrcal_wr_cnt_reg[0]),
        .I2(wrcal_wr_cnt_reg[1]),
        .O(wrcal_wr_cnt0[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFF444444F4)) 
    \wrcal_wr_cnt[3]_i_1 
       (.I0(\wrcal_wr_cnt[3]_i_4_n_0 ),
        .I1(prech_req_posedge_r_i_3_n_0),
        .I2(\wrcal_wr_cnt[3]_i_5_n_0 ),
        .I3(wrcal_wr_cnt_reg[2]),
        .I4(wrcal_wr_cnt_reg[3]),
        .I5(wr_lvl_start_reg_1),
        .O(\wrcal_wr_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \wrcal_wr_cnt[3]_i_2 
       (.I0(pi_dqs_found_start_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\wrcal_wr_cnt[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair328" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wrcal_wr_cnt[3]_i_3 
       (.I0(wrcal_wr_cnt_reg[3]),
        .I1(wrcal_wr_cnt_reg[2]),
        .I2(wrcal_wr_cnt_reg[1]),
        .I3(wrcal_wr_cnt_reg[0]),
        .O(wrcal_wr_cnt0[3]));
  (* SOFT_HLUTNM = "soft_lutpair300" *) 
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    \wrcal_wr_cnt[3]_i_4 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .O(\wrcal_wr_cnt[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair407" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \wrcal_wr_cnt[3]_i_5 
       (.I0(wrcal_wr_cnt_reg[1]),
        .I1(wrcal_wr_cnt_reg[0]),
        .O(\wrcal_wr_cnt[3]_i_5_n_0 ));
  FDRE \wrcal_wr_cnt_reg[0] 
       (.C(CLK),
        .CE(\wrcal_wr_cnt[3]_i_2_n_0 ),
        .D(\wrcal_wr_cnt[0]_i_1_n_0 ),
        .Q(wrcal_wr_cnt_reg[0]),
        .R(\wrcal_wr_cnt[3]_i_1_n_0 ));
  FDRE \wrcal_wr_cnt_reg[1] 
       (.C(CLK),
        .CE(\wrcal_wr_cnt[3]_i_2_n_0 ),
        .D(\wrcal_wr_cnt[1]_i_1_n_0 ),
        .Q(wrcal_wr_cnt_reg[1]),
        .R(\wrcal_wr_cnt[3]_i_1_n_0 ));
  FDSE \wrcal_wr_cnt_reg[2] 
       (.C(CLK),
        .CE(\wrcal_wr_cnt[3]_i_2_n_0 ),
        .D(wrcal_wr_cnt0[2]),
        .Q(wrcal_wr_cnt_reg[2]),
        .S(\wrcal_wr_cnt[3]_i_1_n_0 ));
  FDRE \wrcal_wr_cnt_reg[3] 
       (.C(CLK),
        .CE(\wrcal_wr_cnt[3]_i_2_n_0 ),
        .D(wrcal_wr_cnt0[3]),
        .Q(wrcal_wr_cnt_reg[3]),
        .R(\wrcal_wr_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair361" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[121]_i_1 
       (.I0(first_wrcal_pat_r),
        .I1(D[3]),
        .O(\wrdq_div2_4to1_rdlvl_first.phy_wrdata[121]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair362" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_2 
       (.I0(first_wrcal_pat_r),
        .I1(D[3]),
        .O(\wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair360" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[25]_i_1 
       (.I0(first_rdlvl_pat_r),
        .I1(D[3]),
        .O(\wrdq_div2_4to1_rdlvl_first.phy_wrdata[25]_i_1_n_0 ));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[109] 
       (.C(CLK),
        .CE(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0 ),
        .D(D[2]),
        .Q(phy_wrdata[109]),
        .R(1'b0));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[111] 
       (.C(CLK),
        .CE(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0 ),
        .D(D[3]),
        .Q(phy_wrdata[111]),
        .R(1'b0));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[121] 
       (.C(CLK),
        .CE(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0 ),
        .D(\wrdq_div2_4to1_rdlvl_first.phy_wrdata[121]_i_1_n_0 ),
        .Q(phy_wrdata[121]),
        .R(1'b0));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[123] 
       (.C(CLK),
        .CE(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0 ),
        .D(D[4]),
        .Q(phy_wrdata[123]),
        .R(1'b0));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126] 
       (.C(CLK),
        .CE(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0 ),
        .D(\wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_2_n_0 ),
        .Q(phy_wrdata[126]),
        .R(1'b0));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[13] 
       (.C(CLK),
        .CE(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0 ),
        .D(D[0]),
        .Q(phy_wrdata[13]),
        .R(1'b0));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[25] 
       (.C(CLK),
        .CE(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0 ),
        .D(\wrdq_div2_4to1_rdlvl_first.phy_wrdata[25]_i_1_n_0 ),
        .Q(phy_wrdata[25]),
        .R(1'b0));
  FDRE \wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[46] 
       (.C(CLK),
        .CE(\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126]_0 ),
        .D(D[1]),
        .Q(phy_wrdata[46]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000007F7F7F00)) 
    write_calib_i_1
       (.I0(done_dqs_tap_inc),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ),
        .I3(wrlvl_active_r1),
        .I4(phy_write_calib),
        .I5(\num_refresh_reg[3]_0 ),
        .O(write_calib_i_1_n_0));
  FDRE write_calib_reg
       (.C(CLK),
        .CE(1'b1),
        .D(write_calib_i_1_n_0),
        .Q(phy_write_calib),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000005540)) 
    wrlvl_active_i_1
       (.I0(wr_lvl_start_reg_1),
        .I1(wrlvl_odt),
        .I2(\en_cnt_div4.wrlvl_odt_i_2_n_0 ),
        .I3(wrlvl_active),
        .I4(done_dqs_tap_inc),
        .I5(wrlvl_rank_done),
        .O(wrlvl_active_i_1_n_0));
  FDRE wrlvl_active_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_active),
        .Q(wrlvl_active_r1),
        .R(1'b0));
  FDRE wrlvl_active_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_active_i_1_n_0),
        .Q(wrlvl_active),
        .R(1'b0));
  FDRE wrlvl_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_done_r),
        .Q(wrlvl_done_r1),
        .R(1'b0));
  FDRE wrlvl_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_done_r_reg_0),
        .Q(wrlvl_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000004454)) 
    wrlvl_final_if_rst_i_1
       (.I0(\num_refresh_reg[3]_0 ),
        .I1(wrlvl_final_if_rst),
        .I2(wrlvl_done_r),
        .I3(wrlvl_final_if_rst_i_2_n_0),
        .I4(\num_refresh[3]_i_7_n_0 ),
        .I5(\wrcal_wr_cnt[3]_i_2_n_0 ),
        .O(wrlvl_final_if_rst_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFD)) 
    wrlvl_final_if_rst_i_2
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[0] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\num_refresh[3]_i_5_n_0 ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(wrlvl_final_if_rst_i_2_n_0));
  FDRE wrlvl_final_if_rst_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_final_if_rst_i_1_n_0),
        .Q(wrlvl_final_if_rst),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000AA20)) 
    wrlvl_odt_ctl_i_1
       (.I0(wrlvl_odt_ctl_i_2_n_0),
        .I1(wrlvl_rank_done_r1),
        .I2(wrlvl_rank_done),
        .I3(wrlvl_odt_ctl),
        .I4(\num_refresh_reg[3]_0 ),
        .O(wrlvl_odt_ctl_i_1_n_0));
  LUT6 #(
    .INIT(64'hFBFFFBFFFBFFFFFF)) 
    wrlvl_odt_ctl_i_2
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(prech_req_posedge_r_i_3_n_0),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_7_n_0 ),
        .I5(init_state_r1[3]),
        .O(wrlvl_odt_ctl_i_2_n_0));
  FDRE wrlvl_odt_ctl_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_odt_ctl_i_1_n_0),
        .Q(wrlvl_odt_ctl),
        .R(1'b0));
  FDRE wrlvl_rank_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_rank_done),
        .Q(wrlvl_rank_done_r1),
        .R(1'b0));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r6_reg_srl5 " *) 
  SRL16E wrlvl_rank_done_r6_reg_srl5
       (.A0(1'b0),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(wrlvl_rank_done_r1),
        .Q(wrlvl_rank_done_r6_reg_srl5_n_0));
  FDRE wrlvl_rank_done_r7_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_rank_done_r6_reg_srl5_n_0),
        .Q(wrlvl_rank_done_r7),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_rdlvl
   (\rd_mux_sel_r_reg[0]_0 ,
    new_cnt_cpt_r_reg_0,
    samp_edge_cnt0_en_r,
    idelay_ce_int,
    idelay_inc_int,
    rdlvl_prech_req,
    pi_fine_dly_dec_done_reg_0,
    pi_cnt_dec_reg_0,
    D,
    rdlvl_stg1_rank_done,
    rdlvl_last_byte_done,
    rdlvl_pi_incdec,
    \calib_sel_reg[1] ,
    \calib_sel_reg[1]_0 ,
    \calib_sel_reg[1]_1 ,
    pi_en_stg2_f_reg_0,
    pi_stg2_f_incdec_reg_0,
    pi_stg2_load_reg_0,
    rdlvl_stg1_done_int_reg_0,
    p_1_in,
    \cal1_cnt_cpt_r_reg[0]_0 ,
    pi_calib_done_r1_reg,
    \po_stg2_wrcal_cnt_reg[1] ,
    \po_stg2_wrcal_cnt_reg[0] ,
    reset_if_reg,
    COUNTERLOADVAL,
    \pi_stg2_reg_l_reg[5]_0 ,
    \rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 ,
    CLK,
    \gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    found_first_edge_r_reg_0,
    mpr_rdlvl_start_r_reg_0,
    rdlvl_stg1_start_r_reg_0,
    E,
    dqs_po_dec_done_r1_reg_0,
    \samp_edge_cnt1_r_reg[0]_0 ,
    in0,
    \pi_dqs_found_lanes_r1_reg[3] ,
    tempmon_pi_f_en_r,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    \pi_dqs_found_lanes_r1_reg[3]_1 ,
    calib_zero_inputs,
    tempmon_pi_f_inc_r,
    \idelay_tap_cnt_r_reg[0][1][1]_0 ,
    pi_dqs_found_done,
    \init_state_r[2]_i_17 ,
    po_cnt_dec_reg,
    \pi_rdval_cnt_reg[5]_0 ,
    \idelay_tap_cnt_r_reg[0][0][0]_0 ,
    Q,
    prech_done,
    store_sr_req_r_reg_0,
    pi_calib_done,
    first_rdlvl_pat_r,
    first_wrcal_pat_r,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0] ,
    reset_if,
    reset_if_reg_0,
    reset_if_r9,
    reset_if_reg_1,
    \idelay_tap_cnt_r_reg[0][1][4]_0 ,
    \tap_cnt_cpt_r_reg[5]_0 ,
    \cnt_shift_r_reg[0]_0 ,
    \wait_cnt_r_reg[0]_0 );
  output \rd_mux_sel_r_reg[0]_0 ;
  output new_cnt_cpt_r_reg_0;
  output samp_edge_cnt0_en_r;
  output idelay_ce_int;
  output idelay_inc_int;
  output rdlvl_prech_req;
  output pi_fine_dly_dec_done_reg_0;
  output pi_cnt_dec_reg_0;
  output [4:0]D;
  output rdlvl_stg1_rank_done;
  output rdlvl_last_byte_done;
  output rdlvl_pi_incdec;
  output \calib_sel_reg[1] ;
  output \calib_sel_reg[1]_0 ;
  output \calib_sel_reg[1]_1 ;
  output pi_en_stg2_f_reg_0;
  output pi_stg2_f_incdec_reg_0;
  output pi_stg2_load_reg_0;
  output rdlvl_stg1_done_int_reg_0;
  output p_1_in;
  output \cal1_cnt_cpt_r_reg[0]_0 ;
  output pi_calib_done_r1_reg;
  output \po_stg2_wrcal_cnt_reg[1] ;
  output \po_stg2_wrcal_cnt_reg[0] ;
  output reset_if_reg;
  output [5:0]COUNTERLOADVAL;
  output [5:0]\pi_stg2_reg_l_reg[5]_0 ;
  input [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 ;
  input CLK;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  input found_first_edge_r_reg_0;
  input mpr_rdlvl_start_r_reg_0;
  input rdlvl_stg1_start_r_reg_0;
  input [0:0]E;
  input dqs_po_dec_done_r1_reg_0;
  input \samp_edge_cnt1_r_reg[0]_0 ;
  input in0;
  input \pi_dqs_found_lanes_r1_reg[3] ;
  input tempmon_pi_f_en_r;
  input \pi_dqs_found_lanes_r1_reg[3]_0 ;
  input \pi_dqs_found_lanes_r1_reg[3]_1 ;
  input calib_zero_inputs;
  input tempmon_pi_f_inc_r;
  input \idelay_tap_cnt_r_reg[0][1][1]_0 ;
  input pi_dqs_found_done;
  input \init_state_r[2]_i_17 ;
  input po_cnt_dec_reg;
  input [5:0]\pi_rdval_cnt_reg[5]_0 ;
  input \idelay_tap_cnt_r_reg[0][0][0]_0 ;
  input [1:0]Q;
  input prech_done;
  input store_sr_req_r_reg_0;
  input pi_calib_done;
  input first_rdlvl_pat_r;
  input first_wrcal_pat_r;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  input reset_if;
  input reset_if_reg_0;
  input reset_if_r9;
  input reset_if_reg_1;
  input [0:0]\idelay_tap_cnt_r_reg[0][1][4]_0 ;
  input [0:0]\tap_cnt_cpt_r_reg[5]_0 ;
  input [0:0]\cnt_shift_r_reg[0]_0 ;
  input [0:0]\wait_cnt_r_reg[0]_0 ;

  wire CLK;
  wire [5:0]COUNTERLOADVAL;
  wire [4:0]D;
  wire [0:0]E;
  wire \FSM_onehot_cal1_state_r[10]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[11]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[13]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[14]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[14]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[15]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[15]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[15]_i_3_n_0 ;
  wire \FSM_onehot_cal1_state_r[16]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[16]_i_3_n_0 ;
  wire \FSM_onehot_cal1_state_r[16]_i_4_n_0 ;
  wire \FSM_onehot_cal1_state_r[1]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[20]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[21]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[21]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[21]_i_3_n_0 ;
  wire \FSM_onehot_cal1_state_r[22]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[22]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[29]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[2]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_10_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_11_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_12_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_13_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_3_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_4_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_5_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_6_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_7_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_9_n_0 ;
  wire \FSM_onehot_cal1_state_r[4]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[5]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[5]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[6]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[6]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[7]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[9]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[12] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[15] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[16] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[1] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[22] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[29] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[31] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[34] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[3] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[7] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[8] ;
  wire [1:0]Q;
  wire [0:0]cal1_cnt_cpt_r;
  wire \cal1_cnt_cpt_r[0]_i_1_n_0 ;
  wire \cal1_cnt_cpt_r_reg[0]_0 ;
  wire \cal1_cnt_cpt_r_reg_n_0_[0] ;
  wire cal1_dlyce_cpt_r;
  wire cal1_dlyce_cpt_r_reg_n_0;
  wire cal1_dlyinc_cpt_r;
  wire cal1_dlyinc_cpt_r_reg_n_0;
  wire cal1_dq_idel_ce;
  wire cal1_dq_idel_inc;
  wire cal1_prech_req_r;
  wire cal1_prech_req_r__0;
  wire \cal1_state_r1[0]_i_1_n_0 ;
  wire \cal1_state_r1[0]_i_2_n_0 ;
  wire \cal1_state_r1[1]_i_1_n_0 ;
  wire \cal1_state_r1[1]_i_2_n_0 ;
  wire \cal1_state_r1[1]_i_3_n_0 ;
  wire \cal1_state_r1[2]_i_1_n_0 ;
  wire \cal1_state_r1[2]_i_2_n_0 ;
  wire \cal1_state_r1[3]_i_1_n_0 ;
  wire \cal1_state_r1[3]_i_2_n_0 ;
  wire \cal1_state_r1[3]_i_3_n_0 ;
  wire \cal1_state_r1[4]_i_1_n_0 ;
  wire \cal1_state_r1[5]_i_1_n_0 ;
  wire \cal1_state_r1_reg_n_0_[0] ;
  wire \cal1_state_r1_reg_n_0_[1] ;
  wire \cal1_state_r1_reg_n_0_[2] ;
  wire \cal1_state_r1_reg_n_0_[3] ;
  wire \cal1_state_r1_reg_n_0_[4] ;
  wire \cal1_state_r1_reg_n_0_[5] ;
  wire cal1_wait_cnt_en_r;
  wire cal1_wait_cnt_en_r0;
  wire cal1_wait_cnt_en_r_i_2_n_0;
  wire \cal1_wait_cnt_r[4]_i_1_n_0 ;
  wire [4:0]cal1_wait_cnt_r_reg;
  wire cal1_wait_r;
  wire cal1_wait_r_i_1_n_0;
  wire \calib_sel_reg[1] ;
  wire \calib_sel_reg[1]_0 ;
  wire \calib_sel_reg[1]_1 ;
  wire calib_zero_inputs;
  wire [5:0]cnt_idel_dec_cpt_r;
  wire [4:0]cnt_idel_dec_cpt_r1;
  wire \cnt_idel_dec_cpt_r[0]_i_2_n_0 ;
  wire \cnt_idel_dec_cpt_r[0]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[1]_i_2_n_0 ;
  wire \cnt_idel_dec_cpt_r[1]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[1]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_11_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_12_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_13_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_14_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_15_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_5_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_6_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_7_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_8_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_9_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_2_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_5_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_6_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_10_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_11_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_12_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_13_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_14_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_5_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_6_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_7_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_9_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_1_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_5_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_6_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_7_n_0 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_0 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_1 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_2 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_3 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_4 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_5 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_6 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_0 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_1 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_2 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_3 ;
  wire \cnt_idel_dec_cpt_r_reg[4]_i_2_n_1 ;
  wire \cnt_idel_dec_cpt_r_reg[4]_i_2_n_3 ;
  wire \cnt_idel_dec_cpt_r_reg[4]_i_8_n_3 ;
  wire \cnt_idel_dec_cpt_r_reg[4]_i_8_n_6 ;
  wire \cnt_idel_dec_cpt_r_reg[4]_i_8_n_7 ;
  wire \cnt_idel_dec_cpt_r_reg[5]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[0] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[1] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[2] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[3] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[4] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[5] ;
  wire [3:0]cnt_shift_r_reg;
  wire [0:0]\cnt_shift_r_reg[0]_0 ;
  wire detect_edge_done_r;
  wire detect_edge_done_r_i_1_n_0;
  wire detect_edge_done_r_i_2_n_0;
  wire [3:0]done_cnt;
  wire done_cnt1;
  wire \done_cnt[0]_i_1_n_0 ;
  wire \done_cnt[1]_i_1_n_0 ;
  wire \done_cnt[2]_i_1_n_0 ;
  wire \done_cnt[3]_i_1_n_0 ;
  wire \done_cnt[3]_i_3_n_0 ;
  wire dqs_po_dec_done_r1;
  wire dqs_po_dec_done_r1_reg_0;
  wire dqs_po_dec_done_r2;
  wire fine_dly_dec_done_r1;
  wire fine_dly_dec_done_r1_i_1_n_0;
  wire fine_dly_dec_done_r1_i_2_n_0;
  wire fine_dly_dec_done_r2;
  wire \first_edge_taps_r[5]_i_1_n_0 ;
  wire \first_edge_taps_r[5]_i_2_n_0 ;
  wire \first_edge_taps_r[5]_i_3_n_0 ;
  wire \first_edge_taps_r_reg_n_0_[0] ;
  wire \first_edge_taps_r_reg_n_0_[1] ;
  wire \first_edge_taps_r_reg_n_0_[2] ;
  wire \first_edge_taps_r_reg_n_0_[3] ;
  wire \first_edge_taps_r_reg_n_0_[4] ;
  wire \first_edge_taps_r_reg_n_0_[5] ;
  wire first_rdlvl_pat_r;
  wire first_wrcal_pat_r;
  wire found_edge_r_i_1_n_0;
  wire found_edge_r_i_2_n_0;
  wire found_edge_r_reg_n_0;
  wire found_first_edge_r_i_1_n_0;
  wire found_first_edge_r_reg_0;
  wire found_first_edge_r_reg_n_0;
  wire found_second_edge_r_i_1_n_0;
  wire found_second_edge_r_reg_n_0;
  wire found_stable_eye_last_r;
  wire found_stable_eye_last_r_i_1_n_0;
  wire found_stable_eye_r_i_1_n_0;
  wire found_stable_eye_r_i_2_n_0;
  wire found_stable_eye_r_reg_n_0;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_139 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_155 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_163 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_187 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_171 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_147 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_179 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_195 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_75 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_107 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_131 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_123 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_91 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_99 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_115 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_83 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_140 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_156 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_164 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_188 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_172 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_148 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_180 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_196 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_76 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_108 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_132 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_124 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_92 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_100 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_116 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_84 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_141 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_157 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_165 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_189 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_173 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_149 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_181 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_197 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_77 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_109 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_133 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_125 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_93 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_101 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_117 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_85 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_142 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_158 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_166 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_190 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_174 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_150 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_182 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_198 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_78 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_110 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_134 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_126 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_94 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_102 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_118 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_86 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_143 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_159 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_167 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_191 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_175 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_151 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_183 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_199 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_79 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_111 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_135 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_127 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_95 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_103 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_119 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_87 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_144 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_160 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_168 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_192 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_176 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_152 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_184 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_200 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_80 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_112 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_136 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_128 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_96 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_104 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_120 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_88 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_145 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_161 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_169 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_193 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_177 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_153 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_185 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_201 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_81 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_113 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_137 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_129 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_97 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_105 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_121 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_89 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_146 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_162 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_170 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_194 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_178 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_154 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_186 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_202 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_82 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_114 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_138 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_130 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_98 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_106 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_122 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_90 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ;
  wire \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ;
  wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 ;
  wire \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ;
  wire \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ;
  wire \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4_n_0 ;
  wire \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ;
  wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ;
  wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ;
  wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ;
  wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 ;
  wire \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ;
  wire \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ;
  wire \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ;
  wire \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ;
  wire \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0 ;
  wire \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ;
  wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ;
  wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 ;
  wire \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ;
  wire \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0 ;
  wire \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ;
  wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ;
  wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 ;
  wire \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ;
  wire \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0 ;
  wire \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ;
  wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ;
  wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 ;
  wire \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ;
  wire \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0 ;
  wire \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ;
  wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ;
  wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 ;
  wire \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ;
  wire \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0 ;
  wire \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ;
  wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ;
  wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 ;
  wire \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ;
  wire \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0 ;
  wire \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ;
  wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ;
  wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 ;
  wire \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ;
  wire \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2_n_0 ;
  wire \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0 ;
  wire \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ;
  wire idel_adj_inc_i_1_n_0;
  wire idel_adj_inc_reg_n_0;
  wire [4:0]idel_dec_cnt;
  wire \idel_dec_cnt[3]_i_2_n_0 ;
  wire \idel_dec_cnt[4]_i_1_n_0 ;
  wire \idel_dec_cnt[4]_i_3_n_0 ;
  wire \idel_dec_cnt[4]_i_4_n_0 ;
  wire \idel_dec_cnt[4]_i_5_n_0 ;
  wire \idel_dec_cnt_reg_n_0_[0] ;
  wire \idel_dec_cnt_reg_n_0_[1] ;
  wire \idel_dec_cnt_reg_n_0_[2] ;
  wire \idel_dec_cnt_reg_n_0_[3] ;
  wire \idel_dec_cnt_reg_n_0_[4] ;
  wire idel_mpr_pat_detect_r;
  wire idel_pat0_data_match_r0;
  wire idel_pat0_match_fall0_and_r;
  wire idel_pat0_match_fall1_and_r;
  wire idel_pat0_match_fall2_and_r;
  wire idel_pat0_match_fall3_and_r;
  wire idel_pat0_match_rise0_and_r;
  wire idel_pat0_match_rise1_and_r;
  wire idel_pat0_match_rise2_and_r;
  wire idel_pat0_match_rise3_and_r;
  wire [7:0]idel_pat0_match_rise3_r;
  wire idel_pat1_data_match_r0;
  wire idel_pat1_match_fall0_and_r;
  wire idel_pat1_match_fall1_and_r;
  wire idel_pat1_match_fall2_and_r;
  wire idel_pat1_match_fall3_and_r;
  wire idel_pat1_match_rise0_and_r;
  wire idel_pat1_match_rise1_and_r;
  wire [7:0]idel_pat1_match_rise1_r;
  wire idel_pat1_match_rise2_and_r;
  wire idel_pat1_match_rise3_and_r;
  wire idel_pat_detect_valid_r_i_1_n_0;
  wire idel_pat_detect_valid_r_reg_n_0;
  wire idelay_ce_int;
  wire idelay_inc_int;
  wire [4:0]idelay_tap_cnt_r;
  wire \idelay_tap_cnt_r[0][0][4]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][0][4]_i_3_n_0 ;
  wire \idelay_tap_cnt_r[0][1][0]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][1][1]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][1][2]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][1][3]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][1][4]_i_2_n_0 ;
  wire \idelay_tap_cnt_r[0][1][4]_i_3_n_0 ;
  wire \idelay_tap_cnt_r_reg[0][0][0]_0 ;
  wire \idelay_tap_cnt_r_reg[0][1][1]_0 ;
  wire [0:0]\idelay_tap_cnt_r_reg[0][1][4]_0 ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][4] ;
  wire [4:0]idelay_tap_cnt_slice_r;
  wire idelay_tap_limit_r_i_1_n_0;
  wire idelay_tap_limit_r_i_2_n_0;
  wire idelay_tap_limit_r_reg_n_0;
  wire in0;
  wire inhibit_edge_detect_r;
  wire \init_state_r[2]_i_17 ;
  wire \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ;
  wire \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ;
  wire \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_5_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ;
  wire \mpr_4to1.stable_idel_cnt_reg_n_0_[0] ;
  wire \mpr_4to1.stable_idel_cnt_reg_n_0_[1] ;
  wire \mpr_4to1.stable_idel_cnt_reg_n_0_[2] ;
  wire mpr_dec_cpt_r;
  wire mpr_dec_cpt_r_i_1_n_0;
  wire mpr_dec_cpt_r_reg_n_0;
  wire mpr_rd_fall0_prev_r;
  wire mpr_rd_fall1_prev_r;
  wire mpr_rd_fall2_prev_r;
  wire mpr_rd_fall3_prev_r;
  wire mpr_rd_rise0_prev_r;
  wire mpr_rd_rise0_prev_r0;
  wire mpr_rd_rise1_prev_r;
  wire mpr_rd_rise2_prev_r;
  wire mpr_rd_rise3_prev_r;
  wire mpr_rdlvl_start_r;
  wire mpr_rdlvl_start_r_reg_0;
  wire new_cnt_cpt_r;
  wire new_cnt_cpt_r_i_2_n_0;
  wire new_cnt_cpt_r_reg_0;
  wire p_0_in;
  wire p_0_in100_in;
  wire p_0_in103_in;
  wire p_0_in118_in;
  wire p_0_in11_in;
  wire p_0_in125_in;
  wire p_0_in128_in;
  wire p_0_in136_in;
  wire p_0_in13_in;
  wire p_0_in144_in;
  wire p_0_in152_in;
  wire p_0_in160_in;
  wire p_0_in168_in;
  wire p_0_in16_in;
  wire p_0_in176_in;
  wire p_0_in184_in;
  wire p_0_in192_in;
  wire p_0_in19_in;
  wire p_0_in200_in;
  wire p_0_in208_in;
  wire p_0_in216_in;
  wire p_0_in224_in;
  wire p_0_in22_in;
  wire p_0_in250_in;
  wire p_0_in25_in;
  wire p_0_in28_in;
  wire p_0_in88_in;
  wire p_0_in91_in;
  wire p_0_in94_in;
  wire p_0_in97_in;
  wire [5:2]p_0_in__0;
  wire [4:0]p_0_in__0__0;
  wire [3:0]p_0_in__1;
  wire [4:0]p_0_in__2;
  wire [4:0]p_0_in__3;
  wire [4:0]p_0_in__4;
  wire [4:0]p_0_in__5;
  wire [4:0]p_0_in__6;
  wire [4:0]p_0_in__7;
  wire [4:0]p_0_in__8;
  wire [4:0]p_0_in__9;
  wire p_12_in;
  wire p_13_in;
  wire p_14_in;
  wire p_1_in;
  wire p_1_in127_in;
  wire p_1_in12_in;
  wire p_1_in135_in;
  wire p_1_in143_in;
  wire p_1_in14_in;
  wire p_1_in151_in;
  wire p_1_in159_in;
  wire p_1_in167_in;
  wire p_1_in175_in;
  wire p_1_in17_in;
  wire p_1_in183_in;
  wire p_1_in191_in;
  wire p_1_in199_in;
  wire p_1_in207_in;
  wire p_1_in20_in;
  wire p_1_in215_in;
  wire p_1_in223_in;
  wire p_1_in231_in;
  wire p_1_in23_in;
  wire p_1_in26_in;
  wire p_1_in29_in;
  wire p_1_in2_in;
  wire p_2_in;
  wire p_2_in129_in;
  wire p_2_in137_in;
  wire p_2_in145_in;
  wire p_2_in153_in;
  wire p_2_in161_in;
  wire p_2_in169_in;
  wire p_2_in177_in;
  wire p_2_in185_in;
  wire p_2_in193_in;
  wire p_2_in201_in;
  wire p_2_in209_in;
  wire p_2_in217_in;
  wire p_2_in225_in;
  wire p_37_in;
  wire p_3_in;
  wire p_3_in130_in;
  wire p_3_in138_in;
  wire p_3_in146_in;
  wire p_3_in154_in;
  wire p_3_in162_in;
  wire p_3_in170_in;
  wire p_3_in178_in;
  wire p_3_in186_in;
  wire p_3_in194_in;
  wire p_3_in202_in;
  wire p_3_in210_in;
  wire p_3_in218_in;
  wire p_3_in226_in;
  wire p_3_in4_in;
  wire p_4_in;
  wire p_4_in131_in;
  wire p_4_in139_in;
  wire p_4_in147_in;
  wire p_4_in155_in;
  wire p_4_in163_in;
  wire p_4_in171_in;
  wire p_4_in179_in;
  wire p_4_in187_in;
  wire p_4_in195_in;
  wire p_4_in203_in;
  wire p_4_in211_in;
  wire p_4_in219_in;
  wire p_4_in227_in;
  wire p_5_in;
  wire p_5_in132_in;
  wire p_5_in140_in;
  wire p_5_in148_in;
  wire p_5_in156_in;
  wire p_5_in164_in;
  wire p_5_in172_in;
  wire p_5_in180_in;
  wire p_5_in188_in;
  wire p_5_in196_in;
  wire p_5_in204_in;
  wire p_5_in212_in;
  wire p_5_in220_in;
  wire p_5_in228_in;
  wire p_6_in126_in;
  wire p_6_in133_in;
  wire p_6_in141_in;
  wire p_6_in149_in;
  wire p_6_in157_in;
  wire p_6_in165_in;
  wire p_6_in173_in;
  wire p_6_in181_in;
  wire p_6_in189_in;
  wire p_6_in197_in;
  wire p_6_in205_in;
  wire p_6_in213_in;
  wire p_6_in221_in;
  wire p_6_in229_in;
  wire p_7_in;
  wire p_7_in134_in;
  wire p_7_in142_in;
  wire p_7_in150_in;
  wire p_7_in158_in;
  wire p_7_in166_in;
  wire p_7_in174_in;
  wire p_7_in182_in;
  wire p_7_in190_in;
  wire p_7_in198_in;
  wire p_7_in206_in;
  wire p_7_in214_in;
  wire p_7_in222_in;
  wire p_7_in230_in;
  wire p_9_in;
  wire pat0_data_match_r0;
  wire pat0_match_fall0_and_r;
  wire [7:0]pat0_match_fall0_r;
  wire pat0_match_fall1_and_r;
  wire [7:0]pat0_match_fall1_r;
  wire pat0_match_fall2_and_r;
  wire [7:0]pat0_match_fall2_r;
  wire pat0_match_fall3_and_r;
  wire [7:0]pat0_match_fall3_r;
  wire pat0_match_rise0_and_r;
  wire [7:0]pat0_match_rise0_r;
  wire pat0_match_rise1_and_r;
  wire [7:0]pat0_match_rise1_r;
  wire pat0_match_rise2_and_r;
  wire [7:0]pat0_match_rise2_r;
  wire pat0_match_rise3_and_r;
  wire [7:0]pat0_match_rise3_r;
  wire pat1_data_match_r0;
  wire pat1_match_fall0_and_r;
  wire pat1_match_fall1_and_r;
  wire pat1_match_fall2_and_r;
  wire pat1_match_fall3_and_r;
  wire pat1_match_rise0_and_r;
  wire pat1_match_rise1_and_r;
  wire pat1_match_rise2_and_r;
  wire pat1_match_rise3_and_r;
  wire pb_cnt_eye_size_r;
  wire pb_detect_edge;
  wire [7:0]pb_detect_edge_done_r;
  wire [7:0]pb_found_stable_eye_r;
  wire pb_found_stable_eye_r53_out;
  wire pb_found_stable_eye_r57_out;
  wire pb_found_stable_eye_r61_out;
  wire pb_found_stable_eye_r65_out;
  wire pb_found_stable_eye_r69_out;
  wire pb_found_stable_eye_r73_out;
  wire pb_found_stable_eye_r77_out;
  wire pi_calib_done;
  wire pi_calib_done_r1_reg;
  wire pi_cnt_dec_i_1_n_0;
  wire pi_cnt_dec_i_2_n_0;
  wire pi_cnt_dec_reg_0;
  wire pi_counter_load_en;
  wire [5:0]pi_counter_load_val;
  wire pi_dqs_found_done;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire \pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_1 ;
  wire pi_en_stg2_f_reg_0;
  wire pi_en_stg2_f_timing;
  wire pi_en_stg2_f_timing_i_1_n_0;
  wire pi_fine_dly_dec_done_reg_0;
  wire [5:0]pi_rdval_cnt;
  wire \pi_rdval_cnt[0]_i_1_n_0 ;
  wire \pi_rdval_cnt[1]_i_1_n_0 ;
  wire \pi_rdval_cnt[2]_i_1_n_0 ;
  wire \pi_rdval_cnt[3]_i_1_n_0 ;
  wire \pi_rdval_cnt[3]_i_2_n_0 ;
  wire \pi_rdval_cnt[3]_i_3_n_0 ;
  wire \pi_rdval_cnt[4]_i_1_n_0 ;
  wire \pi_rdval_cnt[5]_i_1_n_0 ;
  wire \pi_rdval_cnt[5]_i_2_n_0 ;
  wire \pi_rdval_cnt[5]_i_3_n_0 ;
  wire \pi_rdval_cnt[5]_i_4_n_0 ;
  wire [5:0]\pi_rdval_cnt_reg[5]_0 ;
  wire pi_stg2_f_incdec_reg_0;
  wire pi_stg2_f_incdec_timing;
  wire pi_stg2_f_incdec_timing_i_1_n_0;
  wire pi_stg2_load_reg_0;
  wire pi_stg2_load_timing;
  wire pi_stg2_load_timing_i_1_n_0;
  wire [5:0]\pi_stg2_reg_l_reg[5]_0 ;
  wire [5:0]pi_stg2_reg_l_timing;
  wire \pi_stg2_reg_l_timing[0]_i_1_n_0 ;
  wire \pi_stg2_reg_l_timing[1]_i_1_n_0 ;
  wire \pi_stg2_reg_l_timing[2]_i_1_n_0 ;
  wire \pi_stg2_reg_l_timing[3]_i_1_n_0 ;
  wire \pi_stg2_reg_l_timing[4]_i_1_n_0 ;
  wire \pi_stg2_reg_l_timing[5]_i_1_n_0 ;
  wire \pi_stg2_reg_l_timing[5]_i_2_n_0 ;
  wire po_cnt_dec_reg;
  wire \po_stg2_wrcal_cnt_reg[0] ;
  wire \po_stg2_wrcal_cnt_reg[1] ;
  wire prech_done;
  wire \rd_mux_sel_r_reg[0]_0 ;
  wire rdlvl_dqs_tap_cnt_r;
  wire \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ;
  wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ;
  wire rdlvl_last_byte_done;
  wire rdlvl_last_byte_done_int_i_1_n_0;
  wire rdlvl_pi_incdec;
  wire rdlvl_pi_incdec_i_1_n_0;
  wire rdlvl_pi_incdec_i_2_n_0;
  wire rdlvl_pi_incdec_i_3_n_0;
  wire rdlvl_pi_incdec_i_4_n_0;
  wire rdlvl_pi_incdec_i_5_n_0;
  wire rdlvl_pi_stg2_f_en;
  wire rdlvl_pi_stg2_f_incdec;
  wire rdlvl_prech_req;
  wire rdlvl_rank_done_r;
  wire rdlvl_rank_done_r_i_1_n_0;
  wire rdlvl_stg1_done_int;
  wire rdlvl_stg1_done_int_i_1_n_0;
  wire rdlvl_stg1_done_int_reg_0;
  wire rdlvl_stg1_rank_done;
  wire rdlvl_stg1_start_r;
  wire rdlvl_stg1_start_r_reg_0;
  wire \regl_dqs_cnt[0]_i_1_n_0 ;
  wire \regl_dqs_cnt[1]_i_1_n_0 ;
  wire [1:0]regl_dqs_cnt_r;
  wire \regl_dqs_cnt_reg_n_0_[0] ;
  wire \regl_dqs_cnt_reg_n_0_[1] ;
  wire [1:0]regl_rank_cnt;
  wire \regl_rank_cnt[0]_i_1_n_0 ;
  wire \regl_rank_cnt[1]_i_1_n_0 ;
  wire \regl_rank_cnt[1]_i_2_n_0 ;
  wire reset_if;
  wire reset_if_r9;
  wire reset_if_reg;
  wire reset_if_reg_0;
  wire reset_if_reg_1;
  wire [5:0]right_edge_taps_r;
  wire \right_edge_taps_r[5]_i_1_n_0 ;
  wire \right_edge_taps_r[5]_i_3_n_0 ;
  wire \right_edge_taps_r_reg_n_0_[0] ;
  wire \right_edge_taps_r_reg_n_0_[1] ;
  wire \right_edge_taps_r_reg_n_0_[2] ;
  wire \right_edge_taps_r_reg_n_0_[3] ;
  wire \right_edge_taps_r_reg_n_0_[4] ;
  wire \right_edge_taps_r_reg_n_0_[5] ;
  wire \rnk_cnt_r[0]_i_1__0_n_0 ;
  wire \rnk_cnt_r[1]_i_1__0_n_0 ;
  wire \rnk_cnt_r_reg_n_0_[0] ;
  wire \rnk_cnt_r_reg_n_0_[1] ;
  wire samp_cnt_done_r_i_1_n_0;
  wire samp_cnt_done_r_i_2_n_0;
  wire samp_cnt_done_r_i_3_n_0;
  wire samp_cnt_done_r_i_4_n_0;
  wire samp_cnt_done_r_reg_n_0;
  wire samp_edge_cnt0_en_r;
  wire \samp_edge_cnt0_r[0]_i_3_n_0 ;
  wire [11:0]samp_edge_cnt0_r_reg;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_0 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_1 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_2 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_3 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_4 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_5 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_6 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_7 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_0 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_1 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_2 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_3 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_4 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_5 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_6 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_7 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_1 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_2 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_3 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_4 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_5 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_6 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_7 ;
  wire samp_edge_cnt1_en_r;
  wire samp_edge_cnt1_en_r0;
  wire samp_edge_cnt1_en_r_i_2_n_0;
  wire samp_edge_cnt1_en_r_i_3_n_0;
  wire \samp_edge_cnt1_r[0]_i_2_n_0 ;
  wire [11:0]samp_edge_cnt1_r_reg;
  wire \samp_edge_cnt1_r_reg[0]_0 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_1 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_2 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_3 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_4 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_5 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_6 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_7 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_1 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_2 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_3 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_4 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_5 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_6 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_7 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_1 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_2 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_3 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_4 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_5 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_6 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_7 ;
  wire \second_edge_taps_r[1]_i_1_n_0 ;
  wire \second_edge_taps_r[2]_i_1_n_0 ;
  wire \second_edge_taps_r[3]_i_1_n_0 ;
  wire \second_edge_taps_r[4]_i_1_n_0 ;
  wire \second_edge_taps_r[5]_i_1_n_0 ;
  wire \second_edge_taps_r[5]_i_2_n_0 ;
  wire \second_edge_taps_r[5]_i_3_n_0 ;
  wire \second_edge_taps_r_reg_n_0_[0] ;
  wire \second_edge_taps_r_reg_n_0_[1] ;
  wire \second_edge_taps_r_reg_n_0_[2] ;
  wire \second_edge_taps_r_reg_n_0_[3] ;
  wire \second_edge_taps_r_reg_n_0_[4] ;
  wire \second_edge_taps_r_reg_n_0_[5] ;
  wire sr_valid_r1;
  wire sr_valid_r2;
  wire sr_valid_r_i_1_n_0;
  wire sr_valid_r_reg_n_0;
  wire stable_idel_cnt;
  wire stable_idel_cnt0;
  wire store_sr_r0;
  wire store_sr_r_i_1_n_0;
  wire store_sr_r_reg_n_0;
  wire store_sr_req_pulsed_r;
  wire store_sr_req_pulsed_r__0;
  wire store_sr_req_r;
  wire store_sr_req_r_reg_0;
  wire store_sr_req_r_reg_n_0;
  wire tap_cnt_cpt_r;
  wire [0:0]tap_cnt_cpt_r0;
  wire \tap_cnt_cpt_r[1]_i_1_n_0 ;
  wire \tap_cnt_cpt_r[5]_i_4_n_0 ;
  wire \tap_cnt_cpt_r[5]_i_5_n_0 ;
  wire \tap_cnt_cpt_r[5]_i_6_n_0 ;
  wire [0:0]\tap_cnt_cpt_r_reg[5]_0 ;
  wire \tap_cnt_cpt_r_reg_n_0_[0] ;
  wire \tap_cnt_cpt_r_reg_n_0_[1] ;
  wire \tap_cnt_cpt_r_reg_n_0_[2] ;
  wire \tap_cnt_cpt_r_reg_n_0_[3] ;
  wire \tap_cnt_cpt_r_reg_n_0_[4] ;
  wire \tap_cnt_cpt_r_reg_n_0_[5] ;
  wire tap_limit_cpt_r;
  wire tap_limit_cpt_r_i_1_n_0;
  wire tap_limit_cpt_r_i_2_n_0;
  wire tempmon_pi_f_en_r;
  wire tempmon_pi_f_inc_r;
  wire wait_cnt_r0;
  wire [3:0]wait_cnt_r0__0;
  wire \wait_cnt_r[1]_i_1__0_n_0 ;
  wire [3:0]wait_cnt_r_reg;
  wire [0:0]\wait_cnt_r_reg[0]_0 ;
  wire [0:0]\NLW_cnt_idel_dec_cpt_r_reg[2]_i_10_O_UNCONNECTED ;
  wire [0:0]\NLW_cnt_idel_dec_cpt_r_reg[2]_i_2_O_UNCONNECTED ;
  wire [3:1]\NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED ;
  wire [3:2]\NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_O_UNCONNECTED ;
  wire [3:1]\NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_CO_UNCONNECTED ;
  wire [3:2]\NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_O_UNCONNECTED ;
  wire [3:3]\NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_cal1_state_r[10]_i_1 
       (.I0(p_1_in2_in),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[34] ),
        .O(\FSM_onehot_cal1_state_r[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT5 #(
    .INIT(32'h00002AAA)) 
    \FSM_onehot_cal1_state_r[11]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(found_edge_r_reg_n_0),
        .I2(found_stable_eye_last_r),
        .I3(found_first_edge_r_reg_n_0),
        .I4(tap_limit_cpt_r),
        .O(\FSM_onehot_cal1_state_r[11]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFBAA)) 
    \FSM_onehot_cal1_state_r[13]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .I1(mpr_rdlvl_start_r_reg_0),
        .I2(mpr_rdlvl_start_r),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(\FSM_onehot_cal1_state_r[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_onehot_cal1_state_r[14]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(\FSM_onehot_cal1_state_r[14]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[14]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \FSM_onehot_cal1_state_r[14]_i_2 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .I1(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[4] ),
        .I4(\cnt_idel_dec_cpt_r_reg_n_0_[5] ),
        .I5(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .O(\FSM_onehot_cal1_state_r[14]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hBA)) 
    \FSM_onehot_cal1_state_r[15]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[15]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r[15]_i_3_n_0 ),
        .I2(p_12_in),
        .O(\FSM_onehot_cal1_state_r[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \FSM_onehot_cal1_state_r[15]_i_2 
       (.I0(\FSM_onehot_cal1_state_r[16]_i_3_n_0 ),
        .I1(mpr_dec_cpt_r_reg_n_0),
        .I2(\FSM_onehot_cal1_state_r[16]_i_4_n_0 ),
        .O(\FSM_onehot_cal1_state_r[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \FSM_onehot_cal1_state_r[15]_i_3 
       (.I0(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I1(\idel_dec_cnt_reg_n_0_[2] ),
        .I2(\idel_dec_cnt_reg_n_0_[0] ),
        .I3(\idel_dec_cnt_reg_n_0_[1] ),
        .I4(\idel_dec_cnt_reg_n_0_[3] ),
        .I5(\idel_dec_cnt_reg_n_0_[4] ),
        .O(\FSM_onehot_cal1_state_r[15]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h8FFF8F8F88888888)) 
    \FSM_onehot_cal1_state_r[16]_i_1 
       (.I0(p_3_in4_in),
        .I1(store_sr_req_r_reg_0),
        .I2(\FSM_onehot_cal1_state_r[21]_i_2_n_0 ),
        .I3(\FSM_onehot_cal1_state_r[16]_i_3_n_0 ),
        .I4(\FSM_onehot_cal1_state_r[16]_i_4_n_0 ),
        .I5(mpr_dec_cpt_r_reg_n_0),
        .O(\FSM_onehot_cal1_state_r[16]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \FSM_onehot_cal1_state_r[16]_i_3 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(\FSM_onehot_cal1_state_r[14]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[16]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT4 #(
    .INIT(16'h0151)) 
    \FSM_onehot_cal1_state_r[16]_i_4 
       (.I0(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),
        .O(\FSM_onehot_cal1_state_r[16]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \FSM_onehot_cal1_state_r[1]_i_1 
       (.I0(mpr_dec_cpt_r),
        .I1(p_9_in),
        .I2(p_13_in),
        .O(\FSM_onehot_cal1_state_r[1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hBA)) 
    \FSM_onehot_cal1_state_r[20]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(idel_adj_inc_reg_n_0),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .O(\FSM_onehot_cal1_state_r[20]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF1FFF1FFF1F1F1)) 
    \FSM_onehot_cal1_state_r[21]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[21]_i_2_n_0 ),
        .I1(mpr_dec_cpt_r_reg_n_0),
        .I2(\FSM_onehot_cal1_state_r[21]_i_3_n_0 ),
        .I3(p_37_in),
        .I4(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .I5(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .O(\FSM_onehot_cal1_state_r[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \FSM_onehot_cal1_state_r[21]_i_2 
       (.I0(p_12_in),
        .I1(\FSM_onehot_cal1_state_r[15]_i_3_n_0 ),
        .O(\FSM_onehot_cal1_state_r[21]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF808080)) 
    \FSM_onehot_cal1_state_r[21]_i_3 
       (.I0(p_0_in250_in),
        .I1(idel_pat_detect_valid_r_reg_n_0),
        .I2(idel_mpr_pat_detect_r),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I4(idel_adj_inc_reg_n_0),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .O(\FSM_onehot_cal1_state_r[21]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0008AAAA00080008)) 
    \FSM_onehot_cal1_state_r[22]_i_1 
       (.I0(idelay_tap_limit_r_reg_n_0),
        .I1(p_37_in),
        .I2(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .I3(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .I4(idel_mpr_pat_detect_r),
        .I5(\FSM_onehot_cal1_state_r[22]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_cal1_state_r[22]_i_2 
       (.I0(p_0_in250_in),
        .I1(idel_pat_detect_valid_r_reg_n_0),
        .O(\FSM_onehot_cal1_state_r[22]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \FSM_onehot_cal1_state_r[29]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(found_edge_r_reg_n_0),
        .I2(found_stable_eye_last_r),
        .I3(found_first_edge_r_reg_n_0),
        .I4(tap_limit_cpt_r),
        .O(\FSM_onehot_cal1_state_r[29]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0004555500040004)) 
    \FSM_onehot_cal1_state_r[2]_i_1 
       (.I0(idelay_tap_limit_r_reg_n_0),
        .I1(p_37_in),
        .I2(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .I3(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .I4(idel_mpr_pat_detect_r),
        .I5(\FSM_onehot_cal1_state_r[22]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF5554)) 
    \FSM_onehot_cal1_state_r[34]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_3_n_0 ),
        .I1(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I2(\FSM_onehot_cal1_state_r[34]_i_5_n_0 ),
        .I3(\FSM_onehot_cal1_state_r[34]_i_6_n_0 ),
        .I4(\FSM_onehot_cal1_state_r[34]_i_7_n_0 ),
        .I5(mpr_dec_cpt_r),
        .O(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF8F8FFF8)) 
    \FSM_onehot_cal1_state_r[34]_i_10 
       (.I0(prech_done),
        .I1(cal1_prech_req_r),
        .I2(p_0_in118_in),
        .I3(p_3_in4_in),
        .I4(cal1_wait_r),
        .I5(\FSM_onehot_cal1_state_r[34]_i_13_n_0 ),
        .O(\FSM_onehot_cal1_state_r[34]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \FSM_onehot_cal1_state_r[34]_i_11 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I1(p_14_in),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I5(p_13_in),
        .O(\FSM_onehot_cal1_state_r[34]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \FSM_onehot_cal1_state_r[34]_i_12 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(cal1_wait_r),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .O(\FSM_onehot_cal1_state_r[34]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_cal1_state_r[34]_i_13 
       (.I0(cal1_dq_idel_inc),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .O(\FSM_onehot_cal1_state_r[34]_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_onehot_cal1_state_r[34]_i_2 
       (.I0(p_0_in250_in),
        .I1(idel_pat_detect_valid_r_reg_n_0),
        .O(\FSM_onehot_cal1_state_r[34]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT5 #(
    .INIT(32'h0000222A)) 
    \FSM_onehot_cal1_state_r[34]_i_3 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_9_n_0 ),
        .I1(detect_edge_done_r),
        .I2(p_37_in),
        .I3(store_sr_req_pulsed_r),
        .I4(p_0_in250_in),
        .O(\FSM_onehot_cal1_state_r[34]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \FSM_onehot_cal1_state_r[34]_i_4 
       (.I0(p_13_in),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I2(p_14_in),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I4(store_sr_req_pulsed_r),
        .O(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \FSM_onehot_cal1_state_r[34]_i_5 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[34] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .O(\FSM_onehot_cal1_state_r[34]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \FSM_onehot_cal1_state_r[34]_i_6 
       (.I0(p_0_in250_in),
        .I1(p_37_in),
        .I2(p_9_in),
        .I3(p_12_in),
        .O(\FSM_onehot_cal1_state_r[34]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF40F04040)) 
    \FSM_onehot_cal1_state_r[34]_i_7 
       (.I0(mpr_rdlvl_start_r),
        .I1(mpr_rdlvl_start_r_reg_0),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I3(rdlvl_stg1_start_r),
        .I4(rdlvl_stg1_start_r_reg_0),
        .I5(\FSM_onehot_cal1_state_r[34]_i_10_n_0 ),
        .O(\FSM_onehot_cal1_state_r[34]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_onehot_cal1_state_r[34]_i_8 
       (.I0(p_3_in4_in),
        .I1(store_sr_req_r_reg_0),
        .O(mpr_dec_cpt_r));
  LUT6 #(
    .INIT(64'hFFFFFFFF00010000)) 
    \FSM_onehot_cal1_state_r[34]_i_9 
       (.I0(detect_edge_done_r),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I2(p_9_in),
        .I3(\FSM_onehot_cal1_state_r[34]_i_11_n_0 ),
        .I4(\cal1_state_r1[1]_i_2_n_0 ),
        .I5(\FSM_onehot_cal1_state_r[34]_i_12_n_0 ),
        .O(\FSM_onehot_cal1_state_r[34]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \FSM_onehot_cal1_state_r[4]_i_1 
       (.I0(mpr_dec_cpt_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r[14]_i_2_n_0 ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .O(\FSM_onehot_cal1_state_r[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000008)) 
    \FSM_onehot_cal1_state_r[5]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ),
        .I1(\regl_dqs_cnt_reg_n_0_[0] ),
        .I2(\regl_dqs_cnt_reg_n_0_[1] ),
        .I3(regl_rank_cnt[0]),
        .I4(regl_rank_cnt[1]),
        .O(\FSM_onehot_cal1_state_r[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00020000)) 
    \FSM_onehot_cal1_state_r[5]_i_2 
       (.I0(p_0_in118_in),
        .I1(done_cnt[3]),
        .I2(done_cnt[2]),
        .I3(done_cnt[1]),
        .I4(done_cnt[0]),
        .O(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFB00FFFFFB00FB00)) 
    \FSM_onehot_cal1_state_r[6]_i_1 
       (.I0(\regl_dqs_cnt_reg_n_0_[1] ),
        .I1(\regl_dqs_cnt_reg_n_0_[0] ),
        .I2(\FSM_onehot_cal1_state_r[6]_i_2_n_0 ),
        .I3(p_0_in118_in),
        .I4(\cal1_cnt_cpt_r_reg[0]_0 ),
        .I5(cal1_prech_req_r),
        .O(\FSM_onehot_cal1_state_r[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \FSM_onehot_cal1_state_r[6]_i_2 
       (.I0(done_cnt[3]),
        .I1(done_cnt[2]),
        .I2(done_cnt[1]),
        .I3(done_cnt[0]),
        .I4(regl_rank_cnt[0]),
        .I5(regl_rank_cnt[1]),
        .O(\FSM_onehot_cal1_state_r[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_onehot_cal1_state_r[6]_i_3 
       (.I0(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .O(\cal1_cnt_cpt_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT4 #(
    .INIT(16'h8880)) 
    \FSM_onehot_cal1_state_r[7]_i_1 
       (.I0(cal1_prech_req_r),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .O(\FSM_onehot_cal1_state_r[7]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_onehot_cal1_state_r[8]_i_1 
       (.I0(cal1_prech_req_r),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .O(cal1_cnt_cpt_r));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \FSM_onehot_cal1_state_r[9]_i_1 
       (.I0(mpr_rdlvl_start_r),
        .I1(mpr_rdlvl_start_r_reg_0),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(\FSM_onehot_cal1_state_r[9]_i_1_n_0 ));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[0] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .Q(p_13_in),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[10] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[10]_i_1_n_0 ),
        .Q(p_0_in250_in),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[11] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[11]_i_1_n_0 ),
        .Q(p_14_in),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[12] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(p_14_in),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[13] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[13]_i_1_n_0 ),
        .Q(p_3_in4_in),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[14] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[14]_i_1_n_0 ),
        .Q(p_9_in),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[15] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[15]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[16] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[16]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[1] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[1]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[20] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[20]_i_1_n_0 ),
        .Q(p_37_in),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[21] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[21]_i_1_n_0 ),
        .Q(store_sr_req_pulsed_r),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[22] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[22]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[29] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[29]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[2] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[2]_i_1_n_0 ),
        .Q(cal1_dq_idel_inc),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[31] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[32] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .Q(p_12_in),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[34] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[34]_i_2_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[34] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[3] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(cal1_dq_idel_inc),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[4] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[4]_i_1_n_0 ),
        .Q(cal1_prech_req_r),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[5] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[5]_i_1_n_0 ),
        .Q(rdlvl_stg1_done_int),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[6] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[6]_i_1_n_0 ),
        .Q(p_0_in118_in),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDSE #(
    .INIT(1'b1)) 
    \FSM_onehot_cal1_state_r_reg[7] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[7]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .S(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[8] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(cal1_cnt_cpt_r),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[9] 
       (.C(CLK),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[9]_i_1_n_0 ),
        .Q(p_1_in2_in),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  LUT6 #(
    .INIT(64'h15E015E015E055E0)) 
    \cal1_cnt_cpt_r[0]_i_1 
       (.I0(p_0_in118_in),
        .I1(prech_done),
        .I2(cal1_prech_req_r),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I4(\rnk_cnt_r_reg_n_0_[1] ),
        .I5(\rnk_cnt_r_reg_n_0_[0] ),
        .O(\cal1_cnt_cpt_r[0]_i_1_n_0 ));
  FDRE \cal1_cnt_cpt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r[0]_i_1_n_0 ),
        .Q(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  LUT3 #(
    .INIT(8'hBA)) 
    cal1_dlyce_cpt_r_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(tap_limit_cpt_r),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .O(cal1_dlyce_cpt_r));
  FDRE cal1_dlyce_cpt_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_dlyce_cpt_r),
        .Q(cal1_dlyce_cpt_r_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT2 #(
    .INIT(4'h2)) 
    cal1_dlyinc_cpt_r_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I1(tap_limit_cpt_r),
        .O(cal1_dlyinc_cpt_r));
  FDRE cal1_dlyinc_cpt_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_dlyinc_cpt_r),
        .Q(cal1_dlyinc_cpt_r_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  LUT2 #(
    .INIT(4'hE)) 
    cal1_dq_idel_ce_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .I1(cal1_dq_idel_inc),
        .O(cal1_dq_idel_ce));
  FDRE cal1_dq_idel_ce_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_dq_idel_ce),
        .Q(idelay_ce_int),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  FDRE cal1_dq_idel_inc_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_dq_idel_inc),
        .Q(idelay_inc_int),
        .R(found_first_edge_r_reg_0));
  FDRE cal1_prech_req_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_prech_req_r),
        .Q(cal1_prech_req_r__0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \cal1_state_r1[0]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_6_n_0 ),
        .I1(\cal1_state_r1[0]_i_2_n_0 ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I3(p_1_in2_in),
        .I4(p_3_in4_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .O(\cal1_state_r1[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \cal1_state_r1[0]_i_2 
       (.I0(rdlvl_stg1_done_int),
        .I1(p_0_in118_in),
        .I2(p_14_in),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .O(\cal1_state_r1[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFD)) 
    \cal1_state_r1[1]_i_1 
       (.I0(\cal1_state_r1[1]_i_2_n_0 ),
        .I1(p_13_in),
        .I2(cal1_prech_req_r),
        .I3(p_0_in250_in),
        .I4(p_37_in),
        .I5(\cal1_state_r1[1]_i_3_n_0 ),
        .O(\cal1_state_r1[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \cal1_state_r1[1]_i_2 
       (.I0(p_12_in),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[34] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\cal1_state_r1[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \cal1_state_r1[1]_i_3 
       (.I0(rdlvl_stg1_done_int),
        .I1(p_0_in118_in),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .O(\cal1_state_r1[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \cal1_state_r1[2]_i_1 
       (.I0(\cal1_state_r1[3]_i_3_n_0 ),
        .I1(\cal1_state_r1[2]_i_2_n_0 ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .I3(cal1_prech_req_r),
        .I4(p_12_in),
        .I5(rdlvl_stg1_done_int),
        .O(\cal1_state_r1[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \cal1_state_r1[2]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I1(p_1_in2_in),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I3(cal1_dq_idel_inc),
        .O(\cal1_state_r1[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \cal1_state_r1[3]_i_1 
       (.I0(\cal1_state_r1[3]_i_2_n_0 ),
        .I1(\cal1_state_r1[3]_i_3_n_0 ),
        .I2(rdlvl_stg1_done_int),
        .I3(p_0_in118_in),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .O(\cal1_state_r1[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \cal1_state_r1[3]_i_2 
       (.I0(p_1_in2_in),
        .I1(store_sr_req_pulsed_r),
        .I2(cal1_prech_req_r),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .O(\cal1_state_r1[3]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \cal1_state_r1[3]_i_3 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[34] ),
        .I2(p_9_in),
        .I3(p_0_in250_in),
        .O(\cal1_state_r1[3]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \cal1_state_r1[4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[34] ),
        .I1(p_1_in2_in),
        .I2(p_0_in118_in),
        .I3(p_0_in250_in),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .O(\cal1_state_r1[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \cal1_state_r1[5]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .I1(p_13_in),
        .I2(p_14_in),
        .O(\cal1_state_r1[5]_i_1_n_0 ));
  FDRE \cal1_state_r1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_state_r1[0]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \cal1_state_r1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_state_r1[1]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \cal1_state_r1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_state_r1[2]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \cal1_state_r1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_state_r1[3]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \cal1_state_r1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_state_r1[4]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \cal1_state_r1_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_state_r1[5]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[5] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    cal1_wait_cnt_en_r_i_1
       (.I0(\cal1_state_r1[5]_i_1_n_0 ),
        .I1(cal1_wait_cnt_en_r_i_2_n_0),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I4(p_9_in),
        .I5(p_3_in4_in),
        .O(cal1_wait_cnt_en_r0));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    cal1_wait_cnt_en_r_i_2
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I1(p_1_in2_in),
        .I2(p_12_in),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[34] ),
        .O(cal1_wait_cnt_en_r_i_2_n_0));
  FDRE cal1_wait_cnt_en_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_wait_cnt_en_r0),
        .Q(cal1_wait_cnt_en_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \cal1_wait_cnt_r[0]_i_1 
       (.I0(cal1_wait_cnt_r_reg[0]),
        .O(p_0_in__0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cal1_wait_cnt_r[1]_i_1 
       (.I0(cal1_wait_cnt_r_reg[0]),
        .I1(cal1_wait_cnt_r_reg[1]),
        .O(p_0_in__0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cal1_wait_cnt_r[2]_i_1 
       (.I0(cal1_wait_cnt_r_reg[2]),
        .I1(cal1_wait_cnt_r_reg[1]),
        .I2(cal1_wait_cnt_r_reg[0]),
        .O(p_0_in__0__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cal1_wait_cnt_r[3]_i_1 
       (.I0(cal1_wait_cnt_r_reg[3]),
        .I1(cal1_wait_cnt_r_reg[0]),
        .I2(cal1_wait_cnt_r_reg[1]),
        .I3(cal1_wait_cnt_r_reg[2]),
        .O(p_0_in__0__0[3]));
  LUT6 #(
    .INIT(64'h40000000FFFFFFFF)) 
    \cal1_wait_cnt_r[4]_i_1 
       (.I0(cal1_wait_cnt_r_reg[4]),
        .I1(cal1_wait_cnt_r_reg[3]),
        .I2(cal1_wait_cnt_r_reg[0]),
        .I3(cal1_wait_cnt_r_reg[1]),
        .I4(cal1_wait_cnt_r_reg[2]),
        .I5(cal1_wait_cnt_en_r),
        .O(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cal1_wait_cnt_r[4]_i_2 
       (.I0(cal1_wait_cnt_r_reg[4]),
        .I1(cal1_wait_cnt_r_reg[2]),
        .I2(cal1_wait_cnt_r_reg[1]),
        .I3(cal1_wait_cnt_r_reg[0]),
        .I4(cal1_wait_cnt_r_reg[3]),
        .O(p_0_in__0__0[4]));
  FDRE \cal1_wait_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0__0[0]),
        .Q(cal1_wait_cnt_r_reg[0]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  FDRE \cal1_wait_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0__0[1]),
        .Q(cal1_wait_cnt_r_reg[1]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  FDRE \cal1_wait_cnt_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0__0[2]),
        .Q(cal1_wait_cnt_r_reg[2]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  FDRE \cal1_wait_cnt_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0__0[3]),
        .Q(cal1_wait_cnt_r_reg[3]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  FDRE \cal1_wait_cnt_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0__0[4]),
        .Q(cal1_wait_cnt_r_reg[4]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFFFFFFFFFFFFFF)) 
    cal1_wait_r_i_1
       (.I0(cal1_wait_cnt_en_r),
        .I1(cal1_wait_cnt_r_reg[4]),
        .I2(cal1_wait_cnt_r_reg[3]),
        .I3(cal1_wait_cnt_r_reg[0]),
        .I4(cal1_wait_cnt_r_reg[1]),
        .I5(cal1_wait_cnt_r_reg[2]),
        .O(cal1_wait_r_i_1_n_0));
  FDRE cal1_wait_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_wait_r_i_1_n_0),
        .Q(cal1_wait_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF7020)) 
    \cnt_idel_dec_cpt_r[0]_i_1 
       (.I0(found_second_edge_r_reg_n_0),
        .I1(cnt_idel_dec_cpt_r1[0]),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I3(\cnt_idel_dec_cpt_r[0]_i_2_n_0 ),
        .I4(\cnt_idel_dec_cpt_r[0]_i_3_n_0 ),
        .O(cnt_idel_dec_cpt_r[0]));
  LUT6 #(
    .INIT(64'hB800B8FFB8FFB800)) 
    \cnt_idel_dec_cpt_r[0]_i_2 
       (.I0(\cnt_idel_dec_cpt_r_reg[2]_i_10_n_6 ),
        .I1(found_first_edge_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\right_edge_taps_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT4 #(
    .INIT(16'h8F88)) 
    \cnt_idel_dec_cpt_r[0]_i_3 
       (.I0(\pi_rdval_cnt_reg[5]_0 [0]),
        .I1(p_3_in4_in),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF28AA2800)) 
    \cnt_idel_dec_cpt_r[1]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(cnt_idel_dec_cpt_r1[0]),
        .I2(cnt_idel_dec_cpt_r1[1]),
        .I3(found_second_edge_r_reg_n_0),
        .I4(\cnt_idel_dec_cpt_r[1]_i_2_n_0 ),
        .I5(\cnt_idel_dec_cpt_r[1]_i_3_n_0 ),
        .O(cnt_idel_dec_cpt_r[1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \cnt_idel_dec_cpt_r[1]_i_2 
       (.I0(\cnt_idel_dec_cpt_r_reg[2]_i_10_n_5 ),
        .I1(found_first_edge_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I3(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ),
        .I4(\cnt_idel_dec_cpt_r[1]_i_4_n_0 ),
        .O(\cnt_idel_dec_cpt_r[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT5 #(
    .INIT(32'hF88F8888)) 
    \cnt_idel_dec_cpt_r[1]_i_3 
       (.I0(\pi_rdval_cnt_reg[5]_0 [1]),
        .I1(p_3_in4_in),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT4 #(
    .INIT(16'h4BB4)) 
    \cnt_idel_dec_cpt_r[1]_i_4 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\right_edge_taps_r_reg_n_0_[1] ),
        .I2(\right_edge_taps_r_reg_n_0_[2] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF28AA2800)) 
    \cnt_idel_dec_cpt_r[2]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(cnt_idel_dec_cpt_r1[2]),
        .I2(\cnt_idel_dec_cpt_r[2]_i_3_n_0 ),
        .I3(found_second_edge_r_reg_n_0),
        .I4(\cnt_idel_dec_cpt_r[2]_i_4_n_0 ),
        .I5(\cnt_idel_dec_cpt_r[2]_i_5_n_0 ),
        .O(cnt_idel_dec_cpt_r[2]));
  LUT6 #(
    .INIT(64'h08AEF751F75108AE)) 
    \cnt_idel_dec_cpt_r[2]_i_11 
       (.I0(\right_edge_taps_r_reg_n_0_[2] ),
        .I1(\right_edge_taps_r_reg_n_0_[1] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I4(\right_edge_taps_r_reg_n_0_[3] ),
        .I5(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_12 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I1(\first_edge_taps_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_12_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_13 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I1(\first_edge_taps_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_14 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I1(\first_edge_taps_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_14_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_15 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\first_edge_taps_r_reg_n_0_[0] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_15_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \cnt_idel_dec_cpt_r[2]_i_3 
       (.I0(cnt_idel_dec_cpt_r1[0]),
        .I1(cnt_idel_dec_cpt_r1[1]),
        .O(\cnt_idel_dec_cpt_r[2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \cnt_idel_dec_cpt_r[2]_i_4 
       (.I0(\cnt_idel_dec_cpt_r_reg[2]_i_10_n_4 ),
        .I1(found_first_edge_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I3(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ),
        .I4(\cnt_idel_dec_cpt_r[2]_i_11_n_0 ),
        .O(\cnt_idel_dec_cpt_r[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hF888F888F88888F8)) 
    \cnt_idel_dec_cpt_r[2]_i_5 
       (.I0(\pi_rdval_cnt_reg[5]_0 [2]),
        .I1(p_3_in4_in),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .I4(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I5(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_6 
       (.I0(\second_edge_taps_r_reg_n_0_[3] ),
        .I1(\first_edge_taps_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_7 
       (.I0(\second_edge_taps_r_reg_n_0_[2] ),
        .I1(\first_edge_taps_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_8 
       (.I0(\second_edge_taps_r_reg_n_0_[1] ),
        .I1(\first_edge_taps_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_9 
       (.I0(\second_edge_taps_r_reg_n_0_[0] ),
        .I1(\first_edge_taps_r_reg_n_0_[0] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF28AA2800)) 
    \cnt_idel_dec_cpt_r[3]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(cnt_idel_dec_cpt_r1[3]),
        .I2(\cnt_idel_dec_cpt_r[3]_i_2_n_0 ),
        .I3(found_second_edge_r_reg_n_0),
        .I4(\cnt_idel_dec_cpt_r[3]_i_3_n_0 ),
        .I5(\cnt_idel_dec_cpt_r[3]_i_4_n_0 ),
        .O(cnt_idel_dec_cpt_r[3]));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \cnt_idel_dec_cpt_r[3]_i_2 
       (.I0(cnt_idel_dec_cpt_r1[2]),
        .I1(cnt_idel_dec_cpt_r1[1]),
        .I2(cnt_idel_dec_cpt_r1[0]),
        .O(\cnt_idel_dec_cpt_r[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \cnt_idel_dec_cpt_r[3]_i_3 
       (.I0(\cnt_idel_dec_cpt_r_reg[4]_i_8_n_7 ),
        .I1(found_first_edge_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I3(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ),
        .I4(\cnt_idel_dec_cpt_r[3]_i_5_n_0 ),
        .O(\cnt_idel_dec_cpt_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hF88888F8F888F888)) 
    \cnt_idel_dec_cpt_r[3]_i_4 
       (.I0(\pi_rdval_cnt_reg[5]_0 [3]),
        .I1(p_3_in4_in),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .I4(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .I5(\cnt_idel_dec_cpt_r[3]_i_6_n_0 ),
        .O(\cnt_idel_dec_cpt_r[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT3 #(
    .INIT(8'h69)) 
    \cnt_idel_dec_cpt_r[3]_i_5 
       (.I0(\cnt_idel_dec_cpt_r[4]_i_14_n_0 ),
        .I1(\right_edge_taps_r_reg_n_0_[4] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \cnt_idel_dec_cpt_r[3]_i_6 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I1(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .O(\cnt_idel_dec_cpt_r[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF28AA2800)) 
    \cnt_idel_dec_cpt_r[4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(cnt_idel_dec_cpt_r1[4]),
        .I2(\cnt_idel_dec_cpt_r[4]_i_3_n_0 ),
        .I3(found_second_edge_r_reg_n_0),
        .I4(\cnt_idel_dec_cpt_r[4]_i_4_n_0 ),
        .I5(\cnt_idel_dec_cpt_r[4]_i_5_n_0 ),
        .O(cnt_idel_dec_cpt_r[4]));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT5 #(
    .INIT(32'h2BD4D42B)) 
    \cnt_idel_dec_cpt_r[4]_i_10 
       (.I0(\right_edge_taps_r_reg_n_0_[4] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I2(\cnt_idel_dec_cpt_r[4]_i_14_n_0 ),
        .I3(\right_edge_taps_r_reg_n_0_[5] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \cnt_idel_dec_cpt_r[4]_i_11 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .I1(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[4]_i_12 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I1(\first_edge_taps_r_reg_n_0_[5] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_12_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[4]_i_13 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I1(\first_edge_taps_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hF7510000FFFFF751)) 
    \cnt_idel_dec_cpt_r[4]_i_14 
       (.I0(\right_edge_taps_r_reg_n_0_[2] ),
        .I1(\right_edge_taps_r_reg_n_0_[1] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\right_edge_taps_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \cnt_idel_dec_cpt_r[4]_i_3 
       (.I0(cnt_idel_dec_cpt_r1[3]),
        .I1(cnt_idel_dec_cpt_r1[0]),
        .I2(cnt_idel_dec_cpt_r1[1]),
        .I3(cnt_idel_dec_cpt_r1[2]),
        .O(\cnt_idel_dec_cpt_r[4]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \cnt_idel_dec_cpt_r[4]_i_4 
       (.I0(\cnt_idel_dec_cpt_r_reg[4]_i_8_n_6 ),
        .I1(found_first_edge_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I3(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ),
        .I4(\cnt_idel_dec_cpt_r[4]_i_10_n_0 ),
        .O(\cnt_idel_dec_cpt_r[4]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h8FF88888)) 
    \cnt_idel_dec_cpt_r[4]_i_5 
       (.I0(\pi_rdval_cnt_reg[5]_0 [4]),
        .I1(p_3_in4_in),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[4] ),
        .I3(\cnt_idel_dec_cpt_r[4]_i_11_n_0 ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[4]_i_6 
       (.I0(\second_edge_taps_r_reg_n_0_[5] ),
        .I1(\first_edge_taps_r_reg_n_0_[5] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[4]_i_7 
       (.I0(\second_edge_taps_r_reg_n_0_[4] ),
        .I1(\first_edge_taps_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \cnt_idel_dec_cpt_r[4]_i_9 
       (.I0(\right_edge_taps_r_reg_n_0_[2] ),
        .I1(\right_edge_taps_r_reg_n_0_[3] ),
        .I2(\right_edge_taps_r_reg_n_0_[0] ),
        .I3(\right_edge_taps_r_reg_n_0_[1] ),
        .I4(\right_edge_taps_r_reg_n_0_[5] ),
        .I5(\right_edge_taps_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \cnt_idel_dec_cpt_r[5]_i_1 
       (.I0(mpr_dec_cpt_r),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF44F444F444F4)) 
    \cnt_idel_dec_cpt_r[5]_i_2 
       (.I0(\cnt_idel_dec_cpt_r_reg[5]_i_3_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I3(\cnt_idel_dec_cpt_r[5]_i_4_n_0 ),
        .I4(p_3_in4_in),
        .I5(\pi_rdval_cnt_reg[5]_0 [5]),
        .O(cnt_idel_dec_cpt_r[5]));
  LUT6 #(
    .INIT(64'h5555555555555556)) 
    \cnt_idel_dec_cpt_r[5]_i_4 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[5] ),
        .I1(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I4(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I5(\cnt_idel_dec_cpt_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[5]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hBFABEAFE)) 
    \cnt_idel_dec_cpt_r[5]_i_5 
       (.I0(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ),
        .I1(\cnt_idel_dec_cpt_r[5]_i_7_n_0 ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I3(\right_edge_taps_r_reg_n_0_[5] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .O(\cnt_idel_dec_cpt_r[5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_idel_dec_cpt_r[5]_i_6 
       (.I0(\cnt_idel_dec_cpt_r_reg[4]_i_2_n_1 ),
        .I1(cnt_idel_dec_cpt_r1[3]),
        .I2(cnt_idel_dec_cpt_r1[0]),
        .I3(cnt_idel_dec_cpt_r1[1]),
        .I4(cnt_idel_dec_cpt_r1[2]),
        .I5(cnt_idel_dec_cpt_r1[4]),
        .O(\cnt_idel_dec_cpt_r[5]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'h8E)) 
    \cnt_idel_dec_cpt_r[5]_i_7 
       (.I0(\cnt_idel_dec_cpt_r[4]_i_14_n_0 ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I2(\right_edge_taps_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[5]_i_7_n_0 ));
  FDRE \cnt_idel_dec_cpt_r_reg[0] 
       (.C(CLK),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[0]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \cnt_idel_dec_cpt_r_reg[1] 
       (.C(CLK),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[1]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \cnt_idel_dec_cpt_r_reg[2] 
       (.C(CLK),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[2]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .R(1'b0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \cnt_idel_dec_cpt_r_reg[2]_i_10 
       (.CI(1'b0),
        .CO({\cnt_idel_dec_cpt_r_reg[2]_i_10_n_0 ,\cnt_idel_dec_cpt_r_reg[2]_i_10_n_1 ,\cnt_idel_dec_cpt_r_reg[2]_i_10_n_2 ,\cnt_idel_dec_cpt_r_reg[2]_i_10_n_3 }),
        .CYINIT(1'b1),
        .DI({\tap_cnt_cpt_r_reg_n_0_[3] ,\tap_cnt_cpt_r_reg_n_0_[2] ,\tap_cnt_cpt_r_reg_n_0_[1] ,\tap_cnt_cpt_r_reg_n_0_[0] }),
        .O({\cnt_idel_dec_cpt_r_reg[2]_i_10_n_4 ,\cnt_idel_dec_cpt_r_reg[2]_i_10_n_5 ,\cnt_idel_dec_cpt_r_reg[2]_i_10_n_6 ,\NLW_cnt_idel_dec_cpt_r_reg[2]_i_10_O_UNCONNECTED [0]}),
        .S({\cnt_idel_dec_cpt_r[2]_i_12_n_0 ,\cnt_idel_dec_cpt_r[2]_i_13_n_0 ,\cnt_idel_dec_cpt_r[2]_i_14_n_0 ,\cnt_idel_dec_cpt_r[2]_i_15_n_0 }));
  CARRY4 \cnt_idel_dec_cpt_r_reg[2]_i_2 
       (.CI(1'b0),
        .CO({\cnt_idel_dec_cpt_r_reg[2]_i_2_n_0 ,\cnt_idel_dec_cpt_r_reg[2]_i_2_n_1 ,\cnt_idel_dec_cpt_r_reg[2]_i_2_n_2 ,\cnt_idel_dec_cpt_r_reg[2]_i_2_n_3 }),
        .CYINIT(1'b1),
        .DI({\second_edge_taps_r_reg_n_0_[3] ,\second_edge_taps_r_reg_n_0_[2] ,\second_edge_taps_r_reg_n_0_[1] ,\second_edge_taps_r_reg_n_0_[0] }),
        .O({cnt_idel_dec_cpt_r1[2:0],\NLW_cnt_idel_dec_cpt_r_reg[2]_i_2_O_UNCONNECTED [0]}),
        .S({\cnt_idel_dec_cpt_r[2]_i_6_n_0 ,\cnt_idel_dec_cpt_r[2]_i_7_n_0 ,\cnt_idel_dec_cpt_r[2]_i_8_n_0 ,\cnt_idel_dec_cpt_r[2]_i_9_n_0 }));
  FDRE \cnt_idel_dec_cpt_r_reg[3] 
       (.C(CLK),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[3]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \cnt_idel_dec_cpt_r_reg[4] 
       (.C(CLK),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[4]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[4] ),
        .R(1'b0));
  CARRY4 \cnt_idel_dec_cpt_r_reg[4]_i_2 
       (.CI(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_0 ),
        .CO({\NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED [3],\cnt_idel_dec_cpt_r_reg[4]_i_2_n_1 ,\NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED [1],\cnt_idel_dec_cpt_r_reg[4]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,\second_edge_taps_r_reg_n_0_[5] ,\second_edge_taps_r_reg_n_0_[4] }),
        .O({\NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_O_UNCONNECTED [3:2],cnt_idel_dec_cpt_r1[4:3]}),
        .S({1'b0,1'b1,\cnt_idel_dec_cpt_r[4]_i_6_n_0 ,\cnt_idel_dec_cpt_r[4]_i_7_n_0 }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \cnt_idel_dec_cpt_r_reg[4]_i_8 
       (.CI(\cnt_idel_dec_cpt_r_reg[2]_i_10_n_0 ),
        .CO({\NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_CO_UNCONNECTED [3:1],\cnt_idel_dec_cpt_r_reg[4]_i_8_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\tap_cnt_cpt_r_reg_n_0_[4] }),
        .O({\NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_O_UNCONNECTED [3:2],\cnt_idel_dec_cpt_r_reg[4]_i_8_n_6 ,\cnt_idel_dec_cpt_r_reg[4]_i_8_n_7 }),
        .S({1'b0,1'b0,\cnt_idel_dec_cpt_r[4]_i_12_n_0 ,\cnt_idel_dec_cpt_r[4]_i_13_n_0 }));
  FDRE \cnt_idel_dec_cpt_r_reg[5] 
       (.C(CLK),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[5]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[5] ),
        .R(1'b0));
  MUXF7 \cnt_idel_dec_cpt_r_reg[5]_i_3 
       (.I0(\cnt_idel_dec_cpt_r[5]_i_5_n_0 ),
        .I1(\cnt_idel_dec_cpt_r[5]_i_6_n_0 ),
        .O(\cnt_idel_dec_cpt_r_reg[5]_i_3_n_0 ),
        .S(found_second_edge_r_reg_n_0));
  LUT4 #(
    .INIT(16'h5554)) 
    \cnt_shift_r[0]_i_1 
       (.I0(cnt_shift_r_reg[0]),
        .I1(cnt_shift_r_reg[1]),
        .I2(cnt_shift_r_reg[3]),
        .I3(cnt_shift_r_reg[2]),
        .O(p_0_in__1[0]));
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_shift_r[1]_i_1 
       (.I0(cnt_shift_r_reg[1]),
        .I1(cnt_shift_r_reg[0]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_shift_r[2]_i_1 
       (.I0(cnt_shift_r_reg[2]),
        .I1(cnt_shift_r_reg[0]),
        .I2(cnt_shift_r_reg[1]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_shift_r[3]_i_2 
       (.I0(cnt_shift_r_reg[3]),
        .I1(cnt_shift_r_reg[1]),
        .I2(cnt_shift_r_reg[0]),
        .I3(cnt_shift_r_reg[2]),
        .O(p_0_in__1[3]));
  FDSE \cnt_shift_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in__1[0]),
        .Q(cnt_shift_r_reg[0]),
        .S(\cnt_shift_r_reg[0]_0 ));
  FDRE \cnt_shift_r_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in__1[1]),
        .Q(cnt_shift_r_reg[1]),
        .R(\cnt_shift_r_reg[0]_0 ));
  FDRE \cnt_shift_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in__1[2]),
        .Q(cnt_shift_r_reg[2]),
        .R(\cnt_shift_r_reg[0]_0 ));
  FDRE \cnt_shift_r_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in__1[3]),
        .Q(cnt_shift_r_reg[3]),
        .R(\cnt_shift_r_reg[0]_0 ));
  LUT3 #(
    .INIT(8'hBF)) 
    \ctl_lane_cnt[1]_i_2 
       (.I0(po_cnt_dec_reg),
        .I1(pi_fine_dly_dec_done_reg_0),
        .I2(dqs_po_dec_done_r1_reg_0),
        .O(p_1_in));
  LUT5 #(
    .INIT(32'h00008000)) 
    detect_edge_done_r_i_1
       (.I0(pb_detect_edge_done_r[6]),
        .I1(pb_detect_edge_done_r[7]),
        .I2(pb_detect_edge_done_r[4]),
        .I3(pb_detect_edge_done_r[5]),
        .I4(detect_edge_done_r_i_2_n_0),
        .O(detect_edge_done_r_i_1_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    detect_edge_done_r_i_2
       (.I0(pb_detect_edge_done_r[1]),
        .I1(pb_detect_edge_done_r[0]),
        .I2(pb_detect_edge_done_r[3]),
        .I3(pb_detect_edge_done_r[2]),
        .O(detect_edge_done_r_i_2_n_0));
  FDRE detect_edge_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(detect_edge_done_r_i_1_n_0),
        .Q(detect_edge_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000005554)) 
    \done_cnt[0]_i_1 
       (.I0(done_cnt[0]),
        .I1(done_cnt[3]),
        .I2(done_cnt[1]),
        .I3(done_cnt[2]),
        .I4(done_cnt1),
        .I5(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .O(\done_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT5 #(
    .INIT(32'hFAAFFAAE)) 
    \done_cnt[1]_i_1 
       (.I0(done_cnt1),
        .I1(done_cnt[3]),
        .I2(done_cnt[1]),
        .I3(done_cnt[0]),
        .I4(done_cnt[2]),
        .O(\done_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000A9A8)) 
    \done_cnt[2]_i_1 
       (.I0(done_cnt[2]),
        .I1(done_cnt[0]),
        .I2(done_cnt[1]),
        .I3(done_cnt[3]),
        .I4(done_cnt1),
        .I5(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .O(\done_cnt[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT5 #(
    .INIT(32'hEEEEEEEA)) 
    \done_cnt[3]_i_1 
       (.I0(done_cnt1),
        .I1(done_cnt[3]),
        .I2(done_cnt[1]),
        .I3(done_cnt[0]),
        .I4(done_cnt[2]),
        .O(\done_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT4 #(
    .INIT(16'h888F)) 
    \done_cnt[3]_i_2 
       (.I0(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I1(p_0_in118_in),
        .I2(\done_cnt[3]_i_3_n_0 ),
        .I3(rdlvl_stg1_done_int),
        .O(done_cnt1));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT4 #(
    .INIT(16'hFFFD)) 
    \done_cnt[3]_i_3 
       (.I0(done_cnt[0]),
        .I1(done_cnt[1]),
        .I2(done_cnt[2]),
        .I3(done_cnt[3]),
        .O(\done_cnt[3]_i_3_n_0 ));
  FDRE \done_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\done_cnt[0]_i_1_n_0 ),
        .Q(done_cnt[0]),
        .R(1'b0));
  FDRE \done_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\done_cnt[1]_i_1_n_0 ),
        .Q(done_cnt[1]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [0]));
  FDRE \done_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\done_cnt[2]_i_1_n_0 ),
        .Q(done_cnt[2]),
        .R(1'b0));
  FDRE \done_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\done_cnt[3]_i_1_n_0 ),
        .Q(done_cnt[3]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [0]));
  FDRE dqs_po_dec_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_po_dec_done_r1_reg_0),
        .Q(dqs_po_dec_done_r1),
        .R(1'b0));
  FDRE dqs_po_dec_done_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_po_dec_done_r1),
        .Q(dqs_po_dec_done_r2),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF22F2)) 
    fine_dly_dec_done_r1_i_1
       (.I0(pi_cnt_dec_reg_0),
        .I1(fine_dly_dec_done_r1_i_2_n_0),
        .I2(dqs_po_dec_done_r2),
        .I3(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I4(fine_dly_dec_done_r1),
        .O(fine_dly_dec_done_r1_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    fine_dly_dec_done_r1_i_2
       (.I0(pi_rdval_cnt[4]),
        .I1(pi_rdval_cnt[5]),
        .I2(pi_rdval_cnt[1]),
        .I3(pi_rdval_cnt[0]),
        .I4(pi_rdval_cnt[2]),
        .I5(pi_rdval_cnt[3]),
        .O(fine_dly_dec_done_r1_i_2_n_0));
  FDRE fine_dly_dec_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(fine_dly_dec_done_r1_i_1_n_0),
        .Q(fine_dly_dec_done_r1),
        .R(found_first_edge_r_reg_0));
  FDRE fine_dly_dec_done_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(fine_dly_dec_done_r1),
        .Q(fine_dly_dec_done_r2),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h4)) 
    \first_edge_taps_r[5]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(cal1_prech_req_r),
        .O(\first_edge_taps_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0000FFFF0080)) 
    \first_edge_taps_r[5]_i_2 
       (.I0(found_edge_r_reg_n_0),
        .I1(store_sr_req_pulsed_r),
        .I2(detect_edge_done_r),
        .I3(tap_limit_cpt_r),
        .I4(cal1_prech_req_r),
        .I5(\first_edge_taps_r[5]_i_3_n_0 ),
        .O(\first_edge_taps_r[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \first_edge_taps_r[5]_i_3 
       (.I0(found_first_edge_r_reg_n_0),
        .I1(found_stable_eye_last_r),
        .O(\first_edge_taps_r[5]_i_3_n_0 ));
  FDRE \first_edge_taps_r_reg[0] 
       (.C(CLK),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\first_edge_taps_r_reg_n_0_[0] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[1] 
       (.C(CLK),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\first_edge_taps_r_reg_n_0_[1] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[2] 
       (.C(CLK),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\first_edge_taps_r_reg_n_0_[2] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[3] 
       (.C(CLK),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\first_edge_taps_r_reg_n_0_[3] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[4] 
       (.C(CLK),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\first_edge_taps_r_reg_n_0_[4] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[5] 
       (.C(CLK),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\first_edge_taps_r_reg_n_0_[5] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    found_edge_r_i_1
       (.I0(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .I1(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .I2(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .I3(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .I4(found_edge_r_i_2_n_0),
        .O(found_edge_r_i_1_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    found_edge_r_i_2
       (.I0(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .I1(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .I2(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .I3(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .O(found_edge_r_i_2_n_0));
  FDRE found_edge_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(found_edge_r_i_1_n_0),
        .Q(found_edge_r_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFF555555BA000000)) 
    found_first_edge_r_i_1
       (.I0(cal1_prech_req_r),
        .I1(tap_limit_cpt_r),
        .I2(detect_edge_done_r),
        .I3(store_sr_req_pulsed_r),
        .I4(found_edge_r_reg_n_0),
        .I5(found_first_edge_r_reg_n_0),
        .O(found_first_edge_r_i_1_n_0));
  FDRE found_first_edge_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(found_first_edge_r_i_1_n_0),
        .Q(found_first_edge_r_reg_n_0),
        .R(found_first_edge_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT5 #(
    .INIT(32'h80FF8000)) 
    found_second_edge_r_i_1
       (.I0(store_sr_req_pulsed_r),
        .I1(found_stable_eye_last_r),
        .I2(found_first_edge_r_reg_n_0),
        .I3(\second_edge_taps_r[5]_i_2_n_0 ),
        .I4(found_second_edge_r_reg_n_0),
        .O(found_second_edge_r_i_1_n_0));
  FDRE found_second_edge_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(found_second_edge_r_i_1_n_0),
        .Q(found_second_edge_r_reg_n_0),
        .R(in0));
  LUT3 #(
    .INIT(8'hB8)) 
    found_stable_eye_last_r_i_1
       (.I0(found_stable_eye_r_reg_n_0),
        .I1(detect_edge_done_r),
        .I2(found_stable_eye_last_r),
        .O(found_stable_eye_last_r_i_1_n_0));
  FDRE found_stable_eye_last_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(found_stable_eye_last_r_i_1_n_0),
        .Q(found_stable_eye_last_r),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT5 #(
    .INIT(32'h00008000)) 
    found_stable_eye_r_i_1
       (.I0(pb_found_stable_eye_r[2]),
        .I1(pb_found_stable_eye_r[3]),
        .I2(pb_found_stable_eye_r[0]),
        .I3(pb_found_stable_eye_r[1]),
        .I4(found_stable_eye_r_i_2_n_0),
        .O(found_stable_eye_r_i_1_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    found_stable_eye_r_i_2
       (.I0(pb_found_stable_eye_r[5]),
        .I1(pb_found_stable_eye_r[4]),
        .I2(pb_found_stable_eye_r[7]),
        .I3(pb_found_stable_eye_r[6]),
        .O(found_stable_eye_r_i_2_n_0));
  FDRE found_stable_eye_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(found_stable_eye_r_i_1_n_0),
        .Q(found_stable_eye_r_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h2F202F2F2F202020)) 
    \gen_byte_sel_div2.byte_sel_cnt[0]_i_2 
       (.I0(Q[0]),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I2(D[3]),
        .I3(regl_dqs_cnt_r[0]),
        .I4(p_0_in118_in),
        .I5(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .O(\po_stg2_wrcal_cnt_reg[0] ));
  LUT5 #(
    .INIT(32'h2F202020)) 
    \gen_byte_sel_div2.byte_sel_cnt[1]_i_3 
       (.I0(Q[1]),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I2(D[3]),
        .I3(p_0_in118_in),
        .I4(regl_dqs_cnt_r[1]),
        .O(\po_stg2_wrcal_cnt_reg[1] ));
  FDRE \gen_mux_rd[0].mux_rd_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r[0][0]_i_1 
       (.I0(store_sr_r_reg_n_0),
        .I1(sr_valid_r_reg_n_0),
        .O(store_sr_r0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_139 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_155 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_163 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_187 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_171 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_147 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_179 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_195 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_75 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_107 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_131 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_123 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_91 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_99 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_115 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_83 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_140 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_156 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_164 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_188 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_172 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_148 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_180 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_196 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_76 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_108 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_132 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_124 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_92 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_100 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_116 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_84 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_141 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_157 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_165 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_189 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_173 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_149 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_181 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_197 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_77 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_109 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_133 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_125 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_93 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_101 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_117 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_85 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_142 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_158 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_166 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_190 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_174 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_150 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_182 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_198 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_78 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_110 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_134 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_126 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_94 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_102 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_118 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_86 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_143 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_159 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_167 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_191 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_175 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_151 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_183 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_199 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_79 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_111 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_135 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_127 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_95 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_103 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_119 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_87 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_144 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_160 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_168 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_192 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_176 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_152 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_184 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_200 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_80 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_112 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_136 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_128 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_96 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_104 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_120 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_88 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_145 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_161 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_169 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_193 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_177 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_153 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_185 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_201 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_81 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_113 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_137 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_129 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_97 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_105 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_121 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_89 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_146 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_162 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_170 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_194 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_178 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_154 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_186 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0] 
       (.C(CLK),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_202 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_82 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_114 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_138 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_130 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_98 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_106 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_122 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7][0] 
       (.C(CLK),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_90 ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ),
        .Q(pat0_match_fall2_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67 ),
        .Q(pat0_match_fall3_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35 ),
        .Q(pat0_match_rise0_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ),
        .Q(pat0_match_rise1_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27 ),
        .Q(pat0_match_fall1_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19 ),
        .Q(idel_pat1_match_rise1_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59 ),
        .Q(pat0_match_rise3_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ),
        .Q(pat0_match_fall0_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12 ),
        .Q(pat0_match_fall0_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ),
        .Q(pat0_match_fall1_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20 ),
        .Q(idel_pat1_match_rise1_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ),
        .Q(pat0_match_fall2_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52 ),
        .Q(pat0_match_rise2_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36 ),
        .Q(pat0_match_rise0_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ),
        .Q(pat0_match_rise1_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60 ),
        .Q(pat0_match_rise3_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13 ),
        .Q(pat0_match_fall0_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21 ),
        .Q(pat0_match_rise1_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61 ),
        .Q(idel_pat0_match_rise3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45 ),
        .Q(pat0_match_fall2_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37 ),
        .Q(pat0_match_rise0_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ),
        .Q(pat0_match_rise3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ),
        .Q(pat0_match_fall1_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30 ),
        .Q(pat0_match_fall1_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ),
        .Q(pat0_match_fall2_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ),
        .Q(pat0_match_rise0_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22 ),
        .Q(pat0_match_rise1_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14 ),
        .Q(pat0_match_fall0_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62 ),
        .Q(pat0_match_rise3_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ),
        .Q(pat0_match_fall2_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71 ),
        .Q(pat0_match_fall3_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39 ),
        .Q(pat0_match_rise0_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ),
        .Q(pat0_match_rise1_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31 ),
        .Q(pat0_match_fall1_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23 ),
        .Q(idel_pat1_match_rise1_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63 ),
        .Q(pat0_match_rise3_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ),
        .Q(pat0_match_fall0_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16 ),
        .Q(pat0_match_fall0_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ),
        .Q(pat0_match_fall1_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24 ),
        .Q(idel_pat1_match_rise1_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ),
        .Q(pat0_match_fall2_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56 ),
        .Q(pat0_match_rise2_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40 ),
        .Q(pat0_match_rise0_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ),
        .Q(pat0_match_rise1_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64 ),
        .Q(pat0_match_rise3_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17 ),
        .Q(pat0_match_fall0_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25 ),
        .Q(pat0_match_rise1_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65 ),
        .Q(idel_pat0_match_rise3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49 ),
        .Q(pat0_match_fall2_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41 ),
        .Q(pat0_match_rise0_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ),
        .Q(pat0_match_rise3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ),
        .Q(pat0_match_fall1_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34 ),
        .Q(pat0_match_fall1_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ),
        .Q(pat0_match_fall2_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ),
        .Q(pat0_match_rise0_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26 ),
        .Q(pat0_match_rise1_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18 ),
        .Q(pat0_match_fall0_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66 ),
        .Q(pat0_match_rise3_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.idel_pat0_data_match_r_i_1 
       (.I0(idel_pat0_match_rise1_and_r),
        .I1(idel_pat0_match_rise0_and_r),
        .I2(idel_pat0_match_fall3_and_r),
        .I3(idel_pat0_match_fall0_and_r),
        .I4(\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ),
        .O(idel_pat0_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.idel_pat0_data_match_r_i_2 
       (.I0(idel_pat0_match_rise3_and_r),
        .I1(idel_pat0_match_fall1_and_r),
        .I2(idel_pat0_match_fall2_and_r),
        .I3(idel_pat0_match_rise2_and_r),
        .O(\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(idel_pat0_data_match_r0),
        .Q(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),
        .I2(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ),
        .I3(pat0_match_fall0_r[2]),
        .I4(pat0_match_fall0_r[5]),
        .I5(pat0_match_fall0_r[6]),
        .O(\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_fall0_and_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ),
        .I2(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ),
        .I3(pat0_match_fall1_r[1]),
        .I4(pat0_match_fall1_r[5]),
        .I5(pat0_match_fall1_r[7]),
        .O(\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_fall1_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ),
        .I1(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ),
        .I2(pat0_match_fall2_r[3]),
        .O(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ),
        .I2(pat0_match_fall2_r[0]),
        .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ),
        .I4(pat0_match_fall2_r[4]),
        .I5(pat0_match_fall2_r[7]),
        .O(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ),
        .I2(pat0_match_fall3_r[6]),
        .I3(pat0_match_fall3_r[4]),
        .I4(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2 
       (.I0(pat0_match_fall3_r[0]),
        .I1(pat0_match_fall3_r[2]),
        .I2(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ),
        .O(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ),
        .I3(pat0_match_rise0_r[7]),
        .I4(pat0_match_rise0_r[3]),
        .O(\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ),
        .I1(idel_pat1_match_rise1_r[5]),
        .I2(idel_pat1_match_rise1_r[1]),
        .I3(pat0_match_rise1_r[4]),
        .I4(pat0_match_rise1_r[0]),
        .O(\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_rise1_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1 
       (.I0(pat0_match_rise2_r[6]),
        .I1(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ),
        .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),
        .O(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ),
        .I3(pat0_match_rise2_r[2]),
        .I4(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ),
        .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ),
        .O(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ),
        .I1(idel_pat0_match_rise3_r[6]),
        .I2(idel_pat0_match_rise3_r[2]),
        .I3(idel_pat0_match_rise3_r[5]),
        .I4(idel_pat0_match_rise3_r[1]),
        .O(\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.idel_pat1_data_match_r_i_1 
       (.I0(idel_pat1_match_fall0_and_r),
        .I1(idel_pat1_match_rise1_and_r),
        .I2(idel_pat1_match_rise3_and_r),
        .I3(idel_pat1_match_fall2_and_r),
        .I4(\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ),
        .O(idel_pat1_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.idel_pat1_data_match_r_i_2 
       (.I0(idel_pat1_match_rise2_and_r),
        .I1(idel_pat1_match_fall1_and_r),
        .I2(idel_pat1_match_rise0_and_r),
        .I3(idel_pat1_match_fall3_and_r),
        .O(\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(idel_pat1_data_match_r0),
        .Q(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ),
        .I1(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ),
        .I2(pat0_match_fall0_r[7]),
        .O(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg ),
        .I1(pat0_match_fall0_r[3]),
        .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ),
        .I5(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_fall0_and_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),
        .I1(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ),
        .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2 
       (.I0(pat0_match_fall1_r[4]),
        .I1(pat0_match_fall1_r[0]),
        .I2(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ),
        .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1 
       (.I0(pat0_match_fall2_r[6]),
        .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ),
        .I2(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ),
        .I3(pat0_match_fall2_r[5]),
        .I4(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ),
        .I1(idel_pat1_match_rise1_r[6]),
        .I2(idel_pat1_match_rise1_r[2]),
        .I3(idel_pat1_match_rise1_r[7]),
        .I4(idel_pat1_match_rise1_r[3]),
        .O(\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_and_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ),
        .I1(pat0_match_rise2_r[4]),
        .I2(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ),
        .I3(pat0_match_rise2_r[1]),
        .I4(pat0_match_rise2_r[5]),
        .I5(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ),
        .I1(idel_pat0_match_rise3_r[5]),
        .I2(idel_pat0_match_rise3_r[1]),
        .I3(pat0_match_rise3_r[6]),
        .I4(pat0_match_rise3_r[2]),
        .O(\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_rise3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat0_data_match_r_i_1 
       (.I0(pat0_match_rise2_and_r),
        .I1(pat0_match_fall2_and_r),
        .I2(pat0_match_fall3_and_r),
        .I3(pat0_match_rise3_and_r),
        .I4(\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ),
        .O(pat0_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.pat0_data_match_r_i_2 
       (.I0(pat0_match_fall1_and_r),
        .I1(pat0_match_rise0_and_r),
        .I2(pat0_match_fall0_and_r),
        .I3(pat0_match_rise1_and_r),
        .O(\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pat0_data_match_r0),
        .Q(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat0_match_fall0_and_r_i_1 
       (.I0(pat0_match_fall0_r[6]),
        .I1(\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ),
        .I2(pat0_match_fall0_r[7]),
        .O(\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat0_match_fall0_and_r_i_2 
       (.I0(pat0_match_fall0_r[4]),
        .I1(pat0_match_fall0_r[2]),
        .I2(pat0_match_fall0_r[0]),
        .I3(pat0_match_fall0_r[1]),
        .I4(pat0_match_fall0_r[3]),
        .I5(pat0_match_fall0_r[5]),
        .O(\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ),
        .Q(pat0_match_fall0_and_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat0_match_fall1_and_r_i_1 
       (.I0(pat0_match_fall1_r[6]),
        .I1(\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ),
        .I2(pat0_match_fall1_r[7]),
        .O(\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat0_match_fall1_and_r_i_2 
       (.I0(pat0_match_fall1_r[4]),
        .I1(pat0_match_fall1_r[1]),
        .I2(pat0_match_fall1_r[3]),
        .I3(pat0_match_fall1_r[2]),
        .I4(pat0_match_fall1_r[0]),
        .I5(pat0_match_fall1_r[5]),
        .O(\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ),
        .Q(pat0_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_fall2_and_r_i_1 
       (.I0(pat0_match_fall2_r[7]),
        .I1(pat0_match_fall2_r[5]),
        .I2(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ),
        .I3(pat0_match_fall2_r[6]),
        .I4(pat0_match_fall2_r[3]),
        .O(\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_fall2_and_r_i_2 
       (.I0(pat0_match_fall2_r[2]),
        .I1(pat0_match_fall2_r[1]),
        .I2(pat0_match_fall2_r[0]),
        .I3(pat0_match_fall2_r[4]),
        .O(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ),
        .Q(pat0_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ),
        .I1(pat0_match_fall3_r[4]),
        .I2(pat0_match_fall3_r[1]),
        .I3(pat0_match_fall3_r[5]),
        .I4(pat0_match_fall3_r[0]),
        .O(\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_fall3_and_r_i_2 
       (.I0(pat0_match_fall3_r[2]),
        .I1(pat0_match_fall3_r[7]),
        .I2(pat0_match_fall3_r[3]),
        .I3(pat0_match_fall3_r[6]),
        .O(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ),
        .Q(pat0_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ),
        .I1(pat0_match_rise0_r[5]),
        .I2(pat0_match_rise0_r[1]),
        .I3(pat0_match_rise0_r[4]),
        .I4(pat0_match_rise0_r[0]),
        .O(\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_rise0_and_r_i_2 
       (.I0(pat0_match_rise0_r[2]),
        .I1(pat0_match_rise0_r[6]),
        .I2(pat0_match_rise0_r[3]),
        .I3(pat0_match_rise0_r[7]),
        .O(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ),
        .Q(pat0_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ),
        .I1(pat0_match_rise1_r[5]),
        .I2(pat0_match_rise1_r[1]),
        .I3(pat0_match_rise1_r[4]),
        .I4(pat0_match_rise1_r[0]),
        .O(\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_rise1_and_r_i_2 
       (.I0(pat0_match_rise1_r[3]),
        .I1(pat0_match_rise1_r[7]),
        .I2(pat0_match_rise1_r[2]),
        .I3(pat0_match_rise1_r[6]),
        .O(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ),
        .Q(pat0_match_rise1_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat0_match_rise2_and_r_i_1 
       (.I0(pat0_match_rise2_r[7]),
        .I1(\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ),
        .I2(pat0_match_rise2_r[6]),
        .O(\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat0_match_rise2_and_r_i_2 
       (.I0(pat0_match_rise2_r[4]),
        .I1(pat0_match_rise2_r[2]),
        .I2(pat0_match_rise2_r[0]),
        .I3(pat0_match_rise2_r[1]),
        .I4(pat0_match_rise2_r[3]),
        .I5(pat0_match_rise2_r[5]),
        .O(\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ),
        .Q(pat0_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_rise3_and_r_i_1 
       (.I0(pat0_match_rise3_r[6]),
        .I1(pat0_match_rise3_r[2]),
        .I2(pat0_match_rise3_r[5]),
        .I3(pat0_match_rise3_r[1]),
        .I4(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_rise3_and_r_i_2 
       (.I0(pat0_match_rise3_r[3]),
        .I1(pat0_match_rise3_r[7]),
        .I2(pat0_match_rise3_r[0]),
        .I3(pat0_match_rise3_r[4]),
        .O(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ),
        .Q(pat0_match_rise3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat1_data_match_r_i_1 
       (.I0(pat1_match_rise0_and_r),
        .I1(pat1_match_rise3_and_r),
        .I2(pat1_match_fall3_and_r),
        .I3(pat1_match_rise2_and_r),
        .I4(\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ),
        .O(pat1_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.pat1_data_match_r_i_2 
       (.I0(pat1_match_fall1_and_r),
        .I1(pat1_match_fall2_and_r),
        .I2(pat1_match_fall0_and_r),
        .I3(pat1_match_rise1_and_r),
        .O(\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pat1_data_match_r0),
        .Q(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat1_match_fall0_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),
        .I2(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ),
        .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ),
        .I4(pat0_match_fall0_r[5]),
        .I5(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat1_match_fall0_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ),
        .I1(pat0_match_fall0_r[1]),
        .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ),
        .Q(pat1_match_fall0_and_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat1_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ),
        .I2(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ),
        .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ),
        .I5(pat0_match_fall1_r[7]),
        .O(\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat1_match_fall1_and_r_i_2 
       (.I0(pat0_match_fall1_r[3]),
        .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ),
        .Q(pat1_match_fall1_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat1_match_fall2_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ),
        .I1(\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ),
        .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat1_match_fall2_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ),
        .I2(pat0_match_fall2_r[1]),
        .I3(\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ),
        .I5(pat0_match_fall2_r[5]),
        .O(\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ),
        .Q(pat1_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat1_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ),
        .I2(pat0_match_fall3_r[7]),
        .I3(pat0_match_fall3_r[5]),
        .I4(\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.pat1_match_fall3_and_r_i_2 
       (.I0(pat0_match_fall3_r[1]),
        .I1(pat0_match_fall3_r[3]),
        .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ),
        .Q(pat1_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat1_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat1_match_rise0_and_r_i_2 
       (.I0(pat0_match_rise0_r[0]),
        .I1(pat0_match_rise0_r[4]),
        .I2(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ),
        .Q(pat1_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat1_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ),
        .I1(idel_pat1_match_rise1_r[7]),
        .I2(idel_pat1_match_rise1_r[3]),
        .I3(pat0_match_rise1_r[6]),
        .I4(pat0_match_rise1_r[2]),
        .O(\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat1_match_rise1_and_r_i_2 
       (.I0(idel_pat1_match_rise1_r[0]),
        .I1(idel_pat1_match_rise1_r[4]),
        .I2(idel_pat1_match_rise1_r[1]),
        .I3(idel_pat1_match_rise1_r[5]),
        .O(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ),
        .Q(pat1_match_rise1_and_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat1_match_rise2_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ),
        .I1(pat0_match_rise2_r[4]),
        .I2(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ),
        .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ),
        .I5(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat1_match_rise2_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ),
        .I2(pat0_match_rise2_r[0]),
        .O(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ),
        .Q(pat1_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat1_match_rise3_and_r_i_1 
       (.I0(pat0_match_rise3_r[6]),
        .I1(pat0_match_rise3_r[2]),
        .I2(pat0_match_rise3_r[5]),
        .I3(pat0_match_rise3_r[1]),
        .I4(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat1_match_rise3_and_r_i_2 
       (.I0(idel_pat0_match_rise3_r[4]),
        .I1(idel_pat0_match_rise3_r[7]),
        .I2(idel_pat0_match_rise3_r[0]),
        .I3(idel_pat0_match_rise3_r[3]),
        .O(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ),
        .Q(pat1_match_rise3_and_r),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7][0] 
       (.C(CLK),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66 ),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ),
        .I2(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ),
        .I4(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2 
       (.I0(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ),
        .I2(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_139 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_155 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_163 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_187 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_171 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_147 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_179 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_195 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1 
       (.I0(sr_valid_r2),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ),
        .I2(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ),
        .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2 
       (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ),
        .I2(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_11 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_75 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_27 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_107 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_43 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_131 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_67 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_123 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_35 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_91 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_19 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_99 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_51 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_115 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_59 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_83 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_diff_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg ),
        .Q(p_1_in29_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_1 
       (.I0(p_7_in222_in),
        .I1(p_5_in220_in),
        .I2(p_6_in221_in),
        .I3(p_1_in223_in),
        .I4(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2 
       (.I0(p_3_in218_in),
        .I1(p_4_in219_in),
        .I2(p_0_in216_in),
        .I3(p_2_in217_in),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_140 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ),
        .Q(p_0_in216_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_156 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ),
        .Q(p_3_in218_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_164 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ),
        .Q(p_5_in220_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_188 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ),
        .Q(p_7_in222_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_172 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ),
        .Q(p_1_in223_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_148 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ),
        .Q(p_2_in217_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_180 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ),
        .Q(p_4_in219_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_196 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ),
        .Q(p_6_in221_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_diff_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg ),
        .Q(p_0_in103_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_1 
       (.I0(p_2_in225_in),
        .I1(p_0_in224_in),
        .I2(p_6_in229_in),
        .I3(p_3_in226_in),
        .I4(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2 
       (.I0(p_7_in230_in),
        .I1(p_1_in231_in),
        .I2(p_4_in227_in),
        .I3(p_5_in228_in),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_12 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_76 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ),
        .Q(p_0_in224_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_28 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_108 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ),
        .Q(p_3_in226_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_44 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_132 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ),
        .Q(p_5_in228_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_68 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_124 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ),
        .Q(p_7_in230_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_36 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_92 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ),
        .Q(p_1_in231_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_20 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_100 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ),
        .Q(p_2_in225_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_52 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_116 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ),
        .Q(p_4_in227_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_60 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_84 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ),
        .Q(p_6_in229_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_diff_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg ),
        .Q(p_1_in26_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_1 
       (.I0(p_7_in206_in),
        .I1(p_5_in204_in),
        .I2(p_6_in205_in),
        .I3(p_1_in207_in),
        .I4(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2 
       (.I0(p_3_in202_in),
        .I1(p_4_in203_in),
        .I2(p_0_in200_in),
        .I3(p_2_in201_in),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_141 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ),
        .Q(p_0_in200_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_157 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ),
        .Q(p_3_in202_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_165 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ),
        .Q(p_5_in204_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_189 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ),
        .Q(p_7_in206_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_173 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ),
        .Q(p_1_in207_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_149 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ),
        .Q(p_2_in201_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_181 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ),
        .Q(p_4_in203_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_197 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ),
        .Q(p_6_in205_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_diff_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg ),
        .Q(p_0_in100_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_1 
       (.I0(p_7_in214_in),
        .I1(p_5_in212_in),
        .I2(p_6_in213_in),
        .I3(p_1_in215_in),
        .I4(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2 
       (.I0(p_3_in210_in),
        .I1(p_4_in211_in),
        .I2(p_0_in208_in),
        .I3(p_2_in209_in),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_13 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_77 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ),
        .Q(p_0_in208_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_29 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_109 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ),
        .Q(p_3_in210_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_45 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_133 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ),
        .Q(p_5_in212_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_69 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_125 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ),
        .Q(p_7_in214_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_37 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_93 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ),
        .Q(p_1_in215_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_21 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_101 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ),
        .Q(p_2_in209_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_53 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_117 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ),
        .Q(p_4_in211_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_61 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_85 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ),
        .Q(p_6_in213_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_diff_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg ),
        .Q(p_1_in23_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_1 
       (.I0(p_7_in190_in),
        .I1(p_4_in187_in),
        .I2(p_0_in184_in),
        .I3(p_1_in191_in),
        .I4(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2 
       (.I0(p_2_in185_in),
        .I1(p_3_in186_in),
        .I2(p_5_in188_in),
        .I3(p_6_in189_in),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_142 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ),
        .Q(p_0_in184_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_158 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ),
        .Q(p_3_in186_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_166 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ),
        .Q(p_5_in188_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_190 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ),
        .Q(p_7_in190_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_174 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ),
        .Q(p_1_in191_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_150 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ),
        .Q(p_2_in185_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_182 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ),
        .Q(p_4_in187_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_198 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ),
        .Q(p_6_in189_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_diff_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg ),
        .Q(p_0_in97_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_1 
       (.I0(p_4_in195_in),
        .I1(p_7_in198_in),
        .I2(p_6_in197_in),
        .I3(p_1_in199_in),
        .I4(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2 
       (.I0(p_3_in194_in),
        .I1(p_5_in196_in),
        .I2(p_0_in192_in),
        .I3(p_2_in193_in),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_14 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_78 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ),
        .Q(p_0_in192_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_30 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_110 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ),
        .Q(p_3_in194_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_46 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_134 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ),
        .Q(p_5_in196_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_70 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_126 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ),
        .Q(p_7_in198_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_38 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_94 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ),
        .Q(p_1_in199_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_22 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_102 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ),
        .Q(p_2_in193_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_54 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_118 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ),
        .Q(p_4_in195_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_62 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_86 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ),
        .Q(p_6_in197_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_diff_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg ),
        .Q(p_1_in20_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_1 
       (.I0(p_6_in173_in),
        .I1(p_5_in172_in),
        .I2(p_7_in174_in),
        .I3(p_1_in175_in),
        .I4(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2 
       (.I0(p_3_in170_in),
        .I1(p_4_in171_in),
        .I2(p_0_in168_in),
        .I3(p_2_in169_in),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_143 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ),
        .Q(p_0_in168_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_159 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ),
        .Q(p_3_in170_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_167 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ),
        .Q(p_5_in172_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_191 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ),
        .Q(p_7_in174_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_175 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ),
        .Q(p_1_in175_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_151 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ),
        .Q(p_2_in169_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_183 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ),
        .Q(p_4_in171_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_199 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ),
        .Q(p_6_in173_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_diff_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg ),
        .Q(p_0_in94_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_1 
       (.I0(p_6_in181_in),
        .I1(p_5_in180_in),
        .I2(p_7_in182_in),
        .I3(p_1_in183_in),
        .I4(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2 
       (.I0(p_3_in178_in),
        .I1(p_4_in179_in),
        .I2(p_0_in176_in),
        .I3(p_2_in177_in),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_15 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_79 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ),
        .Q(p_0_in176_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_31 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_111 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ),
        .Q(p_3_in178_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_47 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_135 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ),
        .Q(p_5_in180_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_71 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_127 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ),
        .Q(p_7_in182_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_39 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_95 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ),
        .Q(p_1_in183_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_23 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_103 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ),
        .Q(p_2_in177_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_55 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_119 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ),
        .Q(p_4_in179_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_63 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_87 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ),
        .Q(p_6_in181_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_diff_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg ),
        .Q(p_1_in17_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_1 
       (.I0(p_7_in158_in),
        .I1(p_6_in157_in),
        .I2(p_0_in152_in),
        .I3(p_1_in159_in),
        .I4(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2 
       (.I0(p_4_in155_in),
        .I1(p_5_in156_in),
        .I2(p_2_in153_in),
        .I3(p_3_in154_in),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_144 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ),
        .Q(p_0_in152_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_160 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ),
        .Q(p_3_in154_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_168 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ),
        .Q(p_5_in156_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_192 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ),
        .Q(p_7_in158_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_176 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ),
        .Q(p_1_in159_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_152 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ),
        .Q(p_2_in153_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_184 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ),
        .Q(p_4_in155_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_200 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ),
        .Q(p_6_in157_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_diff_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg ),
        .Q(p_0_in91_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_1 
       (.I0(p_7_in166_in),
        .I1(p_6_in165_in),
        .I2(p_0_in160_in),
        .I3(p_1_in167_in),
        .I4(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2 
       (.I0(p_4_in163_in),
        .I1(p_5_in164_in),
        .I2(p_2_in161_in),
        .I3(p_3_in162_in),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_16 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_80 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ),
        .Q(p_0_in160_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_32 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_112 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ),
        .Q(p_3_in162_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_48 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_136 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ),
        .Q(p_5_in164_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_72 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_128 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ),
        .Q(p_7_in166_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_40 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_96 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ),
        .Q(p_1_in167_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_24 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_104 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ),
        .Q(p_2_in161_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_56 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_120 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ),
        .Q(p_4_in163_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_64 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_88 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ),
        .Q(p_6_in165_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_diff_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg ),
        .Q(p_1_in14_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_1 
       (.I0(p_7_in142_in),
        .I1(p_6_in141_in),
        .I2(p_0_in136_in),
        .I3(p_1_in143_in),
        .I4(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2 
       (.I0(p_4_in139_in),
        .I1(p_5_in140_in),
        .I2(p_2_in137_in),
        .I3(p_3_in138_in),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_145 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ),
        .Q(p_0_in136_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_161 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ),
        .Q(p_3_in138_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_169 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ),
        .Q(p_5_in140_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_193 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ),
        .Q(p_7_in142_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_177 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ),
        .Q(p_1_in143_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_153 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ),
        .Q(p_2_in137_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_185 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ),
        .Q(p_4_in139_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_201 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ),
        .Q(p_6_in141_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_diff_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg ),
        .Q(p_0_in88_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_1 
       (.I0(p_7_in150_in),
        .I1(p_6_in149_in),
        .I2(p_0_in144_in),
        .I3(p_1_in151_in),
        .I4(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2 
       (.I0(p_4_in147_in),
        .I1(p_5_in148_in),
        .I2(p_2_in145_in),
        .I3(p_3_in146_in),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_17 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_81 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ),
        .Q(p_0_in144_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_33 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_113 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ),
        .Q(p_3_in146_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_49 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_137 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ),
        .Q(p_5_in148_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_73 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_129 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ),
        .Q(p_7_in150_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_41 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_97 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ),
        .Q(p_1_in151_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_25 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_105 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ),
        .Q(p_2_in145_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_57 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_121 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ),
        .Q(p_4_in147_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_65 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_89 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ),
        .Q(p_6_in149_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg ),
        .Q(p_1_in12_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_1 
       (.I0(p_7_in),
        .I1(p_6_in126_in),
        .I2(p_0_in125_in),
        .I3(p_1_in127_in),
        .I4(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2 
       (.I0(p_4_in),
        .I1(p_5_in),
        .I2(p_2_in),
        .I3(p_3_in),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_146 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ),
        .Q(p_0_in125_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_162 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ),
        .Q(p_3_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_170 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ),
        .Q(p_5_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_194 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ),
        .Q(p_7_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_178 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ),
        .Q(p_1_in127_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_154 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ),
        .Q(p_2_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_186 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ),
        .Q(p_4_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_202 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ),
        .Q(p_6_in126_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg ),
        .Q(p_0_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_1 
       (.I0(p_7_in134_in),
        .I1(p_6_in133_in),
        .I2(p_0_in128_in),
        .I3(p_1_in135_in),
        .I4(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2 
       (.I0(p_4_in131_in),
        .I1(p_5_in132_in),
        .I2(p_2_in129_in),
        .I3(p_3_in130_in),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_18 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_82 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ),
        .Q(p_0_in128_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_34 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_114 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ),
        .Q(p_3_in130_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_50 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_138 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ),
        .Q(p_5_in132_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_74 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_130 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ),
        .Q(p_7_in134_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_42 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_98 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ),
        .Q(p_1_in135_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_26 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_106 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ),
        .Q(p_2_in129_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_58 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_122 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ),
        .Q(p_4_in131_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_66 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_90 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ),
        .Q(p_6_in133_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [0]),
        .O(p_0_in__2[0]));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [0]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [1]),
        .O(p_0_in__2[1]));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [2]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [1]),
        .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [0]),
        .O(p_0_in__2[2]));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [3]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [0]),
        .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [1]),
        .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [2]),
        .O(p_0_in__2[3]));
  LUT4 #(
    .INIT(16'hFEAA)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(store_sr_req_pulsed_r),
        .I2(p_37_in),
        .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h22200000)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[0]),
        .I2(p_37_in),
        .I3(store_sr_req_pulsed_r),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(pb_cnt_eye_size_r));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [4]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [2]),
        .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [1]),
        .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [0]),
        .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [3]),
        .O(p_0_in__2[4]));
  LUT6 #(
    .INIT(64'h0F0F0F000F0E0F0E)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4 
       (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),
        .I2(pb_detect_edge_done_r[0]),
        .I3(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I4(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT5 #(
    .INIT(32'hBFFFFFFF)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [4]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [2]),
        .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [1]),
        .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [0]),
        .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [3]),
        .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][0] 
       (.C(CLK),
        .CE(pb_cnt_eye_size_r),
        .D(p_0_in__2[0]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [0]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][1] 
       (.C(CLK),
        .CE(pb_cnt_eye_size_r),
        .D(p_0_in__2[1]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [1]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][2] 
       (.C(CLK),
        .CE(pb_cnt_eye_size_r),
        .D(p_0_in__2[2]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [2]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][3] 
       (.C(CLK),
        .CE(pb_cnt_eye_size_r),
        .D(p_0_in__2[3]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [3]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][4] 
       (.C(CLK),
        .CE(pb_cnt_eye_size_r),
        .D(p_0_in__2[4]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_203 [4]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1 
       (.I0(p_37_in),
        .I1(store_sr_req_pulsed_r),
        .I2(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(pb_detect_edge_done_r[0]),
        .O(\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_detect_edge_done_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[0]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5050505050505551)) 
    \gen_track_left_edge[0].pb_found_edge_r[0]_i_1 
       (.I0(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .I3(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I4(pb_detect_edge_done_r[0]),
        .I5(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4_n_0 ),
        .O(\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_found_edge_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ),
        .Q(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'hFFFFFFFA00000002)) 
    \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1 
       (.I0(pb_found_stable_eye_r77_out),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(pb_detect_edge_done_r[0]),
        .I4(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4_n_0 ),
        .I5(pb_found_stable_eye_r[0]),
        .O(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .O(pb_found_stable_eye_r77_out));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3 
       (.I0(store_sr_req_pulsed_r),
        .I1(p_37_in),
        .O(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),
        .O(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_4_n_0 ));
  FDRE \gen_track_left_edge[0].pb_found_stable_eye_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[0]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[0]),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .I4(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ),
        .Q(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [0]),
        .O(p_0_in__3[0]));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [0]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [1]),
        .O(p_0_in__3[1]));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [2]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [1]),
        .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [0]),
        .O(p_0_in__3[2]));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [3]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [0]),
        .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [1]),
        .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [2]),
        .O(p_0_in__3[3]));
  LUT4 #(
    .INIT(16'hFEAA)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(store_sr_req_pulsed_r),
        .I2(p_37_in),
        .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h22200000)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[1]),
        .I2(p_37_in),
        .I3(store_sr_req_pulsed_r),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [4]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [2]),
        .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [1]),
        .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [0]),
        .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [3]),
        .O(p_0_in__3[4]));
  LUT6 #(
    .INIT(64'h0F0F0F000F0E0F0E)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4 
       (.I0(p_0_in103_in),
        .I1(p_1_in29_in),
        .I2(pb_detect_edge_done_r[1]),
        .I3(p_0_in28_in),
        .I4(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT5 #(
    .INIT(32'hBFFFFFFF)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [4]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [2]),
        .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [1]),
        .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [0]),
        .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [3]),
        .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__3[0]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [0]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__3[1]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [1]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__3[2]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [2]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__3[3]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [3]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__3[4]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_204 [4]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1 
       (.I0(p_37_in),
        .I1(store_sr_req_pulsed_r),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in103_in),
        .I4(pb_detect_edge_done_r[1]),
        .O(\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_detect_edge_done_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[1]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5050505050505551)) 
    \gen_track_left_edge[1].pb_found_edge_r[1]_i_1 
       (.I0(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .I3(p_0_in28_in),
        .I4(pb_detect_edge_done_r[1]),
        .I5(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0 ),
        .O(\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_found_edge_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ),
        .Q(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'hFFFFFFFA00000002)) 
    \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1 
       (.I0(pb_found_stable_eye_r73_out),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(pb_detect_edge_done_r[1]),
        .I4(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0 ),
        .I5(pb_found_stable_eye_r[1]),
        .O(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .I2(p_0_in28_in),
        .O(pb_found_stable_eye_r73_out));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3 
       (.I0(p_0_in103_in),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in28_in),
        .I3(p_1_in29_in),
        .O(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_3_n_0 ));
  FDRE \gen_track_left_edge[1].pb_found_stable_eye_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[1]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[1]),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(p_0_in103_in),
        .I4(p_0_in28_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_last_tap_jitter_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ),
        .Q(p_0_in28_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [0]),
        .O(p_0_in__4[0]));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [0]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [1]),
        .O(p_0_in__4[1]));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [2]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [1]),
        .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [0]),
        .O(p_0_in__4[2]));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [3]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [0]),
        .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [1]),
        .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [2]),
        .O(p_0_in__4[3]));
  LUT4 #(
    .INIT(16'hFEAA)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(store_sr_req_pulsed_r),
        .I2(p_37_in),
        .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h22200000)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[2]),
        .I2(p_37_in),
        .I3(store_sr_req_pulsed_r),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [4]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [2]),
        .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [1]),
        .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [0]),
        .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [3]),
        .O(p_0_in__4[4]));
  LUT6 #(
    .INIT(64'h0F0F0F000F0E0F0E)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4 
       (.I0(p_0_in100_in),
        .I1(p_1_in26_in),
        .I2(pb_detect_edge_done_r[2]),
        .I3(p_0_in25_in),
        .I4(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT5 #(
    .INIT(32'hBFFFFFFF)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [4]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [2]),
        .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [1]),
        .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [0]),
        .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [3]),
        .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__4[0]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [0]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__4[1]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [1]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__4[2]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [2]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__4[3]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [3]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__4[4]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_205 [4]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1 
       (.I0(p_37_in),
        .I1(store_sr_req_pulsed_r),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in100_in),
        .I4(pb_detect_edge_done_r[2]),
        .O(\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_detect_edge_done_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[2]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5050505050505551)) 
    \gen_track_left_edge[2].pb_found_edge_r[2]_i_1 
       (.I0(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .I3(p_0_in25_in),
        .I4(pb_detect_edge_done_r[2]),
        .I5(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0 ),
        .O(\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_found_edge_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ),
        .Q(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'hFFFFFFFA00000002)) 
    \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1 
       (.I0(pb_found_stable_eye_r69_out),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(pb_detect_edge_done_r[2]),
        .I4(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0 ),
        .I5(pb_found_stable_eye_r[2]),
        .O(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .I2(p_0_in25_in),
        .O(pb_found_stable_eye_r69_out));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3 
       (.I0(p_0_in100_in),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in25_in),
        .I3(p_1_in26_in),
        .O(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_3_n_0 ));
  FDRE \gen_track_left_edge[2].pb_found_stable_eye_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[2]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[2]),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(p_0_in100_in),
        .I4(p_0_in25_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_last_tap_jitter_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ),
        .Q(p_0_in25_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [0]),
        .O(p_0_in__5[0]));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [0]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [1]),
        .O(p_0_in__5[1]));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [2]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [1]),
        .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [0]),
        .O(p_0_in__5[2]));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [3]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [0]),
        .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [1]),
        .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [2]),
        .O(p_0_in__5[3]));
  LUT4 #(
    .INIT(16'hFEAA)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(store_sr_req_pulsed_r),
        .I2(p_37_in),
        .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h22200000)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[3]),
        .I2(p_37_in),
        .I3(store_sr_req_pulsed_r),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [4]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [2]),
        .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [1]),
        .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [0]),
        .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [3]),
        .O(p_0_in__5[4]));
  LUT6 #(
    .INIT(64'h0F0F0F000F0E0F0E)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4 
       (.I0(p_0_in97_in),
        .I1(p_1_in23_in),
        .I2(pb_detect_edge_done_r[3]),
        .I3(p_0_in22_in),
        .I4(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT5 #(
    .INIT(32'hBFFFFFFF)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [4]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [2]),
        .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [1]),
        .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [0]),
        .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [3]),
        .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__5[0]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [0]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__5[1]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [1]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__5[2]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [2]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__5[3]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [3]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__5[4]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_206 [4]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1 
       (.I0(p_37_in),
        .I1(store_sr_req_pulsed_r),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in97_in),
        .I4(pb_detect_edge_done_r[3]),
        .O(\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_detect_edge_done_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[3]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5050505050505551)) 
    \gen_track_left_edge[3].pb_found_edge_r[3]_i_1 
       (.I0(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .I3(p_0_in22_in),
        .I4(pb_detect_edge_done_r[3]),
        .I5(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0 ),
        .O(\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_found_edge_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ),
        .Q(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'hFFFFFFFA00000002)) 
    \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1 
       (.I0(pb_found_stable_eye_r65_out),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(pb_detect_edge_done_r[3]),
        .I4(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0 ),
        .I5(pb_found_stable_eye_r[3]),
        .O(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .I2(p_0_in22_in),
        .O(pb_found_stable_eye_r65_out));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3 
       (.I0(p_0_in97_in),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in22_in),
        .I3(p_1_in23_in),
        .O(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_3_n_0 ));
  FDRE \gen_track_left_edge[3].pb_found_stable_eye_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[3]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[3]),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(p_0_in97_in),
        .I4(p_0_in22_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_last_tap_jitter_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ),
        .Q(p_0_in22_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [0]),
        .O(p_0_in__6[0]));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [0]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [1]),
        .O(p_0_in__6[1]));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [2]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [1]),
        .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [0]),
        .O(p_0_in__6[2]));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [3]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [0]),
        .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [1]),
        .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [2]),
        .O(p_0_in__6[3]));
  LUT4 #(
    .INIT(16'hFEAA)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(store_sr_req_pulsed_r),
        .I2(p_37_in),
        .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h22200000)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[4]),
        .I2(p_37_in),
        .I3(store_sr_req_pulsed_r),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [4]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [2]),
        .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [1]),
        .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [0]),
        .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [3]),
        .O(p_0_in__6[4]));
  LUT6 #(
    .INIT(64'h0F0F0F000F0E0F0E)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4 
       (.I0(p_0_in94_in),
        .I1(p_1_in20_in),
        .I2(pb_detect_edge_done_r[4]),
        .I3(p_0_in19_in),
        .I4(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT5 #(
    .INIT(32'hBFFFFFFF)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [4]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [2]),
        .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [1]),
        .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [0]),
        .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [3]),
        .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__6[0]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [0]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__6[1]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [1]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__6[2]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [2]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__6[3]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [3]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__6[4]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_207 [4]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1 
       (.I0(p_37_in),
        .I1(store_sr_req_pulsed_r),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in94_in),
        .I4(pb_detect_edge_done_r[4]),
        .O(\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_detect_edge_done_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[4]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5050505050505551)) 
    \gen_track_left_edge[4].pb_found_edge_r[4]_i_1 
       (.I0(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .I3(p_0_in19_in),
        .I4(pb_detect_edge_done_r[4]),
        .I5(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0 ),
        .O(\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_found_edge_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ),
        .Q(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'hFFFFFFFA00000002)) 
    \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1 
       (.I0(pb_found_stable_eye_r61_out),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(pb_detect_edge_done_r[4]),
        .I4(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0 ),
        .I5(pb_found_stable_eye_r[4]),
        .O(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .I2(p_0_in19_in),
        .O(pb_found_stable_eye_r61_out));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3 
       (.I0(p_0_in94_in),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in19_in),
        .I3(p_1_in20_in),
        .O(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_3_n_0 ));
  FDRE \gen_track_left_edge[4].pb_found_stable_eye_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[4]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[4]),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(p_0_in94_in),
        .I4(p_0_in19_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_last_tap_jitter_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ),
        .Q(p_0_in19_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [0]),
        .O(p_0_in__7[0]));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [0]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [1]),
        .O(p_0_in__7[1]));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [2]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [1]),
        .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [0]),
        .O(p_0_in__7[2]));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [3]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [0]),
        .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [1]),
        .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [2]),
        .O(p_0_in__7[3]));
  LUT4 #(
    .INIT(16'hFEAA)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(store_sr_req_pulsed_r),
        .I2(p_37_in),
        .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h22200000)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[5]),
        .I2(p_37_in),
        .I3(store_sr_req_pulsed_r),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [4]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [2]),
        .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [1]),
        .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [0]),
        .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [3]),
        .O(p_0_in__7[4]));
  LUT6 #(
    .INIT(64'h0F0F0F000F0E0F0E)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4 
       (.I0(p_0_in91_in),
        .I1(p_1_in17_in),
        .I2(pb_detect_edge_done_r[5]),
        .I3(p_0_in16_in),
        .I4(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT5 #(
    .INIT(32'hBFFFFFFF)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [4]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [2]),
        .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [1]),
        .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [0]),
        .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [3]),
        .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__7[0]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [0]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__7[1]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [1]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__7[2]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [2]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__7[3]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [3]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__7[4]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_208 [4]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1 
       (.I0(p_37_in),
        .I1(store_sr_req_pulsed_r),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in91_in),
        .I4(pb_detect_edge_done_r[5]),
        .O(\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_detect_edge_done_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[5]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5050505050505551)) 
    \gen_track_left_edge[5].pb_found_edge_r[5]_i_1 
       (.I0(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .I3(p_0_in16_in),
        .I4(pb_detect_edge_done_r[5]),
        .I5(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0 ),
        .O(\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_found_edge_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ),
        .Q(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'hFFFFFFFA00000002)) 
    \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1 
       (.I0(pb_found_stable_eye_r57_out),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(pb_detect_edge_done_r[5]),
        .I4(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0 ),
        .I5(pb_found_stable_eye_r[5]),
        .O(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .I2(p_0_in16_in),
        .O(pb_found_stable_eye_r57_out));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3 
       (.I0(p_0_in91_in),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in16_in),
        .I3(p_1_in17_in),
        .O(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_3_n_0 ));
  FDRE \gen_track_left_edge[5].pb_found_stable_eye_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[5]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[5]),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(p_0_in91_in),
        .I4(p_0_in16_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_last_tap_jitter_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ),
        .Q(p_0_in16_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [0]),
        .O(p_0_in__8[0]));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [0]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [1]),
        .O(p_0_in__8[1]));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [2]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [1]),
        .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [0]),
        .O(p_0_in__8[2]));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [3]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [0]),
        .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [1]),
        .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [2]),
        .O(p_0_in__8[3]));
  LUT4 #(
    .INIT(16'hFEAA)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(store_sr_req_pulsed_r),
        .I2(p_37_in),
        .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h22200000)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[6]),
        .I2(p_37_in),
        .I3(store_sr_req_pulsed_r),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [4]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [2]),
        .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [1]),
        .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [0]),
        .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [3]),
        .O(p_0_in__8[4]));
  LUT6 #(
    .INIT(64'h0F0F0F000F0E0F0E)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4 
       (.I0(p_0_in88_in),
        .I1(p_1_in14_in),
        .I2(pb_detect_edge_done_r[6]),
        .I3(p_0_in13_in),
        .I4(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT5 #(
    .INIT(32'hBFFFFFFF)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [4]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [2]),
        .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [1]),
        .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [0]),
        .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [3]),
        .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__8[0]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [0]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__8[1]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [1]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__8[2]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [2]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__8[3]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [3]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__8[4]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_209 [4]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1 
       (.I0(p_37_in),
        .I1(store_sr_req_pulsed_r),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in88_in),
        .I4(pb_detect_edge_done_r[6]),
        .O(\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_detect_edge_done_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[6]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5050505050505551)) 
    \gen_track_left_edge[6].pb_found_edge_r[6]_i_1 
       (.I0(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .I3(p_0_in13_in),
        .I4(pb_detect_edge_done_r[6]),
        .I5(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0 ),
        .O(\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_found_edge_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ),
        .Q(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'hFFFFFFFA00000002)) 
    \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1 
       (.I0(pb_found_stable_eye_r53_out),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(pb_detect_edge_done_r[6]),
        .I4(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0 ),
        .I5(pb_found_stable_eye_r[6]),
        .O(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .I2(p_0_in13_in),
        .O(pb_found_stable_eye_r53_out));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3 
       (.I0(p_0_in88_in),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in13_in),
        .I3(p_1_in14_in),
        .O(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_3_n_0 ));
  FDRE \gen_track_left_edge[6].pb_found_stable_eye_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[6]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[6]),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(p_0_in88_in),
        .I4(p_0_in13_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_last_tap_jitter_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ),
        .Q(p_0_in13_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [0]),
        .O(p_0_in__9[0]));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [0]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [1]),
        .O(p_0_in__9[1]));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [2]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [1]),
        .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [0]),
        .O(p_0_in__9[2]));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [3]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [0]),
        .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [1]),
        .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [2]),
        .O(p_0_in__9[3]));
  LUT4 #(
    .INIT(16'hFEAA)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(store_sr_req_pulsed_r),
        .I2(p_37_in),
        .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h22200000)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[7]),
        .I2(p_37_in),
        .I3(store_sr_req_pulsed_r),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [4]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [2]),
        .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [1]),
        .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [0]),
        .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [3]),
        .O(p_0_in__9[4]));
  LUT6 #(
    .INIT(64'h0F0F0F000F0E0F0E)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4 
       (.I0(p_0_in),
        .I1(p_1_in12_in),
        .I2(pb_detect_edge_done_r[7]),
        .I3(p_0_in11_in),
        .I4(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT5 #(
    .INIT(32'hBFFFFFFF)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [4]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [2]),
        .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [1]),
        .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [0]),
        .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [3]),
        .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][0] 
       (.C(CLK),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__9[0]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [0]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][1] 
       (.C(CLK),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__9[1]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [1]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][2] 
       (.C(CLK),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__9[2]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [2]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][3] 
       (.C(CLK),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__9[3]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [3]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][4] 
       (.C(CLK),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__9[4]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_210 [4]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1 
       (.I0(p_37_in),
        .I1(store_sr_req_pulsed_r),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in),
        .I4(pb_detect_edge_done_r[7]),
        .O(\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_detect_edge_done_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[7]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5050505050505551)) 
    \gen_track_left_edge[7].pb_found_edge_r[7]_i_1 
       (.I0(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .I3(p_0_in11_in),
        .I4(pb_detect_edge_done_r[7]),
        .I5(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0 ),
        .O(\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_found_edge_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ),
        .Q(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'hFFFFFFFA00000002)) 
    \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1 
       (.I0(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2_n_0 ),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(pb_detect_edge_done_r[7]),
        .I4(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0 ),
        .I5(pb_found_stable_eye_r[7]),
        .O(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .I2(p_0_in11_in),
        .O(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3 
       (.I0(p_0_in),
        .I1(samp_cnt_done_r_reg_n_0),
        .I2(p_0_in11_in),
        .I3(p_1_in12_in),
        .O(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_3_n_0 ));
  FDRE \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[7]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[7]),
        .I2(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_3_n_0 ),
        .I3(p_0_in),
        .I4(p_0_in11_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ),
        .Q(p_0_in11_in),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hC580)) 
    idel_adj_inc_i_1
       (.I0(\idel_dec_cnt[4]_i_3_n_0 ),
        .I1(cal1_wait_r),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I3(idel_adj_inc_reg_n_0),
        .O(idel_adj_inc_i_1_n_0));
  FDRE idel_adj_inc_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idel_adj_inc_i_1_n_0),
        .Q(idel_adj_inc_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  LUT6 #(
    .INIT(64'hF444F4F4F4444444)) 
    \idel_dec_cnt[0]_i_1 
       (.I0(\idel_dec_cnt_reg_n_0_[0] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),
        .O(idel_dec_cnt[0]));
  LUT5 #(
    .INIT(32'hFF909090)) 
    \idel_dec_cnt[1]_i_1 
       (.I0(\idel_dec_cnt_reg_n_0_[0] ),
        .I1(\idel_dec_cnt_reg_n_0_[1] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I4(idelay_tap_cnt_r[1]),
        .O(idel_dec_cnt[1]));
  LUT6 #(
    .INIT(64'hFFFF888288828882)) 
    \idel_dec_cnt[2]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .I1(\idel_dec_cnt_reg_n_0_[2] ),
        .I2(\idel_dec_cnt_reg_n_0_[1] ),
        .I3(\idel_dec_cnt_reg_n_0_[0] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I5(idelay_tap_cnt_r[2]),
        .O(idel_dec_cnt[2]));
  LUT5 #(
    .INIT(32'hFF282828)) 
    \idel_dec_cnt[3]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .I1(\idel_dec_cnt_reg_n_0_[3] ),
        .I2(\idel_dec_cnt[3]_i_2_n_0 ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I4(idelay_tap_cnt_r[3]),
        .O(idel_dec_cnt[3]));
  LUT3 #(
    .INIT(8'h01)) 
    \idel_dec_cnt[3]_i_2 
       (.I0(\idel_dec_cnt_reg_n_0_[1] ),
        .I1(\idel_dec_cnt_reg_n_0_[0] ),
        .I2(\idel_dec_cnt_reg_n_0_[2] ),
        .O(\idel_dec_cnt[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFEEEFEEEFEEE)) 
    \idel_dec_cnt[4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[15]_i_2_n_0 ),
        .I1(\idel_dec_cnt[4]_i_3_n_0 ),
        .I2(\FSM_onehot_cal1_state_r[22]_i_2_n_0 ),
        .I3(idel_mpr_pat_detect_r),
        .I4(\idel_dec_cnt[4]_i_4_n_0 ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .O(\idel_dec_cnt[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFF606060)) 
    \idel_dec_cnt[4]_i_2 
       (.I0(\idel_dec_cnt_reg_n_0_[4] ),
        .I1(\idel_dec_cnt[4]_i_5_n_0 ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I4(idelay_tap_cnt_r[4]),
        .O(idel_dec_cnt[4]));
  LUT4 #(
    .INIT(16'hA800)) 
    \idel_dec_cnt[4]_i_3 
       (.I0(detect_edge_done_r),
        .I1(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .I2(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .I3(p_37_in),
        .O(\idel_dec_cnt[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \idel_dec_cnt[4]_i_4 
       (.I0(\idel_dec_cnt_reg_n_0_[4] ),
        .I1(\idel_dec_cnt_reg_n_0_[3] ),
        .I2(\idel_dec_cnt_reg_n_0_[1] ),
        .I3(\idel_dec_cnt_reg_n_0_[0] ),
        .I4(\idel_dec_cnt_reg_n_0_[2] ),
        .O(\idel_dec_cnt[4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \idel_dec_cnt[4]_i_5 
       (.I0(\idel_dec_cnt_reg_n_0_[2] ),
        .I1(\idel_dec_cnt_reg_n_0_[0] ),
        .I2(\idel_dec_cnt_reg_n_0_[1] ),
        .I3(\idel_dec_cnt_reg_n_0_[3] ),
        .O(\idel_dec_cnt[4]_i_5_n_0 ));
  FDRE \idel_dec_cnt_reg[0] 
       (.C(CLK),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[0]),
        .Q(\idel_dec_cnt_reg_n_0_[0] ),
        .R(found_first_edge_r_reg_0));
  FDRE \idel_dec_cnt_reg[1] 
       (.C(CLK),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[1]),
        .Q(\idel_dec_cnt_reg_n_0_[1] ),
        .R(found_first_edge_r_reg_0));
  FDRE \idel_dec_cnt_reg[2] 
       (.C(CLK),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[2]),
        .Q(\idel_dec_cnt_reg_n_0_[2] ),
        .R(found_first_edge_r_reg_0));
  FDRE \idel_dec_cnt_reg[3] 
       (.C(CLK),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[3]),
        .Q(\idel_dec_cnt_reg_n_0_[3] ),
        .R(found_first_edge_r_reg_0));
  FDRE \idel_dec_cnt_reg[4] 
       (.C(CLK),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[4]),
        .Q(\idel_dec_cnt_reg_n_0_[4] ),
        .R(found_first_edge_r_reg_0));
  LUT4 #(
    .INIT(16'hCCCE)) 
    idel_pat_detect_valid_r_i_1
       (.I0(idel_pat_detect_valid_r_reg_n_0),
        .I1(p_0_in250_in),
        .I2(cal1_dq_idel_inc),
        .I3(store_sr_req_pulsed_r),
        .O(idel_pat_detect_valid_r_i_1_n_0));
  FDRE idel_pat_detect_valid_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idel_pat_detect_valid_r_i_1_n_0),
        .Q(idel_pat_detect_valid_r_reg_n_0),
        .R(found_first_edge_r_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF1111F111)) 
    \idelay_tap_cnt_r[0][0][4]_i_1 
       (.I0(\idelay_tap_cnt_r_reg[0][0][0]_0 ),
        .I1(Q[0]),
        .I2(\idelay_tap_cnt_r[0][0][4]_i_3_n_0 ),
        .I3(idelay_ce_int),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .O(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \idelay_tap_cnt_r[0][0][4]_i_3 
       (.I0(\rnk_cnt_r_reg_n_0_[0] ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .O(\idelay_tap_cnt_r[0][0][4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \idelay_tap_cnt_r[0][1][0]_i_1 
       (.I0(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .I1(idelay_ce_int),
        .I2(idelay_tap_cnt_slice_r[0]),
        .O(\idelay_tap_cnt_r[0][1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT5 #(
    .INIT(32'h04404004)) 
    \idelay_tap_cnt_r[0][1][1]_i_1 
       (.I0(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .I1(idelay_ce_int),
        .I2(idelay_tap_cnt_slice_r[0]),
        .I3(idelay_tap_cnt_slice_r[1]),
        .I4(idelay_inc_int),
        .O(\idelay_tap_cnt_r[0][1][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0444400044400004)) 
    \idelay_tap_cnt_r[0][1][2]_i_1 
       (.I0(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .I1(idelay_ce_int),
        .I2(idelay_inc_int),
        .I3(idelay_tap_cnt_slice_r[0]),
        .I4(idelay_tap_cnt_slice_r[2]),
        .I5(idelay_tap_cnt_slice_r[1]),
        .O(\idelay_tap_cnt_r[0][1][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h04404004)) 
    \idelay_tap_cnt_r[0][1][3]_i_1 
       (.I0(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .I1(idelay_ce_int),
        .I2(idelay_tap_cnt_slice_r[2]),
        .I3(idelay_tap_cnt_slice_r[3]),
        .I4(\idelay_tap_cnt_r[0][1][4]_i_3_n_0 ),
        .O(\idelay_tap_cnt_r[0][1][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1444444100000000)) 
    \idelay_tap_cnt_r[0][1][4]_i_2 
       (.I0(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .I1(idelay_tap_cnt_slice_r[4]),
        .I2(idelay_tap_cnt_slice_r[3]),
        .I3(idelay_tap_cnt_slice_r[2]),
        .I4(\idelay_tap_cnt_r[0][1][4]_i_3_n_0 ),
        .I5(idelay_ce_int),
        .O(\idelay_tap_cnt_r[0][1][4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h80FE)) 
    \idelay_tap_cnt_r[0][1][4]_i_3 
       (.I0(idelay_tap_cnt_slice_r[1]),
        .I1(idelay_inc_int),
        .I2(idelay_tap_cnt_slice_r[0]),
        .I3(idelay_tap_cnt_slice_r[2]),
        .O(\idelay_tap_cnt_r[0][1][4]_i_3_n_0 ));
  FDRE \idelay_tap_cnt_r_reg[0][0][0] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][1][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][0][1] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][1][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][0][2] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][1][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][0][3] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][1][3]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][0][4] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r[0][0][4]_i_1_n_0 ),
        .D(\idelay_tap_cnt_r[0][1][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][0] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r_reg[0][1][4]_0 ),
        .D(\idelay_tap_cnt_r[0][1][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][1] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r_reg[0][1][4]_0 ),
        .D(\idelay_tap_cnt_r[0][1][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][2] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r_reg[0][1][4]_0 ),
        .D(\idelay_tap_cnt_r[0][1][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][3] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r_reg[0][1][4]_0 ),
        .D(\idelay_tap_cnt_r[0][1][3]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][4] 
       (.C(CLK),
        .CE(\idelay_tap_cnt_r_reg[0][1][4]_0 ),
        .D(\idelay_tap_cnt_r[0][1][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][4] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \idelay_tap_cnt_slice_r[0]_i_1 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),
        .O(idelay_tap_cnt_r[0]));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \idelay_tap_cnt_slice_r[1]_i_1 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][1][1] ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\idelay_tap_cnt_r_reg_n_0_[0][0][1] ),
        .O(idelay_tap_cnt_r[1]));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \idelay_tap_cnt_slice_r[2]_i_1 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][1][2] ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\idelay_tap_cnt_r_reg_n_0_[0][0][2] ),
        .O(idelay_tap_cnt_r[2]));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \idelay_tap_cnt_slice_r[3]_i_1 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][1][3] ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\idelay_tap_cnt_r_reg_n_0_[0][0][3] ),
        .O(idelay_tap_cnt_r[3]));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \idelay_tap_cnt_slice_r[4]_i_1 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][1][4] ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\idelay_tap_cnt_r_reg_n_0_[0][0][4] ),
        .O(idelay_tap_cnt_r[4]));
  FDRE \idelay_tap_cnt_slice_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[0]),
        .Q(idelay_tap_cnt_slice_r[0]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  FDRE \idelay_tap_cnt_slice_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[1]),
        .Q(idelay_tap_cnt_slice_r[1]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  FDRE \idelay_tap_cnt_slice_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[2]),
        .Q(idelay_tap_cnt_slice_r[2]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  FDRE \idelay_tap_cnt_slice_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[3]),
        .Q(idelay_tap_cnt_slice_r[3]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  FDRE \idelay_tap_cnt_slice_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[4]),
        .Q(idelay_tap_cnt_slice_r[4]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  LUT6 #(
    .INIT(64'h000000000000AAEA)) 
    idelay_tap_limit_r_i_1
       (.I0(idelay_tap_limit_r_reg_n_0),
        .I1(idelay_tap_cnt_r[0]),
        .I2(idelay_tap_cnt_r[3]),
        .I3(idelay_tap_limit_r_i_2_n_0),
        .I4(new_cnt_cpt_r_reg_0),
        .I5(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .O(idelay_tap_limit_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h3FFF5F5F3FFFFFFF)) 
    idelay_tap_limit_r_i_2
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][0][4] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][1][4] ),
        .I2(idelay_tap_cnt_r[1]),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][1][2] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][2] ),
        .O(idelay_tap_limit_r_i_2_n_0));
  FDRE idelay_tap_limit_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_tap_limit_r_i_1_n_0),
        .Q(idelay_tap_limit_r_reg_n_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT4 #(
    .INIT(16'h20AA)) 
    \init_state_r[1]_i_29 
       (.I0(pi_calib_done),
        .I1(D[3]),
        .I2(rdlvl_last_byte_done),
        .I3(pi_dqs_found_done),
        .O(pi_calib_done_r1_reg));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT4 #(
    .INIT(16'h4404)) 
    \init_state_r[2]_i_30 
       (.I0(D[3]),
        .I1(pi_dqs_found_done),
        .I2(\init_state_r[2]_i_17 ),
        .I3(rdlvl_last_byte_done),
        .O(rdlvl_stg1_done_int_reg_0));
  LUT5 #(
    .INIT(32'h00000020)) 
    \mpr_4to1.idel_mpr_pat_detect_r_i_1 
       (.I0(\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ),
        .I1(p_1_in2_in),
        .I2(\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ),
        .I3(inhibit_edge_detect_r),
        .I4(\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ),
        .O(\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00100000)) 
    \mpr_4to1.idel_mpr_pat_detect_r_i_2 
       (.I0(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ),
        .I1(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .I4(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ),
        .I5(idel_mpr_pat_detect_r),
        .O(\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    \mpr_4to1.idel_mpr_pat_detect_r_i_3 
       (.I0(idel_pat_detect_valid_r_reg_n_0),
        .I1(p_0_in250_in),
        .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .O(\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ));
  FDRE \mpr_4to1.idel_mpr_pat_detect_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ),
        .Q(idel_mpr_pat_detect_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hF700FFFF)) 
    \mpr_4to1.inhibit_edge_detect_r_i_1 
       (.I0(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ),
        .I1(p_0_in250_in),
        .I2(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ),
        .I3(inhibit_edge_detect_r),
        .I4(\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFEA)) 
    \mpr_4to1.inhibit_edge_detect_r_i_2 
       (.I0(idelay_tap_cnt_r[1]),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][1][4] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][0][4] ),
        .I4(idelay_tap_cnt_r[2]),
        .I5(idelay_tap_cnt_r[3]),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFBFF)) 
    \mpr_4to1.inhibit_edge_detect_r_i_3 
       (.I0(mpr_rd_rise0_prev_r),
        .I1(mpr_rd_fall2_prev_r),
        .I2(mpr_rd_rise3_prev_r),
        .I3(mpr_rd_fall3_prev_r),
        .I4(\mpr_4to1.inhibit_edge_detect_r_i_5_n_0 ),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555555554)) 
    \mpr_4to1.inhibit_edge_detect_r_i_4 
       (.I0(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .I1(\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ),
        .I2(mpr_rd_fall2_prev_r),
        .I3(mpr_rd_fall1_prev_r),
        .I4(mpr_rd_fall3_prev_r),
        .I5(mpr_rd_fall0_prev_r),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hFFDF)) 
    \mpr_4to1.inhibit_edge_detect_r_i_5 
       (.I0(mpr_rd_fall1_prev_r),
        .I1(mpr_rd_rise1_prev_r),
        .I2(mpr_rd_fall0_prev_r),
        .I3(mpr_rd_rise2_prev_r),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \mpr_4to1.inhibit_edge_detect_r_i_6 
       (.I0(mpr_rd_rise1_prev_r),
        .I1(mpr_rd_rise0_prev_r),
        .I2(mpr_rd_rise2_prev_r),
        .I3(mpr_rd_rise3_prev_r),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ));
  FDRE \mpr_4to1.inhibit_edge_detect_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ),
        .Q(inhibit_edge_detect_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h06)) 
    \mpr_4to1.stable_idel_cnt[0]_i_1 
       (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .I1(stable_idel_cnt),
        .I2(stable_idel_cnt0),
        .O(\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT4 #(
    .INIT(16'h006A)) 
    \mpr_4to1.stable_idel_cnt[1]_i_1 
       (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I1(stable_idel_cnt),
        .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .I3(stable_idel_cnt0),
        .O(\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT5 #(
    .INIT(32'h00006AAA)) 
    \mpr_4to1.stable_idel_cnt[2]_i_1 
       (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .I1(stable_idel_cnt),
        .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .I4(stable_idel_cnt0),
        .O(\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \mpr_4to1.stable_idel_cnt[2]_i_2 
       (.I0(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ),
        .I1(idel_pat_detect_valid_r_reg_n_0),
        .I2(p_0_in250_in),
        .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .I4(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_cal1_state_r[16]_i_4_n_0 ),
        .O(stable_idel_cnt));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \mpr_4to1.stable_idel_cnt[2]_i_3 
       (.I0(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .I2(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .O(stable_idel_cnt0));
  LUT6 #(
    .INIT(64'hFFFFFFFFBEFFFFBE)) 
    \mpr_4to1.stable_idel_cnt[2]_i_4 
       (.I0(\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .I2(mpr_rd_fall1_prev_r),
        .I3(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .I4(mpr_rd_fall2_prev_r),
        .I5(\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ),
        .O(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \mpr_4to1.stable_idel_cnt[2]_i_5 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .I1(mpr_rd_rise0_prev_r),
        .I2(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .I3(mpr_rd_fall0_prev_r),
        .O(\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6FF6)) 
    \mpr_4to1.stable_idel_cnt[2]_i_6 
       (.I0(mpr_rd_rise3_prev_r),
        .I1(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .I2(mpr_rd_rise2_prev_r),
        .I3(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .I4(\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ),
        .O(\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \mpr_4to1.stable_idel_cnt[2]_i_7 
       (.I0(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .I1(mpr_rd_fall3_prev_r),
        .I2(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .I3(mpr_rd_rise1_prev_r),
        .O(\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ));
  FDRE \mpr_4to1.stable_idel_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ),
        .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \mpr_4to1.stable_idel_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ),
        .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \mpr_4to1.stable_idel_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ),
        .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT3 #(
    .INIT(8'hDC)) 
    mpr_dec_cpt_r_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(mpr_dec_cpt_r),
        .I2(mpr_dec_cpt_r_reg_n_0),
        .O(mpr_dec_cpt_r_i_1_n_0));
  FDRE mpr_dec_cpt_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mpr_dec_cpt_r_i_1_n_0),
        .Q(mpr_dec_cpt_r_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  FDRE mpr_rd_fall0_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .Q(mpr_rd_fall0_prev_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hEA)) 
    mpr_rd_fall1_prev_r_i_1
       (.I0(p_1_in2_in),
        .I1(idel_pat_detect_valid_r_reg_n_0),
        .I2(p_0_in250_in),
        .O(mpr_rd_rise0_prev_r0));
  FDRE mpr_rd_fall1_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .Q(mpr_rd_fall1_prev_r),
        .R(1'b0));
  FDRE mpr_rd_fall2_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .Q(mpr_rd_fall2_prev_r),
        .R(1'b0));
  FDRE mpr_rd_fall3_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .Q(mpr_rd_fall3_prev_r),
        .R(1'b0));
  FDRE mpr_rd_rise0_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .Q(mpr_rd_rise0_prev_r),
        .R(1'b0));
  FDRE mpr_rd_rise1_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .Q(mpr_rd_rise1_prev_r),
        .R(1'b0));
  FDRE mpr_rd_rise2_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .Q(mpr_rd_rise2_prev_r),
        .R(1'b0));
  FDRE mpr_rd_rise3_prev_r_reg
       (.C(CLK),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .Q(mpr_rd_rise3_prev_r),
        .R(1'b0));
  FDRE mpr_rdlvl_start_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mpr_rdlvl_start_r_reg_0),
        .Q(mpr_rdlvl_start_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAAAAAEAEEAAAA)) 
    new_cnt_cpt_r_i_1
       (.I0(new_cnt_cpt_r_i_2_n_0),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I2(mpr_rdlvl_start_r),
        .I3(mpr_rdlvl_start_r_reg_0),
        .I4(rdlvl_stg1_start_r_reg_0),
        .I5(rdlvl_stg1_start_r),
        .O(new_cnt_cpt_r));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT5 #(
    .INIT(32'hEF000000)) 
    new_cnt_cpt_r_i_2
       (.I0(\rnk_cnt_r_reg_n_0_[0] ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(cal1_prech_req_r),
        .I4(prech_done),
        .O(new_cnt_cpt_r_i_2_n_0));
  FDRE new_cnt_cpt_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(new_cnt_cpt_r),
        .Q(new_cnt_cpt_r_reg_0),
        .R(found_first_edge_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_1 
       (.I0(\pi_dqs_found_lanes_r1_reg[3] ),
        .I1(pi_counter_load_en),
        .I2(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(\calib_sel_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_10 
       (.I0(\pi_dqs_found_lanes_r1_reg[3] ),
        .I1(pi_counter_load_val[1]),
        .I2(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(COUNTERLOADVAL[1]));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_10__0 
       (.I0(pi_counter_load_val[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I2(\pi_dqs_found_lanes_r1_reg[3] ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(\pi_stg2_reg_l_reg[5]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_11 
       (.I0(\pi_dqs_found_lanes_r1_reg[3] ),
        .I1(pi_counter_load_val[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(COUNTERLOADVAL[0]));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_11__0 
       (.I0(pi_counter_load_val[0]),
        .I1(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I2(\pi_dqs_found_lanes_r1_reg[3] ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(\pi_stg2_reg_l_reg[5]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_1__0 
       (.I0(pi_counter_load_en),
        .I1(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I2(\pi_dqs_found_lanes_r1_reg[3] ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(pi_stg2_load_reg_0));
  LUT6 #(
    .INIT(64'h00000000FCFC00A8)) 
    \phaser_in_gen.phaser_in_i_3 
       (.I0(\pi_dqs_found_lanes_r1_reg[3] ),
        .I1(rdlvl_pi_stg2_f_en),
        .I2(tempmon_pi_f_en_r),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I4(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I5(calib_zero_inputs),
        .O(\calib_sel_reg[1] ));
  LUT6 #(
    .INIT(64'h00000000EEEEE000)) 
    \phaser_in_gen.phaser_in_i_3__0 
       (.I0(rdlvl_pi_stg2_f_en),
        .I1(tempmon_pi_f_en_r),
        .I2(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I3(\pi_dqs_found_lanes_r1_reg[3] ),
        .I4(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I5(calib_zero_inputs),
        .O(pi_en_stg2_f_reg_0));
  LUT6 #(
    .INIT(64'h00000000FCFC00A8)) 
    \phaser_in_gen.phaser_in_i_4 
       (.I0(\pi_dqs_found_lanes_r1_reg[3] ),
        .I1(rdlvl_pi_stg2_f_incdec),
        .I2(tempmon_pi_f_inc_r),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I4(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I5(calib_zero_inputs),
        .O(\calib_sel_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h00000000EEEEE000)) 
    \phaser_in_gen.phaser_in_i_4__0 
       (.I0(rdlvl_pi_stg2_f_incdec),
        .I1(tempmon_pi_f_inc_r),
        .I2(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I3(\pi_dqs_found_lanes_r1_reg[3] ),
        .I4(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I5(calib_zero_inputs),
        .O(pi_stg2_f_incdec_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_6 
       (.I0(\pi_dqs_found_lanes_r1_reg[3] ),
        .I1(pi_counter_load_val[5]),
        .I2(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(COUNTERLOADVAL[5]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_6__0 
       (.I0(pi_counter_load_val[5]),
        .I1(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I2(\pi_dqs_found_lanes_r1_reg[3] ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(\pi_stg2_reg_l_reg[5]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_7 
       (.I0(\pi_dqs_found_lanes_r1_reg[3] ),
        .I1(pi_counter_load_val[4]),
        .I2(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(COUNTERLOADVAL[4]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_7__0 
       (.I0(pi_counter_load_val[4]),
        .I1(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I2(\pi_dqs_found_lanes_r1_reg[3] ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(\pi_stg2_reg_l_reg[5]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_8 
       (.I0(\pi_dqs_found_lanes_r1_reg[3] ),
        .I1(pi_counter_load_val[3]),
        .I2(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(COUNTERLOADVAL[3]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_8__0 
       (.I0(pi_counter_load_val[3]),
        .I1(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I2(\pi_dqs_found_lanes_r1_reg[3] ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(\pi_stg2_reg_l_reg[5]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_9 
       (.I0(\pi_dqs_found_lanes_r1_reg[3] ),
        .I1(pi_counter_load_val[2]),
        .I2(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(COUNTERLOADVAL[2]));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_9__0 
       (.I0(pi_counter_load_val[2]),
        .I1(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .I2(\pi_dqs_found_lanes_r1_reg[3] ),
        .I3(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .I4(calib_zero_inputs),
        .O(\pi_stg2_reg_l_reg[5]_0 [2]));
  LUT6 #(
    .INIT(64'h0000000000000800)) 
    pi_cnt_dec_i_1
       (.I0(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I1(wait_cnt_r_reg[0]),
        .I2(wait_cnt_r_reg[1]),
        .I3(dqs_po_dec_done_r2),
        .I4(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .I5(pi_cnt_dec_i_2_n_0),
        .O(pi_cnt_dec_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT2 #(
    .INIT(4'hE)) 
    pi_cnt_dec_i_2
       (.I0(wait_cnt_r_reg[2]),
        .I1(wait_cnt_r_reg[3]),
        .O(pi_cnt_dec_i_2_n_0));
  FDRE pi_cnt_dec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_cnt_dec_i_1_n_0),
        .Q(pi_cnt_dec_reg_0),
        .R(1'b0));
  FDRE pi_en_stg2_f_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_en_stg2_f_timing),
        .Q(rdlvl_pi_stg2_f_en),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    pi_en_stg2_f_timing_i_1
       (.I0(cal1_dlyce_cpt_r_reg_n_0),
        .I1(pi_cnt_dec_reg_0),
        .O(pi_en_stg2_f_timing_i_1_n_0));
  FDRE pi_en_stg2_f_timing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_en_stg2_f_timing_i_1_n_0),
        .Q(pi_en_stg2_f_timing),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  FDRE pi_fine_dly_dec_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(fine_dly_dec_done_r2),
        .Q(pi_fine_dly_dec_done_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \pi_rdval_cnt[0]_i_1 
       (.I0(\pi_rdval_cnt_reg[5]_0 [0]),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I4(pi_rdval_cnt[0]),
        .O(\pi_rdval_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB0808080808FB08)) 
    \pi_rdval_cnt[1]_i_1 
       (.I0(\pi_rdval_cnt_reg[5]_0 [1]),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I4(pi_rdval_cnt[1]),
        .I5(pi_rdval_cnt[0]),
        .O(\pi_rdval_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B888888888B8)) 
    \pi_rdval_cnt[2]_i_1 
       (.I0(\pi_rdval_cnt_reg[5]_0 [2]),
        .I1(\pi_rdval_cnt[3]_i_2_n_0 ),
        .I2(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I3(pi_rdval_cnt[0]),
        .I4(pi_rdval_cnt[1]),
        .I5(pi_rdval_cnt[2]),
        .O(\pi_rdval_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B888B88888B888)) 
    \pi_rdval_cnt[3]_i_1 
       (.I0(\pi_rdval_cnt_reg[5]_0 [3]),
        .I1(\pi_rdval_cnt[3]_i_2_n_0 ),
        .I2(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I3(\pi_rdval_cnt[3]_i_3_n_0 ),
        .I4(pi_rdval_cnt[2]),
        .I5(pi_rdval_cnt[3]),
        .O(\pi_rdval_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \pi_rdval_cnt[3]_i_2 
       (.I0(dqs_po_dec_done_r1),
        .I1(dqs_po_dec_done_r2),
        .O(\pi_rdval_cnt[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \pi_rdval_cnt[3]_i_3 
       (.I0(pi_rdval_cnt[0]),
        .I1(pi_rdval_cnt[1]),
        .O(\pi_rdval_cnt[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0808FBFBFB080808)) 
    \pi_rdval_cnt[4]_i_1 
       (.I0(\pi_rdval_cnt_reg[5]_0 [4]),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(pi_rdval_cnt[5]),
        .I4(\pi_rdval_cnt[5]_i_4_n_0 ),
        .I5(pi_rdval_cnt[4]),
        .O(\pi_rdval_cnt[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hBBFB)) 
    \pi_rdval_cnt[5]_i_1 
       (.I0(pi_cnt_dec_reg_0),
        .I1(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I2(dqs_po_dec_done_r1),
        .I3(dqs_po_dec_done_r2),
        .O(\pi_rdval_cnt[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB080808FB08FB08)) 
    \pi_rdval_cnt[5]_i_2 
       (.I0(\pi_rdval_cnt_reg[5]_0 [5]),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(pi_rdval_cnt[5]),
        .I4(pi_rdval_cnt[4]),
        .I5(\pi_rdval_cnt[5]_i_4_n_0 ),
        .O(\pi_rdval_cnt[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \pi_rdval_cnt[5]_i_3 
       (.I0(pi_rdval_cnt[4]),
        .I1(pi_rdval_cnt[5]),
        .I2(pi_rdval_cnt[2]),
        .I3(pi_rdval_cnt[3]),
        .I4(pi_rdval_cnt[0]),
        .I5(pi_rdval_cnt[1]),
        .O(\pi_rdval_cnt[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \pi_rdval_cnt[5]_i_4 
       (.I0(pi_rdval_cnt[1]),
        .I1(pi_rdval_cnt[0]),
        .I2(pi_rdval_cnt[3]),
        .I3(pi_rdval_cnt[2]),
        .O(\pi_rdval_cnt[5]_i_4_n_0 ));
  FDRE \pi_rdval_cnt_reg[0] 
       (.C(CLK),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[0]_i_1_n_0 ),
        .Q(pi_rdval_cnt[0]),
        .R(found_first_edge_r_reg_0));
  FDRE \pi_rdval_cnt_reg[1] 
       (.C(CLK),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[1]_i_1_n_0 ),
        .Q(pi_rdval_cnt[1]),
        .R(found_first_edge_r_reg_0));
  FDRE \pi_rdval_cnt_reg[2] 
       (.C(CLK),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[2]_i_1_n_0 ),
        .Q(pi_rdval_cnt[2]),
        .R(found_first_edge_r_reg_0));
  FDRE \pi_rdval_cnt_reg[3] 
       (.C(CLK),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[3]_i_1_n_0 ),
        .Q(pi_rdval_cnt[3]),
        .R(found_first_edge_r_reg_0));
  FDRE \pi_rdval_cnt_reg[4] 
       (.C(CLK),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[4]_i_1_n_0 ),
        .Q(pi_rdval_cnt[4]),
        .R(found_first_edge_r_reg_0));
  FDRE \pi_rdval_cnt_reg[5] 
       (.C(CLK),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[5]_i_2_n_0 ),
        .Q(pi_rdval_cnt[5]),
        .R(found_first_edge_r_reg_0));
  FDRE pi_stg2_f_incdec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_f_incdec_timing),
        .Q(rdlvl_pi_stg2_f_incdec),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0008)) 
    pi_stg2_f_incdec_timing_i_1
       (.I0(cal1_dlyce_cpt_r_reg_n_0),
        .I1(cal1_dlyinc_cpt_r_reg_n_0),
        .I2(pi_cnt_dec_reg_0),
        .I3(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .O(pi_stg2_f_incdec_timing_i_1_n_0));
  FDRE pi_stg2_f_incdec_timing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_f_incdec_timing_i_1_n_0),
        .Q(pi_stg2_f_incdec_timing),
        .R(1'b0));
  FDRE pi_stg2_load_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_load_timing),
        .Q(pi_counter_load_en),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT3 #(
    .INIT(8'h04)) 
    pi_stg2_load_timing_i_1
       (.I0(\regl_dqs_cnt_reg_n_0_[1] ),
        .I1(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ),
        .I2(\regl_rank_cnt[1]_i_2_n_0 ),
        .O(pi_stg2_load_timing_i_1_n_0));
  FDRE pi_stg2_load_timing_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_load_timing_i_1_n_0),
        .Q(pi_stg2_load_timing),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[0]),
        .Q(pi_counter_load_val[0]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[1]),
        .Q(pi_counter_load_val[1]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[2]),
        .Q(pi_counter_load_val[2]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[3]),
        .Q(pi_counter_load_val[3]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[4]),
        .Q(pi_counter_load_val[4]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[5]),
        .Q(pi_counter_load_val[5]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \pi_stg2_reg_l_timing[0]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ),
        .I1(\regl_dqs_cnt_reg_n_0_[0] ),
        .I2(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ),
        .O(\pi_stg2_reg_l_timing[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \pi_stg2_reg_l_timing[1]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ),
        .I1(\regl_dqs_cnt_reg_n_0_[0] ),
        .I2(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ),
        .O(\pi_stg2_reg_l_timing[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \pi_stg2_reg_l_timing[2]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ),
        .I1(\regl_dqs_cnt_reg_n_0_[0] ),
        .I2(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ),
        .O(\pi_stg2_reg_l_timing[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \pi_stg2_reg_l_timing[3]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ),
        .I1(\regl_dqs_cnt_reg_n_0_[0] ),
        .I2(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ),
        .O(\pi_stg2_reg_l_timing[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \pi_stg2_reg_l_timing[4]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ),
        .I1(\regl_dqs_cnt_reg_n_0_[0] ),
        .I2(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ),
        .O(\pi_stg2_reg_l_timing[4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \pi_stg2_reg_l_timing[5]_i_1 
       (.I0(\regl_rank_cnt[1]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ),
        .I2(\regl_dqs_cnt_reg_n_0_[1] ),
        .O(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \pi_stg2_reg_l_timing[5]_i_2 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ),
        .I1(\regl_dqs_cnt_reg_n_0_[0] ),
        .I2(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ),
        .O(\pi_stg2_reg_l_timing[5]_i_2_n_0 ));
  FDRE \pi_stg2_reg_l_timing_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_stg2_reg_l_timing[0]_i_1_n_0 ),
        .Q(pi_stg2_reg_l_timing[0]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  FDRE \pi_stg2_reg_l_timing_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_stg2_reg_l_timing[1]_i_1_n_0 ),
        .Q(pi_stg2_reg_l_timing[1]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  FDRE \pi_stg2_reg_l_timing_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_stg2_reg_l_timing[2]_i_1_n_0 ),
        .Q(pi_stg2_reg_l_timing[2]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  FDRE \pi_stg2_reg_l_timing_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_stg2_reg_l_timing[3]_i_1_n_0 ),
        .Q(pi_stg2_reg_l_timing[3]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  FDRE \pi_stg2_reg_l_timing_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_stg2_reg_l_timing[4]_i_1_n_0 ),
        .Q(pi_stg2_reg_l_timing[4]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  FDRE \pi_stg2_reg_l_timing_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\pi_stg2_reg_l_timing[5]_i_2_n_0 ),
        .Q(pi_stg2_reg_l_timing[5]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  FDRE \rd_mux_sel_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rd_mux_sel_r_reg[0]_0 ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0002)) 
    \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rd_mux_sel_r_reg[0]_0 ),
        .O(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0100000000000000)) 
    \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2 
       (.I0(\cal1_state_r1_reg_n_0_[4] ),
        .I1(\cal1_state_r1_reg_n_0_[0] ),
        .I2(\cal1_state_r1_reg_n_0_[5] ),
        .I3(\cal1_state_r1_reg_n_0_[2] ),
        .I4(\cal1_state_r1_reg_n_0_[3] ),
        .I5(\cal1_state_r1_reg_n_0_[1] ),
        .O(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0200)) 
    \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1 
       (.I0(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rd_mux_sel_r_reg[0]_0 ),
        .O(rdlvl_dqs_tap_cnt_r));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][0] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ),
        .R(found_first_edge_r_reg_0));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][1] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ),
        .R(found_first_edge_r_reg_0));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][2] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ),
        .R(found_first_edge_r_reg_0));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][3] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ),
        .R(found_first_edge_r_reg_0));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][4] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ),
        .R(found_first_edge_r_reg_0));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][5] 
       (.C(CLK),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ),
        .R(found_first_edge_r_reg_0));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][0] 
       (.C(CLK),
        .CE(rdlvl_dqs_tap_cnt_r),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][1] 
       (.C(CLK),
        .CE(rdlvl_dqs_tap_cnt_r),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][2] 
       (.C(CLK),
        .CE(rdlvl_dqs_tap_cnt_r),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][3] 
       (.C(CLK),
        .CE(rdlvl_dqs_tap_cnt_r),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][4] 
       (.C(CLK),
        .CE(rdlvl_dqs_tap_cnt_r),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][5] 
       (.C(CLK),
        .CE(rdlvl_dqs_tap_cnt_r),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  LUT6 #(
    .INIT(64'hFFFF0101FFFE0000)) 
    rdlvl_last_byte_done_int_i_1
       (.I0(\FSM_onehot_cal1_state_r[5]_i_1_n_0 ),
        .I1(p_3_in4_in),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I4(cal1_prech_req_r),
        .I5(rdlvl_last_byte_done),
        .O(rdlvl_last_byte_done_int_i_1_n_0));
  FDRE rdlvl_last_byte_done_int_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_last_byte_done_int_i_1_n_0),
        .Q(rdlvl_last_byte_done),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  LUT6 #(
    .INIT(64'hAAAAAEFFAAAAA200)) 
    rdlvl_pi_incdec_i_1
       (.I0(rdlvl_pi_incdec_i_2_n_0),
        .I1(cal1_wait_r),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I3(rdlvl_pi_incdec_i_3_n_0),
        .I4(rdlvl_pi_incdec_i_4_n_0),
        .I5(rdlvl_pi_incdec),
        .O(rdlvl_pi_incdec_i_1_n_0));
  LUT6 #(
    .INIT(64'hFEFEFEFEFEFEFEEE)) 
    rdlvl_pi_incdec_i_2
       (.I0(mpr_dec_cpt_r),
        .I1(rdlvl_pi_incdec_i_5_n_0),
        .I2(cal1_wait_r),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .I5(p_3_in4_in),
        .O(rdlvl_pi_incdec_i_2_n_0));
  LUT3 #(
    .INIT(8'hFE)) 
    rdlvl_pi_incdec_i_3
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[31] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .O(rdlvl_pi_incdec_i_3_n_0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    rdlvl_pi_incdec_i_4
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I1(p_3_in4_in),
        .I2(p_37_in),
        .I3(p_0_in250_in),
        .I4(p_14_in),
        .O(rdlvl_pi_incdec_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT5 #(
    .INIT(32'hFFEFEEEE)) 
    rdlvl_pi_incdec_i_5
       (.I0(p_14_in),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I2(mpr_rdlvl_start_r_reg_0),
        .I3(mpr_rdlvl_start_r),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(rdlvl_pi_incdec_i_5_n_0));
  FDRE rdlvl_pi_incdec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_pi_incdec_i_1_n_0),
        .Q(rdlvl_pi_incdec),
        .R(found_first_edge_r_reg_0));
  FDRE rdlvl_prech_req_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal1_prech_req_r__0),
        .Q(rdlvl_prech_req),
        .R(found_first_edge_r_reg_0));
  LUT6 #(
    .INIT(64'hAAAAAAAFAAAAAAA8)) 
    rdlvl_rank_done_r_i_1
       (.I0(rdlvl_rank_done_r),
        .I1(prech_done),
        .I2(p_3_in4_in),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I4(p_0_in118_in),
        .I5(rdlvl_stg1_rank_done),
        .O(rdlvl_rank_done_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT2 #(
    .INIT(4'h8)) 
    rdlvl_rank_done_r_i_2
       (.I0(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I1(cal1_prech_req_r),
        .O(rdlvl_rank_done_r));
  FDRE rdlvl_rank_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_rank_done_r_i_1_n_0),
        .Q(rdlvl_stg1_rank_done),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT2 #(
    .INIT(4'hE)) 
    rdlvl_stg1_done_int_i_1
       (.I0(rdlvl_stg1_done_int),
        .I1(D[3]),
        .O(rdlvl_stg1_done_int_i_1_n_0));
  (* syn_maxfan = "30" *) 
  FDRE rdlvl_stg1_done_int_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_stg1_done_int_i_1_n_0),
        .Q(D[3]),
        .R(found_first_edge_r_reg_0));
  FDRE rdlvl_stg1_start_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(rdlvl_stg1_start_r_reg_0),
        .Q(rdlvl_stg1_start_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000006666666E)) 
    \regl_dqs_cnt[0]_i_1 
       (.I0(\regl_dqs_cnt_reg_n_0_[0] ),
        .I1(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ),
        .I2(\regl_dqs_cnt_reg_n_0_[1] ),
        .I3(regl_rank_cnt[0]),
        .I4(regl_rank_cnt[1]),
        .I5(\regl_rank_cnt[1]_i_2_n_0 ),
        .O(\regl_dqs_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT4 #(
    .INIT(16'h1500)) 
    \regl_dqs_cnt[1]_i_1 
       (.I0(\regl_rank_cnt[1]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ),
        .I2(\regl_dqs_cnt_reg_n_0_[0] ),
        .I3(\regl_dqs_cnt_reg_n_0_[1] ),
        .O(\regl_dqs_cnt[1]_i_1_n_0 ));
  FDRE \regl_dqs_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\regl_dqs_cnt_reg_n_0_[0] ),
        .Q(regl_dqs_cnt_r[0]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\regl_dqs_cnt_reg_n_0_[1] ),
        .Q(regl_dqs_cnt_r[1]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\regl_dqs_cnt[0]_i_1_n_0 ),
        .Q(\regl_dqs_cnt_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \regl_dqs_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\regl_dqs_cnt[1]_i_1_n_0 ),
        .Q(\regl_dqs_cnt_reg_n_0_[1] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000AA6AAA2A)) 
    \regl_rank_cnt[0]_i_1 
       (.I0(regl_rank_cnt[0]),
        .I1(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ),
        .I2(\regl_dqs_cnt_reg_n_0_[0] ),
        .I3(\regl_dqs_cnt_reg_n_0_[1] ),
        .I4(regl_rank_cnt[1]),
        .I5(\regl_rank_cnt[1]_i_2_n_0 ),
        .O(\regl_rank_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AA6AAAAA)) 
    \regl_rank_cnt[1]_i_1 
       (.I0(regl_rank_cnt[1]),
        .I1(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ),
        .I2(\regl_dqs_cnt_reg_n_0_[0] ),
        .I3(\regl_dqs_cnt_reg_n_0_[1] ),
        .I4(regl_rank_cnt[0]),
        .I5(\regl_rank_cnt[1]_i_2_n_0 ),
        .O(\regl_rank_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT5 #(
    .INIT(32'hAAAAAAAB)) 
    \regl_rank_cnt[1]_i_2 
       (.I0(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .I1(done_cnt[3]),
        .I2(done_cnt[1]),
        .I3(done_cnt[0]),
        .I4(done_cnt[2]),
        .O(\regl_rank_cnt[1]_i_2_n_0 ));
  FDRE \regl_rank_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\regl_rank_cnt[0]_i_1_n_0 ),
        .Q(regl_rank_cnt[0]),
        .R(1'b0));
  FDRE \regl_rank_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\regl_rank_cnt[1]_i_1_n_0 ),
        .Q(regl_rank_cnt[1]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT5 #(
    .INIT(32'h000000AE)) 
    reset_if_i_1
       (.I0(reset_if),
        .I1(D[3]),
        .I2(reset_if_reg_0),
        .I3(reset_if_r9),
        .I4(reset_if_reg_1),
        .O(reset_if_reg));
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[0]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .O(right_edge_taps_r[0]));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[1]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(right_edge_taps_r[1]));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[2]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .O(right_edge_taps_r[2]));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[3]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .O(right_edge_taps_r[3]));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[4]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .O(right_edge_taps_r[4]));
  LUT4 #(
    .INIT(16'hBAAA)) 
    \right_edge_taps_r[5]_i_1 
       (.I0(cal1_prech_req_r),
        .I1(found_first_edge_r_reg_n_0),
        .I2(found_stable_eye_last_r),
        .I3(\right_edge_taps_r[5]_i_3_n_0 ),
        .O(\right_edge_taps_r[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[5]_i_2 
       (.I0(store_sr_req_pulsed_r),
        .I1(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .O(right_edge_taps_r[5]));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \right_edge_taps_r[5]_i_3 
       (.I0(found_edge_r_reg_n_0),
        .I1(store_sr_req_pulsed_r),
        .I2(detect_edge_done_r),
        .I3(tap_limit_cpt_r),
        .O(\right_edge_taps_r[5]_i_3_n_0 ));
  FDRE \right_edge_taps_r_reg[0] 
       (.C(CLK),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[0]),
        .Q(\right_edge_taps_r_reg_n_0_[0] ),
        .R(found_first_edge_r_reg_0));
  FDRE \right_edge_taps_r_reg[1] 
       (.C(CLK),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[1]),
        .Q(\right_edge_taps_r_reg_n_0_[1] ),
        .R(found_first_edge_r_reg_0));
  FDRE \right_edge_taps_r_reg[2] 
       (.C(CLK),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[2]),
        .Q(\right_edge_taps_r_reg_n_0_[2] ),
        .R(found_first_edge_r_reg_0));
  FDRE \right_edge_taps_r_reg[3] 
       (.C(CLK),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[3]),
        .Q(\right_edge_taps_r_reg_n_0_[3] ),
        .R(found_first_edge_r_reg_0));
  FDRE \right_edge_taps_r_reg[4] 
       (.C(CLK),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[4]),
        .Q(\right_edge_taps_r_reg_n_0_[4] ),
        .R(found_first_edge_r_reg_0));
  FDRE \right_edge_taps_r_reg[5] 
       (.C(CLK),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[5]),
        .Q(\right_edge_taps_r_reg_n_0_[5] ),
        .R(found_first_edge_r_reg_0));
  LUT6 #(
    .INIT(64'h1515C88855558888)) 
    \rnk_cnt_r[0]_i_1__0 
       (.I0(p_0_in118_in),
        .I1(cal1_prech_req_r),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\rnk_cnt_r_reg_n_0_[1] ),
        .I4(\rnk_cnt_r_reg_n_0_[0] ),
        .I5(prech_done),
        .O(\rnk_cnt_r[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h15C8DD005588DD00)) 
    \rnk_cnt_r[1]_i_1__0 
       (.I0(p_0_in118_in),
        .I1(cal1_prech_req_r),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\rnk_cnt_r_reg_n_0_[1] ),
        .I4(\rnk_cnt_r_reg_n_0_[0] ),
        .I5(prech_done),
        .O(\rnk_cnt_r[1]_i_1__0_n_0 ));
  FDRE \rnk_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rnk_cnt_r[0]_i_1__0_n_0 ),
        .Q(\rnk_cnt_r_reg_n_0_[0] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  FDRE \rnk_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rnk_cnt_r[1]_i_1__0_n_0 ),
        .Q(\rnk_cnt_r_reg_n_0_[1] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  LUT6 #(
    .INIT(64'h00000000AAAE0000)) 
    samp_cnt_done_r_i_1
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(samp_cnt_done_r_i_2_n_0),
        .I2(samp_cnt_done_r_i_3_n_0),
        .I3(samp_cnt_done_r_i_4_n_0),
        .I4(samp_edge_cnt0_en_r),
        .I5(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .O(samp_cnt_done_r_i_1_n_0));
  LUT4 #(
    .INIT(16'h0001)) 
    samp_cnt_done_r_i_2
       (.I0(samp_edge_cnt1_r_reg[11]),
        .I1(samp_edge_cnt1_r_reg[2]),
        .I2(samp_edge_cnt1_r_reg[4]),
        .I3(samp_edge_cnt1_r_reg[1]),
        .O(samp_cnt_done_r_i_2_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    samp_cnt_done_r_i_3
       (.I0(samp_edge_cnt1_r_reg[7]),
        .I1(samp_edge_cnt1_r_reg[5]),
        .I2(samp_edge_cnt1_r_reg[9]),
        .I3(samp_edge_cnt1_r_reg[6]),
        .O(samp_cnt_done_r_i_3_n_0));
  LUT4 #(
    .INIT(16'hFFFD)) 
    samp_cnt_done_r_i_4
       (.I0(samp_edge_cnt1_r_reg[0]),
        .I1(samp_edge_cnt1_r_reg[8]),
        .I2(samp_edge_cnt1_r_reg[10]),
        .I3(samp_edge_cnt1_r_reg[3]),
        .O(samp_cnt_done_r_i_4_n_0));
  FDRE samp_cnt_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(samp_cnt_done_r_i_1_n_0),
        .Q(samp_cnt_done_r_reg_n_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT2 #(
    .INIT(4'hE)) 
    samp_edge_cnt0_en_r_i_1
       (.I0(p_37_in),
        .I1(store_sr_req_pulsed_r),
        .O(pb_detect_edge));
  FDRE samp_edge_cnt0_en_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pb_detect_edge),
        .Q(samp_edge_cnt0_en_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \samp_edge_cnt0_r[0]_i_3 
       (.I0(samp_edge_cnt0_r_reg[0]),
        .O(\samp_edge_cnt0_r[0]_i_3_n_0 ));
  FDRE \samp_edge_cnt0_r_reg[0] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[0]_i_2_n_7 ),
        .Q(samp_edge_cnt0_r_reg[0]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \samp_edge_cnt0_r_reg[0]_i_2 
       (.CI(1'b0),
        .CO({\samp_edge_cnt0_r_reg[0]_i_2_n_0 ,\samp_edge_cnt0_r_reg[0]_i_2_n_1 ,\samp_edge_cnt0_r_reg[0]_i_2_n_2 ,\samp_edge_cnt0_r_reg[0]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\samp_edge_cnt0_r_reg[0]_i_2_n_4 ,\samp_edge_cnt0_r_reg[0]_i_2_n_5 ,\samp_edge_cnt0_r_reg[0]_i_2_n_6 ,\samp_edge_cnt0_r_reg[0]_i_2_n_7 }),
        .S({samp_edge_cnt0_r_reg[3:1],\samp_edge_cnt0_r[0]_i_3_n_0 }));
  FDRE \samp_edge_cnt0_r_reg[10] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[8]_i_1_n_5 ),
        .Q(samp_edge_cnt0_r_reg[10]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[11] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[8]_i_1_n_4 ),
        .Q(samp_edge_cnt0_r_reg[11]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[1] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[0]_i_2_n_6 ),
        .Q(samp_edge_cnt0_r_reg[1]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[2] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[0]_i_2_n_5 ),
        .Q(samp_edge_cnt0_r_reg[2]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[3] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[0]_i_2_n_4 ),
        .Q(samp_edge_cnt0_r_reg[3]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[4] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[4]_i_1_n_7 ),
        .Q(samp_edge_cnt0_r_reg[4]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \samp_edge_cnt0_r_reg[4]_i_1 
       (.CI(\samp_edge_cnt0_r_reg[0]_i_2_n_0 ),
        .CO({\samp_edge_cnt0_r_reg[4]_i_1_n_0 ,\samp_edge_cnt0_r_reg[4]_i_1_n_1 ,\samp_edge_cnt0_r_reg[4]_i_1_n_2 ,\samp_edge_cnt0_r_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\samp_edge_cnt0_r_reg[4]_i_1_n_4 ,\samp_edge_cnt0_r_reg[4]_i_1_n_5 ,\samp_edge_cnt0_r_reg[4]_i_1_n_6 ,\samp_edge_cnt0_r_reg[4]_i_1_n_7 }),
        .S(samp_edge_cnt0_r_reg[7:4]));
  FDRE \samp_edge_cnt0_r_reg[5] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[4]_i_1_n_6 ),
        .Q(samp_edge_cnt0_r_reg[5]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[6] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[4]_i_1_n_5 ),
        .Q(samp_edge_cnt0_r_reg[6]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[7] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[4]_i_1_n_4 ),
        .Q(samp_edge_cnt0_r_reg[7]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[8] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[8]_i_1_n_7 ),
        .Q(samp_edge_cnt0_r_reg[8]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \samp_edge_cnt0_r_reg[8]_i_1 
       (.CI(\samp_edge_cnt0_r_reg[4]_i_1_n_0 ),
        .CO({\NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED [3],\samp_edge_cnt0_r_reg[8]_i_1_n_1 ,\samp_edge_cnt0_r_reg[8]_i_1_n_2 ,\samp_edge_cnt0_r_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\samp_edge_cnt0_r_reg[8]_i_1_n_4 ,\samp_edge_cnt0_r_reg[8]_i_1_n_5 ,\samp_edge_cnt0_r_reg[8]_i_1_n_6 ,\samp_edge_cnt0_r_reg[8]_i_1_n_7 }),
        .S(samp_edge_cnt0_r_reg[11:8]));
  FDRE \samp_edge_cnt0_r_reg[9] 
       (.C(CLK),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[8]_i_1_n_6 ),
        .Q(samp_edge_cnt0_r_reg[9]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    samp_edge_cnt1_en_r_i_1
       (.I0(samp_edge_cnt1_en_r_i_2_n_0),
        .I1(samp_edge_cnt1_en_r_i_3_n_0),
        .I2(samp_edge_cnt0_r_reg[3]),
        .I3(samp_edge_cnt0_r_reg[0]),
        .I4(samp_edge_cnt0_r_reg[10]),
        .O(samp_edge_cnt1_en_r0));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    samp_edge_cnt1_en_r_i_2
       (.I0(samp_edge_cnt0_r_reg[6]),
        .I1(samp_edge_cnt0_r_reg[5]),
        .I2(samp_edge_cnt0_r_reg[7]),
        .I3(sr_valid_r2),
        .I4(samp_edge_cnt0_r_reg[8]),
        .I5(samp_edge_cnt0_r_reg[11]),
        .O(samp_edge_cnt1_en_r_i_2_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    samp_edge_cnt1_en_r_i_3
       (.I0(samp_edge_cnt0_r_reg[9]),
        .I1(samp_edge_cnt0_r_reg[4]),
        .I2(samp_edge_cnt0_r_reg[1]),
        .I3(samp_edge_cnt0_r_reg[2]),
        .O(samp_edge_cnt1_en_r_i_3_n_0));
  FDRE samp_edge_cnt1_en_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(samp_edge_cnt1_en_r0),
        .Q(samp_edge_cnt1_en_r),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \samp_edge_cnt1_r[0]_i_2 
       (.I0(samp_edge_cnt1_r_reg[0]),
        .O(\samp_edge_cnt1_r[0]_i_2_n_0 ));
  FDRE \samp_edge_cnt1_r_reg[0] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[0]_i_1_n_7 ),
        .Q(samp_edge_cnt1_r_reg[0]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \samp_edge_cnt1_r_reg[0]_i_1 
       (.CI(1'b0),
        .CO({\samp_edge_cnt1_r_reg[0]_i_1_n_0 ,\samp_edge_cnt1_r_reg[0]_i_1_n_1 ,\samp_edge_cnt1_r_reg[0]_i_1_n_2 ,\samp_edge_cnt1_r_reg[0]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\samp_edge_cnt1_r_reg[0]_i_1_n_4 ,\samp_edge_cnt1_r_reg[0]_i_1_n_5 ,\samp_edge_cnt1_r_reg[0]_i_1_n_6 ,\samp_edge_cnt1_r_reg[0]_i_1_n_7 }),
        .S({samp_edge_cnt1_r_reg[3:1],\samp_edge_cnt1_r[0]_i_2_n_0 }));
  FDRE \samp_edge_cnt1_r_reg[10] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[8]_i_1_n_5 ),
        .Q(samp_edge_cnt1_r_reg[10]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[11] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[8]_i_1_n_4 ),
        .Q(samp_edge_cnt1_r_reg[11]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[1] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[0]_i_1_n_6 ),
        .Q(samp_edge_cnt1_r_reg[1]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[2] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[0]_i_1_n_5 ),
        .Q(samp_edge_cnt1_r_reg[2]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[3] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[0]_i_1_n_4 ),
        .Q(samp_edge_cnt1_r_reg[3]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[4] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[4]_i_1_n_7 ),
        .Q(samp_edge_cnt1_r_reg[4]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \samp_edge_cnt1_r_reg[4]_i_1 
       (.CI(\samp_edge_cnt1_r_reg[0]_i_1_n_0 ),
        .CO({\samp_edge_cnt1_r_reg[4]_i_1_n_0 ,\samp_edge_cnt1_r_reg[4]_i_1_n_1 ,\samp_edge_cnt1_r_reg[4]_i_1_n_2 ,\samp_edge_cnt1_r_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\samp_edge_cnt1_r_reg[4]_i_1_n_4 ,\samp_edge_cnt1_r_reg[4]_i_1_n_5 ,\samp_edge_cnt1_r_reg[4]_i_1_n_6 ,\samp_edge_cnt1_r_reg[4]_i_1_n_7 }),
        .S(samp_edge_cnt1_r_reg[7:4]));
  FDRE \samp_edge_cnt1_r_reg[5] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[4]_i_1_n_6 ),
        .Q(samp_edge_cnt1_r_reg[5]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[6] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[4]_i_1_n_5 ),
        .Q(samp_edge_cnt1_r_reg[6]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[7] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[4]_i_1_n_4 ),
        .Q(samp_edge_cnt1_r_reg[7]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[8] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[8]_i_1_n_7 ),
        .Q(samp_edge_cnt1_r_reg[8]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \samp_edge_cnt1_r_reg[8]_i_1 
       (.CI(\samp_edge_cnt1_r_reg[4]_i_1_n_0 ),
        .CO({\NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED [3],\samp_edge_cnt1_r_reg[8]_i_1_n_1 ,\samp_edge_cnt1_r_reg[8]_i_1_n_2 ,\samp_edge_cnt1_r_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\samp_edge_cnt1_r_reg[8]_i_1_n_4 ,\samp_edge_cnt1_r_reg[8]_i_1_n_5 ,\samp_edge_cnt1_r_reg[8]_i_1_n_6 ,\samp_edge_cnt1_r_reg[8]_i_1_n_7 }),
        .S(samp_edge_cnt1_r_reg[11:8]));
  FDRE \samp_edge_cnt1_r_reg[9] 
       (.C(CLK),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[8]_i_1_n_6 ),
        .Q(samp_edge_cnt1_r_reg[9]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \second_edge_taps_r[0]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .O(tap_cnt_cpt_r0));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT3 #(
    .INIT(8'h82)) 
    \second_edge_taps_r[1]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(\second_edge_taps_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT4 #(
    .INIT(16'hA802)) 
    \second_edge_taps_r[2]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .O(\second_edge_taps_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT5 #(
    .INIT(32'hAAA80002)) 
    \second_edge_taps_r[3]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .O(\second_edge_taps_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAA800000002)) 
    \second_edge_taps_r[4]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I5(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .O(\second_edge_taps_r[4]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \second_edge_taps_r[5]_i_1 
       (.I0(\second_edge_taps_r[5]_i_2_n_0 ),
        .I1(store_sr_req_pulsed_r),
        .O(\second_edge_taps_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00800000)) 
    \second_edge_taps_r[5]_i_2 
       (.I0(found_edge_r_reg_n_0),
        .I1(store_sr_req_pulsed_r),
        .I2(detect_edge_done_r),
        .I3(tap_limit_cpt_r),
        .I4(\first_edge_taps_r[5]_i_3_n_0 ),
        .I5(cal1_prech_req_r),
        .O(\second_edge_taps_r[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    \second_edge_taps_r[5]_i_3 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I5(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .O(\second_edge_taps_r[5]_i_3_n_0 ));
  FDRE \second_edge_taps_r_reg[0] 
       (.C(CLK),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(tap_cnt_cpt_r0),
        .Q(\second_edge_taps_r_reg_n_0_[0] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE \second_edge_taps_r_reg[1] 
       (.C(CLK),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[1]_i_1_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \second_edge_taps_r_reg[2] 
       (.C(CLK),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[2]_i_1_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \second_edge_taps_r_reg[3] 
       (.C(CLK),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[3]_i_1_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \second_edge_taps_r_reg[4] 
       (.C(CLK),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[4]_i_1_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \second_edge_taps_r_reg[5] 
       (.C(CLK),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[5]_i_3_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[5] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE sr_valid_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(sr_valid_r_reg_n_0),
        .Q(sr_valid_r1),
        .R(1'b0));
  FDRE sr_valid_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(sr_valid_r1),
        .Q(sr_valid_r2),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000008)) 
    sr_valid_r_i_1
       (.I0(E),
        .I1(rdlvl_stg1_start_r_reg_0),
        .I2(cnt_shift_r_reg[2]),
        .I3(cnt_shift_r_reg[3]),
        .I4(cnt_shift_r_reg[1]),
        .I5(cnt_shift_r_reg[0]),
        .O(sr_valid_r_i_1_n_0));
  FDRE sr_valid_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(sr_valid_r_i_1_n_0),
        .Q(sr_valid_r_reg_n_0),
        .R(in0));
  LUT3 #(
    .INIT(8'hBA)) 
    store_sr_r_i_1
       (.I0(store_sr_req_r_reg_n_0),
        .I1(sr_valid_r_reg_n_0),
        .I2(store_sr_r_reg_n_0),
        .O(store_sr_r_i_1_n_0));
  FDRE store_sr_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(store_sr_r_i_1_n_0),
        .Q(store_sr_r_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  FDRE store_sr_req_pulsed_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(store_sr_req_pulsed_r),
        .Q(store_sr_req_pulsed_r__0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT5 #(
    .INIT(32'h4F444444)) 
    store_sr_req_r_i_1
       (.I0(store_sr_req_pulsed_r__0),
        .I1(store_sr_req_pulsed_r),
        .I2(cal1_wait_r),
        .I3(store_sr_req_r_reg_0),
        .I4(p_3_in4_in),
        .O(store_sr_req_r));
  FDRE store_sr_req_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(store_sr_req_r),
        .Q(store_sr_req_r_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][1][4]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'h69)) 
    \tap_cnt_cpt_r[1]_i_1 
       (.I0(cal1_dlyinc_cpt_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(\tap_cnt_cpt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT4 #(
    .INIT(16'h6AA9)) 
    \tap_cnt_cpt_r[2]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I3(cal1_dlyinc_cpt_r_reg_n_0),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT5 #(
    .INIT(32'h6CCCCCC9)) 
    \tap_cnt_cpt_r[3]_i_1 
       (.I0(cal1_dlyinc_cpt_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .O(p_0_in__0[3]));
  LUT6 #(
    .INIT(64'h6CCCCCCCCCCCCCC9)) 
    \tap_cnt_cpt_r[4]_i_1 
       (.I0(cal1_dlyinc_cpt_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I5(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .O(p_0_in__0[4]));
  LUT4 #(
    .INIT(16'hAA8A)) 
    \tap_cnt_cpt_r[5]_i_2 
       (.I0(cal1_dlyce_cpt_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I2(\tap_cnt_cpt_r[5]_i_4_n_0 ),
        .I3(cal1_dlyinc_cpt_r_reg_n_0),
        .O(tap_cnt_cpt_r));
  LUT4 #(
    .INIT(16'h1DD1)) 
    \tap_cnt_cpt_r[5]_i_3 
       (.I0(\tap_cnt_cpt_r[5]_i_5_n_0 ),
        .I1(cal1_dlyinc_cpt_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I3(\tap_cnt_cpt_r[5]_i_6_n_0 ),
        .O(p_0_in__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \tap_cnt_cpt_r[5]_i_4 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .O(\tap_cnt_cpt_r[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555555556)) 
    \tap_cnt_cpt_r[5]_i_5 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .O(\tap_cnt_cpt_r[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \tap_cnt_cpt_r[5]_i_6 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .O(\tap_cnt_cpt_r[5]_i_6_n_0 ));
  FDRE \tap_cnt_cpt_r_reg[0] 
       (.C(CLK),
        .CE(tap_cnt_cpt_r),
        .D(tap_cnt_cpt_r0),
        .Q(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .R(\tap_cnt_cpt_r_reg[5]_0 ));
  FDRE \tap_cnt_cpt_r_reg[1] 
       (.C(CLK),
        .CE(tap_cnt_cpt_r),
        .D(\tap_cnt_cpt_r[1]_i_1_n_0 ),
        .Q(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .R(\tap_cnt_cpt_r_reg[5]_0 ));
  FDRE \tap_cnt_cpt_r_reg[2] 
       (.C(CLK),
        .CE(tap_cnt_cpt_r),
        .D(p_0_in__0[2]),
        .Q(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .R(\tap_cnt_cpt_r_reg[5]_0 ));
  FDRE \tap_cnt_cpt_r_reg[3] 
       (.C(CLK),
        .CE(tap_cnt_cpt_r),
        .D(p_0_in__0[3]),
        .Q(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .R(\tap_cnt_cpt_r_reg[5]_0 ));
  FDRE \tap_cnt_cpt_r_reg[4] 
       (.C(CLK),
        .CE(tap_cnt_cpt_r),
        .D(p_0_in__0[4]),
        .Q(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .R(\tap_cnt_cpt_r_reg[5]_0 ));
  FDRE \tap_cnt_cpt_r_reg[5] 
       (.C(CLK),
        .CE(tap_cnt_cpt_r),
        .D(p_0_in__0[5]),
        .Q(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .R(\tap_cnt_cpt_r_reg[5]_0 ));
  LUT6 #(
    .INIT(64'h000000000000AA80)) 
    tap_limit_cpt_r_i_1
       (.I0(tap_limit_cpt_r_i_2_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I2(\tap_cnt_cpt_r[5]_i_6_n_0 ),
        .I3(tap_limit_cpt_r),
        .I4(\idelay_tap_cnt_r_reg[0][1][1]_0 ),
        .I5(new_cnt_cpt_r_reg_0),
        .O(tap_limit_cpt_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    tap_limit_cpt_r_i_2
       (.I0(\cal1_state_r1_reg_n_0_[4] ),
        .I1(\cal1_state_r1_reg_n_0_[0] ),
        .I2(\cal1_state_r1_reg_n_0_[5] ),
        .I3(\cal1_state_r1_reg_n_0_[2] ),
        .I4(\cal1_state_r1_reg_n_0_[3] ),
        .I5(\cal1_state_r1_reg_n_0_[1] ),
        .O(tap_limit_cpt_r_i_2_n_0));
  FDRE tap_limit_cpt_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tap_limit_cpt_r_i_1_n_0),
        .Q(tap_limit_cpt_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_cnt_r[0]_i_1__0 
       (.I0(wait_cnt_r_reg[0]),
        .O(wait_cnt_r0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wait_cnt_r[1]_i_1__0 
       (.I0(wait_cnt_r_reg[0]),
        .I1(wait_cnt_r_reg[1]),
        .O(\wait_cnt_r[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wait_cnt_r[2]_i_1__0 
       (.I0(wait_cnt_r_reg[2]),
        .I1(wait_cnt_r_reg[1]),
        .I2(wait_cnt_r_reg[0]),
        .O(wait_cnt_r0__0[2]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \wait_cnt_r[3]_i_2__0 
       (.I0(dqs_po_dec_done_r2),
        .I1(wait_cnt_r_reg[2]),
        .I2(wait_cnt_r_reg[3]),
        .I3(wait_cnt_r_reg[0]),
        .I4(wait_cnt_r_reg[1]),
        .O(wait_cnt_r0));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wait_cnt_r[3]_i_3__0 
       (.I0(wait_cnt_r_reg[3]),
        .I1(wait_cnt_r_reg[2]),
        .I2(wait_cnt_r_reg[0]),
        .I3(wait_cnt_r_reg[1]),
        .O(wait_cnt_r0__0[3]));
  FDRE \wait_cnt_r_reg[0] 
       (.C(CLK),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0[0]),
        .Q(wait_cnt_r_reg[0]),
        .R(\wait_cnt_r_reg[0]_0 ));
  FDRE \wait_cnt_r_reg[1] 
       (.C(CLK),
        .CE(wait_cnt_r0),
        .D(\wait_cnt_r[1]_i_1__0_n_0 ),
        .Q(wait_cnt_r_reg[1]),
        .R(\wait_cnt_r_reg[0]_0 ));
  FDRE \wait_cnt_r_reg[2] 
       (.C(CLK),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0[2]),
        .Q(wait_cnt_r_reg[2]),
        .R(\wait_cnt_r_reg[0]_0 ));
  FDSE \wait_cnt_r_reg[3] 
       (.C(CLK),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0[3]),
        .Q(wait_cnt_r_reg[3]),
        .S(\wait_cnt_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[109]_i_1 
       (.I0(D[3]),
        .O(D[2]));
  LUT2 #(
    .INIT(4'h2)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[123]_i_1 
       (.I0(D[3]),
        .I1(first_wrcal_pat_r),
        .O(D[4]));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[13]_i_1 
       (.I0(D[3]),
        .I1(first_rdlvl_pat_r),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[46]_i_1 
       (.I0(D[3]),
        .I1(first_wrcal_pat_r),
        .O(D[1]));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_tempmon
   (pi_f_inc_reg_0,
    pi_f_dec_reg_0,
    delay_done_r4_reg,
    rdlvl_stg1_done_int_reg,
    calib_sel0,
    init_calib_complete_reg,
    wrcal_done_reg,
    CLK,
    pi_f_dec_reg_1,
    mc_ref_zq_wip,
    \three_dec_max_limit_reg[0]_0 ,
    ck_addr_cmd_delay_done,
    \gen_byte_sel_div2.byte_sel_cnt_reg[1] ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ,
    D,
    \calib_sel_reg[0] ,
    calib_complete,
    pi_dqs_found_done,
    \device_temp_101_reg[11]_0 );
  output pi_f_inc_reg_0;
  output pi_f_dec_reg_0;
  output delay_done_r4_reg;
  output rdlvl_stg1_done_int_reg;
  output calib_sel0;
  output init_calib_complete_reg;
  output wrcal_done_reg;
  input CLK;
  input pi_f_dec_reg_1;
  input mc_ref_zq_wip;
  input [3:0]\three_dec_max_limit_reg[0]_0 ;
  input ck_addr_cmd_delay_done;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[1] ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ;
  input [0:0]D;
  input \calib_sel_reg[0] ;
  input calib_complete;
  input pi_dqs_found_done;
  input [11:0]\device_temp_101_reg[11]_0 ;

  wire CLK;
  wire [0:0]D;
  wire calib_complete;
  wire calib_sel0;
  wire \calib_sel_reg[0] ;
  wire ck_addr_cmd_delay_done;
  wire delay_done_r4_reg;
  wire [11:0]device_temp_101;
  wire [11:0]\device_temp_101_reg[11]_0 ;
  wire [11:0]device_temp_init;
  wire \device_temp_init[11]_i_2_n_0 ;
  wire \device_temp_init[11]_i_3_n_0 ;
  wire [11:0]four_dec_min_limit;
  wire \four_dec_min_limit[11]_i_2_n_0 ;
  wire \four_dec_min_limit[11]_i_3_n_0 ;
  wire \four_dec_min_limit[5]_i_2_n_0 ;
  wire \four_dec_min_limit[5]_i_3_n_0 ;
  wire \four_dec_min_limit[5]_i_4_n_0 ;
  wire \four_dec_min_limit[9]_i_2_n_0 ;
  wire \four_dec_min_limit[9]_i_3_n_0 ;
  wire \four_dec_min_limit[9]_i_4_n_0 ;
  wire \four_dec_min_limit[9]_i_5_n_0 ;
  wire [11:2]four_dec_min_limit_nxt;
  wire \four_dec_min_limit_reg[11]_i_1_n_3 ;
  wire \four_dec_min_limit_reg[5]_i_1_n_0 ;
  wire \four_dec_min_limit_reg[5]_i_1_n_1 ;
  wire \four_dec_min_limit_reg[5]_i_1_n_2 ;
  wire \four_dec_min_limit_reg[5]_i_1_n_3 ;
  wire \four_dec_min_limit_reg[9]_i_1_n_0 ;
  wire \four_dec_min_limit_reg[9]_i_1_n_1 ;
  wire \four_dec_min_limit_reg[9]_i_1_n_2 ;
  wire \four_dec_min_limit_reg[9]_i_1_n_3 ;
  wire [11:2]four_inc_max_limit;
  wire \four_inc_max_limit[11]_i_2_n_0 ;
  wire \four_inc_max_limit[11]_i_3_n_0 ;
  wire \four_inc_max_limit[4]_i_2_n_0 ;
  wire \four_inc_max_limit[4]_i_3_n_0 ;
  wire \four_inc_max_limit[4]_i_4_n_0 ;
  wire \four_inc_max_limit[4]_i_5_n_0 ;
  wire \four_inc_max_limit[8]_i_2_n_0 ;
  wire \four_inc_max_limit[8]_i_3_n_0 ;
  wire [11:2]four_inc_max_limit_nxt;
  wire \four_inc_max_limit_reg[11]_i_1_n_2 ;
  wire \four_inc_max_limit_reg[11]_i_1_n_3 ;
  wire \four_inc_max_limit_reg[4]_i_1_n_0 ;
  wire \four_inc_max_limit_reg[4]_i_1_n_1 ;
  wire \four_inc_max_limit_reg[4]_i_1_n_2 ;
  wire \four_inc_max_limit_reg[4]_i_1_n_3 ;
  wire \four_inc_max_limit_reg[8]_i_1_n_0 ;
  wire \four_inc_max_limit_reg[8]_i_1_n_1 ;
  wire \four_inc_max_limit_reg[8]_i_1_n_2 ;
  wire \four_inc_max_limit_reg[8]_i_1_n_3 ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[1] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ;
  wire init_calib_complete_reg;
  wire mc_ref_zq_wip;
  wire [11:1]neutral_max_limit;
  wire \neutral_max_limit[1]_i_1_n_0 ;
  wire \neutral_max_limit[4]_i_2_n_0 ;
  wire \neutral_max_limit[4]_i_3_n_0 ;
  wire \neutral_max_limit[4]_i_4_n_0 ;
  wire \neutral_max_limit[8]_i_2_n_0 ;
  wire \neutral_max_limit[8]_i_3_n_0 ;
  wire [11:2]neutral_max_limit_nxt;
  wire \neutral_max_limit_reg[11]_i_1_n_2 ;
  wire \neutral_max_limit_reg[11]_i_1_n_3 ;
  wire \neutral_max_limit_reg[4]_i_1_n_0 ;
  wire \neutral_max_limit_reg[4]_i_1_n_1 ;
  wire \neutral_max_limit_reg[4]_i_1_n_2 ;
  wire \neutral_max_limit_reg[4]_i_1_n_3 ;
  wire \neutral_max_limit_reg[8]_i_1_n_0 ;
  wire \neutral_max_limit_reg[8]_i_1_n_1 ;
  wire \neutral_max_limit_reg[8]_i_1_n_2 ;
  wire \neutral_max_limit_reg[8]_i_1_n_3 ;
  wire [11:2]neutral_min_limit;
  wire \neutral_min_limit[11]_i_2_n_0 ;
  wire \neutral_min_limit[11]_i_3_n_0 ;
  wire \neutral_min_limit[5]_i_2_n_0 ;
  wire \neutral_min_limit[5]_i_3_n_0 ;
  wire \neutral_min_limit[5]_i_4_n_0 ;
  wire \neutral_min_limit[9]_i_2_n_0 ;
  wire \neutral_min_limit[9]_i_3_n_0 ;
  wire \neutral_min_limit[9]_i_4_n_0 ;
  wire \neutral_min_limit[9]_i_5_n_0 ;
  wire [11:2]neutral_min_limit_nxt;
  wire \neutral_min_limit_reg[11]_i_1_n_3 ;
  wire \neutral_min_limit_reg[5]_i_1_n_0 ;
  wire \neutral_min_limit_reg[5]_i_1_n_1 ;
  wire \neutral_min_limit_reg[5]_i_1_n_2 ;
  wire \neutral_min_limit_reg[5]_i_1_n_3 ;
  wire \neutral_min_limit_reg[9]_i_1_n_0 ;
  wire \neutral_min_limit_reg[9]_i_1_n_1 ;
  wire \neutral_min_limit_reg[9]_i_1_n_2 ;
  wire \neutral_min_limit_reg[9]_i_1_n_3 ;
  wire [11:1]one_dec_max_limit;
  wire \one_dec_max_limit[1]_i_1_n_0 ;
  wire \one_dec_max_limit[4]_i_2_n_0 ;
  wire \one_dec_max_limit[8]_i_2_n_0 ;
  wire \one_dec_max_limit[8]_i_3_n_0 ;
  wire \one_dec_max_limit[8]_i_4_n_0 ;
  wire [11:2]one_dec_max_limit_nxt;
  wire \one_dec_max_limit_reg[11]_i_1_n_2 ;
  wire \one_dec_max_limit_reg[11]_i_1_n_3 ;
  wire \one_dec_max_limit_reg[4]_i_1_n_0 ;
  wire \one_dec_max_limit_reg[4]_i_1_n_1 ;
  wire \one_dec_max_limit_reg[4]_i_1_n_2 ;
  wire \one_dec_max_limit_reg[4]_i_1_n_3 ;
  wire \one_dec_max_limit_reg[8]_i_1_n_0 ;
  wire \one_dec_max_limit_reg[8]_i_1_n_1 ;
  wire \one_dec_max_limit_reg[8]_i_1_n_2 ;
  wire \one_dec_max_limit_reg[8]_i_1_n_3 ;
  wire [11:2]one_dec_min_limit;
  wire \one_dec_min_limit[11]_i_2_n_0 ;
  wire \one_dec_min_limit[11]_i_3_n_0 ;
  wire \one_dec_min_limit[5]_i_2_n_0 ;
  wire \one_dec_min_limit[5]_i_3_n_0 ;
  wire \one_dec_min_limit[5]_i_4_n_0 ;
  wire \one_dec_min_limit[9]_i_2_n_0 ;
  wire \one_dec_min_limit[9]_i_3_n_0 ;
  wire \one_dec_min_limit[9]_i_4_n_0 ;
  wire \one_dec_min_limit[9]_i_5_n_0 ;
  wire [11:2]one_dec_min_limit_nxt;
  wire \one_dec_min_limit_reg[11]_i_1_n_3 ;
  wire \one_dec_min_limit_reg[5]_i_1_n_0 ;
  wire \one_dec_min_limit_reg[5]_i_1_n_1 ;
  wire \one_dec_min_limit_reg[5]_i_1_n_2 ;
  wire \one_dec_min_limit_reg[5]_i_1_n_3 ;
  wire \one_dec_min_limit_reg[9]_i_1_n_0 ;
  wire \one_dec_min_limit_reg[9]_i_1_n_1 ;
  wire \one_dec_min_limit_reg[9]_i_1_n_2 ;
  wire \one_dec_min_limit_reg[9]_i_1_n_3 ;
  wire [11:2]one_inc_max_limit;
  wire \one_inc_max_limit[11]_i_2_n_0 ;
  wire \one_inc_max_limit[11]_i_3_n_0 ;
  wire \one_inc_max_limit[11]_i_4_n_0 ;
  wire \one_inc_max_limit[4]_i_2_n_0 ;
  wire \one_inc_max_limit[8]_i_2_n_0 ;
  wire \one_inc_max_limit[8]_i_3_n_0 ;
  wire [11:2]one_inc_max_limit_nxt;
  wire \one_inc_max_limit_reg[11]_i_1_n_2 ;
  wire \one_inc_max_limit_reg[11]_i_1_n_3 ;
  wire \one_inc_max_limit_reg[4]_i_1_n_0 ;
  wire \one_inc_max_limit_reg[4]_i_1_n_1 ;
  wire \one_inc_max_limit_reg[4]_i_1_n_2 ;
  wire \one_inc_max_limit_reg[4]_i_1_n_3 ;
  wire \one_inc_max_limit_reg[8]_i_1_n_0 ;
  wire \one_inc_max_limit_reg[8]_i_1_n_1 ;
  wire \one_inc_max_limit_reg[8]_i_1_n_2 ;
  wire \one_inc_max_limit_reg[8]_i_1_n_3 ;
  wire [11:2]one_inc_min_limit;
  wire \one_inc_min_limit[11]_i_2_n_0 ;
  wire \one_inc_min_limit[11]_i_3_n_0 ;
  wire \one_inc_min_limit[5]_i_2_n_0 ;
  wire \one_inc_min_limit[5]_i_3_n_0 ;
  wire \one_inc_min_limit[5]_i_4_n_0 ;
  wire \one_inc_min_limit[9]_i_2_n_0 ;
  wire \one_inc_min_limit[9]_i_3_n_0 ;
  wire \one_inc_min_limit[9]_i_4_n_0 ;
  wire \one_inc_min_limit[9]_i_5_n_0 ;
  wire [11:2]one_inc_min_limit_nxt;
  wire \one_inc_min_limit_reg[11]_i_1_n_3 ;
  wire \one_inc_min_limit_reg[5]_i_1_n_0 ;
  wire \one_inc_min_limit_reg[5]_i_1_n_1 ;
  wire \one_inc_min_limit_reg[5]_i_1_n_2 ;
  wire \one_inc_min_limit_reg[5]_i_1_n_3 ;
  wire \one_inc_min_limit_reg[9]_i_1_n_0 ;
  wire \one_inc_min_limit_reg[9]_i_1_n_1 ;
  wire \one_inc_min_limit_reg[9]_i_1_n_2 ;
  wire \one_inc_min_limit_reg[9]_i_1_n_3 ;
  wire p_0_in;
  wire pi_dqs_found_done;
  wire pi_f_dec_i_2_n_0;
  wire pi_f_dec_nxt;
  wire pi_f_dec_reg_0;
  wire pi_f_dec_reg_1;
  wire pi_f_inc_i_2_n_0;
  wire pi_f_inc_i_3_n_0;
  wire pi_f_inc_i_4_n_0;
  wire pi_f_inc_i_5_n_0;
  wire pi_f_inc_i_6_n_0;
  wire pi_f_inc_i_7_n_0;
  wire pi_f_inc_nxt;
  wire pi_f_inc_reg_0;
  wire rdlvl_stg1_done_int_reg;
  wire temp_cmp_four_dec_min_101;
  wire temp_cmp_four_dec_min_102;
  wire temp_cmp_four_dec_min_102_i_10_n_0;
  wire temp_cmp_four_dec_min_102_i_11_n_0;
  wire temp_cmp_four_dec_min_102_i_12_n_0;
  wire temp_cmp_four_dec_min_102_i_13_n_0;
  wire temp_cmp_four_dec_min_102_i_14_n_0;
  wire temp_cmp_four_dec_min_102_i_3_n_0;
  wire temp_cmp_four_dec_min_102_i_4_n_0;
  wire temp_cmp_four_dec_min_102_i_5_n_0;
  wire temp_cmp_four_dec_min_102_i_6_n_0;
  wire temp_cmp_four_dec_min_102_i_7_n_0;
  wire temp_cmp_four_dec_min_102_i_8_n_0;
  wire temp_cmp_four_dec_min_102_i_9_n_0;
  wire temp_cmp_four_dec_min_102_reg_i_1_n_3;
  wire temp_cmp_four_dec_min_102_reg_i_2_n_0;
  wire temp_cmp_four_dec_min_102_reg_i_2_n_1;
  wire temp_cmp_four_dec_min_102_reg_i_2_n_2;
  wire temp_cmp_four_dec_min_102_reg_i_2_n_3;
  wire temp_cmp_four_inc_max_101;
  wire temp_cmp_four_inc_max_102;
  wire temp_cmp_four_inc_max_102_i_10_n_0;
  wire temp_cmp_four_inc_max_102_i_11_n_0;
  wire temp_cmp_four_inc_max_102_i_12_n_0;
  wire temp_cmp_four_inc_max_102_i_13_n_0;
  wire temp_cmp_four_inc_max_102_i_14_n_0;
  wire temp_cmp_four_inc_max_102_i_3_n_0;
  wire temp_cmp_four_inc_max_102_i_4_n_0;
  wire temp_cmp_four_inc_max_102_i_5_n_0;
  wire temp_cmp_four_inc_max_102_i_6_n_0;
  wire temp_cmp_four_inc_max_102_i_7_n_0;
  wire temp_cmp_four_inc_max_102_i_8_n_0;
  wire temp_cmp_four_inc_max_102_i_9_n_0;
  wire temp_cmp_four_inc_max_102_reg_i_1_n_3;
  wire temp_cmp_four_inc_max_102_reg_i_2_n_0;
  wire temp_cmp_four_inc_max_102_reg_i_2_n_1;
  wire temp_cmp_four_inc_max_102_reg_i_2_n_2;
  wire temp_cmp_four_inc_max_102_reg_i_2_n_3;
  wire temp_cmp_neutral_max_101;
  wire temp_cmp_neutral_max_102;
  wire temp_cmp_neutral_max_102_i_10_n_0;
  wire temp_cmp_neutral_max_102_i_11_n_0;
  wire temp_cmp_neutral_max_102_i_12_n_0;
  wire temp_cmp_neutral_max_102_i_13_n_0;
  wire temp_cmp_neutral_max_102_i_14_n_0;
  wire temp_cmp_neutral_max_102_i_3_n_0;
  wire temp_cmp_neutral_max_102_i_4_n_0;
  wire temp_cmp_neutral_max_102_i_5_n_0;
  wire temp_cmp_neutral_max_102_i_6_n_0;
  wire temp_cmp_neutral_max_102_i_7_n_0;
  wire temp_cmp_neutral_max_102_i_8_n_0;
  wire temp_cmp_neutral_max_102_i_9_n_0;
  wire temp_cmp_neutral_max_102_reg_i_1_n_3;
  wire temp_cmp_neutral_max_102_reg_i_2_n_0;
  wire temp_cmp_neutral_max_102_reg_i_2_n_1;
  wire temp_cmp_neutral_max_102_reg_i_2_n_2;
  wire temp_cmp_neutral_max_102_reg_i_2_n_3;
  wire temp_cmp_neutral_min_101;
  wire temp_cmp_neutral_min_102;
  wire temp_cmp_neutral_min_102_i_10_n_0;
  wire temp_cmp_neutral_min_102_i_11_n_0;
  wire temp_cmp_neutral_min_102_i_12_n_0;
  wire temp_cmp_neutral_min_102_i_13_n_0;
  wire temp_cmp_neutral_min_102_i_14_n_0;
  wire temp_cmp_neutral_min_102_i_3_n_0;
  wire temp_cmp_neutral_min_102_i_4_n_0;
  wire temp_cmp_neutral_min_102_i_5_n_0;
  wire temp_cmp_neutral_min_102_i_6_n_0;
  wire temp_cmp_neutral_min_102_i_7_n_0;
  wire temp_cmp_neutral_min_102_i_8_n_0;
  wire temp_cmp_neutral_min_102_i_9_n_0;
  wire temp_cmp_neutral_min_102_reg_i_1_n_3;
  wire temp_cmp_neutral_min_102_reg_i_2_n_0;
  wire temp_cmp_neutral_min_102_reg_i_2_n_1;
  wire temp_cmp_neutral_min_102_reg_i_2_n_2;
  wire temp_cmp_neutral_min_102_reg_i_2_n_3;
  wire temp_cmp_one_dec_max_101;
  wire temp_cmp_one_dec_max_102;
  wire temp_cmp_one_dec_max_102_i_10_n_0;
  wire temp_cmp_one_dec_max_102_i_11_n_0;
  wire temp_cmp_one_dec_max_102_i_12_n_0;
  wire temp_cmp_one_dec_max_102_i_13_n_0;
  wire temp_cmp_one_dec_max_102_i_14_n_0;
  wire temp_cmp_one_dec_max_102_i_3_n_0;
  wire temp_cmp_one_dec_max_102_i_4_n_0;
  wire temp_cmp_one_dec_max_102_i_5_n_0;
  wire temp_cmp_one_dec_max_102_i_6_n_0;
  wire temp_cmp_one_dec_max_102_i_7_n_0;
  wire temp_cmp_one_dec_max_102_i_8_n_0;
  wire temp_cmp_one_dec_max_102_i_9_n_0;
  wire temp_cmp_one_dec_max_102_reg_i_1_n_3;
  wire temp_cmp_one_dec_max_102_reg_i_2_n_0;
  wire temp_cmp_one_dec_max_102_reg_i_2_n_1;
  wire temp_cmp_one_dec_max_102_reg_i_2_n_2;
  wire temp_cmp_one_dec_max_102_reg_i_2_n_3;
  wire temp_cmp_one_dec_min_101;
  wire temp_cmp_one_dec_min_102;
  wire temp_cmp_one_dec_min_102_i_10_n_0;
  wire temp_cmp_one_dec_min_102_i_11_n_0;
  wire temp_cmp_one_dec_min_102_i_12_n_0;
  wire temp_cmp_one_dec_min_102_i_13_n_0;
  wire temp_cmp_one_dec_min_102_i_14_n_0;
  wire temp_cmp_one_dec_min_102_i_3_n_0;
  wire temp_cmp_one_dec_min_102_i_4_n_0;
  wire temp_cmp_one_dec_min_102_i_5_n_0;
  wire temp_cmp_one_dec_min_102_i_6_n_0;
  wire temp_cmp_one_dec_min_102_i_7_n_0;
  wire temp_cmp_one_dec_min_102_i_8_n_0;
  wire temp_cmp_one_dec_min_102_i_9_n_0;
  wire temp_cmp_one_dec_min_102_reg_i_1_n_3;
  wire temp_cmp_one_dec_min_102_reg_i_2_n_0;
  wire temp_cmp_one_dec_min_102_reg_i_2_n_1;
  wire temp_cmp_one_dec_min_102_reg_i_2_n_2;
  wire temp_cmp_one_dec_min_102_reg_i_2_n_3;
  wire temp_cmp_one_inc_max_101;
  wire temp_cmp_one_inc_max_102;
  wire temp_cmp_one_inc_max_102_i_10_n_0;
  wire temp_cmp_one_inc_max_102_i_11_n_0;
  wire temp_cmp_one_inc_max_102_i_12_n_0;
  wire temp_cmp_one_inc_max_102_i_13_n_0;
  wire temp_cmp_one_inc_max_102_i_14_n_0;
  wire temp_cmp_one_inc_max_102_i_3_n_0;
  wire temp_cmp_one_inc_max_102_i_4_n_0;
  wire temp_cmp_one_inc_max_102_i_5_n_0;
  wire temp_cmp_one_inc_max_102_i_6_n_0;
  wire temp_cmp_one_inc_max_102_i_7_n_0;
  wire temp_cmp_one_inc_max_102_i_8_n_0;
  wire temp_cmp_one_inc_max_102_i_9_n_0;
  wire temp_cmp_one_inc_max_102_reg_i_1_n_3;
  wire temp_cmp_one_inc_max_102_reg_i_2_n_0;
  wire temp_cmp_one_inc_max_102_reg_i_2_n_1;
  wire temp_cmp_one_inc_max_102_reg_i_2_n_2;
  wire temp_cmp_one_inc_max_102_reg_i_2_n_3;
  wire temp_cmp_one_inc_min_101;
  wire temp_cmp_one_inc_min_102;
  wire temp_cmp_one_inc_min_102_i_10_n_0;
  wire temp_cmp_one_inc_min_102_i_11_n_0;
  wire temp_cmp_one_inc_min_102_i_12_n_0;
  wire temp_cmp_one_inc_min_102_i_13_n_0;
  wire temp_cmp_one_inc_min_102_i_14_n_0;
  wire temp_cmp_one_inc_min_102_i_3_n_0;
  wire temp_cmp_one_inc_min_102_i_4_n_0;
  wire temp_cmp_one_inc_min_102_i_5_n_0;
  wire temp_cmp_one_inc_min_102_i_6_n_0;
  wire temp_cmp_one_inc_min_102_i_7_n_0;
  wire temp_cmp_one_inc_min_102_i_8_n_0;
  wire temp_cmp_one_inc_min_102_i_9_n_0;
  wire temp_cmp_one_inc_min_102_reg_i_1_n_3;
  wire temp_cmp_one_inc_min_102_reg_i_2_n_0;
  wire temp_cmp_one_inc_min_102_reg_i_2_n_1;
  wire temp_cmp_one_inc_min_102_reg_i_2_n_2;
  wire temp_cmp_one_inc_min_102_reg_i_2_n_3;
  wire temp_cmp_three_dec_max_101;
  wire temp_cmp_three_dec_max_102;
  wire temp_cmp_three_dec_max_102_i_10_n_0;
  wire temp_cmp_three_dec_max_102_i_11_n_0;
  wire temp_cmp_three_dec_max_102_i_12_n_0;
  wire temp_cmp_three_dec_max_102_i_13_n_0;
  wire temp_cmp_three_dec_max_102_i_14_n_0;
  wire temp_cmp_three_dec_max_102_i_3_n_0;
  wire temp_cmp_three_dec_max_102_i_4_n_0;
  wire temp_cmp_three_dec_max_102_i_5_n_0;
  wire temp_cmp_three_dec_max_102_i_6_n_0;
  wire temp_cmp_three_dec_max_102_i_7_n_0;
  wire temp_cmp_three_dec_max_102_i_8_n_0;
  wire temp_cmp_three_dec_max_102_i_9_n_0;
  wire temp_cmp_three_dec_max_102_reg_i_1_n_3;
  wire temp_cmp_three_dec_max_102_reg_i_2_n_0;
  wire temp_cmp_three_dec_max_102_reg_i_2_n_1;
  wire temp_cmp_three_dec_max_102_reg_i_2_n_2;
  wire temp_cmp_three_dec_max_102_reg_i_2_n_3;
  wire temp_cmp_three_dec_min_101;
  wire temp_cmp_three_dec_min_102;
  wire temp_cmp_three_dec_min_102_i_10_n_0;
  wire temp_cmp_three_dec_min_102_i_11_n_0;
  wire temp_cmp_three_dec_min_102_i_12_n_0;
  wire temp_cmp_three_dec_min_102_i_13_n_0;
  wire temp_cmp_three_dec_min_102_i_14_n_0;
  wire temp_cmp_three_dec_min_102_i_3_n_0;
  wire temp_cmp_three_dec_min_102_i_4_n_0;
  wire temp_cmp_three_dec_min_102_i_5_n_0;
  wire temp_cmp_three_dec_min_102_i_6_n_0;
  wire temp_cmp_three_dec_min_102_i_7_n_0;
  wire temp_cmp_three_dec_min_102_i_8_n_0;
  wire temp_cmp_three_dec_min_102_i_9_n_0;
  wire temp_cmp_three_dec_min_102_reg_i_1_n_3;
  wire temp_cmp_three_dec_min_102_reg_i_2_n_0;
  wire temp_cmp_three_dec_min_102_reg_i_2_n_1;
  wire temp_cmp_three_dec_min_102_reg_i_2_n_2;
  wire temp_cmp_three_dec_min_102_reg_i_2_n_3;
  wire temp_cmp_three_inc_max_101;
  wire temp_cmp_three_inc_max_102;
  wire temp_cmp_three_inc_max_102_i_10_n_0;
  wire temp_cmp_three_inc_max_102_i_11_n_0;
  wire temp_cmp_three_inc_max_102_i_12_n_0;
  wire temp_cmp_three_inc_max_102_i_13_n_0;
  wire temp_cmp_three_inc_max_102_i_14_n_0;
  wire temp_cmp_three_inc_max_102_i_3_n_0;
  wire temp_cmp_three_inc_max_102_i_4_n_0;
  wire temp_cmp_three_inc_max_102_i_5_n_0;
  wire temp_cmp_three_inc_max_102_i_6_n_0;
  wire temp_cmp_three_inc_max_102_i_7_n_0;
  wire temp_cmp_three_inc_max_102_i_8_n_0;
  wire temp_cmp_three_inc_max_102_i_9_n_0;
  wire temp_cmp_three_inc_max_102_reg_i_1_n_3;
  wire temp_cmp_three_inc_max_102_reg_i_2_n_0;
  wire temp_cmp_three_inc_max_102_reg_i_2_n_1;
  wire temp_cmp_three_inc_max_102_reg_i_2_n_2;
  wire temp_cmp_three_inc_max_102_reg_i_2_n_3;
  wire temp_cmp_three_inc_min_101;
  wire temp_cmp_three_inc_min_102;
  wire temp_cmp_three_inc_min_102_i_10_n_0;
  wire temp_cmp_three_inc_min_102_i_11_n_0;
  wire temp_cmp_three_inc_min_102_i_12_n_0;
  wire temp_cmp_three_inc_min_102_i_13_n_0;
  wire temp_cmp_three_inc_min_102_i_14_n_0;
  wire temp_cmp_three_inc_min_102_i_3_n_0;
  wire temp_cmp_three_inc_min_102_i_4_n_0;
  wire temp_cmp_three_inc_min_102_i_5_n_0;
  wire temp_cmp_three_inc_min_102_i_6_n_0;
  wire temp_cmp_three_inc_min_102_i_7_n_0;
  wire temp_cmp_three_inc_min_102_i_8_n_0;
  wire temp_cmp_three_inc_min_102_i_9_n_0;
  wire temp_cmp_three_inc_min_102_reg_i_1_n_3;
  wire temp_cmp_three_inc_min_102_reg_i_2_n_0;
  wire temp_cmp_three_inc_min_102_reg_i_2_n_1;
  wire temp_cmp_three_inc_min_102_reg_i_2_n_2;
  wire temp_cmp_three_inc_min_102_reg_i_2_n_3;
  wire temp_cmp_two_dec_max_101;
  wire temp_cmp_two_dec_max_102;
  wire temp_cmp_two_dec_max_102_i_10_n_0;
  wire temp_cmp_two_dec_max_102_i_11_n_0;
  wire temp_cmp_two_dec_max_102_i_12_n_0;
  wire temp_cmp_two_dec_max_102_i_13_n_0;
  wire temp_cmp_two_dec_max_102_i_14_n_0;
  wire temp_cmp_two_dec_max_102_i_3_n_0;
  wire temp_cmp_two_dec_max_102_i_4_n_0;
  wire temp_cmp_two_dec_max_102_i_5_n_0;
  wire temp_cmp_two_dec_max_102_i_6_n_0;
  wire temp_cmp_two_dec_max_102_i_7_n_0;
  wire temp_cmp_two_dec_max_102_i_8_n_0;
  wire temp_cmp_two_dec_max_102_i_9_n_0;
  wire temp_cmp_two_dec_max_102_reg_i_1_n_3;
  wire temp_cmp_two_dec_max_102_reg_i_2_n_0;
  wire temp_cmp_two_dec_max_102_reg_i_2_n_1;
  wire temp_cmp_two_dec_max_102_reg_i_2_n_2;
  wire temp_cmp_two_dec_max_102_reg_i_2_n_3;
  wire temp_cmp_two_dec_min_101;
  wire temp_cmp_two_dec_min_102;
  wire temp_cmp_two_dec_min_102_i_10_n_0;
  wire temp_cmp_two_dec_min_102_i_11_n_0;
  wire temp_cmp_two_dec_min_102_i_12_n_0;
  wire temp_cmp_two_dec_min_102_i_13_n_0;
  wire temp_cmp_two_dec_min_102_i_14_n_0;
  wire temp_cmp_two_dec_min_102_i_3_n_0;
  wire temp_cmp_two_dec_min_102_i_4_n_0;
  wire temp_cmp_two_dec_min_102_i_5_n_0;
  wire temp_cmp_two_dec_min_102_i_6_n_0;
  wire temp_cmp_two_dec_min_102_i_7_n_0;
  wire temp_cmp_two_dec_min_102_i_8_n_0;
  wire temp_cmp_two_dec_min_102_i_9_n_0;
  wire temp_cmp_two_dec_min_102_reg_i_1_n_3;
  wire temp_cmp_two_dec_min_102_reg_i_2_n_0;
  wire temp_cmp_two_dec_min_102_reg_i_2_n_1;
  wire temp_cmp_two_dec_min_102_reg_i_2_n_2;
  wire temp_cmp_two_dec_min_102_reg_i_2_n_3;
  wire temp_cmp_two_inc_max_101;
  wire temp_cmp_two_inc_max_102;
  wire temp_cmp_two_inc_max_102_i_10_n_0;
  wire temp_cmp_two_inc_max_102_i_11_n_0;
  wire temp_cmp_two_inc_max_102_i_12_n_0;
  wire temp_cmp_two_inc_max_102_i_13_n_0;
  wire temp_cmp_two_inc_max_102_i_14_n_0;
  wire temp_cmp_two_inc_max_102_i_3_n_0;
  wire temp_cmp_two_inc_max_102_i_4_n_0;
  wire temp_cmp_two_inc_max_102_i_5_n_0;
  wire temp_cmp_two_inc_max_102_i_6_n_0;
  wire temp_cmp_two_inc_max_102_i_7_n_0;
  wire temp_cmp_two_inc_max_102_i_8_n_0;
  wire temp_cmp_two_inc_max_102_i_9_n_0;
  wire temp_cmp_two_inc_max_102_reg_i_1_n_3;
  wire temp_cmp_two_inc_max_102_reg_i_2_n_0;
  wire temp_cmp_two_inc_max_102_reg_i_2_n_1;
  wire temp_cmp_two_inc_max_102_reg_i_2_n_2;
  wire temp_cmp_two_inc_max_102_reg_i_2_n_3;
  wire temp_cmp_two_inc_min_101;
  wire temp_cmp_two_inc_min_102;
  wire temp_cmp_two_inc_min_102_i_10_n_0;
  wire temp_cmp_two_inc_min_102_i_11_n_0;
  wire temp_cmp_two_inc_min_102_i_12_n_0;
  wire temp_cmp_two_inc_min_102_i_13_n_0;
  wire temp_cmp_two_inc_min_102_i_14_n_0;
  wire temp_cmp_two_inc_min_102_i_3_n_0;
  wire temp_cmp_two_inc_min_102_i_4_n_0;
  wire temp_cmp_two_inc_min_102_i_5_n_0;
  wire temp_cmp_two_inc_min_102_i_6_n_0;
  wire temp_cmp_two_inc_min_102_i_7_n_0;
  wire temp_cmp_two_inc_min_102_i_8_n_0;
  wire temp_cmp_two_inc_min_102_i_9_n_0;
  wire temp_cmp_two_inc_min_102_reg_i_1_n_3;
  wire temp_cmp_two_inc_min_102_reg_i_2_n_0;
  wire temp_cmp_two_inc_min_102_reg_i_2_n_1;
  wire temp_cmp_two_inc_min_102_reg_i_2_n_2;
  wire temp_cmp_two_inc_min_102_reg_i_2_n_3;
  wire tempmon_init_complete;
  wire tempmon_sample_en_101;
  wire tempmon_sample_en_102;
  wire [10:0]tempmon_state;
  wire \tempmon_state[10]_i_10_n_0 ;
  wire \tempmon_state[10]_i_11_n_0 ;
  wire \tempmon_state[10]_i_12_n_0 ;
  wire \tempmon_state[10]_i_13_n_0 ;
  wire \tempmon_state[10]_i_14_n_0 ;
  wire \tempmon_state[10]_i_15_n_0 ;
  wire \tempmon_state[10]_i_1_n_0 ;
  wire \tempmon_state[10]_i_3_n_0 ;
  wire \tempmon_state[10]_i_4_n_0 ;
  wire \tempmon_state[10]_i_5_n_0 ;
  wire \tempmon_state[10]_i_6_n_0 ;
  wire \tempmon_state[10]_i_7_n_0 ;
  wire \tempmon_state[10]_i_8_n_0 ;
  wire \tempmon_state[10]_i_9_n_0 ;
  wire \tempmon_state[6]_i_2_n_0 ;
  wire tempmon_state_init;
  wire [10:0]tempmon_state_nxt;
  wire [11:0]three_dec_max_limit;
  wire \three_dec_max_limit[0]_i_1_n_0 ;
  wire \three_dec_max_limit[10]_i_1_n_0 ;
  wire \three_dec_max_limit[11]_i_1_n_0 ;
  wire \three_dec_max_limit[11]_i_3_n_0 ;
  wire \three_dec_max_limit[1]_i_1_n_0 ;
  wire \three_dec_max_limit[2]_i_1_n_0 ;
  wire \three_dec_max_limit[3]_i_1_n_0 ;
  wire \three_dec_max_limit[4]_i_1_n_0 ;
  wire \three_dec_max_limit[5]_i_1_n_0 ;
  wire \three_dec_max_limit[6]_i_1_n_0 ;
  wire \three_dec_max_limit[7]_i_1_n_0 ;
  wire \three_dec_max_limit[8]_i_1_n_0 ;
  wire \three_dec_max_limit[8]_i_3_n_0 ;
  wire \three_dec_max_limit[8]_i_4_n_0 ;
  wire \three_dec_max_limit[9]_i_1_n_0 ;
  wire [3:0]\three_dec_max_limit_reg[0]_0 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_2 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_3 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_5 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_6 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_7 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_0 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_1 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_2 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_3 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_4 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_5 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_6 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_0 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_1 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_2 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_3 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_4 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_5 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_6 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_7 ;
  wire [11:0]three_dec_min_limit;
  wire \three_dec_min_limit[11]_i_2_n_0 ;
  wire \three_dec_min_limit[11]_i_3_n_0 ;
  wire \three_dec_min_limit[5]_i_2_n_0 ;
  wire \three_dec_min_limit[5]_i_3_n_0 ;
  wire \three_dec_min_limit[5]_i_4_n_0 ;
  wire \three_dec_min_limit[9]_i_2_n_0 ;
  wire \three_dec_min_limit[9]_i_3_n_0 ;
  wire \three_dec_min_limit[9]_i_4_n_0 ;
  wire \three_dec_min_limit[9]_i_5_n_0 ;
  wire [11:2]three_dec_min_limit_nxt;
  wire \three_dec_min_limit_reg[11]_i_1_n_3 ;
  wire \three_dec_min_limit_reg[5]_i_1_n_0 ;
  wire \three_dec_min_limit_reg[5]_i_1_n_1 ;
  wire \three_dec_min_limit_reg[5]_i_1_n_2 ;
  wire \three_dec_min_limit_reg[5]_i_1_n_3 ;
  wire \three_dec_min_limit_reg[9]_i_1_n_0 ;
  wire \three_dec_min_limit_reg[9]_i_1_n_1 ;
  wire \three_dec_min_limit_reg[9]_i_1_n_2 ;
  wire \three_dec_min_limit_reg[9]_i_1_n_3 ;
  wire [11:2]three_inc_max_limit;
  wire \three_inc_max_limit[11]_i_2_n_0 ;
  wire \three_inc_max_limit[11]_i_3_n_0 ;
  wire \three_inc_max_limit[4]_i_2_n_0 ;
  wire \three_inc_max_limit[4]_i_3_n_0 ;
  wire \three_inc_max_limit[8]_i_2_n_0 ;
  wire \three_inc_max_limit[8]_i_3_n_0 ;
  wire \three_inc_max_limit[8]_i_4_n_0 ;
  wire [11:2]three_inc_max_limit_nxt;
  wire \three_inc_max_limit_reg[11]_i_1_n_2 ;
  wire \three_inc_max_limit_reg[11]_i_1_n_3 ;
  wire \three_inc_max_limit_reg[4]_i_1_n_0 ;
  wire \three_inc_max_limit_reg[4]_i_1_n_1 ;
  wire \three_inc_max_limit_reg[4]_i_1_n_2 ;
  wire \three_inc_max_limit_reg[4]_i_1_n_3 ;
  wire \three_inc_max_limit_reg[4]_i_1_n_7 ;
  wire \three_inc_max_limit_reg[8]_i_1_n_0 ;
  wire \three_inc_max_limit_reg[8]_i_1_n_1 ;
  wire \three_inc_max_limit_reg[8]_i_1_n_2 ;
  wire \three_inc_max_limit_reg[8]_i_1_n_3 ;
  wire [11:1]three_inc_min_limit;
  wire \three_inc_min_limit[11]_i_2_n_0 ;
  wire \three_inc_min_limit[11]_i_3_n_0 ;
  wire \three_inc_min_limit[5]_i_2_n_0 ;
  wire \three_inc_min_limit[5]_i_3_n_0 ;
  wire \three_inc_min_limit[5]_i_4_n_0 ;
  wire \three_inc_min_limit[9]_i_2_n_0 ;
  wire \three_inc_min_limit[9]_i_3_n_0 ;
  wire \three_inc_min_limit[9]_i_4_n_0 ;
  wire \three_inc_min_limit[9]_i_5_n_0 ;
  wire [11:2]three_inc_min_limit_nxt;
  wire \three_inc_min_limit_reg[11]_i_1_n_3 ;
  wire \three_inc_min_limit_reg[5]_i_1_n_0 ;
  wire \three_inc_min_limit_reg[5]_i_1_n_1 ;
  wire \three_inc_min_limit_reg[5]_i_1_n_2 ;
  wire \three_inc_min_limit_reg[5]_i_1_n_3 ;
  wire \three_inc_min_limit_reg[9]_i_1_n_0 ;
  wire \three_inc_min_limit_reg[9]_i_1_n_1 ;
  wire \three_inc_min_limit_reg[9]_i_1_n_2 ;
  wire \three_inc_min_limit_reg[9]_i_1_n_3 ;
  wire [11:0]two_dec_max_limit;
  wire \two_dec_max_limit[0]_i_1_n_0 ;
  wire \two_dec_max_limit[11]_i_2_n_0 ;
  wire \two_dec_max_limit[4]_i_2_n_0 ;
  wire \two_dec_max_limit[4]_i_3_n_0 ;
  wire \two_dec_max_limit[8]_i_2_n_0 ;
  wire [11:1]two_dec_max_limit_nxt;
  wire \two_dec_max_limit_reg[11]_i_1_n_2 ;
  wire \two_dec_max_limit_reg[11]_i_1_n_3 ;
  wire \two_dec_max_limit_reg[4]_i_1_n_0 ;
  wire \two_dec_max_limit_reg[4]_i_1_n_1 ;
  wire \two_dec_max_limit_reg[4]_i_1_n_2 ;
  wire \two_dec_max_limit_reg[4]_i_1_n_3 ;
  wire \two_dec_max_limit_reg[8]_i_1_n_0 ;
  wire \two_dec_max_limit_reg[8]_i_1_n_1 ;
  wire \two_dec_max_limit_reg[8]_i_1_n_2 ;
  wire \two_dec_max_limit_reg[8]_i_1_n_3 ;
  wire [11:2]two_dec_min_limit;
  wire \two_dec_min_limit[11]_i_2_n_0 ;
  wire \two_dec_min_limit[11]_i_3_n_0 ;
  wire \two_dec_min_limit[5]_i_2_n_0 ;
  wire \two_dec_min_limit[5]_i_3_n_0 ;
  wire \two_dec_min_limit[5]_i_4_n_0 ;
  wire \two_dec_min_limit[9]_i_2_n_0 ;
  wire \two_dec_min_limit[9]_i_3_n_0 ;
  wire \two_dec_min_limit[9]_i_4_n_0 ;
  wire \two_dec_min_limit[9]_i_5_n_0 ;
  wire [11:2]two_dec_min_limit_nxt;
  wire \two_dec_min_limit_reg[11]_i_1_n_3 ;
  wire \two_dec_min_limit_reg[5]_i_1_n_0 ;
  wire \two_dec_min_limit_reg[5]_i_1_n_1 ;
  wire \two_dec_min_limit_reg[5]_i_1_n_2 ;
  wire \two_dec_min_limit_reg[5]_i_1_n_3 ;
  wire \two_dec_min_limit_reg[9]_i_1_n_0 ;
  wire \two_dec_min_limit_reg[9]_i_1_n_1 ;
  wire \two_dec_min_limit_reg[9]_i_1_n_2 ;
  wire \two_dec_min_limit_reg[9]_i_1_n_3 ;
  wire [11:2]two_inc_max_limit;
  wire \two_inc_max_limit[11]_i_2_n_0 ;
  wire \two_inc_max_limit[11]_i_3_n_0 ;
  wire \two_inc_max_limit[11]_i_4_n_0 ;
  wire \two_inc_max_limit[4]_i_2_n_0 ;
  wire \two_inc_max_limit[4]_i_3_n_0 ;
  wire \two_inc_max_limit[4]_i_4_n_0 ;
  wire \two_inc_max_limit[8]_i_2_n_0 ;
  wire [11:2]two_inc_max_limit_nxt;
  wire \two_inc_max_limit_reg[11]_i_1_n_2 ;
  wire \two_inc_max_limit_reg[11]_i_1_n_3 ;
  wire \two_inc_max_limit_reg[4]_i_1_n_0 ;
  wire \two_inc_max_limit_reg[4]_i_1_n_1 ;
  wire \two_inc_max_limit_reg[4]_i_1_n_2 ;
  wire \two_inc_max_limit_reg[4]_i_1_n_3 ;
  wire \two_inc_max_limit_reg[8]_i_1_n_0 ;
  wire \two_inc_max_limit_reg[8]_i_1_n_1 ;
  wire \two_inc_max_limit_reg[8]_i_1_n_2 ;
  wire \two_inc_max_limit_reg[8]_i_1_n_3 ;
  wire [11:1]two_inc_min_limit;
  wire \two_inc_min_limit[11]_i_2_n_0 ;
  wire \two_inc_min_limit[11]_i_3_n_0 ;
  wire \two_inc_min_limit[5]_i_2_n_0 ;
  wire \two_inc_min_limit[5]_i_3_n_0 ;
  wire \two_inc_min_limit[5]_i_4_n_0 ;
  wire \two_inc_min_limit[9]_i_2_n_0 ;
  wire \two_inc_min_limit[9]_i_3_n_0 ;
  wire \two_inc_min_limit[9]_i_4_n_0 ;
  wire \two_inc_min_limit[9]_i_5_n_0 ;
  wire [11:2]two_inc_min_limit_nxt;
  wire \two_inc_min_limit_reg[11]_i_1_n_3 ;
  wire \two_inc_min_limit_reg[5]_i_1_n_0 ;
  wire \two_inc_min_limit_reg[5]_i_1_n_1 ;
  wire \two_inc_min_limit_reg[5]_i_1_n_2 ;
  wire \two_inc_min_limit_reg[5]_i_1_n_3 ;
  wire \two_inc_min_limit_reg[9]_i_1_n_0 ;
  wire \two_inc_min_limit_reg[9]_i_1_n_1 ;
  wire \two_inc_min_limit_reg[9]_i_1_n_2 ;
  wire \two_inc_min_limit_reg[9]_i_1_n_3 ;
  wire update_temp_101__0;
  wire update_temp_102;
  wire wrcal_done_reg;
  wire [3:1]\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [0:0]\NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [0:0]\NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [0:0]\NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED;
  wire [2:2]\NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED ;
  wire [3:3]\NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED ;
  wire [0:0]\NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED ;
  wire [3:1]\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [0:0]\NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [0:0]\NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT4 #(
    .INIT(16'hABAA)) 
    \calib_sel[1]_i_2 
       (.I0(\calib_sel_reg[0] ),
        .I1(pi_f_inc_reg_0),
        .I2(pi_f_dec_reg_0),
        .I3(calib_complete),
        .O(calib_sel0));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \calib_zero_inputs[0]_i_1 
       (.I0(calib_complete),
        .I1(pi_f_dec_reg_0),
        .I2(pi_f_inc_reg_0),
        .O(init_calib_complete_reg));
  FDRE \device_temp_101_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [0]),
        .Q(device_temp_101[0]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_101_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [10]),
        .Q(device_temp_101[10]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_101_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [11]),
        .Q(device_temp_101[11]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_101_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [1]),
        .Q(device_temp_101[1]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_101_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [2]),
        .Q(device_temp_101[2]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_101_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [3]),
        .Q(device_temp_101[3]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_101_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [4]),
        .Q(device_temp_101[4]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_101_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [5]),
        .Q(device_temp_101[5]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_101_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [6]),
        .Q(device_temp_101[6]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_101_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [7]),
        .Q(device_temp_101[7]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_101_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [8]),
        .Q(device_temp_101[8]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_101_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [9]),
        .Q(device_temp_101[9]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  LUT5 #(
    .INIT(32'h00000001)) 
    \device_temp_init[11]_i_1 
       (.I0(tempmon_state[9]),
        .I1(tempmon_state[7]),
        .I2(tempmon_state[8]),
        .I3(\device_temp_init[11]_i_2_n_0 ),
        .I4(\device_temp_init[11]_i_3_n_0 ),
        .O(tempmon_state_init));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \device_temp_init[11]_i_2 
       (.I0(tempmon_state[1]),
        .I1(tempmon_state[2]),
        .I2(tempmon_state[3]),
        .I3(tempmon_state[10]),
        .O(\device_temp_init[11]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \device_temp_init[11]_i_3 
       (.I0(tempmon_state[0]),
        .I1(tempmon_state[4]),
        .I2(tempmon_state[5]),
        .I3(tempmon_state[6]),
        .O(\device_temp_init[11]_i_3_n_0 ));
  FDRE \device_temp_init_reg[0] 
       (.C(CLK),
        .CE(tempmon_state_init),
        .D(device_temp_101[0]),
        .Q(device_temp_init[0]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_init_reg[10] 
       (.C(CLK),
        .CE(tempmon_state_init),
        .D(device_temp_101[10]),
        .Q(device_temp_init[10]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_init_reg[11] 
       (.C(CLK),
        .CE(tempmon_state_init),
        .D(device_temp_101[11]),
        .Q(device_temp_init[11]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_init_reg[1] 
       (.C(CLK),
        .CE(tempmon_state_init),
        .D(device_temp_101[1]),
        .Q(device_temp_init[1]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_init_reg[2] 
       (.C(CLK),
        .CE(tempmon_state_init),
        .D(device_temp_101[2]),
        .Q(device_temp_init[2]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_init_reg[3] 
       (.C(CLK),
        .CE(tempmon_state_init),
        .D(device_temp_101[3]),
        .Q(device_temp_init[3]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_init_reg[4] 
       (.C(CLK),
        .CE(tempmon_state_init),
        .D(device_temp_101[4]),
        .Q(device_temp_init[4]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_init_reg[5] 
       (.C(CLK),
        .CE(tempmon_state_init),
        .D(device_temp_101[5]),
        .Q(device_temp_init[5]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_init_reg[6] 
       (.C(CLK),
        .CE(tempmon_state_init),
        .D(device_temp_101[6]),
        .Q(device_temp_init[6]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_init_reg[7] 
       (.C(CLK),
        .CE(tempmon_state_init),
        .D(device_temp_101[7]),
        .Q(device_temp_init[7]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_init_reg[8] 
       (.C(CLK),
        .CE(tempmon_state_init),
        .D(device_temp_101[8]),
        .Q(device_temp_init[8]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \device_temp_init_reg[9] 
       (.C(CLK),
        .CE(tempmon_state_init),
        .D(device_temp_101[9]),
        .Q(device_temp_init[9]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[11]_i_2 
       (.I0(three_dec_max_limit[11]),
        .O(\four_dec_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[11]_i_3 
       (.I0(three_dec_max_limit[10]),
        .O(\four_dec_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[5]_i_2 
       (.I0(three_dec_max_limit[5]),
        .O(\four_dec_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[5]_i_3 
       (.I0(three_dec_max_limit[4]),
        .O(\four_dec_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[5]_i_4 
       (.I0(three_dec_max_limit[3]),
        .O(\four_dec_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[9]_i_2 
       (.I0(three_dec_max_limit[9]),
        .O(\four_dec_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[9]_i_3 
       (.I0(three_dec_max_limit[8]),
        .O(\four_dec_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[9]_i_4 
       (.I0(three_dec_max_limit[7]),
        .O(\four_dec_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[9]_i_5 
       (.I0(three_dec_max_limit[6]),
        .O(\four_dec_min_limit[9]_i_5_n_0 ));
  FDRE \four_dec_min_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_max_limit[0]),
        .Q(four_dec_min_limit[0]),
        .R(pi_f_dec_reg_1));
  FDRE \four_dec_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[10]),
        .Q(four_dec_min_limit[10]),
        .R(pi_f_dec_reg_1));
  FDRE \four_dec_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[11]),
        .Q(four_dec_min_limit[11]),
        .R(pi_f_dec_reg_1));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \four_dec_min_limit_reg[11]_i_1 
       (.CI(\four_dec_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\four_dec_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,three_dec_max_limit[10]}),
        .O({\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],four_dec_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\four_dec_min_limit[11]_i_2_n_0 ,\four_dec_min_limit[11]_i_3_n_0 }));
  FDRE \four_dec_min_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_max_limit[1]),
        .Q(four_dec_min_limit[1]),
        .R(pi_f_dec_reg_1));
  FDRE \four_dec_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[2]),
        .Q(four_dec_min_limit[2]),
        .R(pi_f_dec_reg_1));
  FDRE \four_dec_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[3]),
        .Q(four_dec_min_limit[3]),
        .R(pi_f_dec_reg_1));
  FDRE \four_dec_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[4]),
        .Q(four_dec_min_limit[4]),
        .R(pi_f_dec_reg_1));
  FDRE \four_dec_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[5]),
        .Q(four_dec_min_limit[5]),
        .R(pi_f_dec_reg_1));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \four_dec_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\four_dec_min_limit_reg[5]_i_1_n_0 ,\four_dec_min_limit_reg[5]_i_1_n_1 ,\four_dec_min_limit_reg[5]_i_1_n_2 ,\four_dec_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({three_dec_max_limit[5:3],1'b0}),
        .O(four_dec_min_limit_nxt[5:2]),
        .S({\four_dec_min_limit[5]_i_2_n_0 ,\four_dec_min_limit[5]_i_3_n_0 ,\four_dec_min_limit[5]_i_4_n_0 ,three_dec_max_limit[2]}));
  FDRE \four_dec_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[6]),
        .Q(four_dec_min_limit[6]),
        .R(pi_f_dec_reg_1));
  FDRE \four_dec_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[7]),
        .Q(four_dec_min_limit[7]),
        .R(pi_f_dec_reg_1));
  FDRE \four_dec_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[8]),
        .Q(four_dec_min_limit[8]),
        .R(pi_f_dec_reg_1));
  FDRE \four_dec_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[9]),
        .Q(four_dec_min_limit[9]),
        .R(pi_f_dec_reg_1));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \four_dec_min_limit_reg[9]_i_1 
       (.CI(\four_dec_min_limit_reg[5]_i_1_n_0 ),
        .CO({\four_dec_min_limit_reg[9]_i_1_n_0 ,\four_dec_min_limit_reg[9]_i_1_n_1 ,\four_dec_min_limit_reg[9]_i_1_n_2 ,\four_dec_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(three_dec_max_limit[9:6]),
        .O(four_dec_min_limit_nxt[9:6]),
        .S({\four_dec_min_limit[9]_i_2_n_0 ,\four_dec_min_limit[9]_i_3_n_0 ,\four_dec_min_limit[9]_i_4_n_0 ,\four_dec_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\four_inc_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\four_inc_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[4]_i_2 
       (.I0(device_temp_init[4]),
        .O(\four_inc_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[4]_i_3 
       (.I0(device_temp_init[3]),
        .O(\four_inc_max_limit[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[4]_i_4 
       (.I0(device_temp_init[2]),
        .O(\four_inc_max_limit[4]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[4]_i_5 
       (.I0(device_temp_init[1]),
        .O(\four_inc_max_limit[4]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[8]_i_2 
       (.I0(device_temp_init[7]),
        .O(\four_inc_max_limit[8]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[8]_i_3 
       (.I0(device_temp_init[5]),
        .O(\four_inc_max_limit[8]_i_3_n_0 ));
  FDRE \four_inc_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[10]),
        .Q(four_inc_max_limit[10]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \four_inc_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[11]),
        .Q(four_inc_max_limit[11]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \four_inc_max_limit_reg[11]_i_1 
       (.CI(\four_inc_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\four_inc_max_limit_reg[11]_i_1_n_2 ,\four_inc_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[10],1'b0}),
        .O({\NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],four_inc_max_limit_nxt[11:9]}),
        .S({1'b0,\four_inc_max_limit[11]_i_2_n_0 ,\four_inc_max_limit[11]_i_3_n_0 ,device_temp_init[9]}));
  FDRE \four_inc_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[2]),
        .Q(four_inc_max_limit[2]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \four_inc_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[3]),
        .Q(four_inc_max_limit[3]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \four_inc_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[4]),
        .Q(four_inc_max_limit[4]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \four_inc_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\four_inc_max_limit_reg[4]_i_1_n_0 ,\four_inc_max_limit_reg[4]_i_1_n_1 ,\four_inc_max_limit_reg[4]_i_1_n_2 ,\four_inc_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI(device_temp_init[4:1]),
        .O({four_inc_max_limit_nxt[4:2],two_dec_max_limit_nxt[1]}),
        .S({\four_inc_max_limit[4]_i_2_n_0 ,\four_inc_max_limit[4]_i_3_n_0 ,\four_inc_max_limit[4]_i_4_n_0 ,\four_inc_max_limit[4]_i_5_n_0 }));
  FDRE \four_inc_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[5]),
        .Q(four_inc_max_limit[5]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \four_inc_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[6]),
        .Q(four_inc_max_limit[6]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \four_inc_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[7]),
        .Q(four_inc_max_limit[7]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  FDRE \four_inc_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[8]),
        .Q(four_inc_max_limit[8]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \four_inc_max_limit_reg[8]_i_1 
       (.CI(\four_inc_max_limit_reg[4]_i_1_n_0 ),
        .CO({\four_inc_max_limit_reg[8]_i_1_n_0 ,\four_inc_max_limit_reg[8]_i_1_n_1 ,\four_inc_max_limit_reg[8]_i_1_n_2 ,\four_inc_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[7],1'b0,device_temp_init[5]}),
        .O(four_inc_max_limit_nxt[8:5]),
        .S({device_temp_init[8],\four_inc_max_limit[8]_i_2_n_0 ,device_temp_init[6],\four_inc_max_limit[8]_i_3_n_0 }));
  FDRE \four_inc_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[9]),
        .Q(four_inc_max_limit[9]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  LUT6 #(
    .INIT(64'hAAAAAA2AAAAAAAAA)) 
    \gen_byte_sel_div2.byte_sel_cnt[1]_i_2 
       (.I0(ck_addr_cmd_delay_done),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[1] ),
        .I2(\gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ),
        .I3(pi_f_inc_reg_0),
        .I4(pi_f_dec_reg_0),
        .I5(D),
        .O(delay_done_r4_reg));
  LUT6 #(
    .INIT(64'h88800000FFFFFFFF)) 
    \gen_byte_sel_div2.calib_in_common_i_4 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ),
        .I1(D),
        .I2(pi_f_dec_reg_0),
        .I3(pi_f_inc_reg_0),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[1] ),
        .I5(pi_dqs_found_done),
        .O(wrcal_done_reg));
  LUT5 #(
    .INIT(32'hFDFFFFFF)) 
    \gen_byte_sel_div2.calib_in_common_i_5 
       (.I0(D),
        .I1(pi_f_dec_reg_0),
        .I2(pi_f_inc_reg_0),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[1] ),
        .O(rdlvl_stg1_done_int_reg));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \neutral_max_limit[1]_i_1 
       (.I0(device_temp_init[0]),
        .I1(device_temp_init[1]),
        .O(\neutral_max_limit[1]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[4]_i_2 
       (.I0(device_temp_init[4]),
        .O(\neutral_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[4]_i_3 
       (.I0(device_temp_init[2]),
        .O(\neutral_max_limit[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[4]_i_4 
       (.I0(device_temp_init[1]),
        .O(\neutral_max_limit[4]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[8]_i_2 
       (.I0(device_temp_init[6]),
        .O(\neutral_max_limit[8]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[8]_i_3 
       (.I0(device_temp_init[5]),
        .O(\neutral_max_limit[8]_i_3_n_0 ));
  FDRE \neutral_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[10]),
        .Q(neutral_max_limit[10]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \neutral_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[11]),
        .Q(neutral_max_limit[11]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \neutral_max_limit_reg[11]_i_1 
       (.CI(\neutral_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\neutral_max_limit_reg[11]_i_1_n_2 ,\neutral_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED [3],neutral_max_limit_nxt[11:9]}),
        .S({1'b0,device_temp_init[11:9]}));
  FDRE \neutral_max_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\neutral_max_limit[1]_i_1_n_0 ),
        .Q(neutral_max_limit[1]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \neutral_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[2]),
        .Q(neutral_max_limit[2]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \neutral_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[3]),
        .Q(neutral_max_limit[3]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \neutral_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[4]),
        .Q(neutral_max_limit[4]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \neutral_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\neutral_max_limit_reg[4]_i_1_n_0 ,\neutral_max_limit_reg[4]_i_1_n_1 ,\neutral_max_limit_reg[4]_i_1_n_2 ,\neutral_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({device_temp_init[4],1'b0,device_temp_init[2:1]}),
        .O({neutral_max_limit_nxt[4:2],\NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),
        .S({\neutral_max_limit[4]_i_2_n_0 ,device_temp_init[3],\neutral_max_limit[4]_i_3_n_0 ,\neutral_max_limit[4]_i_4_n_0 }));
  FDRE \neutral_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[5]),
        .Q(neutral_max_limit[5]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \neutral_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[6]),
        .Q(neutral_max_limit[6]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \neutral_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[7]),
        .Q(neutral_max_limit[7]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \neutral_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[8]),
        .Q(neutral_max_limit[8]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \neutral_max_limit_reg[8]_i_1 
       (.CI(\neutral_max_limit_reg[4]_i_1_n_0 ),
        .CO({\neutral_max_limit_reg[8]_i_1_n_0 ,\neutral_max_limit_reg[8]_i_1_n_1 ,\neutral_max_limit_reg[8]_i_1_n_2 ,\neutral_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[6:5]}),
        .O(neutral_max_limit_nxt[8:5]),
        .S({device_temp_init[8:7],\neutral_max_limit[8]_i_2_n_0 ,\neutral_max_limit[8]_i_3_n_0 }));
  FDRE \neutral_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[9]),
        .Q(neutral_max_limit[9]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[11]_i_2 
       (.I0(one_inc_max_limit[11]),
        .O(\neutral_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[11]_i_3 
       (.I0(one_inc_max_limit[10]),
        .O(\neutral_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[5]_i_2 
       (.I0(one_inc_max_limit[5]),
        .O(\neutral_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[5]_i_3 
       (.I0(one_inc_max_limit[4]),
        .O(\neutral_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[5]_i_4 
       (.I0(one_inc_max_limit[3]),
        .O(\neutral_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[9]_i_2 
       (.I0(one_inc_max_limit[9]),
        .O(\neutral_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[9]_i_3 
       (.I0(one_inc_max_limit[8]),
        .O(\neutral_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[9]_i_4 
       (.I0(one_inc_max_limit[7]),
        .O(\neutral_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[9]_i_5 
       (.I0(one_inc_max_limit[6]),
        .O(\neutral_min_limit[9]_i_5_n_0 ));
  FDRE \neutral_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[10]),
        .Q(neutral_min_limit[10]),
        .R(pi_f_dec_reg_1));
  FDRE \neutral_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[11]),
        .Q(neutral_min_limit[11]),
        .R(pi_f_dec_reg_1));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \neutral_min_limit_reg[11]_i_1 
       (.CI(\neutral_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\neutral_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,one_inc_max_limit[10]}),
        .O({\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],neutral_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\neutral_min_limit[11]_i_2_n_0 ,\neutral_min_limit[11]_i_3_n_0 }));
  FDRE \neutral_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[2]),
        .Q(neutral_min_limit[2]),
        .R(pi_f_dec_reg_1));
  FDRE \neutral_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[3]),
        .Q(neutral_min_limit[3]),
        .R(pi_f_dec_reg_1));
  FDRE \neutral_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[4]),
        .Q(neutral_min_limit[4]),
        .R(pi_f_dec_reg_1));
  FDRE \neutral_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[5]),
        .Q(neutral_min_limit[5]),
        .R(pi_f_dec_reg_1));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \neutral_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\neutral_min_limit_reg[5]_i_1_n_0 ,\neutral_min_limit_reg[5]_i_1_n_1 ,\neutral_min_limit_reg[5]_i_1_n_2 ,\neutral_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({one_inc_max_limit[5:3],1'b0}),
        .O(neutral_min_limit_nxt[5:2]),
        .S({\neutral_min_limit[5]_i_2_n_0 ,\neutral_min_limit[5]_i_3_n_0 ,\neutral_min_limit[5]_i_4_n_0 ,one_inc_max_limit[2]}));
  FDRE \neutral_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[6]),
        .Q(neutral_min_limit[6]),
        .R(pi_f_dec_reg_1));
  FDRE \neutral_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[7]),
        .Q(neutral_min_limit[7]),
        .R(pi_f_dec_reg_1));
  FDRE \neutral_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[8]),
        .Q(neutral_min_limit[8]),
        .R(pi_f_dec_reg_1));
  FDRE \neutral_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[9]),
        .Q(neutral_min_limit[9]),
        .R(pi_f_dec_reg_1));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \neutral_min_limit_reg[9]_i_1 
       (.CI(\neutral_min_limit_reg[5]_i_1_n_0 ),
        .CO({\neutral_min_limit_reg[9]_i_1_n_0 ,\neutral_min_limit_reg[9]_i_1_n_1 ,\neutral_min_limit_reg[9]_i_1_n_2 ,\neutral_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(one_inc_max_limit[9:6]),
        .O(neutral_min_limit_nxt[9:6]),
        .S({\neutral_min_limit[9]_i_2_n_0 ,\neutral_min_limit[9]_i_3_n_0 ,\neutral_min_limit[9]_i_4_n_0 ,\neutral_min_limit[9]_i_5_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \one_dec_max_limit[1]_i_1 
       (.I0(device_temp_init[1]),
        .I1(device_temp_init[0]),
        .O(\one_dec_max_limit[1]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_max_limit[4]_i_2 
       (.I0(device_temp_init[2]),
        .O(\one_dec_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_max_limit[8]_i_2 
       (.I0(device_temp_init[8]),
        .O(\one_dec_max_limit[8]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_max_limit[8]_i_3 
       (.I0(device_temp_init[6]),
        .O(\one_dec_max_limit[8]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_max_limit[8]_i_4 
       (.I0(device_temp_init[5]),
        .O(\one_dec_max_limit[8]_i_4_n_0 ));
  FDRE \one_dec_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[10]),
        .Q(one_dec_max_limit[10]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \one_dec_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[11]),
        .Q(one_dec_max_limit[11]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \one_dec_max_limit_reg[11]_i_1 
       (.CI(\one_dec_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\one_dec_max_limit_reg[11]_i_1_n_2 ,\one_dec_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED [3],one_dec_max_limit_nxt[11:9]}),
        .S({1'b0,device_temp_init[11:9]}));
  FDRE \one_dec_max_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\one_dec_max_limit[1]_i_1_n_0 ),
        .Q(one_dec_max_limit[1]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \one_dec_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[2]),
        .Q(one_dec_max_limit[2]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \one_dec_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[3]),
        .Q(one_dec_max_limit[3]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \one_dec_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[4]),
        .Q(one_dec_max_limit[4]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \one_dec_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\one_dec_max_limit_reg[4]_i_1_n_0 ,\one_dec_max_limit_reg[4]_i_1_n_1 ,\one_dec_max_limit_reg[4]_i_1_n_2 ,\one_dec_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({1'b0,1'b0,device_temp_init[2],1'b0}),
        .O({one_dec_max_limit_nxt[4:2],\NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),
        .S({device_temp_init[4:3],\one_dec_max_limit[4]_i_2_n_0 ,device_temp_init[1]}));
  FDRE \one_dec_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[5]),
        .Q(one_dec_max_limit[5]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \one_dec_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[6]),
        .Q(one_dec_max_limit[6]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \one_dec_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[7]),
        .Q(one_dec_max_limit[7]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \one_dec_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[8]),
        .Q(one_dec_max_limit[8]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \one_dec_max_limit_reg[8]_i_1 
       (.CI(\one_dec_max_limit_reg[4]_i_1_n_0 ),
        .CO({\one_dec_max_limit_reg[8]_i_1_n_0 ,\one_dec_max_limit_reg[8]_i_1_n_1 ,\one_dec_max_limit_reg[8]_i_1_n_2 ,\one_dec_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[8],1'b0,device_temp_init[6:5]}),
        .O(one_dec_max_limit_nxt[8:5]),
        .S({\one_dec_max_limit[8]_i_2_n_0 ,device_temp_init[7],\one_dec_max_limit[8]_i_3_n_0 ,\one_dec_max_limit[8]_i_4_n_0 }));
  FDRE \one_dec_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[9]),
        .Q(one_dec_max_limit[9]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[11]_i_2 
       (.I0(neutral_max_limit[11]),
        .O(\one_dec_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[11]_i_3 
       (.I0(neutral_max_limit[10]),
        .O(\one_dec_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[5]_i_2 
       (.I0(neutral_max_limit[5]),
        .O(\one_dec_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[5]_i_3 
       (.I0(neutral_max_limit[4]),
        .O(\one_dec_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[5]_i_4 
       (.I0(neutral_max_limit[3]),
        .O(\one_dec_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[9]_i_2 
       (.I0(neutral_max_limit[9]),
        .O(\one_dec_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[9]_i_3 
       (.I0(neutral_max_limit[8]),
        .O(\one_dec_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[9]_i_4 
       (.I0(neutral_max_limit[7]),
        .O(\one_dec_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[9]_i_5 
       (.I0(neutral_max_limit[6]),
        .O(\one_dec_min_limit[9]_i_5_n_0 ));
  FDRE \one_dec_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[10]),
        .Q(one_dec_min_limit[10]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_dec_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[11]),
        .Q(one_dec_min_limit[11]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \one_dec_min_limit_reg[11]_i_1 
       (.CI(\one_dec_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\one_dec_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,neutral_max_limit[10]}),
        .O({\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_dec_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\one_dec_min_limit[11]_i_2_n_0 ,\one_dec_min_limit[11]_i_3_n_0 }));
  FDRE \one_dec_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[2]),
        .Q(one_dec_min_limit[2]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_dec_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[3]),
        .Q(one_dec_min_limit[3]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_dec_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[4]),
        .Q(one_dec_min_limit[4]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_dec_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[5]),
        .Q(one_dec_min_limit[5]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \one_dec_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\one_dec_min_limit_reg[5]_i_1_n_0 ,\one_dec_min_limit_reg[5]_i_1_n_1 ,\one_dec_min_limit_reg[5]_i_1_n_2 ,\one_dec_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({neutral_max_limit[5:3],1'b0}),
        .O(one_dec_min_limit_nxt[5:2]),
        .S({\one_dec_min_limit[5]_i_2_n_0 ,\one_dec_min_limit[5]_i_3_n_0 ,\one_dec_min_limit[5]_i_4_n_0 ,neutral_max_limit[2]}));
  FDRE \one_dec_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[6]),
        .Q(one_dec_min_limit[6]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_dec_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[7]),
        .Q(one_dec_min_limit[7]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_dec_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[8]),
        .Q(one_dec_min_limit[8]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_dec_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[9]),
        .Q(one_dec_min_limit[9]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \one_dec_min_limit_reg[9]_i_1 
       (.CI(\one_dec_min_limit_reg[5]_i_1_n_0 ),
        .CO({\one_dec_min_limit_reg[9]_i_1_n_0 ,\one_dec_min_limit_reg[9]_i_1_n_1 ,\one_dec_min_limit_reg[9]_i_1_n_2 ,\one_dec_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(neutral_max_limit[9:6]),
        .O(one_dec_min_limit_nxt[9:6]),
        .S({\one_dec_min_limit[9]_i_2_n_0 ,\one_dec_min_limit[9]_i_3_n_0 ,\one_dec_min_limit[9]_i_4_n_0 ,\one_dec_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\one_inc_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\one_inc_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[11]_i_4 
       (.I0(device_temp_init[9]),
        .O(\one_inc_max_limit[11]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[4]_i_2 
       (.I0(device_temp_init[3]),
        .O(\one_inc_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[8]_i_2 
       (.I0(device_temp_init[8]),
        .O(\one_inc_max_limit[8]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[8]_i_3 
       (.I0(device_temp_init[7]),
        .O(\one_inc_max_limit[8]_i_3_n_0 ));
  FDRE \one_inc_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[10]),
        .Q(one_inc_max_limit[10]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \one_inc_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[11]),
        .Q(one_inc_max_limit[11]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \one_inc_max_limit_reg[11]_i_1 
       (.CI(\one_inc_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\one_inc_max_limit_reg[11]_i_1_n_2 ,\one_inc_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[10:9]}),
        .O({\NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],one_inc_max_limit_nxt[11:9]}),
        .S({1'b0,\one_inc_max_limit[11]_i_2_n_0 ,\one_inc_max_limit[11]_i_3_n_0 ,\one_inc_max_limit[11]_i_4_n_0 }));
  FDRE \one_inc_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[2]),
        .Q(one_inc_max_limit[2]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \one_inc_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[3]),
        .Q(one_inc_max_limit[3]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \one_inc_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[4]),
        .Q(one_inc_max_limit[4]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \one_inc_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\one_inc_max_limit_reg[4]_i_1_n_0 ,\one_inc_max_limit_reg[4]_i_1_n_1 ,\one_inc_max_limit_reg[4]_i_1_n_2 ,\one_inc_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({1'b0,device_temp_init[3],1'b0,1'b0}),
        .O({one_inc_max_limit_nxt[4:2],\NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),
        .S({device_temp_init[4],\one_inc_max_limit[4]_i_2_n_0 ,device_temp_init[2:1]}));
  FDRE \one_inc_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[5]),
        .Q(one_inc_max_limit[5]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \one_inc_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[6]),
        .Q(one_inc_max_limit[6]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \one_inc_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[7]),
        .Q(one_inc_max_limit[7]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \one_inc_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[8]),
        .Q(one_inc_max_limit[8]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \one_inc_max_limit_reg[8]_i_1 
       (.CI(\one_inc_max_limit_reg[4]_i_1_n_0 ),
        .CO({\one_inc_max_limit_reg[8]_i_1_n_0 ,\one_inc_max_limit_reg[8]_i_1_n_1 ,\one_inc_max_limit_reg[8]_i_1_n_2 ,\one_inc_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[8:7],1'b0,1'b0}),
        .O(one_inc_max_limit_nxt[8:5]),
        .S({\one_inc_max_limit[8]_i_2_n_0 ,\one_inc_max_limit[8]_i_3_n_0 ,device_temp_init[6:5]}));
  FDRE \one_inc_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[9]),
        .Q(one_inc_max_limit[9]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[11]_i_2 
       (.I0(two_inc_max_limit[11]),
        .O(\one_inc_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[11]_i_3 
       (.I0(two_inc_max_limit[10]),
        .O(\one_inc_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[5]_i_2 
       (.I0(two_inc_max_limit[5]),
        .O(\one_inc_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[5]_i_3 
       (.I0(two_inc_max_limit[4]),
        .O(\one_inc_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[5]_i_4 
       (.I0(two_inc_max_limit[3]),
        .O(\one_inc_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[9]_i_2 
       (.I0(two_inc_max_limit[9]),
        .O(\one_inc_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[9]_i_3 
       (.I0(two_inc_max_limit[8]),
        .O(\one_inc_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[9]_i_4 
       (.I0(two_inc_max_limit[7]),
        .O(\one_inc_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[9]_i_5 
       (.I0(two_inc_max_limit[6]),
        .O(\one_inc_min_limit[9]_i_5_n_0 ));
  FDRE \one_inc_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[10]),
        .Q(one_inc_min_limit[10]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_inc_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[11]),
        .Q(one_inc_min_limit[11]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \one_inc_min_limit_reg[11]_i_1 
       (.CI(\one_inc_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\one_inc_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,two_inc_max_limit[10]}),
        .O({\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_inc_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\one_inc_min_limit[11]_i_2_n_0 ,\one_inc_min_limit[11]_i_3_n_0 }));
  FDRE \one_inc_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[2]),
        .Q(one_inc_min_limit[2]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_inc_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[3]),
        .Q(one_inc_min_limit[3]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_inc_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[4]),
        .Q(one_inc_min_limit[4]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_inc_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[5]),
        .Q(one_inc_min_limit[5]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \one_inc_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\one_inc_min_limit_reg[5]_i_1_n_0 ,\one_inc_min_limit_reg[5]_i_1_n_1 ,\one_inc_min_limit_reg[5]_i_1_n_2 ,\one_inc_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({two_inc_max_limit[5:3],1'b0}),
        .O(one_inc_min_limit_nxt[5:2]),
        .S({\one_inc_min_limit[5]_i_2_n_0 ,\one_inc_min_limit[5]_i_3_n_0 ,\one_inc_min_limit[5]_i_4_n_0 ,two_inc_max_limit[2]}));
  FDRE \one_inc_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[6]),
        .Q(one_inc_min_limit[6]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_inc_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[7]),
        .Q(one_inc_min_limit[7]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_inc_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[8]),
        .Q(one_inc_min_limit[8]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \one_inc_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[9]),
        .Q(one_inc_min_limit[9]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \one_inc_min_limit_reg[9]_i_1 
       (.CI(\one_inc_min_limit_reg[5]_i_1_n_0 ),
        .CO({\one_inc_min_limit_reg[9]_i_1_n_0 ,\one_inc_min_limit_reg[9]_i_1_n_1 ,\one_inc_min_limit_reg[9]_i_1_n_2 ,\one_inc_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(two_inc_max_limit[9:6]),
        .O(one_inc_min_limit_nxt[9:6]),
        .S({\one_inc_min_limit[9]_i_2_n_0 ,\one_inc_min_limit[9]_i_3_n_0 ,\one_inc_min_limit[9]_i_4_n_0 ,\one_inc_min_limit[9]_i_5_n_0 }));
  LUT4 #(
    .INIT(16'h8A88)) 
    pi_f_dec_i_1
       (.I0(\tempmon_state[10]_i_6_n_0 ),
        .I1(\tempmon_state[10]_i_5_n_0 ),
        .I2(pi_f_dec_i_2_n_0),
        .I3(update_temp_102),
        .O(pi_f_dec_nxt));
  LUT6 #(
    .INIT(64'h0000077707770777)) 
    pi_f_dec_i_2
       (.I0(tempmon_state[3]),
        .I1(temp_cmp_three_inc_max_102),
        .I2(temp_cmp_two_inc_max_102),
        .I3(tempmon_state[4]),
        .I4(temp_cmp_one_inc_max_102),
        .I5(tempmon_state[5]),
        .O(pi_f_dec_i_2_n_0));
  FDRE pi_f_dec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_f_dec_nxt),
        .Q(pi_f_dec_reg_0),
        .R(pi_f_dec_reg_1));
  LUT6 #(
    .INIT(64'hFFF7555500000000)) 
    pi_f_inc_i_1
       (.I0(pi_f_inc_i_2_n_0),
        .I1(pi_f_inc_i_3_n_0),
        .I2(pi_f_inc_i_4_n_0),
        .I3(pi_f_inc_i_5_n_0),
        .I4(update_temp_102),
        .I5(\tempmon_state[10]_i_6_n_0 ),
        .O(pi_f_inc_nxt));
  LUT6 #(
    .INIT(64'h00FFF7FFF7FFF7FF)) 
    pi_f_inc_i_2
       (.I0(temp_cmp_one_inc_min_102),
        .I1(tempmon_state[5]),
        .I2(temp_cmp_one_inc_max_102),
        .I3(update_temp_102),
        .I4(temp_cmp_four_dec_min_102),
        .I5(tempmon_state[10]),
        .O(pi_f_inc_i_2_n_0));
  LUT6 #(
    .INIT(64'hF7000000F777F777)) 
    pi_f_inc_i_3
       (.I0(tempmon_state[8]),
        .I1(temp_cmp_two_dec_min_102),
        .I2(temp_cmp_two_dec_max_102),
        .I3(update_temp_102),
        .I4(temp_cmp_one_dec_max_102),
        .I5(pi_f_inc_i_6_n_0),
        .O(pi_f_inc_i_3_n_0));
  LUT6 #(
    .INIT(64'h40FF404040404040)) 
    pi_f_inc_i_4
       (.I0(temp_cmp_three_inc_max_102),
        .I1(tempmon_state[3]),
        .I2(temp_cmp_three_inc_min_102),
        .I3(temp_cmp_two_inc_max_102),
        .I4(tempmon_state[4]),
        .I5(temp_cmp_two_inc_min_102),
        .O(pi_f_inc_i_4_n_0));
  LUT6 #(
    .INIT(64'h0808FF88FF08FF88)) 
    pi_f_inc_i_5
       (.I0(tempmon_state[9]),
        .I1(temp_cmp_three_dec_min_102),
        .I2(temp_cmp_three_dec_max_102),
        .I3(pi_f_inc_i_7_n_0),
        .I4(update_temp_102),
        .I5(temp_cmp_neutral_max_102),
        .O(pi_f_inc_i_5_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    pi_f_inc_i_6
       (.I0(tempmon_state[7]),
        .I1(temp_cmp_one_dec_min_102),
        .O(pi_f_inc_i_6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT2 #(
    .INIT(4'h8)) 
    pi_f_inc_i_7
       (.I0(tempmon_state[6]),
        .I1(temp_cmp_neutral_min_102),
        .O(pi_f_inc_i_7_n_0));
  FDRE pi_f_inc_reg
       (.C(CLK),
        .CE(1'b1),
        .D(pi_f_inc_nxt),
        .Q(pi_f_inc_reg_0),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_10
       (.I0(four_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(four_dec_min_limit[1]),
        .O(temp_cmp_four_dec_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_11
       (.I0(four_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(four_dec_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_four_dec_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_12
       (.I0(four_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(four_dec_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_four_dec_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_13
       (.I0(four_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(four_dec_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_four_dec_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_14
       (.I0(four_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(four_dec_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_four_dec_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_3
       (.I0(four_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(four_dec_min_limit[11]),
        .O(temp_cmp_four_dec_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_4
       (.I0(four_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(four_dec_min_limit[9]),
        .O(temp_cmp_four_dec_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_5
       (.I0(four_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(four_dec_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_four_dec_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_6
       (.I0(four_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(four_dec_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_four_dec_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_7
       (.I0(four_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(four_dec_min_limit[7]),
        .O(temp_cmp_four_dec_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_8
       (.I0(four_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(four_dec_min_limit[5]),
        .O(temp_cmp_four_dec_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_9
       (.I0(four_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(four_dec_min_limit[3]),
        .O(temp_cmp_four_dec_min_102_i_9_n_0));
  FDRE temp_cmp_four_dec_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_four_dec_min_101),
        .Q(temp_cmp_four_dec_min_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_four_dec_min_102_reg_i_1
       (.CI(temp_cmp_four_dec_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_dec_min_101,temp_cmp_four_dec_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_four_dec_min_102_i_3_n_0,temp_cmp_four_dec_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_four_dec_min_102_i_5_n_0,temp_cmp_four_dec_min_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_four_dec_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_four_dec_min_102_reg_i_2_n_0,temp_cmp_four_dec_min_102_reg_i_2_n_1,temp_cmp_four_dec_min_102_reg_i_2_n_2,temp_cmp_four_dec_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_four_dec_min_102_i_7_n_0,temp_cmp_four_dec_min_102_i_8_n_0,temp_cmp_four_dec_min_102_i_9_n_0,temp_cmp_four_dec_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_four_dec_min_102_i_11_n_0,temp_cmp_four_dec_min_102_i_12_n_0,temp_cmp_four_dec_min_102_i_13_n_0,temp_cmp_four_dec_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(neutral_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_four_inc_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(four_inc_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(four_inc_max_limit[7]),
        .O(temp_cmp_four_inc_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(four_inc_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(four_inc_max_limit[5]),
        .O(temp_cmp_four_inc_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(four_inc_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(four_inc_max_limit[3]),
        .O(temp_cmp_four_inc_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(neutral_max_limit[1]),
        .O(temp_cmp_four_inc_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(four_inc_max_limit[10]),
        .I2(four_inc_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_four_inc_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(four_inc_max_limit[8]),
        .I2(four_inc_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_four_inc_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(four_inc_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(four_inc_max_limit[11]),
        .O(temp_cmp_four_inc_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(four_inc_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(four_inc_max_limit[9]),
        .O(temp_cmp_four_inc_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(four_inc_max_limit[6]),
        .I2(four_inc_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_four_inc_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(four_inc_max_limit[4]),
        .I2(four_inc_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_four_inc_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(four_inc_max_limit[2]),
        .I2(four_inc_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_four_inc_max_102_i_9_n_0));
  FDRE temp_cmp_four_inc_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_four_inc_max_101),
        .Q(temp_cmp_four_inc_max_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_four_inc_max_102_reg_i_1
       (.CI(temp_cmp_four_inc_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_inc_max_101,temp_cmp_four_inc_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_four_inc_max_102_i_3_n_0,temp_cmp_four_inc_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_four_inc_max_102_i_5_n_0,temp_cmp_four_inc_max_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_four_inc_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_four_inc_max_102_reg_i_2_n_0,temp_cmp_four_inc_max_102_reg_i_2_n_1,temp_cmp_four_inc_max_102_reg_i_2_n_2,temp_cmp_four_inc_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_four_inc_max_102_i_7_n_0,temp_cmp_four_inc_max_102_i_8_n_0,temp_cmp_four_inc_max_102_i_9_n_0,temp_cmp_four_inc_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_four_inc_max_102_i_11_n_0,temp_cmp_four_inc_max_102_i_12_n_0,temp_cmp_four_inc_max_102_i_13_n_0,temp_cmp_four_inc_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(neutral_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_neutral_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(neutral_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(neutral_max_limit[7]),
        .O(temp_cmp_neutral_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(neutral_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(neutral_max_limit[5]),
        .O(temp_cmp_neutral_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(neutral_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(neutral_max_limit[3]),
        .O(temp_cmp_neutral_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(neutral_max_limit[1]),
        .O(temp_cmp_neutral_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(neutral_max_limit[10]),
        .I2(neutral_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_neutral_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(neutral_max_limit[8]),
        .I2(neutral_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_neutral_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(neutral_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(neutral_max_limit[11]),
        .O(temp_cmp_neutral_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(neutral_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(neutral_max_limit[9]),
        .O(temp_cmp_neutral_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(neutral_max_limit[6]),
        .I2(neutral_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_neutral_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(neutral_max_limit[4]),
        .I2(neutral_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_neutral_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(neutral_max_limit[2]),
        .I2(neutral_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_neutral_max_102_i_9_n_0));
  FDRE temp_cmp_neutral_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_neutral_max_101),
        .Q(temp_cmp_neutral_max_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_neutral_max_102_reg_i_1
       (.CI(temp_cmp_neutral_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_max_101,temp_cmp_neutral_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_neutral_max_102_i_3_n_0,temp_cmp_neutral_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_neutral_max_102_i_5_n_0,temp_cmp_neutral_max_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_neutral_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_neutral_max_102_reg_i_2_n_0,temp_cmp_neutral_max_102_reg_i_2_n_1,temp_cmp_neutral_max_102_reg_i_2_n_2,temp_cmp_neutral_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_neutral_max_102_i_7_n_0,temp_cmp_neutral_max_102_i_8_n_0,temp_cmp_neutral_max_102_i_9_n_0,temp_cmp_neutral_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_neutral_max_102_i_11_n_0,temp_cmp_neutral_max_102_i_12_n_0,temp_cmp_neutral_max_102_i_13_n_0,temp_cmp_neutral_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(two_inc_min_limit[1]),
        .O(temp_cmp_neutral_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_11
       (.I0(neutral_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(neutral_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_neutral_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_12
       (.I0(neutral_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(neutral_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_neutral_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_13
       (.I0(neutral_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(neutral_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_neutral_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(two_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_neutral_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_3
       (.I0(neutral_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(neutral_min_limit[11]),
        .O(temp_cmp_neutral_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_4
       (.I0(neutral_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(neutral_min_limit[9]),
        .O(temp_cmp_neutral_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_5
       (.I0(neutral_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(neutral_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_neutral_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_6
       (.I0(neutral_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(neutral_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_neutral_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_7
       (.I0(neutral_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(neutral_min_limit[7]),
        .O(temp_cmp_neutral_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_8
       (.I0(neutral_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(neutral_min_limit[5]),
        .O(temp_cmp_neutral_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_9
       (.I0(neutral_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(neutral_min_limit[3]),
        .O(temp_cmp_neutral_min_102_i_9_n_0));
  FDRE temp_cmp_neutral_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_neutral_min_101),
        .Q(temp_cmp_neutral_min_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_neutral_min_102_reg_i_1
       (.CI(temp_cmp_neutral_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_min_101,temp_cmp_neutral_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_neutral_min_102_i_3_n_0,temp_cmp_neutral_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_neutral_min_102_i_5_n_0,temp_cmp_neutral_min_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_neutral_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_neutral_min_102_reg_i_2_n_0,temp_cmp_neutral_min_102_reg_i_2_n_1,temp_cmp_neutral_min_102_reg_i_2_n_2,temp_cmp_neutral_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_neutral_min_102_i_7_n_0,temp_cmp_neutral_min_102_i_8_n_0,temp_cmp_neutral_min_102_i_9_n_0,temp_cmp_neutral_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_neutral_min_102_i_11_n_0,temp_cmp_neutral_min_102_i_12_n_0,temp_cmp_neutral_min_102_i_13_n_0,temp_cmp_neutral_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(one_dec_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_one_dec_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(one_dec_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(one_dec_max_limit[7]),
        .O(temp_cmp_one_dec_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(one_dec_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(one_dec_max_limit[5]),
        .O(temp_cmp_one_dec_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(one_dec_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(one_dec_max_limit[3]),
        .O(temp_cmp_one_dec_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(one_dec_max_limit[1]),
        .O(temp_cmp_one_dec_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(one_dec_max_limit[10]),
        .I2(one_dec_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_one_dec_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(one_dec_max_limit[8]),
        .I2(one_dec_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_one_dec_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(one_dec_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(one_dec_max_limit[11]),
        .O(temp_cmp_one_dec_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(one_dec_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(one_dec_max_limit[9]),
        .O(temp_cmp_one_dec_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(one_dec_max_limit[6]),
        .I2(one_dec_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_one_dec_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(one_dec_max_limit[4]),
        .I2(one_dec_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_one_dec_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(one_dec_max_limit[2]),
        .I2(one_dec_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_one_dec_max_102_i_9_n_0));
  FDRE temp_cmp_one_dec_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_one_dec_max_101),
        .Q(temp_cmp_one_dec_max_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_one_dec_max_102_reg_i_1
       (.CI(temp_cmp_one_dec_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_max_101,temp_cmp_one_dec_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_one_dec_max_102_i_3_n_0,temp_cmp_one_dec_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_one_dec_max_102_i_5_n_0,temp_cmp_one_dec_max_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_one_dec_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_one_dec_max_102_reg_i_2_n_0,temp_cmp_one_dec_max_102_reg_i_2_n_1,temp_cmp_one_dec_max_102_reg_i_2_n_2,temp_cmp_one_dec_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_one_dec_max_102_i_7_n_0,temp_cmp_one_dec_max_102_i_8_n_0,temp_cmp_one_dec_max_102_i_9_n_0,temp_cmp_one_dec_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_one_dec_max_102_i_11_n_0,temp_cmp_one_dec_max_102_i_12_n_0,temp_cmp_one_dec_max_102_i_13_n_0,temp_cmp_one_dec_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(three_inc_min_limit[1]),
        .O(temp_cmp_one_dec_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_11
       (.I0(one_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(one_dec_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_one_dec_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_12
       (.I0(one_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(one_dec_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_one_dec_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_13
       (.I0(one_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(one_dec_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_one_dec_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(three_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_one_dec_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_3
       (.I0(one_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(one_dec_min_limit[11]),
        .O(temp_cmp_one_dec_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_4
       (.I0(one_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(one_dec_min_limit[9]),
        .O(temp_cmp_one_dec_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_5
       (.I0(one_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(one_dec_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_one_dec_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_6
       (.I0(one_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(one_dec_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_one_dec_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_7
       (.I0(one_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(one_dec_min_limit[7]),
        .O(temp_cmp_one_dec_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_8
       (.I0(one_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(one_dec_min_limit[5]),
        .O(temp_cmp_one_dec_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_9
       (.I0(one_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(one_dec_min_limit[3]),
        .O(temp_cmp_one_dec_min_102_i_9_n_0));
  FDRE temp_cmp_one_dec_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_one_dec_min_101),
        .Q(temp_cmp_one_dec_min_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_one_dec_min_102_reg_i_1
       (.CI(temp_cmp_one_dec_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_min_101,temp_cmp_one_dec_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_one_dec_min_102_i_3_n_0,temp_cmp_one_dec_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_one_dec_min_102_i_5_n_0,temp_cmp_one_dec_min_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_one_dec_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_one_dec_min_102_reg_i_2_n_0,temp_cmp_one_dec_min_102_reg_i_2_n_1,temp_cmp_one_dec_min_102_reg_i_2_n_2,temp_cmp_one_dec_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_one_dec_min_102_i_7_n_0,temp_cmp_one_dec_min_102_i_8_n_0,temp_cmp_one_dec_min_102_i_9_n_0,temp_cmp_one_dec_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_one_dec_min_102_i_11_n_0,temp_cmp_one_dec_min_102_i_12_n_0,temp_cmp_one_dec_min_102_i_13_n_0,temp_cmp_one_dec_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(one_dec_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_one_inc_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(one_inc_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(one_inc_max_limit[7]),
        .O(temp_cmp_one_inc_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(one_inc_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(one_inc_max_limit[5]),
        .O(temp_cmp_one_inc_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(one_inc_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(one_inc_max_limit[3]),
        .O(temp_cmp_one_inc_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(one_dec_max_limit[1]),
        .O(temp_cmp_one_inc_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(one_inc_max_limit[10]),
        .I2(one_inc_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_one_inc_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(one_inc_max_limit[8]),
        .I2(one_inc_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_one_inc_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(one_inc_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(one_inc_max_limit[11]),
        .O(temp_cmp_one_inc_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(one_inc_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(one_inc_max_limit[9]),
        .O(temp_cmp_one_inc_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(one_inc_max_limit[6]),
        .I2(one_inc_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_one_inc_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(one_inc_max_limit[4]),
        .I2(one_inc_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_one_inc_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(one_inc_max_limit[2]),
        .I2(one_inc_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_one_inc_max_102_i_9_n_0));
  FDRE temp_cmp_one_inc_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_one_inc_max_101),
        .Q(temp_cmp_one_inc_max_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_one_inc_max_102_reg_i_1
       (.CI(temp_cmp_one_inc_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_max_101,temp_cmp_one_inc_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_one_inc_max_102_i_3_n_0,temp_cmp_one_inc_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_one_inc_max_102_i_5_n_0,temp_cmp_one_inc_max_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_one_inc_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_one_inc_max_102_reg_i_2_n_0,temp_cmp_one_inc_max_102_reg_i_2_n_1,temp_cmp_one_inc_max_102_reg_i_2_n_2,temp_cmp_one_inc_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_one_inc_max_102_i_7_n_0,temp_cmp_one_inc_max_102_i_8_n_0,temp_cmp_one_inc_max_102_i_9_n_0,temp_cmp_one_inc_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_one_inc_max_102_i_11_n_0,temp_cmp_one_inc_max_102_i_12_n_0,temp_cmp_one_inc_max_102_i_13_n_0,temp_cmp_one_inc_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(three_inc_min_limit[1]),
        .O(temp_cmp_one_inc_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_11
       (.I0(one_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(one_inc_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_one_inc_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_12
       (.I0(one_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(one_inc_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_one_inc_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_13
       (.I0(one_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(one_inc_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_one_inc_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(three_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_one_inc_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_3
       (.I0(one_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(one_inc_min_limit[11]),
        .O(temp_cmp_one_inc_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_4
       (.I0(one_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(one_inc_min_limit[9]),
        .O(temp_cmp_one_inc_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_5
       (.I0(one_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(one_inc_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_one_inc_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_6
       (.I0(one_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(one_inc_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_one_inc_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_7
       (.I0(one_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(one_inc_min_limit[7]),
        .O(temp_cmp_one_inc_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_8
       (.I0(one_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(one_inc_min_limit[5]),
        .O(temp_cmp_one_inc_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_9
       (.I0(one_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(one_inc_min_limit[3]),
        .O(temp_cmp_one_inc_min_102_i_9_n_0));
  FDRE temp_cmp_one_inc_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_one_inc_min_101),
        .Q(temp_cmp_one_inc_min_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_one_inc_min_102_reg_i_1
       (.CI(temp_cmp_one_inc_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_min_101,temp_cmp_one_inc_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_one_inc_min_102_i_3_n_0,temp_cmp_one_inc_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_one_inc_min_102_i_5_n_0,temp_cmp_one_inc_min_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_one_inc_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_one_inc_min_102_reg_i_2_n_0,temp_cmp_one_inc_min_102_reg_i_2_n_1,temp_cmp_one_inc_min_102_reg_i_2_n_2,temp_cmp_one_inc_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_one_inc_min_102_i_7_n_0,temp_cmp_one_inc_min_102_i_8_n_0,temp_cmp_one_inc_min_102_i_9_n_0,temp_cmp_one_inc_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_one_inc_min_102_i_11_n_0,temp_cmp_one_inc_min_102_i_12_n_0,temp_cmp_one_inc_min_102_i_13_n_0,temp_cmp_one_inc_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(three_dec_max_limit[0]),
        .I2(three_dec_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_three_dec_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(three_dec_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(three_dec_max_limit[7]),
        .O(temp_cmp_three_dec_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(three_dec_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(three_dec_max_limit[5]),
        .O(temp_cmp_three_dec_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(three_dec_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(three_dec_max_limit[3]),
        .O(temp_cmp_three_dec_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(three_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(three_dec_max_limit[1]),
        .O(temp_cmp_three_dec_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(three_dec_max_limit[10]),
        .I2(three_dec_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_three_dec_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(three_dec_max_limit[8]),
        .I2(three_dec_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_three_dec_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(three_dec_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(three_dec_max_limit[11]),
        .O(temp_cmp_three_dec_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(three_dec_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(three_dec_max_limit[9]),
        .O(temp_cmp_three_dec_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(three_dec_max_limit[6]),
        .I2(three_dec_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_three_dec_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(three_dec_max_limit[4]),
        .I2(three_dec_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_three_dec_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(three_dec_max_limit[2]),
        .I2(three_dec_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_three_dec_max_102_i_9_n_0));
  FDRE temp_cmp_three_dec_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_three_dec_max_101),
        .Q(temp_cmp_three_dec_max_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_three_dec_max_102_reg_i_1
       (.CI(temp_cmp_three_dec_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_max_101,temp_cmp_three_dec_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_three_dec_max_102_i_3_n_0,temp_cmp_three_dec_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_three_dec_max_102_i_5_n_0,temp_cmp_three_dec_max_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_three_dec_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_three_dec_max_102_reg_i_2_n_0,temp_cmp_three_dec_max_102_reg_i_2_n_1,temp_cmp_three_dec_max_102_reg_i_2_n_2,temp_cmp_three_dec_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_three_dec_max_102_i_7_n_0,temp_cmp_three_dec_max_102_i_8_n_0,temp_cmp_three_dec_max_102_i_9_n_0,temp_cmp_three_dec_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_three_dec_max_102_i_11_n_0,temp_cmp_three_dec_max_102_i_12_n_0,temp_cmp_three_dec_max_102_i_13_n_0,temp_cmp_three_dec_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(three_dec_min_limit[1]),
        .O(temp_cmp_three_dec_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_11
       (.I0(three_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(three_dec_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_three_dec_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_12
       (.I0(three_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(three_dec_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_three_dec_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_13
       (.I0(three_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(three_dec_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_three_dec_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(three_dec_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_three_dec_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_3
       (.I0(three_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(three_dec_min_limit[11]),
        .O(temp_cmp_three_dec_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_4
       (.I0(three_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(three_dec_min_limit[9]),
        .O(temp_cmp_three_dec_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_5
       (.I0(three_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(three_dec_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_three_dec_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_6
       (.I0(three_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(three_dec_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_three_dec_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_7
       (.I0(three_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(three_dec_min_limit[7]),
        .O(temp_cmp_three_dec_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_8
       (.I0(three_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(three_dec_min_limit[5]),
        .O(temp_cmp_three_dec_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_9
       (.I0(three_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(three_dec_min_limit[3]),
        .O(temp_cmp_three_dec_min_102_i_9_n_0));
  FDRE temp_cmp_three_dec_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_three_dec_min_101),
        .Q(temp_cmp_three_dec_min_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_three_dec_min_102_reg_i_1
       (.CI(temp_cmp_three_dec_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_min_101,temp_cmp_three_dec_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_three_dec_min_102_i_3_n_0,temp_cmp_three_dec_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_three_dec_min_102_i_5_n_0,temp_cmp_three_dec_min_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_three_dec_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_three_dec_min_102_reg_i_2_n_0,temp_cmp_three_dec_min_102_reg_i_2_n_1,temp_cmp_three_dec_min_102_reg_i_2_n_2,temp_cmp_three_dec_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_three_dec_min_102_i_7_n_0,temp_cmp_three_dec_min_102_i_8_n_0,temp_cmp_three_dec_min_102_i_9_n_0,temp_cmp_three_dec_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_three_dec_min_102_i_11_n_0,temp_cmp_three_dec_min_102_i_12_n_0,temp_cmp_three_dec_min_102_i_13_n_0,temp_cmp_three_dec_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(one_dec_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_three_inc_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(three_inc_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(three_inc_max_limit[7]),
        .O(temp_cmp_three_inc_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(three_inc_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(three_inc_max_limit[5]),
        .O(temp_cmp_three_inc_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(three_inc_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(three_inc_max_limit[3]),
        .O(temp_cmp_three_inc_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(one_dec_max_limit[1]),
        .O(temp_cmp_three_inc_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(three_inc_max_limit[10]),
        .I2(three_inc_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_three_inc_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(three_inc_max_limit[8]),
        .I2(three_inc_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_three_inc_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(three_inc_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(three_inc_max_limit[11]),
        .O(temp_cmp_three_inc_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(three_inc_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(three_inc_max_limit[9]),
        .O(temp_cmp_three_inc_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(three_inc_max_limit[6]),
        .I2(three_inc_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_three_inc_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(three_inc_max_limit[4]),
        .I2(three_inc_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_three_inc_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(three_inc_max_limit[2]),
        .I2(three_inc_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_three_inc_max_102_i_9_n_0));
  FDRE temp_cmp_three_inc_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_three_inc_max_101),
        .Q(temp_cmp_three_inc_max_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_three_inc_max_102_reg_i_1
       (.CI(temp_cmp_three_inc_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_max_101,temp_cmp_three_inc_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_three_inc_max_102_i_3_n_0,temp_cmp_three_inc_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_three_inc_max_102_i_5_n_0,temp_cmp_three_inc_max_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_three_inc_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_three_inc_max_102_reg_i_2_n_0,temp_cmp_three_inc_max_102_reg_i_2_n_1,temp_cmp_three_inc_max_102_reg_i_2_n_2,temp_cmp_three_inc_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_three_inc_max_102_i_7_n_0,temp_cmp_three_inc_max_102_i_8_n_0,temp_cmp_three_inc_max_102_i_9_n_0,temp_cmp_three_inc_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_three_inc_max_102_i_11_n_0,temp_cmp_three_inc_max_102_i_12_n_0,temp_cmp_three_inc_max_102_i_13_n_0,temp_cmp_three_inc_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(three_inc_min_limit[1]),
        .O(temp_cmp_three_inc_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_11
       (.I0(three_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(three_inc_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_three_inc_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_12
       (.I0(three_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(three_inc_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_three_inc_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_13
       (.I0(three_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(three_inc_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_three_inc_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(three_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_three_inc_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_3
       (.I0(three_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(three_inc_min_limit[11]),
        .O(temp_cmp_three_inc_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_4
       (.I0(three_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(three_inc_min_limit[9]),
        .O(temp_cmp_three_inc_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_5
       (.I0(three_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(three_inc_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_three_inc_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_6
       (.I0(three_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(three_inc_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_three_inc_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_7
       (.I0(three_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(three_inc_min_limit[7]),
        .O(temp_cmp_three_inc_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_8
       (.I0(three_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(three_inc_min_limit[5]),
        .O(temp_cmp_three_inc_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_9
       (.I0(three_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(three_inc_min_limit[3]),
        .O(temp_cmp_three_inc_min_102_i_9_n_0));
  FDRE temp_cmp_three_inc_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_three_inc_min_101),
        .Q(temp_cmp_three_inc_min_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_three_inc_min_102_reg_i_1
       (.CI(temp_cmp_three_inc_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_min_101,temp_cmp_three_inc_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_three_inc_min_102_i_3_n_0,temp_cmp_three_inc_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_three_inc_min_102_i_5_n_0,temp_cmp_three_inc_min_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_three_inc_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_three_inc_min_102_reg_i_2_n_0,temp_cmp_three_inc_min_102_reg_i_2_n_1,temp_cmp_three_inc_min_102_reg_i_2_n_2,temp_cmp_three_inc_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_three_inc_min_102_i_7_n_0,temp_cmp_three_inc_min_102_i_8_n_0,temp_cmp_three_inc_min_102_i_9_n_0,temp_cmp_three_inc_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_three_inc_min_102_i_11_n_0,temp_cmp_three_inc_min_102_i_12_n_0,temp_cmp_three_inc_min_102_i_13_n_0,temp_cmp_three_inc_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(two_dec_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_two_dec_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(two_dec_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(two_dec_max_limit[7]),
        .O(temp_cmp_two_dec_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(two_dec_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(two_dec_max_limit[5]),
        .O(temp_cmp_two_dec_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(two_dec_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(two_dec_max_limit[3]),
        .O(temp_cmp_two_dec_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(two_dec_max_limit[1]),
        .O(temp_cmp_two_dec_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(two_dec_max_limit[10]),
        .I2(two_dec_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_two_dec_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(two_dec_max_limit[8]),
        .I2(two_dec_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_two_dec_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(two_dec_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(two_dec_max_limit[11]),
        .O(temp_cmp_two_dec_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(two_dec_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(two_dec_max_limit[9]),
        .O(temp_cmp_two_dec_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(two_dec_max_limit[6]),
        .I2(two_dec_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_two_dec_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(two_dec_max_limit[4]),
        .I2(two_dec_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_two_dec_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(two_dec_max_limit[2]),
        .I2(two_dec_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_two_dec_max_102_i_9_n_0));
  FDRE temp_cmp_two_dec_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_two_dec_max_101),
        .Q(temp_cmp_two_dec_max_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_two_dec_max_102_reg_i_1
       (.CI(temp_cmp_two_dec_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_max_101,temp_cmp_two_dec_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_two_dec_max_102_i_3_n_0,temp_cmp_two_dec_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_two_dec_max_102_i_5_n_0,temp_cmp_two_dec_max_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_two_dec_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_two_dec_max_102_reg_i_2_n_0,temp_cmp_two_dec_max_102_reg_i_2_n_1,temp_cmp_two_dec_max_102_reg_i_2_n_2,temp_cmp_two_dec_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_two_dec_max_102_i_7_n_0,temp_cmp_two_dec_max_102_i_8_n_0,temp_cmp_two_dec_max_102_i_9_n_0,temp_cmp_two_dec_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_two_dec_max_102_i_11_n_0,temp_cmp_two_dec_max_102_i_12_n_0,temp_cmp_two_dec_max_102_i_13_n_0,temp_cmp_two_dec_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(two_inc_min_limit[1]),
        .O(temp_cmp_two_dec_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_11
       (.I0(two_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(two_dec_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_two_dec_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_12
       (.I0(two_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(two_dec_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_two_dec_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_13
       (.I0(two_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(two_dec_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_two_dec_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(two_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_two_dec_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_3
       (.I0(two_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(two_dec_min_limit[11]),
        .O(temp_cmp_two_dec_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_4
       (.I0(two_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(two_dec_min_limit[9]),
        .O(temp_cmp_two_dec_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_5
       (.I0(two_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(two_dec_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_two_dec_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_6
       (.I0(two_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(two_dec_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_two_dec_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_7
       (.I0(two_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(two_dec_min_limit[7]),
        .O(temp_cmp_two_dec_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_8
       (.I0(two_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(two_dec_min_limit[5]),
        .O(temp_cmp_two_dec_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_9
       (.I0(two_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(two_dec_min_limit[3]),
        .O(temp_cmp_two_dec_min_102_i_9_n_0));
  FDRE temp_cmp_two_dec_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_two_dec_min_101),
        .Q(temp_cmp_two_dec_min_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_two_dec_min_102_reg_i_1
       (.CI(temp_cmp_two_dec_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_min_101,temp_cmp_two_dec_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_two_dec_min_102_i_3_n_0,temp_cmp_two_dec_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_two_dec_min_102_i_5_n_0,temp_cmp_two_dec_min_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_two_dec_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_two_dec_min_102_reg_i_2_n_0,temp_cmp_two_dec_min_102_reg_i_2_n_1,temp_cmp_two_dec_min_102_reg_i_2_n_2,temp_cmp_two_dec_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_two_dec_min_102_i_7_n_0,temp_cmp_two_dec_min_102_i_8_n_0,temp_cmp_two_dec_min_102_i_9_n_0,temp_cmp_two_dec_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_two_dec_min_102_i_11_n_0,temp_cmp_two_dec_min_102_i_12_n_0,temp_cmp_two_dec_min_102_i_13_n_0,temp_cmp_two_dec_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(neutral_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_two_inc_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(two_inc_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(two_inc_max_limit[7]),
        .O(temp_cmp_two_inc_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(two_inc_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(two_inc_max_limit[5]),
        .O(temp_cmp_two_inc_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(two_inc_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(two_inc_max_limit[3]),
        .O(temp_cmp_two_inc_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(neutral_max_limit[1]),
        .O(temp_cmp_two_inc_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(two_inc_max_limit[10]),
        .I2(two_inc_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_two_inc_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(two_inc_max_limit[8]),
        .I2(two_inc_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_two_inc_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(two_inc_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(two_inc_max_limit[11]),
        .O(temp_cmp_two_inc_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(two_inc_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(two_inc_max_limit[9]),
        .O(temp_cmp_two_inc_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(two_inc_max_limit[6]),
        .I2(two_inc_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_two_inc_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(two_inc_max_limit[4]),
        .I2(two_inc_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_two_inc_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(two_inc_max_limit[2]),
        .I2(two_inc_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_two_inc_max_102_i_9_n_0));
  FDRE temp_cmp_two_inc_max_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_two_inc_max_101),
        .Q(temp_cmp_two_inc_max_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_two_inc_max_102_reg_i_1
       (.CI(temp_cmp_two_inc_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_max_101,temp_cmp_two_inc_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_two_inc_max_102_i_3_n_0,temp_cmp_two_inc_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_two_inc_max_102_i_5_n_0,temp_cmp_two_inc_max_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_two_inc_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_two_inc_max_102_reg_i_2_n_0,temp_cmp_two_inc_max_102_reg_i_2_n_1,temp_cmp_two_inc_max_102_reg_i_2_n_2,temp_cmp_two_inc_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_two_inc_max_102_i_7_n_0,temp_cmp_two_inc_max_102_i_8_n_0,temp_cmp_two_inc_max_102_i_9_n_0,temp_cmp_two_inc_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_two_inc_max_102_i_11_n_0,temp_cmp_two_inc_max_102_i_12_n_0,temp_cmp_two_inc_max_102_i_13_n_0,temp_cmp_two_inc_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(two_inc_min_limit[1]),
        .O(temp_cmp_two_inc_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_11
       (.I0(two_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(two_inc_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_two_inc_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_12
       (.I0(two_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(two_inc_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_two_inc_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_13
       (.I0(two_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(two_inc_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_two_inc_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(two_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_two_inc_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_3
       (.I0(two_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(two_inc_min_limit[11]),
        .O(temp_cmp_two_inc_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_4
       (.I0(two_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(two_inc_min_limit[9]),
        .O(temp_cmp_two_inc_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_5
       (.I0(two_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(two_inc_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_two_inc_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_6
       (.I0(two_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(two_inc_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_two_inc_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_7
       (.I0(two_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(two_inc_min_limit[7]),
        .O(temp_cmp_two_inc_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_8
       (.I0(two_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(two_inc_min_limit[5]),
        .O(temp_cmp_two_inc_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_9
       (.I0(two_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(two_inc_min_limit[3]),
        .O(temp_cmp_two_inc_min_102_i_9_n_0));
  FDRE temp_cmp_two_inc_min_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(temp_cmp_two_inc_min_101),
        .Q(temp_cmp_two_inc_min_102),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_two_inc_min_102_reg_i_1
       (.CI(temp_cmp_two_inc_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_min_101,temp_cmp_two_inc_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_two_inc_min_102_i_3_n_0,temp_cmp_two_inc_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_two_inc_min_102_i_5_n_0,temp_cmp_two_inc_min_102_i_6_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 temp_cmp_two_inc_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_two_inc_min_102_reg_i_2_n_0,temp_cmp_two_inc_min_102_reg_i_2_n_1,temp_cmp_two_inc_min_102_reg_i_2_n_2,temp_cmp_two_inc_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_two_inc_min_102_i_7_n_0,temp_cmp_two_inc_min_102_i_8_n_0,temp_cmp_two_inc_min_102_i_9_n_0,temp_cmp_two_inc_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_two_inc_min_102_i_11_n_0,temp_cmp_two_inc_min_102_i_12_n_0,temp_cmp_two_inc_min_102_i_13_n_0,temp_cmp_two_inc_min_102_i_14_n_0}));
  FDRE tempmon_init_complete_reg
       (.C(CLK),
        .CE(tempmon_state_init),
        .D(tempmon_state_init),
        .Q(tempmon_init_complete),
        .R(pi_f_dec_reg_1));
  FDRE tempmon_sample_en_101_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mc_ref_zq_wip),
        .Q(tempmon_sample_en_101),
        .R(pi_f_dec_reg_1));
  FDRE tempmon_sample_en_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(tempmon_sample_en_101),
        .Q(tempmon_sample_en_102),
        .R(pi_f_dec_reg_1));
  LUT1 #(
    .INIT(2'h1)) 
    \tempmon_state[0]_i_1 
       (.I0(\tempmon_state[10]_i_6_n_0 ),
        .O(tempmon_state_nxt[0]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFC444)) 
    \tempmon_state[10]_i_1 
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(update_temp_102),
        .I2(temp_cmp_four_dec_min_102),
        .I3(tempmon_state[10]),
        .I4(\tempmon_state[10]_i_4_n_0 ),
        .I5(\tempmon_state[10]_i_5_n_0 ),
        .O(\tempmon_state[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT5 #(
    .INIT(32'h00010116)) 
    \tempmon_state[10]_i_10 
       (.I0(tempmon_state[0]),
        .I1(tempmon_state[1]),
        .I2(tempmon_state[2]),
        .I3(tempmon_state[3]),
        .I4(tempmon_state[4]),
        .O(\tempmon_state[10]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT5 #(
    .INIT(32'hFFFEFEE8)) 
    \tempmon_state[10]_i_11 
       (.I0(tempmon_state[0]),
        .I1(tempmon_state[1]),
        .I2(tempmon_state[2]),
        .I3(tempmon_state[3]),
        .I4(tempmon_state[4]),
        .O(\tempmon_state[10]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100010116)) 
    \tempmon_state[10]_i_12 
       (.I0(tempmon_state[5]),
        .I1(tempmon_state[6]),
        .I2(tempmon_state[7]),
        .I3(tempmon_state[8]),
        .I4(tempmon_state[9]),
        .I5(tempmon_state[10]),
        .O(\tempmon_state[10]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFEFEE8)) 
    \tempmon_state[10]_i_13 
       (.I0(tempmon_state[5]),
        .I1(tempmon_state[6]),
        .I2(tempmon_state[7]),
        .I3(tempmon_state[8]),
        .I4(tempmon_state[9]),
        .I5(tempmon_state[10]),
        .O(\tempmon_state[10]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \tempmon_state[10]_i_14 
       (.I0(temp_cmp_two_dec_min_102),
        .I1(tempmon_state[8]),
        .I2(temp_cmp_three_inc_min_102),
        .I3(tempmon_state[3]),
        .O(\tempmon_state[10]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \tempmon_state[10]_i_15 
       (.I0(temp_cmp_two_dec_max_102),
        .I1(update_temp_102),
        .I2(tempmon_state[8]),
        .O(\tempmon_state[10]_i_15_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \tempmon_state[10]_i_2 
       (.I0(update_temp_102),
        .I1(temp_cmp_three_dec_max_102),
        .I2(tempmon_state[9]),
        .I3(\tempmon_state[10]_i_6_n_0 ),
        .O(tempmon_state_nxt[10]));
  LUT6 #(
    .INIT(64'h0000022202220222)) 
    \tempmon_state[10]_i_3 
       (.I0(pi_f_dec_i_2_n_0),
        .I1(\tempmon_state[10]_i_7_n_0 ),
        .I2(temp_cmp_one_dec_min_102),
        .I3(tempmon_state[7]),
        .I4(temp_cmp_three_dec_min_102),
        .I5(tempmon_state[9]),
        .O(\tempmon_state[10]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT5 #(
    .INIT(32'hFFEFEFEF)) 
    \tempmon_state[10]_i_4 
       (.I0(\tempmon_state[10]_i_8_n_0 ),
        .I1(tempmon_state[1]),
        .I2(\tempmon_state[10]_i_6_n_0 ),
        .I3(tempmon_state[0]),
        .I4(calib_complete),
        .O(\tempmon_state[10]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFAAEAAAEAAAEAAA)) 
    \tempmon_state[10]_i_5 
       (.I0(\tempmon_state[10]_i_9_n_0 ),
        .I1(tempmon_state[6]),
        .I2(temp_cmp_neutral_max_102),
        .I3(update_temp_102),
        .I4(tempmon_state[7]),
        .I5(temp_cmp_one_dec_max_102),
        .O(\tempmon_state[10]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h0012)) 
    \tempmon_state[10]_i_6 
       (.I0(\tempmon_state[10]_i_10_n_0 ),
        .I1(\tempmon_state[10]_i_11_n_0 ),
        .I2(\tempmon_state[10]_i_12_n_0 ),
        .I3(\tempmon_state[10]_i_13_n_0 ),
        .O(\tempmon_state[10]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \tempmon_state[10]_i_7 
       (.I0(tempmon_state[4]),
        .I1(temp_cmp_two_inc_min_102),
        .I2(tempmon_state[6]),
        .I3(temp_cmp_neutral_min_102),
        .I4(\tempmon_state[10]_i_14_n_0 ),
        .O(\tempmon_state[10]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \tempmon_state[10]_i_8 
       (.I0(temp_cmp_one_inc_min_102),
        .I1(tempmon_state[5]),
        .I2(update_temp_102),
        .O(\tempmon_state[10]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFF8F0F0F8F8F0F0)) 
    \tempmon_state[10]_i_9 
       (.I0(tempmon_state[2]),
        .I1(temp_cmp_four_inc_max_102),
        .I2(\tempmon_state[10]_i_15_n_0 ),
        .I3(tempmon_state[9]),
        .I4(update_temp_102),
        .I5(temp_cmp_three_dec_max_102),
        .O(\tempmon_state[10]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \tempmon_state[1]_i_1 
       (.I0(\tempmon_state[10]_i_6_n_0 ),
        .I1(tempmon_state[0]),
        .O(tempmon_state_nxt[1]));
  LUT4 #(
    .INIT(16'h7000)) 
    \tempmon_state[2]_i_1 
       (.I0(temp_cmp_three_inc_max_102),
        .I1(update_temp_102),
        .I2(tempmon_state[3]),
        .I3(\tempmon_state[10]_i_6_n_0 ),
        .O(tempmon_state_nxt[2]));
  LUT5 #(
    .INIT(32'h8AAA8888)) 
    \tempmon_state[3]_i_1 
       (.I0(\tempmon_state[10]_i_6_n_0 ),
        .I1(tempmon_state[2]),
        .I2(temp_cmp_two_inc_max_102),
        .I3(update_temp_102),
        .I4(tempmon_state[4]),
        .O(tempmon_state_nxt[3]));
  LUT6 #(
    .INIT(64'h8080F000F080F000)) 
    \tempmon_state[4]_i_1 
       (.I0(temp_cmp_three_inc_max_102),
        .I1(tempmon_state[3]),
        .I2(\tempmon_state[10]_i_6_n_0 ),
        .I3(tempmon_state[5]),
        .I4(update_temp_102),
        .I5(temp_cmp_one_inc_max_102),
        .O(tempmon_state_nxt[4]));
  LUT6 #(
    .INIT(64'h8080F000F080F000)) 
    \tempmon_state[5]_i_1 
       (.I0(temp_cmp_two_inc_max_102),
        .I1(tempmon_state[4]),
        .I2(\tempmon_state[10]_i_6_n_0 ),
        .I3(tempmon_state[6]),
        .I4(update_temp_102),
        .I5(temp_cmp_neutral_max_102),
        .O(tempmon_state_nxt[5]));
  LUT6 #(
    .INIT(64'hFFFF0000BFA00000)) 
    \tempmon_state[6]_i_1 
       (.I0(\tempmon_state[6]_i_2_n_0 ),
        .I1(temp_cmp_one_dec_max_102),
        .I2(update_temp_102),
        .I3(tempmon_state[7]),
        .I4(\tempmon_state[10]_i_6_n_0 ),
        .I5(tempmon_state[1]),
        .O(tempmon_state_nxt[6]));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \tempmon_state[6]_i_2 
       (.I0(temp_cmp_one_inc_max_102),
        .I1(tempmon_state[5]),
        .O(\tempmon_state[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h80AAAAAA80008000)) 
    \tempmon_state[7]_i_1 
       (.I0(\tempmon_state[10]_i_6_n_0 ),
        .I1(tempmon_state[6]),
        .I2(temp_cmp_neutral_max_102),
        .I3(update_temp_102),
        .I4(temp_cmp_two_dec_max_102),
        .I5(tempmon_state[8]),
        .O(tempmon_state_nxt[7]));
  LUT6 #(
    .INIT(64'h8080F080F000F000)) 
    \tempmon_state[8]_i_1 
       (.I0(tempmon_state[7]),
        .I1(temp_cmp_one_dec_max_102),
        .I2(\tempmon_state[10]_i_6_n_0 ),
        .I3(tempmon_state[9]),
        .I4(temp_cmp_three_dec_max_102),
        .I5(update_temp_102),
        .O(tempmon_state_nxt[8]));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \tempmon_state[9]_i_1 
       (.I0(\tempmon_state[10]_i_6_n_0 ),
        .I1(temp_cmp_two_dec_max_102),
        .I2(update_temp_102),
        .I3(tempmon_state[8]),
        .I4(tempmon_state[10]),
        .O(tempmon_state_nxt[9]));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDSE \tempmon_state_reg[0] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[0]),
        .Q(tempmon_state[0]),
        .S(\three_dec_max_limit_reg[0]_0 [2]));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[10] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[10]),
        .Q(tempmon_state[10]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[1] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[1]),
        .Q(tempmon_state[1]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[2] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[2]),
        .Q(tempmon_state[2]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[3] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[3]),
        .Q(tempmon_state[3]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[4] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[4]),
        .Q(tempmon_state[4]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[5] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[5]),
        .Q(tempmon_state[5]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[6] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[6]),
        .Q(tempmon_state[6]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[7] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[7]),
        .Q(tempmon_state[7]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[8] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[8]),
        .Q(tempmon_state[8]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[9] 
       (.C(CLK),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[9]),
        .Q(tempmon_state[9]),
        .R(\three_dec_max_limit_reg[0]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \three_dec_max_limit[0]_i_1 
       (.I0(p_0_in),
        .I1(device_temp_init[0]),
        .O(\three_dec_max_limit[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[10]_i_1 
       (.I0(\three_dec_max_limit_reg[11]_i_2_n_6 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[11]_i_1 
       (.I0(\three_dec_max_limit_reg[11]_i_2_n_5 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[11]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_max_limit[11]_i_3 
       (.I0(device_temp_init[9]),
        .O(\three_dec_max_limit[11]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[1]_i_1 
       (.I0(\three_inc_max_limit_reg[4]_i_1_n_7 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[2]_i_1 
       (.I0(\three_dec_max_limit_reg[4]_i_2_n_6 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[3]_i_1 
       (.I0(\three_dec_max_limit_reg[4]_i_2_n_5 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[4]_i_1 
       (.I0(\three_dec_max_limit_reg[4]_i_2_n_4 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[5]_i_1 
       (.I0(\three_dec_max_limit_reg[8]_i_2_n_7 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[6]_i_1 
       (.I0(\three_dec_max_limit_reg[8]_i_2_n_6 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[7]_i_1 
       (.I0(\three_dec_max_limit_reg[8]_i_2_n_5 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[8]_i_1 
       (.I0(\three_dec_max_limit_reg[8]_i_2_n_4 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[8]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_max_limit[8]_i_3 
       (.I0(device_temp_init[8]),
        .O(\three_dec_max_limit[8]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_max_limit[8]_i_4 
       (.I0(device_temp_init[6]),
        .O(\three_dec_max_limit[8]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[9]_i_1 
       (.I0(\three_dec_max_limit_reg[11]_i_2_n_7 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[9]_i_1_n_0 ));
  FDRE \three_dec_max_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[0]_i_1_n_0 ),
        .Q(three_dec_max_limit[0]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_dec_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[10]_i_1_n_0 ),
        .Q(three_dec_max_limit[10]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_dec_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[11]_i_1_n_0 ),
        .Q(three_dec_max_limit[11]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  CARRY4 \three_dec_max_limit_reg[11]_i_2 
       (.CI(\three_dec_max_limit_reg[8]_i_2_n_0 ),
        .CO({p_0_in,\NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED [2],\three_dec_max_limit_reg[11]_i_2_n_2 ,\three_dec_max_limit_reg[11]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,device_temp_init[9]}),
        .O({\NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED [3],\three_dec_max_limit_reg[11]_i_2_n_5 ,\three_dec_max_limit_reg[11]_i_2_n_6 ,\three_dec_max_limit_reg[11]_i_2_n_7 }),
        .S({1'b1,device_temp_init[11:10],\three_dec_max_limit[11]_i_3_n_0 }));
  FDRE \three_dec_max_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[1]_i_1_n_0 ),
        .Q(three_dec_max_limit[1]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_dec_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[2]_i_1_n_0 ),
        .Q(three_dec_max_limit[2]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_dec_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[3]_i_1_n_0 ),
        .Q(three_dec_max_limit[3]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_dec_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[4]_i_1_n_0 ),
        .Q(three_dec_max_limit[4]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  CARRY4 \three_dec_max_limit_reg[4]_i_2 
       (.CI(1'b0),
        .CO({\three_dec_max_limit_reg[4]_i_2_n_0 ,\three_dec_max_limit_reg[4]_i_2_n_1 ,\three_dec_max_limit_reg[4]_i_2_n_2 ,\three_dec_max_limit_reg[4]_i_2_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\three_dec_max_limit_reg[4]_i_2_n_4 ,\three_dec_max_limit_reg[4]_i_2_n_5 ,\three_dec_max_limit_reg[4]_i_2_n_6 ,\NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED [0]}),
        .S(device_temp_init[4:1]));
  FDRE \three_dec_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[5]_i_1_n_0 ),
        .Q(three_dec_max_limit[5]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_dec_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[6]_i_1_n_0 ),
        .Q(three_dec_max_limit[6]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_dec_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[7]_i_1_n_0 ),
        .Q(three_dec_max_limit[7]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_dec_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[8]_i_1_n_0 ),
        .Q(three_dec_max_limit[8]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  CARRY4 \three_dec_max_limit_reg[8]_i_2 
       (.CI(\three_dec_max_limit_reg[4]_i_2_n_0 ),
        .CO({\three_dec_max_limit_reg[8]_i_2_n_0 ,\three_dec_max_limit_reg[8]_i_2_n_1 ,\three_dec_max_limit_reg[8]_i_2_n_2 ,\three_dec_max_limit_reg[8]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[8],1'b0,device_temp_init[6],1'b0}),
        .O({\three_dec_max_limit_reg[8]_i_2_n_4 ,\three_dec_max_limit_reg[8]_i_2_n_5 ,\three_dec_max_limit_reg[8]_i_2_n_6 ,\three_dec_max_limit_reg[8]_i_2_n_7 }),
        .S({\three_dec_max_limit[8]_i_3_n_0 ,device_temp_init[7],\three_dec_max_limit[8]_i_4_n_0 ,device_temp_init[5]}));
  FDRE \three_dec_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\three_dec_max_limit[9]_i_1_n_0 ),
        .Q(three_dec_max_limit[9]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[11]_i_2 
       (.I0(two_dec_max_limit[11]),
        .O(\three_dec_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[11]_i_3 
       (.I0(two_dec_max_limit[10]),
        .O(\three_dec_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[5]_i_2 
       (.I0(two_dec_max_limit[5]),
        .O(\three_dec_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[5]_i_3 
       (.I0(two_dec_max_limit[4]),
        .O(\three_dec_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[5]_i_4 
       (.I0(two_dec_max_limit[3]),
        .O(\three_dec_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[9]_i_2 
       (.I0(two_dec_max_limit[9]),
        .O(\three_dec_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[9]_i_3 
       (.I0(two_dec_max_limit[8]),
        .O(\three_dec_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[9]_i_4 
       (.I0(two_dec_max_limit[7]),
        .O(\three_dec_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[9]_i_5 
       (.I0(two_dec_max_limit[6]),
        .O(\three_dec_min_limit[9]_i_5_n_0 ));
  FDRE \three_dec_min_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit[0]),
        .Q(three_dec_min_limit[0]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \three_dec_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[10]),
        .Q(three_dec_min_limit[10]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \three_dec_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[11]),
        .Q(three_dec_min_limit[11]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \three_dec_min_limit_reg[11]_i_1 
       (.CI(\three_dec_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\three_dec_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,two_dec_max_limit[10]}),
        .O({\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_dec_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\three_dec_min_limit[11]_i_2_n_0 ,\three_dec_min_limit[11]_i_3_n_0 }));
  FDRE \three_dec_min_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit[1]),
        .Q(three_dec_min_limit[1]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \three_dec_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[2]),
        .Q(three_dec_min_limit[2]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \three_dec_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[3]),
        .Q(three_dec_min_limit[3]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \three_dec_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[4]),
        .Q(three_dec_min_limit[4]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \three_dec_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[5]),
        .Q(three_dec_min_limit[5]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \three_dec_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\three_dec_min_limit_reg[5]_i_1_n_0 ,\three_dec_min_limit_reg[5]_i_1_n_1 ,\three_dec_min_limit_reg[5]_i_1_n_2 ,\three_dec_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({two_dec_max_limit[5:3],1'b0}),
        .O(three_dec_min_limit_nxt[5:2]),
        .S({\three_dec_min_limit[5]_i_2_n_0 ,\three_dec_min_limit[5]_i_3_n_0 ,\three_dec_min_limit[5]_i_4_n_0 ,two_dec_max_limit[2]}));
  FDRE \three_dec_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[6]),
        .Q(three_dec_min_limit[6]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \three_dec_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[7]),
        .Q(three_dec_min_limit[7]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \three_dec_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[8]),
        .Q(three_dec_min_limit[8]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  FDRE \three_dec_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[9]),
        .Q(three_dec_min_limit[9]),
        .R(\three_dec_max_limit_reg[0]_0 [0]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \three_dec_min_limit_reg[9]_i_1 
       (.CI(\three_dec_min_limit_reg[5]_i_1_n_0 ),
        .CO({\three_dec_min_limit_reg[9]_i_1_n_0 ,\three_dec_min_limit_reg[9]_i_1_n_1 ,\three_dec_min_limit_reg[9]_i_1_n_2 ,\three_dec_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(two_dec_max_limit[9:6]),
        .O(three_dec_min_limit_nxt[9:6]),
        .S({\three_dec_min_limit[9]_i_2_n_0 ,\three_dec_min_limit[9]_i_3_n_0 ,\three_dec_min_limit[9]_i_4_n_0 ,\three_dec_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\three_inc_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\three_inc_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[4]_i_2 
       (.I0(device_temp_init[3]),
        .O(\three_inc_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[4]_i_3 
       (.I0(device_temp_init[2]),
        .O(\three_inc_max_limit[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[8]_i_2 
       (.I0(device_temp_init[8]),
        .O(\three_inc_max_limit[8]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[8]_i_3 
       (.I0(device_temp_init[7]),
        .O(\three_inc_max_limit[8]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[8]_i_4 
       (.I0(device_temp_init[5]),
        .O(\three_inc_max_limit[8]_i_4_n_0 ));
  FDRE \three_inc_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[10]),
        .Q(three_inc_max_limit[10]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_inc_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[11]),
        .Q(three_inc_max_limit[11]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \three_inc_max_limit_reg[11]_i_1 
       (.CI(\three_inc_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\three_inc_max_limit_reg[11]_i_1_n_2 ,\three_inc_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[10],1'b0}),
        .O({\NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],three_inc_max_limit_nxt[11:9]}),
        .S({1'b0,\three_inc_max_limit[11]_i_2_n_0 ,\three_inc_max_limit[11]_i_3_n_0 ,device_temp_init[9]}));
  FDRE \three_inc_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[2]),
        .Q(three_inc_max_limit[2]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_inc_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[3]),
        .Q(three_inc_max_limit[3]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_inc_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[4]),
        .Q(three_inc_max_limit[4]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \three_inc_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\three_inc_max_limit_reg[4]_i_1_n_0 ,\three_inc_max_limit_reg[4]_i_1_n_1 ,\three_inc_max_limit_reg[4]_i_1_n_2 ,\three_inc_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({1'b0,device_temp_init[3:2],1'b0}),
        .O({three_inc_max_limit_nxt[4:2],\three_inc_max_limit_reg[4]_i_1_n_7 }),
        .S({device_temp_init[4],\three_inc_max_limit[4]_i_2_n_0 ,\three_inc_max_limit[4]_i_3_n_0 ,device_temp_init[1]}));
  FDRE \three_inc_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[5]),
        .Q(three_inc_max_limit[5]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_inc_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[6]),
        .Q(three_inc_max_limit[6]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_inc_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[7]),
        .Q(three_inc_max_limit[7]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  FDRE \three_inc_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[8]),
        .Q(three_inc_max_limit[8]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \three_inc_max_limit_reg[8]_i_1 
       (.CI(\three_inc_max_limit_reg[4]_i_1_n_0 ),
        .CO({\three_inc_max_limit_reg[8]_i_1_n_0 ,\three_inc_max_limit_reg[8]_i_1_n_1 ,\three_inc_max_limit_reg[8]_i_1_n_2 ,\three_inc_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[8:7],1'b0,device_temp_init[5]}),
        .O(three_inc_max_limit_nxt[8:5]),
        .S({\three_inc_max_limit[8]_i_2_n_0 ,\three_inc_max_limit[8]_i_3_n_0 ,device_temp_init[6],\three_inc_max_limit[8]_i_4_n_0 }));
  FDRE \three_inc_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[9]),
        .Q(three_inc_max_limit[9]),
        .R(\three_dec_max_limit_reg[0]_0 [3]));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[11]_i_2 
       (.I0(four_inc_max_limit[11]),
        .O(\three_inc_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[11]_i_3 
       (.I0(four_inc_max_limit[10]),
        .O(\three_inc_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[5]_i_2 
       (.I0(four_inc_max_limit[5]),
        .O(\three_inc_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[5]_i_3 
       (.I0(four_inc_max_limit[4]),
        .O(\three_inc_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[5]_i_4 
       (.I0(four_inc_max_limit[3]),
        .O(\three_inc_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[9]_i_2 
       (.I0(four_inc_max_limit[9]),
        .O(\three_inc_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[9]_i_3 
       (.I0(four_inc_max_limit[8]),
        .O(\three_inc_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[9]_i_4 
       (.I0(four_inc_max_limit[7]),
        .O(\three_inc_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[9]_i_5 
       (.I0(four_inc_max_limit[6]),
        .O(\three_inc_min_limit[9]_i_5_n_0 ));
  FDRE \three_inc_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[10]),
        .Q(three_inc_min_limit[10]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \three_inc_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[11]),
        .Q(three_inc_min_limit[11]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \three_inc_min_limit_reg[11]_i_1 
       (.CI(\three_inc_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\three_inc_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,four_inc_max_limit[10]}),
        .O({\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_inc_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\three_inc_min_limit[11]_i_2_n_0 ,\three_inc_min_limit[11]_i_3_n_0 }));
  FDRE \three_inc_min_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(neutral_max_limit[1]),
        .Q(three_inc_min_limit[1]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \three_inc_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[2]),
        .Q(three_inc_min_limit[2]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \three_inc_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[3]),
        .Q(three_inc_min_limit[3]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \three_inc_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[4]),
        .Q(three_inc_min_limit[4]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \three_inc_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[5]),
        .Q(three_inc_min_limit[5]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \three_inc_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\three_inc_min_limit_reg[5]_i_1_n_0 ,\three_inc_min_limit_reg[5]_i_1_n_1 ,\three_inc_min_limit_reg[5]_i_1_n_2 ,\three_inc_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({four_inc_max_limit[5:3],1'b0}),
        .O(three_inc_min_limit_nxt[5:2]),
        .S({\three_inc_min_limit[5]_i_2_n_0 ,\three_inc_min_limit[5]_i_3_n_0 ,\three_inc_min_limit[5]_i_4_n_0 ,four_inc_max_limit[2]}));
  FDRE \three_inc_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[6]),
        .Q(three_inc_min_limit[6]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \three_inc_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[7]),
        .Q(three_inc_min_limit[7]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \three_inc_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[8]),
        .Q(three_inc_min_limit[8]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \three_inc_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[9]),
        .Q(three_inc_min_limit[9]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \three_inc_min_limit_reg[9]_i_1 
       (.CI(\three_inc_min_limit_reg[5]_i_1_n_0 ),
        .CO({\three_inc_min_limit_reg[9]_i_1_n_0 ,\three_inc_min_limit_reg[9]_i_1_n_1 ,\three_inc_min_limit_reg[9]_i_1_n_2 ,\three_inc_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(four_inc_max_limit[9:6]),
        .O(three_inc_min_limit_nxt[9:6]),
        .S({\three_inc_min_limit[9]_i_2_n_0 ,\three_inc_min_limit[9]_i_3_n_0 ,\three_inc_min_limit[9]_i_4_n_0 ,\three_inc_min_limit[9]_i_5_n_0 }));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[0]_i_1 
       (.I0(device_temp_init[0]),
        .O(\two_dec_max_limit[0]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[11]_i_2 
       (.I0(device_temp_init[9]),
        .O(\two_dec_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[4]_i_2 
       (.I0(device_temp_init[4]),
        .O(\two_dec_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[4]_i_3 
       (.I0(device_temp_init[1]),
        .O(\two_dec_max_limit[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[8]_i_2 
       (.I0(device_temp_init[6]),
        .O(\two_dec_max_limit[8]_i_2_n_0 ));
  FDRE \two_dec_max_limit_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\two_dec_max_limit[0]_i_1_n_0 ),
        .Q(two_dec_max_limit[0]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_dec_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[10]),
        .Q(two_dec_max_limit[10]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_dec_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[11]),
        .Q(two_dec_max_limit[11]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \two_dec_max_limit_reg[11]_i_1 
       (.CI(\two_dec_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\two_dec_max_limit_reg[11]_i_1_n_2 ,\two_dec_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,device_temp_init[9]}),
        .O({\NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED [3],two_dec_max_limit_nxt[11:9]}),
        .S({1'b0,device_temp_init[11:10],\two_dec_max_limit[11]_i_2_n_0 }));
  FDRE \two_dec_max_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[1]),
        .Q(two_dec_max_limit[1]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_dec_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[2]),
        .Q(two_dec_max_limit[2]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_dec_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[3]),
        .Q(two_dec_max_limit[3]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_dec_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[4]),
        .Q(two_dec_max_limit[4]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \two_dec_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\two_dec_max_limit_reg[4]_i_1_n_0 ,\two_dec_max_limit_reg[4]_i_1_n_1 ,\two_dec_max_limit_reg[4]_i_1_n_2 ,\two_dec_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({device_temp_init[4],1'b0,1'b0,device_temp_init[1]}),
        .O({two_dec_max_limit_nxt[4:2],\NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),
        .S({\two_dec_max_limit[4]_i_2_n_0 ,device_temp_init[3:2],\two_dec_max_limit[4]_i_3_n_0 }));
  FDRE \two_dec_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[5]),
        .Q(two_dec_max_limit[5]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_dec_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[6]),
        .Q(two_dec_max_limit[6]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_dec_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[7]),
        .Q(two_dec_max_limit[7]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_dec_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[8]),
        .Q(two_dec_max_limit[8]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \two_dec_max_limit_reg[8]_i_1 
       (.CI(\two_dec_max_limit_reg[4]_i_1_n_0 ),
        .CO({\two_dec_max_limit_reg[8]_i_1_n_0 ,\two_dec_max_limit_reg[8]_i_1_n_1 ,\two_dec_max_limit_reg[8]_i_1_n_2 ,\two_dec_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[6],1'b0}),
        .O(two_dec_max_limit_nxt[8:5]),
        .S({device_temp_init[8:7],\two_dec_max_limit[8]_i_2_n_0 ,device_temp_init[5]}));
  FDRE \two_dec_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[9]),
        .Q(two_dec_max_limit[9]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[11]_i_2 
       (.I0(one_dec_max_limit[11]),
        .O(\two_dec_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[11]_i_3 
       (.I0(one_dec_max_limit[10]),
        .O(\two_dec_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[5]_i_2 
       (.I0(one_dec_max_limit[5]),
        .O(\two_dec_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[5]_i_3 
       (.I0(one_dec_max_limit[4]),
        .O(\two_dec_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[5]_i_4 
       (.I0(one_dec_max_limit[3]),
        .O(\two_dec_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[9]_i_2 
       (.I0(one_dec_max_limit[9]),
        .O(\two_dec_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[9]_i_3 
       (.I0(one_dec_max_limit[8]),
        .O(\two_dec_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[9]_i_4 
       (.I0(one_dec_max_limit[7]),
        .O(\two_dec_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[9]_i_5 
       (.I0(one_dec_max_limit[6]),
        .O(\two_dec_min_limit[9]_i_5_n_0 ));
  FDRE \two_dec_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[10]),
        .Q(two_dec_min_limit[10]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[11]),
        .Q(two_dec_min_limit[11]),
        .R(pi_f_dec_reg_1));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \two_dec_min_limit_reg[11]_i_1 
       (.CI(\two_dec_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\two_dec_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,one_dec_max_limit[10]}),
        .O({\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_dec_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\two_dec_min_limit[11]_i_2_n_0 ,\two_dec_min_limit[11]_i_3_n_0 }));
  FDRE \two_dec_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[2]),
        .Q(two_dec_min_limit[2]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[3]),
        .Q(two_dec_min_limit[3]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[4]),
        .Q(two_dec_min_limit[4]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[5]),
        .Q(two_dec_min_limit[5]),
        .R(pi_f_dec_reg_1));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \two_dec_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\two_dec_min_limit_reg[5]_i_1_n_0 ,\two_dec_min_limit_reg[5]_i_1_n_1 ,\two_dec_min_limit_reg[5]_i_1_n_2 ,\two_dec_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({one_dec_max_limit[5:3],1'b0}),
        .O(two_dec_min_limit_nxt[5:2]),
        .S({\two_dec_min_limit[5]_i_2_n_0 ,\two_dec_min_limit[5]_i_3_n_0 ,\two_dec_min_limit[5]_i_4_n_0 ,one_dec_max_limit[2]}));
  FDRE \two_dec_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[6]),
        .Q(two_dec_min_limit[6]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[7]),
        .Q(two_dec_min_limit[7]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[8]),
        .Q(two_dec_min_limit[8]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[9]),
        .Q(two_dec_min_limit[9]),
        .R(pi_f_dec_reg_1));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \two_dec_min_limit_reg[9]_i_1 
       (.CI(\two_dec_min_limit_reg[5]_i_1_n_0 ),
        .CO({\two_dec_min_limit_reg[9]_i_1_n_0 ,\two_dec_min_limit_reg[9]_i_1_n_1 ,\two_dec_min_limit_reg[9]_i_1_n_2 ,\two_dec_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(one_dec_max_limit[9:6]),
        .O(two_dec_min_limit_nxt[9:6]),
        .S({\two_dec_min_limit[9]_i_2_n_0 ,\two_dec_min_limit[9]_i_3_n_0 ,\two_dec_min_limit[9]_i_4_n_0 ,\two_dec_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\two_inc_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\two_inc_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[11]_i_4 
       (.I0(device_temp_init[9]),
        .O(\two_inc_max_limit[11]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[4]_i_2 
       (.I0(device_temp_init[4]),
        .O(\two_inc_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[4]_i_3 
       (.I0(device_temp_init[3]),
        .O(\two_inc_max_limit[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[4]_i_4 
       (.I0(device_temp_init[1]),
        .O(\two_inc_max_limit[4]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[8]_i_2 
       (.I0(device_temp_init[7]),
        .O(\two_inc_max_limit[8]_i_2_n_0 ));
  FDRE \two_inc_max_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[10]),
        .Q(two_inc_max_limit[10]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_inc_max_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[11]),
        .Q(two_inc_max_limit[11]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \two_inc_max_limit_reg[11]_i_1 
       (.CI(\two_inc_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\two_inc_max_limit_reg[11]_i_1_n_2 ,\two_inc_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[10:9]}),
        .O({\NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],two_inc_max_limit_nxt[11:9]}),
        .S({1'b0,\two_inc_max_limit[11]_i_2_n_0 ,\two_inc_max_limit[11]_i_3_n_0 ,\two_inc_max_limit[11]_i_4_n_0 }));
  FDRE \two_inc_max_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[2]),
        .Q(two_inc_max_limit[2]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_inc_max_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[3]),
        .Q(two_inc_max_limit[3]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_inc_max_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[4]),
        .Q(two_inc_max_limit[4]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \two_inc_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\two_inc_max_limit_reg[4]_i_1_n_0 ,\two_inc_max_limit_reg[4]_i_1_n_1 ,\two_inc_max_limit_reg[4]_i_1_n_2 ,\two_inc_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({device_temp_init[4:3],1'b0,device_temp_init[1]}),
        .O({two_inc_max_limit_nxt[4:2],\NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),
        .S({\two_inc_max_limit[4]_i_2_n_0 ,\two_inc_max_limit[4]_i_3_n_0 ,device_temp_init[2],\two_inc_max_limit[4]_i_4_n_0 }));
  FDRE \two_inc_max_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[5]),
        .Q(two_inc_max_limit[5]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_inc_max_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[6]),
        .Q(two_inc_max_limit[6]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_inc_max_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[7]),
        .Q(two_inc_max_limit[7]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  FDRE \two_inc_max_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[8]),
        .Q(two_inc_max_limit[8]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \two_inc_max_limit_reg[8]_i_1 
       (.CI(\two_inc_max_limit_reg[4]_i_1_n_0 ),
        .CO({\two_inc_max_limit_reg[8]_i_1_n_0 ,\two_inc_max_limit_reg[8]_i_1_n_1 ,\two_inc_max_limit_reg[8]_i_1_n_2 ,\two_inc_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[7],1'b0,1'b0}),
        .O(two_inc_max_limit_nxt[8:5]),
        .S({device_temp_init[8],\two_inc_max_limit[8]_i_2_n_0 ,device_temp_init[6:5]}));
  FDRE \two_inc_max_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[9]),
        .Q(two_inc_max_limit[9]),
        .R(\three_dec_max_limit_reg[0]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[11]_i_2 
       (.I0(three_inc_max_limit[11]),
        .O(\two_inc_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[11]_i_3 
       (.I0(three_inc_max_limit[10]),
        .O(\two_inc_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[5]_i_2 
       (.I0(three_inc_max_limit[5]),
        .O(\two_inc_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[5]_i_3 
       (.I0(three_inc_max_limit[4]),
        .O(\two_inc_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[5]_i_4 
       (.I0(three_inc_max_limit[3]),
        .O(\two_inc_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[9]_i_2 
       (.I0(three_inc_max_limit[9]),
        .O(\two_inc_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[9]_i_3 
       (.I0(three_inc_max_limit[8]),
        .O(\two_inc_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[9]_i_4 
       (.I0(three_inc_max_limit[7]),
        .O(\two_inc_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[9]_i_5 
       (.I0(three_inc_max_limit[6]),
        .O(\two_inc_min_limit[9]_i_5_n_0 ));
  FDRE \two_inc_min_limit_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[10]),
        .Q(two_inc_min_limit[10]),
        .R(pi_f_dec_reg_1));
  FDRE \two_inc_min_limit_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[11]),
        .Q(two_inc_min_limit[11]),
        .R(pi_f_dec_reg_1));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \two_inc_min_limit_reg[11]_i_1 
       (.CI(\two_inc_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\two_inc_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,three_inc_max_limit[10]}),
        .O({\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_inc_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\two_inc_min_limit[11]_i_2_n_0 ,\two_inc_min_limit[11]_i_3_n_0 }));
  FDRE \two_inc_min_limit_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(one_dec_max_limit[1]),
        .Q(two_inc_min_limit[1]),
        .R(pi_f_dec_reg_1));
  FDRE \two_inc_min_limit_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[2]),
        .Q(two_inc_min_limit[2]),
        .R(pi_f_dec_reg_1));
  FDRE \two_inc_min_limit_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[3]),
        .Q(two_inc_min_limit[3]),
        .R(pi_f_dec_reg_1));
  FDRE \two_inc_min_limit_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[4]),
        .Q(two_inc_min_limit[4]),
        .R(pi_f_dec_reg_1));
  FDRE \two_inc_min_limit_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[5]),
        .Q(two_inc_min_limit[5]),
        .R(pi_f_dec_reg_1));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \two_inc_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\two_inc_min_limit_reg[5]_i_1_n_0 ,\two_inc_min_limit_reg[5]_i_1_n_1 ,\two_inc_min_limit_reg[5]_i_1_n_2 ,\two_inc_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({three_inc_max_limit[5:3],1'b0}),
        .O(two_inc_min_limit_nxt[5:2]),
        .S({\two_inc_min_limit[5]_i_2_n_0 ,\two_inc_min_limit[5]_i_3_n_0 ,\two_inc_min_limit[5]_i_4_n_0 ,three_inc_max_limit[2]}));
  FDRE \two_inc_min_limit_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[6]),
        .Q(two_inc_min_limit[6]),
        .R(pi_f_dec_reg_1));
  FDRE \two_inc_min_limit_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[7]),
        .Q(two_inc_min_limit[7]),
        .R(pi_f_dec_reg_1));
  FDRE \two_inc_min_limit_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[8]),
        .Q(two_inc_min_limit[8]),
        .R(pi_f_dec_reg_1));
  FDRE \two_inc_min_limit_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[9]),
        .Q(two_inc_min_limit[9]),
        .R(pi_f_dec_reg_1));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \two_inc_min_limit_reg[9]_i_1 
       (.CI(\two_inc_min_limit_reg[5]_i_1_n_0 ),
        .CO({\two_inc_min_limit_reg[9]_i_1_n_0 ,\two_inc_min_limit_reg[9]_i_1_n_1 ,\two_inc_min_limit_reg[9]_i_1_n_2 ,\two_inc_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(three_inc_max_limit[9:6]),
        .O(two_inc_min_limit_nxt[9:6]),
        .S({\two_inc_min_limit[9]_i_2_n_0 ,\two_inc_min_limit[9]_i_3_n_0 ,\two_inc_min_limit[9]_i_4_n_0 ,\two_inc_min_limit[9]_i_5_n_0 }));
  LUT3 #(
    .INIT(8'h20)) 
    update_temp_101
       (.I0(tempmon_init_complete),
        .I1(tempmon_sample_en_102),
        .I2(tempmon_sample_en_101),
        .O(update_temp_101__0));
  FDRE update_temp_102_reg
       (.C(CLK),
        .CE(1'b1),
        .D(update_temp_101__0),
        .Q(update_temp_102),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_top
   (\rd_ptr_reg[0] ,
    \rd_ptr_reg[1] ,
    \rd_ptr_reg[2] ,
    \rd_ptr_reg[3] ,
    out,
    A_rst_primitives_reg,
    \rd_ptr_reg[0]_0 ,
    \rd_ptr_reg[1]_0 ,
    \rd_ptr_reg[2]_0 ,
    \rd_ptr_reg[3]_0 ,
    \rd_ptr_timing_reg[1] ,
    A_rst_primitives_reg_0,
    \rd_ptr_reg[0]_1 ,
    \rd_ptr_reg[1]_1 ,
    \rd_ptr_reg[2]_1 ,
    \rd_ptr_reg[3]_1 ,
    phy_mc_ctl_full,
    ref_dll_lock,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_reset_n,
    ddr3_dm,
    ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    po_cnt_dec_reg,
    po_cnt_dec_3,
    new_cnt_cpt_r_reg,
    rdlvl_stg1_start_reg,
    samp_edge_cnt0_en_r,
    pi_cnt_dec_reg,
    prbs_rdlvl_done_pulse_reg,
    init_calib_complete,
    init_calib_complete_reg_rep,
    init_calib_complete_reg_rep__0,
    init_calib_complete_reg_rep__1,
    init_calib_complete_reg_rep__2,
    init_calib_complete_reg_rep__9,
    init_complete_r1_timing_reg,
    phy_dout,
    init_calib_complete_reg_rep__0_0,
    \write_buffer.wr_buf_out_data_reg[122] ,
    app_rd_data_valid,
    \my_empty_reg[0] ,
    \my_empty_reg[0]_0 ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    app_rd_data,
    \init_state_r_reg[2] ,
    \wr_ptr_reg[3] ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_reg[3]_1 ,
    p_1_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    phy_mc_data_full,
    wr_en,
    wr_en_2,
    wr_en_3,
    phy_mc_cmd_full,
    ddr_ck_out,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    CLK,
    CLKB0,
    CLKB0_4,
    pll_locked,
    in0,
    RST0,
    SR,
    \smallest_reg[1][0] ,
    \rdlvl_dqs_tap_cnt_r_reg[0][1][4] ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[2] ,
    \samp_edge_cnt1_r_reg[0] ,
    init_calib_complete_reg,
    pi_f_dec_reg,
    mc_ref_zq_wip,
    \cnt_pwron_ce_r_reg[9] ,
    mem_out,
    mc_wrdata_en,
    \idelay_tap_cnt_r_reg[0][1][4] ,
    \my_full_reg[5] ,
    complex_row0_rd_done_reg,
    Q,
    app_rd_data_valid_0,
    \read_fifo.tail_r_reg ,
    dqs_po_stg2_f_incdec_reg,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    mc_cas_n,
    mc_ras_n,
    mc_odt,
    mc_cke,
    mc_we_n,
    \rd_ptr_reg[0]_2 ,
    \wr_ptr_timing_reg[2] ,
    \app_rd_data[112] ,
    SS,
    \wait_cnt_r_reg[0] ,
    \tap_cnt_cpt_r_reg[5] ,
    \cnt_shift_r_reg[0] ,
    \wait_cnt_r_reg[0]_0 ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[4] ,
    \device_temp_101_reg[11] ,
    mc_cmd,
    \phy_ctl_wd_i1_reg[17] ,
    \phy_ctl_wd_i1_reg[18] ,
    \phy_ctl_wd_i1_reg[19] ,
    mc_data_offset,
    \phy_ctl_wd_i1_reg[21] ,
    \phy_ctl_wd_i1_reg[22] ,
    mc_address,
    mc_bank,
    out_fifo,
    out_fifo_0,
    mc_cs_n);
  output \rd_ptr_reg[0] ;
  output \rd_ptr_reg[1] ;
  output \rd_ptr_reg[2] ;
  output \rd_ptr_reg[3] ;
  output [1:0]out;
  output A_rst_primitives_reg;
  output \rd_ptr_reg[0]_0 ;
  output \rd_ptr_reg[1]_0 ;
  output \rd_ptr_reg[2]_0 ;
  output \rd_ptr_reg[3]_0 ;
  output [1:0]\rd_ptr_timing_reg[1] ;
  output A_rst_primitives_reg_0;
  output \rd_ptr_reg[0]_1 ;
  output \rd_ptr_reg[1]_1 ;
  output \rd_ptr_reg[2]_1 ;
  output \rd_ptr_reg[3]_1 ;
  output phy_mc_ctl_full;
  output ref_dll_lock;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output ddr3_reset_n;
  output [1:0]ddr3_dm;
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output po_cnt_dec_reg;
  output po_cnt_dec_3;
  output new_cnt_cpt_r_reg;
  output rdlvl_stg1_start_reg;
  output samp_edge_cnt0_en_r;
  output pi_cnt_dec_reg;
  output prbs_rdlvl_done_pulse_reg;
  output init_calib_complete;
  output init_calib_complete_reg_rep;
  output init_calib_complete_reg_rep__0;
  output init_calib_complete_reg_rep__1;
  output init_calib_complete_reg_rep__2;
  output init_calib_complete_reg_rep__9;
  output init_complete_r1_timing_reg;
  output [32:0]phy_dout;
  output [59:0]init_calib_complete_reg_rep__0_0;
  output [59:0]\write_buffer.wr_buf_out_data_reg[122] ;
  output app_rd_data_valid;
  output \my_empty_reg[0] ;
  output \my_empty_reg[0]_0 ;
  output \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;
  output [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  output [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output [127:0]app_rd_data;
  output \init_state_r_reg[2] ;
  output [3:0]\wr_ptr_reg[3] ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1] ;
  output [3:0]\wr_ptr_reg[3]_0 ;
  output [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_0 ;
  output [3:0]\wr_ptr_reg[3]_1 ;
  output p_1_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output phy_mc_data_full;
  output wr_en;
  output wr_en_2;
  output wr_en_3;
  output phy_mc_cmd_full;
  output [1:0]ddr_ck_out;
  inout [15:0]ddr3_dq;
  inout [1:0]ddr3_dqs_p;
  inout [1:0]ddr3_dqs_n;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input CLK;
  input CLKB0;
  input CLKB0_4;
  input pll_locked;
  input in0;
  input RST0;
  input [0:0]SR;
  input [1:0]\smallest_reg[1][0] ;
  input [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][1][4] ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  input \samp_edge_cnt1_r_reg[0] ;
  input init_calib_complete_reg;
  input pi_f_dec_reg;
  input mc_ref_zq_wip;
  input [3:0]\cnt_pwron_ce_r_reg[9] ;
  input [47:0]mem_out;
  input mc_wrdata_en;
  input \idelay_tap_cnt_r_reg[0][1][4] ;
  input \my_full_reg[5] ;
  input complex_row0_rd_done_reg;
  input [143:0]Q;
  input [0:0]app_rd_data_valid_0;
  input [0:0]\read_fifo.tail_r_reg ;
  input dqs_po_stg2_f_incdec_reg;
  input [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input [2:0]mc_cas_n;
  input [2:0]mc_ras_n;
  input [0:0]mc_odt;
  input [0:0]mc_cke;
  input [2:0]mc_we_n;
  input \rd_ptr_reg[0]_2 ;
  input [0:0]\wr_ptr_timing_reg[2] ;
  input [63:0]\app_rd_data[112] ;
  input [0:0]SS;
  input [0:0]\wait_cnt_r_reg[0] ;
  input [0:0]\tap_cnt_cpt_r_reg[5] ;
  input [0:0]\cnt_shift_r_reg[0] ;
  input [0:0]\wait_cnt_r_reg[0]_0 ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  input [11:0]\device_temp_101_reg[11] ;
  input [1:0]mc_cmd;
  input \phy_ctl_wd_i1_reg[17] ;
  input \phy_ctl_wd_i1_reg[18] ;
  input \phy_ctl_wd_i1_reg[19] ;
  input [0:0]mc_data_offset;
  input \phy_ctl_wd_i1_reg[21] ;
  input \phy_ctl_wd_i1_reg[22] ;
  input [38:0]mc_address;
  input [8:0]mc_bank;
  input [71:0]out_fifo;
  input [71:0]out_fifo_0;
  input [0:0]mc_cs_n;

  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire CLK;
  wire CLKB0;
  wire CLKB0_4;
  wire [143:0]Q;
  wire RST0;
  wire [0:0]SR;
  wire [0:0]SS;
  wire [127:0]app_rd_data;
  wire [63:0]\app_rd_data[112] ;
  wire app_rd_data_valid;
  wire [0:0]app_rd_data_valid_0;
  wire calib_cmd_wren;
  wire calib_in_common;
  wire calib_in_common4_out;
  wire [1:0]calib_sel;
  wire calib_wrdata_en;
  wire [3:0]\cnt_pwron_ce_r_reg[9] ;
  wire [0:0]\cnt_shift_r_reg[0] ;
  wire complex_row0_rd_done_reg;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [1:0]ddr3_dm;
  wire [15:0]ddr3_dq;
  wire [1:0]ddr3_dqs_n;
  wire [1:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire [11:0]\device_temp_101_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire dqs_po_dec_done;
  wire dqs_po_stg2_f_incdec_reg;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  wire freq_refclk;
  wire \gen_byte_sel_div2.calib_in_common_i_1_n_0 ;
  wire [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire \genblk24.phy_ctl_pre_fifo_0/wr_en ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire \genblk24.phy_ctl_pre_fifo_1/wr_en ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire \genblk24.phy_ctl_pre_fifo_2/wr_en ;
  wire idelay_inc;
  wire \idelay_tap_cnt_r_reg[0][1][4] ;
  wire in0;
  wire init_calib_complete;
  wire init_calib_complete_reg;
  wire init_calib_complete_reg_rep;
  wire init_calib_complete_reg_rep__0;
  wire [59:0]init_calib_complete_reg_rep__0_0;
  wire init_calib_complete_reg_rep__1;
  wire init_calib_complete_reg_rep__2;
  wire init_calib_complete_reg_rep__9;
  wire init_complete_r1_timing_reg;
  wire \init_state_r_reg[2] ;
  wire [38:0]mc_address;
  wire [8:0]mc_bank;
  wire [2:0]mc_cas_n;
  wire [0:0]mc_cke;
  wire [1:0]mc_cmd;
  wire [0:0]mc_cs_n;
  wire [0:0]mc_data_offset;
  wire [0:0]mc_odt;
  wire [2:0]mc_ras_n;
  wire mc_ref_zq_wip;
  wire [2:0]mc_we_n;
  wire mc_wrdata_en;
  wire [47:0]mem_out;
  wire mem_refclk;
  wire [41:1]mux_address;
  wire mux_cmd_wren;
  wire [0:0]mux_odt;
  wire mux_reset_n;
  wire mux_wrdata_en;
  wire \my_empty_reg[0] ;
  wire \my_empty_reg[0]_0 ;
  wire \my_full_reg[5] ;
  wire new_cnt_cpt_r_reg;
  wire [1:0]out;
  wire [71:0]out_fifo;
  wire [71:0]out_fifo_0;
  wire p_1_in;
  wire [24:0]p_1_out;
  wire \phy_ctl_wd_i1_reg[17] ;
  wire \phy_ctl_wd_i1_reg[18] ;
  wire \phy_ctl_wd_i1_reg[19] ;
  wire \phy_ctl_wd_i1_reg[21] ;
  wire \phy_ctl_wd_i1_reg[22] ;
  wire [32:0]phy_dout;
  wire phy_mc_cmd_full;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire phy_mc_go;
  wire phy_rddata_en;
  wire phy_read_calib;
  wire phy_write_calib;
  wire pi_cnt_dec_reg;
  wire pi_f_dec_reg;
  wire pi_fine_dly_dec_done;
  wire pll_locked;
  wire po_cnt_dec_3;
  wire po_cnt_dec_reg;
  wire [0:0]po_stg2_wrcal_cnt;
  wire prbs_rdlvl_done_pulse_reg;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;
  wire [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  wire \rd_ptr_reg[0] ;
  wire \rd_ptr_reg[0]_0 ;
  wire \rd_ptr_reg[0]_1 ;
  wire \rd_ptr_reg[0]_2 ;
  wire \rd_ptr_reg[1] ;
  wire \rd_ptr_reg[1]_0 ;
  wire \rd_ptr_reg[1]_1 ;
  wire \rd_ptr_reg[2] ;
  wire \rd_ptr_reg[2]_0 ;
  wire \rd_ptr_reg[2]_1 ;
  wire \rd_ptr_reg[3] ;
  wire \rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg[3]_1 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][1][4] ;
  wire rdlvl_stg1_start_reg;
  wire [0:0]\read_fifo.tail_r_reg ;
  wire ref_dll_lock;
  wire samp_edge_cnt0_en_r;
  wire \samp_edge_cnt1_r_reg[0] ;
  wire [1:0]\smallest_reg[1][0] ;
  wire sync_pulse;
  wire [0:0]\tap_cnt_cpt_r_reg[5] ;
  wire tempmon_pi_f_dec;
  wire tempmon_pi_f_inc;
  wire tempmon_sel_pi_incdec;
  wire u_ddr_calib_top_n_10;
  wire u_ddr_calib_top_n_130;
  wire u_ddr_calib_top_n_19;
  wire u_ddr_calib_top_n_23;
  wire u_ddr_calib_top_n_251;
  wire u_ddr_calib_top_n_253;
  wire u_ddr_calib_top_n_255;
  wire u_ddr_calib_top_n_27;
  wire u_ddr_calib_top_n_3;
  wire u_ddr_calib_top_n_32;
  wire u_ddr_calib_top_n_36;
  wire u_ddr_calib_top_n_40;
  wire u_ddr_calib_top_n_479;
  wire u_ddr_calib_top_n_48;
  wire u_ddr_calib_top_n_54;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire u_ddr_calib_top_n_64;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire u_ddr_calib_top_n_65;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire u_ddr_calib_top_n_66;
  wire u_ddr_calib_top_n_68;
  wire u_ddr_calib_top_n_69;
  wire u_ddr_calib_top_n_70;
  wire u_ddr_calib_top_n_73;
  wire u_ddr_calib_top_n_74;
  wire u_ddr_calib_top_n_75;
  wire u_ddr_calib_top_n_76;
  wire u_ddr_calib_top_n_77;
  wire u_ddr_calib_top_n_78;
  wire u_ddr_calib_top_n_79;
  wire u_ddr_calib_top_n_80;
  wire u_ddr_calib_top_n_81;
  wire u_ddr_calib_top_n_82;
  wire u_ddr_calib_top_n_83;
  wire u_ddr_calib_top_n_84;
  wire u_ddr_calib_top_n_85;
  wire u_ddr_calib_top_n_86;
  wire u_ddr_calib_top_n_87;
  wire u_ddr_calib_top_n_88;
  wire u_ddr_calib_top_n_89;
  wire u_ddr_calib_top_n_9;
  wire u_ddr_calib_top_n_90;
  wire u_ddr_calib_top_n_91;
  wire u_ddr_calib_top_n_92;
  wire u_ddr_calib_top_n_93;
  wire u_ddr_calib_top_n_94;
  wire u_ddr_calib_top_n_95;
  wire u_ddr_calib_top_n_96;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_rst_primitives ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ;
  wire [75:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d8 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d0 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ;
  wire [2:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ;
  wire [6:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ;
  wire [2:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ;
  wire [4:4]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_rst_reg0 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d0 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst_reg0 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_rst_reg0 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ofifo_rst_reg0 ;
  wire [5:0]\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ;
  wire [8:0]\u_ddr_mc_phy/po_counter_read_val_w[0]_0 ;
  wire u_ddr_mc_phy_wrapper_n_327;
  wire u_ddr_mc_phy_wrapper_n_335;
  wire u_ddr_mc_phy_wrapper_n_467;
  wire u_ddr_mc_phy_wrapper_n_52;
  wire u_ddr_mc_phy_wrapper_n_53;
  wire u_ddr_mc_phy_wrapper_n_56;
  wire u_ddr_mc_phy_wrapper_n_57;
  wire u_ddr_mc_phy_wrapper_n_58;
  wire u_ddr_mc_phy_wrapper_n_59;
  wire u_ddr_mc_phy_wrapper_n_60;
  wire u_ddr_mc_phy_wrapper_n_61;
  wire u_ddr_mc_phy_wrapper_n_62;
  wire u_ddr_mc_phy_wrapper_n_63;
  wire u_ddr_mc_phy_wrapper_n_8;
  wire u_ddr_mc_phy_wrapper_n_9;
  wire \u_ddr_phy_init/prbs_rdlvl_done_pulse0 ;
  wire \u_ddr_phy_init/rdlvl_stg1_done_r1 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire [0:0]\wait_cnt_r_reg[0] ;
  wire [0:0]\wait_cnt_r_reg[0]_0 ;
  wire wr_en;
  wire wr_en_2;
  wire wr_en_3;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire [3:0]\wr_ptr_reg[3] ;
  wire [3:0]\wr_ptr_reg[3]_0 ;
  wire [3:0]\wr_ptr_reg[3]_1 ;
  wire [0:0]\wr_ptr_timing_reg[2] ;
  wire \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_1_n_0 ;
  wire [59:0]\write_buffer.wr_buf_out_data_reg[122] ;

  LUT5 #(
    .INIT(32'hBFFF8FFF)) 
    \gen_byte_sel_div2.calib_in_common_i_1 
       (.I0(calib_in_common4_out),
        .I1(u_ddr_calib_top_n_479),
        .I2(pi_fine_dly_dec_done),
        .I3(dqs_po_dec_done),
        .I4(calib_in_common),
        .O(\gen_byte_sel_div2.calib_in_common_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair558" *) 
  LUT2 #(
    .INIT(4'h2)) 
    prbs_rdlvl_done_pulse_i_1
       (.I0(u_ddr_calib_top_n_9),
        .I1(\u_ddr_phy_init/rdlvl_stg1_done_r1 ),
        .O(\u_ddr_phy_init/prbs_rdlvl_done_pulse0 ));
  LUT2 #(
    .INIT(4'hE)) 
    tempmon_pi_f_en_r_i_1
       (.I0(tempmon_pi_f_inc),
        .I1(tempmon_pi_f_dec),
        .O(tempmon_sel_pi_incdec));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_calib_top u_ddr_calib_top
       (.A_rst_primitives(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_rst_primitives ),
        .CLK(CLK),
        .COUNTERLOADVAL(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ),
        .D({p_1_out[24:17],p_1_out[2:0]}),
        .D0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d0 ),
        .D1(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),
        .D2(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),
        .D3(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),
        .D4(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .D5(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),
        .D6(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),
        .D7(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),
        .D8(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .D9(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),
        .E(u_ddr_calib_top_n_251),
        .LD0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ),
        .LD0_0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ),
        .Q(phy_mc_go),
        .SR(SR),
        .SS(SS),
        .app_rd_data({app_rd_data[15:13],app_rd_data[11:5],app_rd_data[3:0]}),
        .calib_cmd_wren(calib_cmd_wren),
        .calib_ctl_wren_reg(u_ddr_calib_top_n_69),
        .calib_in_common(calib_in_common),
        .calib_in_common4_out(calib_in_common4_out),
        .calib_sel(calib_sel),
        .\calib_sel_reg[0]_0 (u_ddr_calib_top_n_90),
        .\calib_sel_reg[1]_0 (u_ddr_calib_top_n_78),
        .\calib_sel_reg[1]_1 (u_ddr_calib_top_n_79),
        .\calib_sel_reg[1]_2 (u_ddr_calib_top_n_80),
        .\calib_sel_reg[1]_3 (u_ddr_calib_top_n_81),
        .\calib_sel_reg[1]_4 (u_ddr_calib_top_n_82),
        .\calib_sel_reg[1]_5 (u_ddr_calib_top_n_83),
        .\calib_sel_reg[1]_6 (u_ddr_calib_top_n_84),
        .\calib_sel_reg[1]_7 (u_ddr_calib_top_n_85),
        .\calib_sel_reg[1]_8 (u_ddr_calib_top_n_86),
        .\calib_sel_reg[1]_9 (u_ddr_calib_top_n_87),
        .calib_wrdata_en(calib_wrdata_en),
        .ck_po_stg2_f_indec_reg(u_ddr_calib_top_n_92),
        .\cmd_pipe_plus.mc_cas_n_reg[2] ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 [6:4],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 [2:0]}),
        .\cmd_pipe_plus.mc_cke_reg[3] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),
        .\cmd_pipe_plus.mc_odt_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),
        .\cmd_pipe_plus.mc_ras_n_reg[2] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),
        .\cmd_pipe_plus.mc_we_n_reg[2] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),
        .\cnt_pwron_ce_r_reg[9] (\cnt_pwron_ce_r_reg[9] ),
        .\cnt_shift_r_reg[0] (\cnt_shift_r_reg[0] ),
        .complex_row0_rd_done_reg(complex_row0_rd_done_reg),
        .\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_66_71 (Q),
        .\device_temp_101_reg[11] (\device_temp_101_reg[11] ),
        .dqs_found_done_r_reg(u_ddr_calib_top_n_479),
        .dqs_po_dec_done(dqs_po_dec_done),
        .dqs_po_stg2_f_incdec_reg(dqs_po_stg2_f_incdec_reg),
        .dqs_wl_po_stg2_c_incdec_reg(u_ddr_calib_top_n_77),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[2] (\en_cnt_div4.enable_wrlvl_cnt_reg[2] ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[4] (\en_cnt_div4.enable_wrlvl_cnt_reg[4] ),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (u_ddr_calib_top_n_70),
        .\gen_byte_sel_div2.calib_in_common_reg_1 (u_ddr_calib_top_n_73),
        .\gen_byte_sel_div2.calib_in_common_reg_2 (u_ddr_calib_top_n_74),
        .\gen_byte_sel_div2.calib_in_common_reg_3 (u_ddr_calib_top_n_75),
        .\gen_byte_sel_div2.calib_in_common_reg_4 (u_ddr_calib_top_n_76),
        .\gen_byte_sel_div2.calib_in_common_reg_5 (u_ddr_calib_top_n_89),
        .\gen_byte_sel_div2.calib_in_common_reg_6 (u_ddr_calib_top_n_91),
        .\gen_byte_sel_div2.calib_in_common_reg_7 (u_ddr_calib_top_n_130),
        .\gen_byte_sel_div2.calib_in_common_reg_8 (\gen_byte_sel_div2.calib_in_common_i_1_n_0 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (phy_dout),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[12] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[1] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[2] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[3] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[4] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[5] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d8 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[6] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[7] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[8] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),
        .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ),
        .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ),
        .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d0 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 [0]),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 (\app_rd_data[112] [0]),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] [10]),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] [8]),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 (u_ddr_mc_phy_wrapper_n_467),
        .idelay_ce_r2_reg_0(u_ddr_calib_top_n_88),
        .idelay_inc(idelay_inc),
        .idelay_ld_reg(\rd_ptr_reg[0]_2 ),
        .idelay_ld_rst(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),
        .\idelay_tap_cnt_r_reg[0][1][4] (\idelay_tap_cnt_r_reg[0][1][4] ),
        .ififo_rst_reg0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_rst_reg0 ),
        .ififo_rst_reg0_1(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_rst_reg0 ),
        .in0(in0),
        .init_calib_complete_reg_0(init_calib_complete_reg),
        .init_calib_complete_reg_rep_0(init_calib_complete_reg_rep),
        .init_calib_complete_reg_rep__0_0(init_calib_complete_reg_rep__0),
        .init_calib_complete_reg_rep__0_1(init_calib_complete_reg_rep__0_0),
        .init_calib_complete_reg_rep__1_0(init_calib_complete_reg_rep__1),
        .init_calib_complete_reg_rep__2_0(init_calib_complete_reg_rep__2),
        .init_calib_complete_reg_rep__4_0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),
        .init_calib_complete_reg_rep__5_0(u_ddr_calib_top_n_64),
        .init_calib_complete_reg_rep__7_0(u_ddr_calib_top_n_65),
        .init_calib_complete_reg_rep__8_0(u_ddr_calib_top_n_66),
        .init_calib_complete_reg_rep__9_0(init_calib_complete_reg_rep__9),
        .\init_state_r_reg[2] (\init_state_r_reg[2] ),
        .mc_address(mc_address),
        .mc_bank(mc_bank),
        .mc_cas_n(mc_cas_n),
        .mc_cke(mc_cke),
        .mc_cmd(mc_cmd),
        .mc_cs_n(mc_cs_n),
        .mc_data_offset(mc_data_offset),
        .mc_odt(mc_odt),
        .mc_ras_n(mc_ras_n),
        .mc_ref_zq_wip(mc_ref_zq_wip),
        .mc_we_n(mc_we_n),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_out({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [75:72],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [67:64],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [59:48],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [43:40],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [35:32],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [19:16],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [3:0]}),
        .mux_cmd_wren(mux_cmd_wren),
        .mux_reset_n(mux_reset_n),
        .mux_wrdata_en(mux_wrdata_en),
        .my_empty(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .\my_empty_reg[3] (\genblk24.phy_ctl_pre_fifo_0/wr_en ),
        .\my_empty_reg[3]_0 (\genblk24.phy_ctl_pre_fifo_1/wr_en ),
        .\my_empty_reg[3]_1 (\genblk24.phy_ctl_pre_fifo_2/wr_en ),
        .\my_empty_reg[5] (u_ddr_calib_top_n_253),
        .\my_empty_reg[5]_0 (u_ddr_calib_top_n_255),
        .new_cnt_cpt_r_reg(new_cnt_cpt_r_reg),
        .ofifo_rst_reg0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst_reg0 ),
        .ofifo_rst_reg0_2(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ofifo_rst_reg0 ),
        .out(u_ddr_calib_top_n_10),
        .out_fifo(out_fifo),
        .out_fifo_0(u_ddr_mc_phy_wrapper_n_56),
        .out_fifo_1(out_fifo_0),
        .out_fifo_2(u_ddr_mc_phy_wrapper_n_57),
        .out_fifo_3(u_ddr_mc_phy_wrapper_n_52),
        .out_fifo_4({mem_out[47:40],mem_out[38:36],mem_out[34:32],mem_out[30:12],mem_out[10:0]}),
        .out_fifo_5(u_ddr_mc_phy_wrapper_n_53),
        .\phy_ctl_wd_i1_reg[17] (\phy_ctl_wd_i1_reg[17] ),
        .\phy_ctl_wd_i1_reg[18] (\phy_ctl_wd_i1_reg[18] ),
        .\phy_ctl_wd_i1_reg[19] (\phy_ctl_wd_i1_reg[19] ),
        .\phy_ctl_wd_i1_reg[21] (\phy_ctl_wd_i1_reg[21] ),
        .\phy_ctl_wd_i1_reg[22] (\phy_ctl_wd_i1_reg[22] ),
        .phy_dout({u_ddr_calib_top_n_19,mux_address[32],mux_address[18],mux_address[4],u_ddr_calib_top_n_23,mux_address[33],mux_address[19],mux_address[5],u_ddr_calib_top_n_27,mux_address[35],mux_address[21],mux_address[7],mux_odt,u_ddr_calib_top_n_32,mux_address[37],mux_address[23],mux_address[9],u_ddr_calib_top_n_36,mux_address[34],mux_address[20],mux_address[6],u_ddr_calib_top_n_40,mux_address[29],mux_address[15],mux_address[1],init_calib_complete,mux_address[41],mux_address[27],mux_address[13],u_ddr_calib_top_n_48,mux_address[36],mux_address[22],mux_address[8],mux_address[39],mux_address[11],u_ddr_calib_top_n_54,mux_address[30],mux_address[16],mux_address[2]}),
        .phy_rddata_en(phy_rddata_en),
        .phy_read_calib(phy_read_calib),
        .phy_write_calib(phy_write_calib),
        .pi_cnt_dec_reg(pi_cnt_dec_reg),
        .pi_dqs_found_lanes({u_ddr_mc_phy_wrapper_n_8,u_ddr_mc_phy_wrapper_n_9}),
        .pi_en_stg2_f_reg(u_ddr_calib_top_n_94),
        .pi_f_dec_reg(pi_f_dec_reg),
        .pi_fine_dly_dec_done(pi_fine_dly_dec_done),
        .pi_phase_locked_all_r1_reg(u_ddr_mc_phy_wrapper_n_335),
        .\pi_rdval_cnt_reg[5] (\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ),
        .\pi_rst_stg1_cal_reg[0] (u_ddr_calib_top_n_93),
        .pi_stg2_f_incdec_reg(u_ddr_calib_top_n_95),
        .pi_stg2_load_reg(u_ddr_calib_top_n_96),
        .\pi_stg2_reg_l_reg[5] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ),
        .po_cnt_dec_3(po_cnt_dec_3),
        .po_cnt_dec_reg(po_cnt_dec_reg),
        .\po_rdval_cnt_reg[8] (\u_ddr_mc_phy/po_counter_read_val_w[0]_0 ),
        .\po_stg2_wrcal_cnt_reg[0] (po_stg2_wrcal_cnt),
        .prbs_rdlvl_done_pulse0(\u_ddr_phy_init/prbs_rdlvl_done_pulse0 ),
        .prbs_rdlvl_done_pulse_reg(prbs_rdlvl_done_pulse_reg),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] (\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] (\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ),
        .\rd_mux_sel_r_reg[0] (u_ddr_calib_top_n_3),
        .\rdlvl_dqs_tap_cnt_r_reg[0][1][4] (\rdlvl_dqs_tap_cnt_r_reg[0][1][4] ),
        .rdlvl_stg1_done_int_reg(u_ddr_calib_top_n_9),
        .rdlvl_stg1_done_r1(\u_ddr_phy_init/rdlvl_stg1_done_r1 ),
        .rdlvl_stg1_start_reg(rdlvl_stg1_start_reg),
        .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),
        .\samp_edge_cnt1_r_reg[0] (\samp_edge_cnt1_r_reg[0] ),
        .\smallest_reg[1][0] (\smallest_reg[1][0] ),
        .store_sr_req_r_reg(u_ddr_mc_phy_wrapper_n_327),
        .\tap_cnt_cpt_r_reg[5] (\tap_cnt_cpt_r_reg[5] ),
        .tempmon_pi_f_dec(tempmon_pi_f_dec),
        .tempmon_pi_f_inc(tempmon_pi_f_inc),
        .tempmon_sel_pi_incdec(tempmon_sel_pi_incdec),
        .\wait_cnt_r_reg[0] (\wait_cnt_r_reg[0] ),
        .\wait_cnt_r_reg[0]_0 (\wait_cnt_r_reg[0]_0 ),
        .wr_en_inferred__0_i_1(u_ddr_mc_phy_wrapper_n_59),
        .wr_en_inferred__0_i_1__0(u_ddr_mc_phy_wrapper_n_61),
        .wr_en_inferred__0_i_1__1(u_ddr_mc_phy_wrapper_n_63),
        .\wr_ptr_timing_reg[0] (u_ddr_mc_phy_wrapper_n_58),
        .\wr_ptr_timing_reg[0]_0 (u_ddr_mc_phy_wrapper_n_60),
        .\wr_ptr_timing_reg[0]_1 (u_ddr_mc_phy_wrapper_n_62),
        .wrcal_done_reg(u_ddr_calib_top_n_68),
        .wrcal_done_reg_0(\my_full_reg[5] ),
        .wrcal_sanity_chk_done_reg(\wr_ptr_timing_reg[2] ),
        .\wrdq_div2_4to1_rdlvl_first.phy_wrdata_reg[126] (\wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_1_n_0 ),
        .\write_buffer.wr_buf_out_data_reg[121] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),
        .\write_buffer.wr_buf_out_data_reg[122] (\write_buffer.wr_buf_out_data_reg[122] ),
        .\write_buffer.wr_buf_out_data_reg[122]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9 ),
        .\write_buffer.wr_buf_out_data_reg[123] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),
        .\write_buffer.wr_buf_out_data_reg[124] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),
        .\write_buffer.wr_buf_out_data_reg[125] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),
        .\write_buffer.wr_buf_out_data_reg[126] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),
        .\write_buffer.wr_buf_out_data_reg[127] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_mc_phy_wrapper u_ddr_mc_phy_wrapper
       (.A_rst_primitives(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_rst_primitives ),
        .A_rst_primitives_reg(A_rst_primitives_reg),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_1(u_ddr_mc_phy_wrapper_n_335),
        .CLK(CLK),
        .CLKB0(CLKB0),
        .CLKB0_4(CLKB0_4),
        .COUNTERLOADVAL(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ),
        .D({p_1_out[24:17],p_1_out[2:0]}),
        .D0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d0 ),
        .D1(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),
        .D2(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),
        .D3(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),
        .D4(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .D5(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),
        .D6(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),
        .D7(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),
        .D8(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .D9(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),
        .E(u_ddr_calib_top_n_251),
        .LD0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ),
        .LD0_0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ),
        .Q(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .RST0(RST0),
        .SR(SR),
        .UNCONN_IN(\genblk24.phy_ctl_pre_fifo_0/wr_en ),
        .UNCONN_IN_0(\genblk24.phy_ctl_pre_fifo_1/wr_en ),
        .UNCONN_IN_1(\genblk24.phy_ctl_pre_fifo_2/wr_en ),
        .app_rd_data(app_rd_data),
        .\app_rd_data[112] (\app_rd_data[112] ),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rd_data_valid_0(u_ddr_calib_top_n_10),
        .app_rd_data_valid_1(app_rd_data_valid_0),
        .calib_cmd_wren(calib_cmd_wren),
        .calib_sel(calib_sel),
        .calib_wrdata_en(calib_wrdata_en),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out(ddr_ck_out),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (u_ddr_calib_top_n_3),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (po_stg2_wrcal_cnt),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 (\u_ddr_phy_wrcal/gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),
        .ififo_rst_reg0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_rst_reg0 ),
        .ififo_rst_reg0_1(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_rst_reg0 ),
        .in0(in0),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .\input_[9].iserdes_dq_.iserdesdq (u_ddr_calib_top_n_81),
        .\input_[9].iserdes_dq_.iserdesdq_0 (u_ddr_calib_top_n_88),
        .\mcGo_r_reg[15] (phy_mc_go),
        .mc_address({mc_address[38],mc_address[36],mc_address[13],mc_address[11]}),
        .mc_cas_n(mc_cas_n[1]),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_out({mem_out[39],mem_out[35],mem_out[31],mem_out[11]}),
        .mem_refclk(mem_refclk),
        .mux_cmd_wren(mux_cmd_wren),
        .mux_reset_n(mux_reset_n),
        .mux_wrdata_en(mux_wrdata_en),
        .\my_empty_reg[0] (\my_empty_reg[0] ),
        .\my_empty_reg[0]_0 (\my_empty_reg[0]_0 ),
        .\my_empty_reg[1] (u_ddr_mc_phy_wrapper_n_52),
        .\my_empty_reg[1]_0 (u_ddr_mc_phy_wrapper_n_53),
        .\my_empty_reg[1]_1 (u_ddr_mc_phy_wrapper_n_56),
        .\my_empty_reg[1]_2 (u_ddr_mc_phy_wrapper_n_57),
        .\my_empty_reg[3] (u_ddr_mc_phy_wrapper_n_59),
        .\my_empty_reg[3]_0 (u_ddr_mc_phy_wrapper_n_61),
        .\my_empty_reg[3]_1 (u_ddr_mc_phy_wrapper_n_63),
        .\my_empty_reg[4] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .\my_empty_reg[4]_rep__0 (u_ddr_mc_phy_wrapper_n_467),
        .\my_empty_reg[5] (u_ddr_mc_phy_wrapper_n_58),
        .\my_empty_reg[5]_0 (u_ddr_mc_phy_wrapper_n_60),
        .\my_empty_reg[5]_1 (u_ddr_mc_phy_wrapper_n_62),
        .\my_empty_reg[7] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),
        .\my_empty_reg[7]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),
        .\my_empty_reg[7]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),
        .\my_empty_reg[7]_10 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),
        .\my_empty_reg[7]_11 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),
        .\my_empty_reg[7]_12 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),
        .\my_empty_reg[7]_13 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d8 ),
        .\my_empty_reg[7]_14 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ),
        .\my_empty_reg[7]_2 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),
        .\my_empty_reg[7]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),
        .\my_empty_reg[7]_4 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),
        .\my_empty_reg[7]_5 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),
        .\my_empty_reg[7]_6 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9 ),
        .\my_empty_reg[7]_7 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d0 ),
        .\my_empty_reg[7]_8 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),
        .\my_empty_reg[7]_9 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),
        .\my_full_reg[5] (\my_full_reg[5] ),
        .ofifo_rst_reg0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst_reg0 ),
        .ofifo_rst_reg0_2(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ofifo_rst_reg0 ),
        .out(out),
        .out_fifo(u_ddr_calib_top_n_64),
        .p_1_in(p_1_in),
        .phy_ctl_wr_i1_reg_0(u_ddr_calib_top_n_69),
        .phy_dout({u_ddr_calib_top_n_19,mux_address[32],mux_address[18],mux_address[4],u_ddr_calib_top_n_23,mux_address[33],mux_address[19],mux_address[5],u_ddr_calib_top_n_27,mux_address[35],mux_address[21],mux_address[7],mux_odt,u_ddr_calib_top_n_32,mux_address[37],mux_address[23],mux_address[9],u_ddr_calib_top_n_36,mux_address[34],mux_address[20],mux_address[6],u_ddr_calib_top_n_40,mux_address[29],mux_address[15],mux_address[1],init_calib_complete,mux_address[41],mux_address[27],mux_address[13],u_ddr_calib_top_n_48,mux_address[36],mux_address[22],mux_address[8],mux_address[39],mux_address[11],u_ddr_calib_top_n_54,mux_address[30],mux_address[16],mux_address[2]}),
        .phy_mc_cmd_full(phy_mc_cmd_full),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .phy_rddata_en(phy_rddata_en),
        .phy_read_calib(phy_read_calib),
        .phy_write_calib(phy_write_calib),
        .\pi_counter_read_val_reg[5] (u_ddr_mc_phy_wrapper_n_327),
        .\pi_counter_read_val_reg[5]_0 (\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ),
        .pi_dqs_found_lanes({u_ddr_mc_phy_wrapper_n_8,u_ddr_mc_phy_wrapper_n_9}),
        .\pi_dqs_found_lanes_r1_reg[2] (u_ddr_calib_top_n_87),
        .\pi_dqs_found_lanes_r1_reg[2]_0 (u_ddr_calib_top_n_80),
        .\pi_dqs_found_lanes_r1_reg[2]_1 (u_ddr_calib_top_n_85),
        .\pi_dqs_found_lanes_r1_reg[2]_2 (u_ddr_calib_top_n_86),
        .\pi_dqs_found_lanes_r1_reg[2]_3 (u_ddr_calib_top_n_84),
        .\pi_dqs_found_lanes_r1_reg[3] (u_ddr_calib_top_n_96),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (u_ddr_calib_top_n_78),
        .\pi_dqs_found_lanes_r1_reg[3]_1 (u_ddr_calib_top_n_94),
        .\pi_dqs_found_lanes_r1_reg[3]_2 (u_ddr_calib_top_n_95),
        .\pi_dqs_found_lanes_r1_reg[3]_3 (u_ddr_calib_top_n_93),
        .\pi_dqs_found_lanes_r1_reg[3]_4 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ),
        .pll_locked(pll_locked),
        .\po_counter_read_val_reg[8] (\u_ddr_mc_phy/po_counter_read_val_w[0]_0 ),
        .\po_counter_read_val_reg[8]_0 (u_ddr_calib_top_n_76),
        .\po_counter_read_val_reg[8]_1 (u_ddr_calib_top_n_130),
        .\po_counter_read_val_reg[8]_10 (u_ddr_calib_top_n_74),
        .\po_counter_read_val_reg[8]_11 (u_ddr_calib_top_n_70),
        .\po_counter_read_val_reg[8]_12 (u_ddr_calib_top_n_75),
        .\po_counter_read_val_reg[8]_13 (u_ddr_calib_top_n_73),
        .\po_counter_read_val_reg[8]_2 (u_ddr_calib_top_n_89),
        .\po_counter_read_val_reg[8]_3 (u_ddr_calib_top_n_91),
        .\po_counter_read_val_reg[8]_4 (u_ddr_calib_top_n_79),
        .\po_counter_read_val_reg[8]_5 (u_ddr_calib_top_n_82),
        .\po_counter_read_val_reg[8]_6 (u_ddr_calib_top_n_83),
        .\po_counter_read_val_reg[8]_7 (u_ddr_calib_top_n_77),
        .\po_counter_read_val_reg[8]_8 (u_ddr_calib_top_n_90),
        .\po_counter_read_val_reg[8]_9 (u_ddr_calib_top_n_92),
        .\rd_ptr_reg[0] (\rd_ptr_reg[0] ),
        .\rd_ptr_reg[0]_0 (\rd_ptr_reg[0]_0 ),
        .\rd_ptr_reg[0]_1 (\rd_ptr_reg[0]_1 ),
        .\rd_ptr_reg[0]_2 (\rd_ptr_reg[0]_2 ),
        .\rd_ptr_reg[1] (\rd_ptr_reg[1] ),
        .\rd_ptr_reg[1]_0 (\rd_ptr_reg[1]_0 ),
        .\rd_ptr_reg[1]_1 (\rd_ptr_reg[1]_1 ),
        .\rd_ptr_reg[2] (\rd_ptr_reg[2] ),
        .\rd_ptr_reg[2]_0 (\rd_ptr_reg[2]_0 ),
        .\rd_ptr_reg[2]_1 (\rd_ptr_reg[2]_1 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3] ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ),
        .\rd_ptr_reg[3]_1 (\rd_ptr_reg[3]_1 ),
        .\rd_ptr_reg[3]_10 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),
        .\rd_ptr_reg[3]_11 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ),
        .\rd_ptr_reg[3]_12 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ),
        .\rd_ptr_reg[3]_2 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [75:72],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [67:64],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [59:48],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [43:40],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [35:32],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [19:16],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_out [3:0]}),
        .\rd_ptr_reg[3]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d0 ),
        .\rd_ptr_reg[3]_4 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d1 ),
        .\rd_ptr_reg[3]_5 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),
        .\rd_ptr_reg[3]_6 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),
        .\rd_ptr_reg[3]_7 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),
        .\rd_ptr_reg[3]_8 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),
        .\rd_ptr_reg[3]_9 ({\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 [6:4],\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 [2:0]}),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .\read_fifo.tail_r_reg (\read_fifo.tail_r_reg ),
        .ref_dll_lock(ref_dll_lock),
        .sync_pulse(sync_pulse),
        .wr_en(wr_en),
        .wr_en_2(wr_en_2),
        .wr_en_3(wr_en_3),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0]_0 ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_reg[3] (\wr_ptr_reg[3] ),
        .\wr_ptr_reg[3]_0 (\wr_ptr_reg[3]_0 ),
        .\wr_ptr_reg[3]_1 (\wr_ptr_reg[3]_1 ),
        .\wr_ptr_timing_reg[0] (init_calib_complete_reg_rep__9),
        .\wr_ptr_timing_reg[0]_0 (u_ddr_calib_top_n_66),
        .\wr_ptr_timing_reg[0]_1 (u_ddr_calib_top_n_65),
        .\wr_ptr_timing_reg[0]_2 (u_ddr_calib_top_n_253),
        .\wr_ptr_timing_reg[0]_3 (u_ddr_calib_top_n_255),
        .\wr_ptr_timing_reg[2] (\wr_ptr_timing_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair558" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_1 
       (.I0(u_ddr_calib_top_n_9),
        .I1(u_ddr_calib_top_n_68),
        .O(\wrdq_div2_4to1_rdlvl_first.phy_wrdata[126]_i_1_n_0 ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_wrcal
   (wrcal_resume_w,
    E,
    wrcal_prech_req,
    wrcal_done_reg_0,
    wrcal_sanity_chk_done_reg_0,
    wrlvl_byte_redo,
    early1_data_reg_0,
    phy_if_reset_w,
    done_dqs_dec237_out,
    early2_data_reg_0,
    Q,
    \po_stg2_wrcal_cnt_reg[0]_0 ,
    cal1_dq_idel_ce_reg,
    wrcal_sanity_chk_done_reg_1,
    wrcal_done_reg_1,
    wrlvl_byte_redo_reg_0,
    wrlvl_byte_redo_reg_1,
    rdlvl_stg1_done_int_reg,
    mem_init_done_r_reg,
    wrlvl_byte_redo_reg_2,
    LD0,
    LD0_0,
    CLK,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ,
    phy_rddata_en,
    wrcal_sanity_chk,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ,
    wrcal_sanity_chk_done_reg_2,
    wrlvl_byte_done,
    idelay_ld_reg_0,
    SR,
    wrlvl_byte_redo_r,
    \FSM_sequential_wl_state_r[4]_i_14 ,
    \FSM_sequential_wl_state_r[4]_i_14_0 ,
    \FSM_sequential_wl_state_r[4]_i_14_1 ,
    \idelay_tap_cnt_r_reg[0][1][4] ,
    idelay_ce_int,
    \idelay_tap_cnt_r_reg[0][1][4]_0 ,
    wrlvl_done_r1,
    D,
    pi_dqs_found_done,
    ddr3_lm_done_r,
    \init_state_r[4]_i_15 ,
    mem_init_done_r,
    calib_zero_inputs,
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 ,
    \input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ,
    \input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ,
    idelay_ld_rst,
    wrcal_done_reg_2,
    wrcal_rd_wait,
    prech_done,
    \cal2_state_r_reg[0]_0 );
  output wrcal_resume_w;
  output [0:0]E;
  output wrcal_prech_req;
  output wrcal_done_reg_0;
  output wrcal_sanity_chk_done_reg_0;
  output wrlvl_byte_redo;
  output early1_data_reg_0;
  output phy_if_reset_w;
  output done_dqs_dec237_out;
  output early2_data_reg_0;
  output [1:0]Q;
  output [0:0]\po_stg2_wrcal_cnt_reg[0]_0 ;
  output cal1_dq_idel_ce_reg;
  output wrcal_sanity_chk_done_reg_1;
  output wrcal_done_reg_1;
  output wrlvl_byte_redo_reg_0;
  output wrlvl_byte_redo_reg_1;
  output rdlvl_stg1_done_int_reg;
  output mem_init_done_r_reg;
  output wrlvl_byte_redo_reg_2;
  output LD0;
  output LD0_0;
  input CLK;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  input phy_rddata_en;
  input wrcal_sanity_chk;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  input [0:0]wrcal_sanity_chk_done_reg_2;
  input wrlvl_byte_done;
  input idelay_ld_reg_0;
  input [0:0]SR;
  input wrlvl_byte_redo_r;
  input \FSM_sequential_wl_state_r[4]_i_14 ;
  input [0:0]\FSM_sequential_wl_state_r[4]_i_14_0 ;
  input [0:0]\FSM_sequential_wl_state_r[4]_i_14_1 ;
  input \idelay_tap_cnt_r_reg[0][1][4] ;
  input idelay_ce_int;
  input \idelay_tap_cnt_r_reg[0][1][4]_0 ;
  input wrlvl_done_r1;
  input [0:0]D;
  input pi_dqs_found_done;
  input ddr3_lm_done_r;
  input \init_state_r[4]_i_15 ;
  input mem_init_done_r;
  input calib_zero_inputs;
  input \input_[9].iserdes_dq_.idelay_dq.idelaye2 ;
  input \input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ;
  input \input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ;
  input idelay_ld_rst;
  input wrcal_done_reg_2;
  input wrcal_rd_wait;
  input prech_done;
  input \cal2_state_r_reg[0]_0 ;

  wire CLK;
  wire [0:0]D;
  wire [0:0]E;
  wire \FSM_sequential_wl_state_r[4]_i_14 ;
  wire [0:0]\FSM_sequential_wl_state_r[4]_i_14_0 ;
  wire [0:0]\FSM_sequential_wl_state_r[4]_i_14_1 ;
  wire LD0;
  wire LD0_0;
  wire [1:0]Q;
  wire [0:0]SR;
  wire cal1_dq_idel_ce_reg;
  wire cal2_done_r;
  wire cal2_done_r_i_1_n_0;
  wire cal2_if_reset_i_1_n_0;
  wire cal2_if_reset_i_2_n_0;
  wire cal2_if_reset_i_3_n_0;
  wire cal2_if_reset_i_4_n_0;
  wire cal2_if_reset_i_5_n_0;
  wire cal2_prech_req_r;
  wire cal2_prech_req_r_i_1_n_0;
  wire cal2_prech_req_r_i_2_n_0;
  wire cal2_state_r;
  wire \cal2_state_r[0]_i_2_n_0 ;
  wire \cal2_state_r[0]_i_3_n_0 ;
  wire \cal2_state_r[0]_i_4_n_0 ;
  wire \cal2_state_r[0]_i_5_n_0 ;
  wire \cal2_state_r[1]_i_2_n_0 ;
  wire \cal2_state_r[1]_i_3_n_0 ;
  wire \cal2_state_r[1]_i_4_n_0 ;
  wire \cal2_state_r[2]_i_1_n_0 ;
  wire \cal2_state_r[2]_i_2_n_0 ;
  wire \cal2_state_r[2]_i_3_n_0 ;
  wire \cal2_state_r[3]_i_10_n_0 ;
  wire \cal2_state_r[3]_i_2_n_0 ;
  wire \cal2_state_r[3]_i_3_n_0 ;
  wire \cal2_state_r[3]_i_4_n_0 ;
  wire \cal2_state_r[3]_i_5_n_0 ;
  wire \cal2_state_r[3]_i_6_n_0 ;
  wire \cal2_state_r[3]_i_7_n_0 ;
  wire \cal2_state_r[3]_i_8_n_0 ;
  wire \cal2_state_r[3]_i_9_n_0 ;
  wire \cal2_state_r_reg[0]_0 ;
  wire \cal2_state_r_reg[0]_i_1_n_0 ;
  wire \cal2_state_r_reg[1]_i_1_n_0 ;
  wire \cal2_state_r_reg_n_0_[0] ;
  wire \cal2_state_r_reg_n_0_[1] ;
  wire \cal2_state_r_reg_n_0_[2] ;
  wire \cal2_state_r_reg_n_0_[3] ;
  wire calib_zero_inputs;
  wire ddr3_lm_done_r;
  wire done_dqs_dec237_out;
  wire early1_data_i_1_n_0;
  wire early1_data_i_2_n_0;
  wire early1_data_i_3_n_0;
  wire early1_data_match_r0;
  wire early1_data_reg_0;
  wire early1_match_fall0_and_r;
  wire [7:0]early1_match_fall0_r;
  wire early1_match_fall1_and_r;
  wire early1_match_fall2_and_r;
  wire early1_match_fall3_and_r;
  wire early1_match_rise0_and_r;
  wire [7:0]early1_match_rise0_r;
  wire early1_match_rise1_and_r;
  wire early1_match_rise2_and_r;
  wire early1_match_rise3_and_r;
  wire early2_data_i_1_n_0;
  wire early2_data_match_r0;
  wire early2_data_reg_0;
  wire early2_data_reg_n_0;
  wire early2_match_fall0_and_r;
  wire [7:0]early2_match_fall0_r;
  wire early2_match_fall1_and_r;
  wire [7:0]early2_match_fall1_r;
  wire early2_match_fall2_and_r;
  wire [7:0]early2_match_fall2_r;
  wire early2_match_fall3_and_r;
  wire [7:0]early2_match_fall3_r;
  wire early2_match_rise0_and_r;
  wire [7:0]early2_match_rise0_r;
  wire early2_match_rise1_and_r;
  wire [7:0]early2_match_rise1_r;
  wire early2_match_rise2_and_r;
  wire [7:0]early2_match_rise2_r;
  wire early2_match_rise3_and_r;
  wire [7:0]early2_match_rise3_r;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ;
  wire \gen_pat_match_div4.early1_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg ;
  wire \gen_pat_match_div4.pat_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ;
  wire \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ;
  wire \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_227 ;
  wire \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_263 ;
  wire \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_241 ;
  wire \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_219 ;
  wire \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_255 ;
  wire \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_211 ;
  wire \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 ;
  wire \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_249 ;
  wire \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_228 ;
  wire \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_264 ;
  wire \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_242 ;
  wire \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_220 ;
  wire \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_256 ;
  wire \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_212 ;
  wire \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_235 ;
  wire \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_250 ;
  wire \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_229 ;
  wire \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_265 ;
  wire \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_243 ;
  wire \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_221 ;
  wire \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_257 ;
  wire \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_213 ;
  wire \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_236 ;
  wire \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_251 ;
  wire \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_230 ;
  wire \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_266 ;
  wire \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_244 ;
  wire \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_222 ;
  wire \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_258 ;
  wire \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_214 ;
  wire \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_237 ;
  wire \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 ;
  wire \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_231 ;
  wire \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_267 ;
  wire \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_245 ;
  wire \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_223 ;
  wire \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_259 ;
  wire \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_215 ;
  wire \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 ;
  wire \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_252 ;
  wire \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_232 ;
  wire \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_268 ;
  wire \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_246 ;
  wire \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_224 ;
  wire \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_260 ;
  wire \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_216 ;
  wire \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_238 ;
  wire \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_253 ;
  wire \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_233 ;
  wire \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_269 ;
  wire \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_247 ;
  wire \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_225 ;
  wire \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_261 ;
  wire \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_217 ;
  wire \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_239 ;
  wire \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_254 ;
  wire \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_234 ;
  wire \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_270 ;
  wire \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_248 ;
  wire \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_226 ;
  wire \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_262 ;
  wire \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_218 ;
  wire \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_240 ;
  wire \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 ;
  wire idelay_ce_int;
  wire idelay_ld;
  wire idelay_ld_done_i_1_n_0;
  wire idelay_ld_done_i_2_n_0;
  wire idelay_ld_done_reg_n_0;
  wire idelay_ld_i_1_n_0;
  wire idelay_ld_i_2_n_0;
  wire idelay_ld_reg_0;
  wire idelay_ld_rst;
  wire \idelay_tap_cnt_r_reg[0][1][4] ;
  wire \idelay_tap_cnt_r_reg[0][1][4]_0 ;
  wire \init_state_r[4]_i_15 ;
  wire \input_[9].iserdes_dq_.idelay_dq.idelaye2 ;
  wire \input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ;
  wire \input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ;
  wire mem_init_done_r;
  wire mem_init_done_r_reg;
  wire \not_empty_wait_cnt[4]_i_1_n_0 ;
  wire \not_empty_wait_cnt_reg_n_0_[0] ;
  wire \not_empty_wait_cnt_reg_n_0_[1] ;
  wire \not_empty_wait_cnt_reg_n_0_[2] ;
  wire \not_empty_wait_cnt_reg_n_0_[3] ;
  wire \not_empty_wait_cnt_reg_n_0_[4] ;
  wire [4:0]p_0_in;
  wire [3:0]p_0_in__0;
  wire p_1_in;
  wire pat_data_match_r0;
  wire pat_match_fall0_and_r;
  wire pat_match_fall1_and_r;
  wire pat_match_fall2_and_r;
  wire pat_match_fall3_and_r;
  wire pat_match_rise0_and_r;
  wire pat_match_rise1_and_r;
  wire pat_match_rise2_and_r;
  wire pat_match_rise3_and_r;
  wire phy_if_reset_w;
  wire phy_rddata_en;
  wire pi_dqs_found_done;
  wire [0:0]\po_stg2_wrcal_cnt_reg[0]_0 ;
  wire prech_done;
  wire rd_active_r1;
  wire rd_active_r3_reg_srl2_n_0;
  wire rdlvl_stg1_done_int_reg;
  wire \tap_inc_wait_cnt[3]_i_1_n_0 ;
  wire [3:0]tap_inc_wait_cnt_reg;
  wire wrcal_done_i_1_n_0;
  wire wrcal_done_reg_0;
  wire wrcal_done_reg_1;
  wire wrcal_done_reg_2;
  wire [1:1]wrcal_dqs_cnt_r;
  wire \wrcal_dqs_cnt_r[0]_i_1_n_0 ;
  wire \wrcal_dqs_cnt_r[0]_i_2_n_0 ;
  wire \wrcal_dqs_cnt_r[1]_i_1_n_0 ;
  wire \wrcal_dqs_cnt_r[1]_i_2_n_0 ;
  wire \wrcal_dqs_cnt_r_reg_n_0_[0] ;
  wire wrcal_pat_resume_r;
  wire wrcal_pat_resume_r2_reg_srl2_n_0;
  wire wrcal_pat_resume_r_i_1_n_0;
  wire wrcal_pat_resume_r_i_2_n_0;
  wire wrcal_pat_resume_r_i_3_n_0;
  wire wrcal_prech_req;
  wire wrcal_rd_wait;
  wire wrcal_resume_w;
  wire wrcal_sanity_chk;
  wire wrcal_sanity_chk_done_i_1_n_0;
  wire wrcal_sanity_chk_done_reg_0;
  wire wrcal_sanity_chk_done_reg_1;
  wire [0:0]wrcal_sanity_chk_done_reg_2;
  wire wrcal_sanity_chk_r_reg_n_0;
  wire wrlvl_byte_done;
  wire wrlvl_byte_done_r;
  wire wrlvl_byte_redo;
  wire wrlvl_byte_redo_i_1_n_0;
  wire wrlvl_byte_redo_i_2_n_0;
  wire wrlvl_byte_redo_i_3_n_0;
  wire wrlvl_byte_redo_r;
  wire wrlvl_byte_redo_reg_0;
  wire wrlvl_byte_redo_reg_1;
  wire wrlvl_byte_redo_reg_2;
  wire wrlvl_done_r1;

  LUT6 #(
    .INIT(64'hCCC000C0DDDDDDDD)) 
    \FSM_sequential_wl_state_r[4]_i_19 
       (.I0(early2_data_reg_n_0),
        .I1(\FSM_sequential_wl_state_r[4]_i_14 ),
        .I2(\FSM_sequential_wl_state_r[4]_i_14_0 ),
        .I3(Q[0]),
        .I4(\FSM_sequential_wl_state_r[4]_i_14_1 ),
        .I5(early1_data_reg_0),
        .O(early2_data_reg_0));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    cal2_done_r_i_1
       (.I0(p_1_in),
        .I1(\cal2_state_r_reg_n_0_[3] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(cal2_done_r),
        .O(cal2_done_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair428" *) 
  LUT2 #(
    .INIT(4'hB)) 
    cal2_done_r_i_2
       (.I0(wrcal_sanity_chk_r_reg_n_0),
        .I1(wrcal_sanity_chk),
        .O(p_1_in));
  FDRE cal2_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal2_done_r_i_1_n_0),
        .Q(cal2_done_r),
        .R(wrcal_sanity_chk_done_reg_2));
  LUT6 #(
    .INIT(64'hFFFFBABF00008A80)) 
    cal2_if_reset_i_1
       (.I0(cal2_if_reset_i_2_n_0),
        .I1(cal2_if_reset_i_3_n_0),
        .I2(\cal2_state_r_reg_n_0_[0] ),
        .I3(cal2_if_reset_i_4_n_0),
        .I4(\cal2_state_r_reg_n_0_[3] ),
        .I5(phy_if_reset_w),
        .O(cal2_if_reset_i_1_n_0));
  LUT6 #(
    .INIT(64'h004F0040F000F000)) 
    cal2_if_reset_i_2
       (.I0(E),
        .I1(rd_active_r1),
        .I2(\cal2_state_r_reg_n_0_[0] ),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(wrcal_sanity_chk_r_reg_n_0),
        .I5(\cal2_state_r_reg_n_0_[1] ),
        .O(cal2_if_reset_i_2_n_0));
  LUT6 #(
    .INIT(64'h00FF000040FF40FF)) 
    cal2_if_reset_i_3
       (.I0(E),
        .I1(wrlvl_byte_done),
        .I2(rd_active_r1),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(idelay_ld_done_i_2_n_0),
        .I5(\cal2_state_r_reg_n_0_[2] ),
        .O(cal2_if_reset_i_3_n_0));
  LUT6 #(
    .INIT(64'hFF80FFFFFF800000)) 
    cal2_if_reset_i_4
       (.I0(prech_done),
        .I1(cal2_prech_req_r_i_2_n_0),
        .I2(wrcal_sanity_chk_r_reg_n_0),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(\cal2_state_r_reg_n_0_[1] ),
        .I5(cal2_if_reset_i_5_n_0),
        .O(cal2_if_reset_i_4_n_0));
  LUT6 #(
    .INIT(64'h8000FFFF80000000)) 
    cal2_if_reset_i_5
       (.I0(tap_inc_wait_cnt_reg[2]),
        .I1(tap_inc_wait_cnt_reg[0]),
        .I2(tap_inc_wait_cnt_reg[1]),
        .I3(tap_inc_wait_cnt_reg[3]),
        .I4(\cal2_state_r_reg_n_0_[2] ),
        .I5(\cal2_state_r_reg[0]_0 ),
        .O(cal2_if_reset_i_5_n_0));
  FDRE cal2_if_reset_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal2_if_reset_i_1_n_0),
        .Q(phy_if_reset_w),
        .R(SR));
  LUT6 #(
    .INIT(64'h0000000010110000)) 
    cal2_prech_req_r_i_1
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(cal2_prech_req_r_i_2_n_0),
        .I3(wrcal_sanity_chk_r_reg_n_0),
        .I4(\cal2_state_r_reg_n_0_[1] ),
        .I5(\cal2_state_r_reg_n_0_[0] ),
        .O(cal2_prech_req_r_i_1_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    cal2_prech_req_r_i_2
       (.I0(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I1(wrcal_dqs_cnt_r),
        .O(cal2_prech_req_r_i_2_n_0));
  FDRE cal2_prech_req_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal2_prech_req_r_i_1_n_0),
        .Q(cal2_prech_req_r),
        .R(wrcal_sanity_chk_done_reg_2));
  LUT6 #(
    .INIT(64'h00000000FF5D005D)) 
    \cal2_state_r[0]_i_2 
       (.I0(\cal2_state_r_reg_n_0_[2] ),
        .I1(idelay_ld_done_reg_n_0),
        .I2(wrcal_sanity_chk_r_reg_n_0),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r[0]_i_4_n_0 ),
        .I5(\cal2_state_r_reg_n_0_[3] ),
        .O(\cal2_state_r[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0000CCE2)) 
    \cal2_state_r[0]_i_3 
       (.I0(\cal2_state_r[0]_i_5_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(tap_inc_wait_cnt_reg[0]),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[3] ),
        .O(\cal2_state_r[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair439" *) 
  LUT4 #(
    .INIT(16'h00DF)) 
    \cal2_state_r[0]_i_4 
       (.I0(prech_done),
        .I1(wrcal_dqs_cnt_r),
        .I2(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .O(\cal2_state_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000555100000000)) 
    \cal2_state_r[0]_i_5 
       (.I0(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),
        .I1(idelay_ld_done_reg_n_0),
        .I2(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I3(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I4(wrcal_sanity_chk_r_reg_n_0),
        .I5(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .O(\cal2_state_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00FF000055007500)) 
    \cal2_state_r[1]_i_2 
       (.I0(prech_done),
        .I1(wrcal_dqs_cnt_r),
        .I2(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(wrcal_sanity_chk_r_reg_n_0),
        .I5(\cal2_state_r_reg_n_0_[2] ),
        .O(\cal2_state_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFA800A8)) 
    \cal2_state_r[1]_i_3 
       (.I0(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .I1(\cal2_state_r[1]_i_4_n_0 ),
        .I2(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(tap_inc_wait_cnt_reg[1]),
        .I5(\cal2_state_r_reg_n_0_[1] ),
        .O(\cal2_state_r[1]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h0E)) 
    \cal2_state_r[1]_i_4 
       (.I0(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I2(wrcal_sanity_chk_r_reg_n_0),
        .O(\cal2_state_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4F4AFFFF4F4A0000)) 
    \cal2_state_r[2]_i_1 
       (.I0(\cal2_state_r_reg_n_0_[1] ),
        .I1(tap_inc_wait_cnt_reg[2]),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r[2]_i_2_n_0 ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(\cal2_state_r[2]_i_3_n_0 ),
        .O(\cal2_state_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \cal2_state_r[2]_i_2 
       (.I0(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),
        .I1(idelay_ld_done_reg_n_0),
        .I2(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I3(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I4(wrcal_sanity_chk_r_reg_n_0),
        .I5(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .O(\cal2_state_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00FF00005D005D00)) 
    \cal2_state_r[2]_i_3 
       (.I0(prech_done),
        .I1(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I2(wrcal_dqs_cnt_r),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(wrcal_sanity_chk_r_reg_n_0),
        .I5(\cal2_state_r_reg_n_0_[2] ),
        .O(\cal2_state_r[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair435" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \cal2_state_r[3]_i_10 
       (.I0(\not_empty_wait_cnt_reg_n_0_[2] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[1] ),
        .I2(\not_empty_wait_cnt_reg_n_0_[0] ),
        .I3(\not_empty_wait_cnt_reg_n_0_[3] ),
        .O(\cal2_state_r[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h00E2FFFF00E20000)) 
    \cal2_state_r[3]_i_2 
       (.I0(\cal2_state_r[3]_i_5_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(tap_inc_wait_cnt_reg[3]),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(\cal2_state_r_reg_n_0_[3] ),
        .O(\cal2_state_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h45404F4F45404A4A)) 
    \cal2_state_r[3]_i_3 
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r[3]_i_6_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(\cal2_state_r[3]_i_7_n_0 ),
        .I4(\cal2_state_r_reg_n_0_[2] ),
        .I5(\cal2_state_r_reg[0]_0 ),
        .O(\cal2_state_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEE222E2)) 
    \cal2_state_r[3]_i_4 
       (.I0(\cal2_state_r[3]_i_8_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[1] ),
        .I2(\cal2_state_r[3]_i_9_n_0 ),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(\cal2_state_r[3]_i_7_n_0 ),
        .I5(\cal2_state_r_reg_n_0_[3] ),
        .O(\cal2_state_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h55550004FFFFFFFF)) 
    \cal2_state_r[3]_i_5 
       (.I0(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),
        .I1(idelay_ld_done_reg_n_0),
        .I2(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I3(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I4(wrcal_sanity_chk_r_reg_n_0),
        .I5(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .O(\cal2_state_r[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h3B3B3B3B38083838)) 
    \cal2_state_r[3]_i_6 
       (.I0(wrcal_sanity_chk),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(wrcal_sanity_chk_r_reg_n_0),
        .I3(wrcal_dqs_cnt_r),
        .I4(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I5(prech_done),
        .O(\cal2_state_r[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair438" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \cal2_state_r[3]_i_7 
       (.I0(tap_inc_wait_cnt_reg[2]),
        .I1(tap_inc_wait_cnt_reg[0]),
        .I2(tap_inc_wait_cnt_reg[1]),
        .I3(tap_inc_wait_cnt_reg[3]),
        .O(\cal2_state_r[3]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'hBBBBB888)) 
    \cal2_state_r[3]_i_8 
       (.I0(idelay_ld_done_i_2_n_0),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(\not_empty_wait_cnt_reg_n_0_[4] ),
        .I3(\cal2_state_r[3]_i_10_n_0 ),
        .I4(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .O(\cal2_state_r[3]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair440" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \cal2_state_r[3]_i_9 
       (.I0(rd_active_r1),
        .I1(wrlvl_byte_done),
        .I2(E),
        .O(\cal2_state_r[3]_i_9_n_0 ));
  FDRE \cal2_state_r_reg[0] 
       (.C(CLK),
        .CE(cal2_state_r),
        .D(\cal2_state_r_reg[0]_i_1_n_0 ),
        .Q(\cal2_state_r_reg_n_0_[0] ),
        .R(wrcal_sanity_chk_done_reg_2));
  MUXF7 \cal2_state_r_reg[0]_i_1 
       (.I0(\cal2_state_r[0]_i_2_n_0 ),
        .I1(\cal2_state_r[0]_i_3_n_0 ),
        .O(\cal2_state_r_reg[0]_i_1_n_0 ),
        .S(\cal2_state_r_reg_n_0_[0] ));
  FDRE \cal2_state_r_reg[1] 
       (.C(CLK),
        .CE(cal2_state_r),
        .D(\cal2_state_r_reg[1]_i_1_n_0 ),
        .Q(\cal2_state_r_reg_n_0_[1] ),
        .R(wrcal_sanity_chk_done_reg_2));
  MUXF7 \cal2_state_r_reg[1]_i_1 
       (.I0(\cal2_state_r[1]_i_2_n_0 ),
        .I1(\cal2_state_r[1]_i_3_n_0 ),
        .O(\cal2_state_r_reg[1]_i_1_n_0 ),
        .S(\cal2_state_r_reg_n_0_[0] ));
  FDRE \cal2_state_r_reg[2] 
       (.C(CLK),
        .CE(cal2_state_r),
        .D(\cal2_state_r[2]_i_1_n_0 ),
        .Q(\cal2_state_r_reg_n_0_[2] ),
        .R(wrcal_sanity_chk_done_reg_2));
  FDRE \cal2_state_r_reg[3] 
       (.C(CLK),
        .CE(cal2_state_r),
        .D(\cal2_state_r[3]_i_2_n_0 ),
        .Q(\cal2_state_r_reg_n_0_[3] ),
        .R(wrcal_sanity_chk_done_reg_2));
  MUXF7 \cal2_state_r_reg[3]_i_1 
       (.I0(\cal2_state_r[3]_i_3_n_0 ),
        .I1(\cal2_state_r[3]_i_4_n_0 ),
        .O(cal2_state_r),
        .S(\cal2_state_r_reg_n_0_[0] ));
  LUT4 #(
    .INIT(16'h2F20)) 
    early1_data_i_1
       (.I0(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[1] ),
        .I2(early1_data_i_2_n_0),
        .I3(early1_data_reg_0),
        .O(early1_data_i_1_n_0));
  LUT5 #(
    .INIT(32'h45400000)) 
    early1_data_i_2
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(early1_data_i_3_n_0),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(wrlvl_byte_redo_i_3_n_0),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .O(early1_data_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair440" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    early1_data_i_3
       (.I0(E),
        .I1(wrlvl_byte_done),
        .I2(rd_active_r1),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .O(early1_data_i_3_n_0));
  FDRE early1_data_reg
       (.C(CLK),
        .CE(1'b1),
        .D(early1_data_i_1_n_0),
        .Q(early1_data_reg_0),
        .R(idelay_ld_reg_0));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    early2_data_i_1
       (.I0(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(early1_data_i_2_n_0),
        .I4(early2_data_reg_n_0),
        .O(early2_data_i_1_n_0));
  FDRE early2_data_reg
       (.C(CLK),
        .CE(1'b1),
        .D(early2_data_i_1_n_0),
        .Q(early2_data_reg_n_0),
        .R(wrcal_sanity_chk_done_reg_2));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early1_data_match_r_i_1 
       (.I0(early1_match_rise0_and_r),
        .I1(early1_match_fall3_and_r),
        .I2(early1_match_fall0_and_r),
        .I3(early1_match_fall2_and_r),
        .I4(\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ),
        .O(early1_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early1_data_match_r_i_2 
       (.I0(early1_match_rise2_and_r),
        .I1(early1_match_rise3_and_r),
        .I2(early1_match_rise1_and_r),
        .I3(early1_match_fall1_and_r),
        .O(\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(early1_data_match_r0),
        .Q(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early1_match_fall0_and_r_i_1 
       (.I0(early1_match_fall0_r[2]),
        .I1(early1_match_fall0_r[0]),
        .I2(early1_match_fall0_r[6]),
        .I3(early1_match_fall0_r[4]),
        .I4(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early1_match_fall0_and_r_i_2 
       (.I0(early1_match_fall0_r[1]),
        .I1(early1_match_fall0_r[3]),
        .I2(early1_match_fall0_r[5]),
        .I3(early1_match_fall0_r[7]),
        .O(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ),
        .Q(early1_match_fall0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg ),
        .O(\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair434" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_fall1_and_r_i_2 
       (.I0(early2_match_fall1_r[0]),
        .I1(early2_match_fall1_r[5]),
        .I2(early2_match_fall1_r[1]),
        .I3(early2_match_fall1_r[4]),
        .O(\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ),
        .Q(early1_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_fall2_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ),
        .I3(early2_match_fall2_r[7]),
        .I4(early2_match_fall2_r[3]),
        .O(\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_fall2_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ),
        .O(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ),
        .Q(early1_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ),
        .O(\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair430" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_fall3_and_r_i_2 
       (.I0(early2_match_fall3_r[1]),
        .I1(early2_match_fall3_r[5]),
        .I2(early2_match_fall3_r[3]),
        .I3(early2_match_fall3_r[7]),
        .O(\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ),
        .Q(early1_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early1_match_rise0_and_r_i_1 
       (.I0(early1_match_rise0_r[2]),
        .I1(early1_match_rise0_r[0]),
        .I2(early1_match_rise0_r[6]),
        .I3(early1_match_rise0_r[4]),
        .I4(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early1_match_rise0_and_r_i_2 
       (.I0(early1_match_rise0_r[1]),
        .I1(early1_match_rise0_r[3]),
        .I2(early1_match_rise0_r[5]),
        .I3(early1_match_rise0_r[7]),
        .O(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ),
        .Q(early1_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ),
        .O(\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair429" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_rise1_and_r_i_2 
       (.I0(early2_match_rise1_r[0]),
        .I1(early2_match_rise1_r[5]),
        .I2(early2_match_rise1_r[1]),
        .I3(early2_match_rise1_r[4]),
        .O(\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ),
        .Q(early1_match_rise1_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair432" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_rise2_and_r_i_1 
       (.I0(early2_match_rise2_r[7]),
        .I1(early2_match_rise2_r[6]),
        .I2(early2_match_rise2_r[3]),
        .I3(early2_match_rise2_r[2]),
        .I4(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_rise2_and_r_i_2 
       (.I0(early2_match_rise2_r[0]),
        .I1(early2_match_rise2_r[4]),
        .I2(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ),
        .O(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ),
        .Q(early1_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_rise3_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ),
        .I1(early2_match_rise3_r[5]),
        .I2(early2_match_rise3_r[1]),
        .I3(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ),
        .O(\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_rise3_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ),
        .I1(early2_match_rise3_r[7]),
        .I2(early2_match_rise3_r[3]),
        .I3(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ),
        .O(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ),
        .Q(early1_match_rise3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early2_data_match_r_i_1 
       (.I0(early2_match_rise3_and_r),
        .I1(early2_match_fall2_and_r),
        .I2(early2_match_fall1_and_r),
        .I3(early2_match_rise0_and_r),
        .I4(\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ),
        .O(early2_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early2_data_match_r_i_2 
       (.I0(early2_match_fall0_and_r),
        .I1(early2_match_rise2_and_r),
        .I2(early2_match_rise1_and_r),
        .I3(early2_match_fall3_and_r),
        .O(\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(early2_data_match_r0),
        .Q(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_fall0_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ),
        .I1(early2_match_fall0_r[3]),
        .I2(early2_match_fall0_r[1]),
        .I3(early2_match_fall0_r[7]),
        .I4(early2_match_fall0_r[5]),
        .O(\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair431" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_fall0_and_r_i_2 
       (.I0(early2_match_fall0_r[4]),
        .I1(early2_match_fall0_r[6]),
        .I2(early2_match_fall0_r[0]),
        .I3(early2_match_fall0_r[2]),
        .O(\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ),
        .Q(early2_match_fall0_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair434" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_fall1_and_r_i_1 
       (.I0(early2_match_fall1_r[4]),
        .I1(early2_match_fall1_r[1]),
        .I2(early2_match_fall1_r[5]),
        .I3(early2_match_fall1_r[0]),
        .I4(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_fall1_and_r_i_2 
       (.I0(early2_match_fall1_r[2]),
        .I1(early2_match_fall1_r[7]),
        .I2(early2_match_fall1_r[3]),
        .I3(early2_match_fall1_r[6]),
        .O(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ),
        .Q(early2_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early2_match_fall2_and_r_i_1 
       (.I0(early2_match_fall2_r[6]),
        .I1(early2_match_fall2_r[1]),
        .I2(early2_match_fall2_r[7]),
        .I3(early2_match_fall2_r[0]),
        .I4(\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early2_match_fall2_and_r_i_2 
       (.I0(early2_match_fall2_r[2]),
        .I1(early2_match_fall2_r[5]),
        .I2(early2_match_fall2_r[3]),
        .I3(early2_match_fall2_r[4]),
        .O(\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ),
        .Q(early2_match_fall2_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair430" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_fall3_and_r_i_1 
       (.I0(early2_match_fall3_r[7]),
        .I1(early2_match_fall3_r[3]),
        .I2(early2_match_fall3_r[5]),
        .I3(early2_match_fall3_r[1]),
        .I4(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_fall3_and_r_i_2 
       (.I0(early2_match_fall3_r[0]),
        .I1(early2_match_fall3_r[6]),
        .I2(early2_match_fall3_r[4]),
        .I3(early2_match_fall3_r[2]),
        .O(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ),
        .Q(early2_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ),
        .I1(early2_match_rise0_r[3]),
        .I2(early2_match_rise0_r[1]),
        .I3(early2_match_rise0_r[7]),
        .I4(early2_match_rise0_r[5]),
        .O(\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair433" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_rise0_and_r_i_2 
       (.I0(early2_match_rise0_r[4]),
        .I1(early2_match_rise0_r[6]),
        .I2(early2_match_rise0_r[0]),
        .I3(early2_match_rise0_r[2]),
        .O(\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ),
        .Q(early2_match_rise0_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair429" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_rise1_and_r_i_1 
       (.I0(early2_match_rise1_r[4]),
        .I1(early2_match_rise1_r[1]),
        .I2(early2_match_rise1_r[5]),
        .I3(early2_match_rise1_r[0]),
        .I4(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_rise1_and_r_i_2 
       (.I0(early2_match_rise1_r[2]),
        .I1(early2_match_rise1_r[7]),
        .I2(early2_match_rise1_r[3]),
        .I3(early2_match_rise1_r[6]),
        .O(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ),
        .Q(early2_match_rise1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_rise2_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ),
        .I1(early2_match_rise2_r[4]),
        .I2(early2_match_rise2_r[0]),
        .I3(early2_match_rise2_r[5]),
        .I4(early2_match_rise2_r[1]),
        .O(\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair432" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_rise2_and_r_i_2 
       (.I0(early2_match_rise2_r[2]),
        .I1(early2_match_rise2_r[3]),
        .I2(early2_match_rise2_r[6]),
        .I3(early2_match_rise2_r[7]),
        .O(\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ),
        .Q(early2_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early2_match_rise3_and_r_i_1 
       (.I0(early2_match_rise3_r[6]),
        .I1(early2_match_rise3_r[5]),
        .I2(early2_match_rise3_r[7]),
        .I3(early2_match_rise3_r[4]),
        .I4(\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early2_match_rise3_and_r_i_2 
       (.I0(early2_match_rise3_r[0]),
        .I1(early2_match_rise3_r[3]),
        .I2(early2_match_rise3_r[1]),
        .I3(early2_match_rise3_r[2]),
        .O(\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ),
        .Q(early2_match_rise3_and_r),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_227 ),
        .Q(early1_match_fall0_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_263 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ),
        .Q(early2_match_fall1_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_219 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_255 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ),
        .Q(early1_match_rise0_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_211 ),
        .Q(early2_match_rise1_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_241 ),
        .Q(early2_match_fall2_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_249 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ),
        .Q(early2_match_rise3_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_227 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ),
        .Q(early2_match_fall0_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_263 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_241 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_219 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ),
        .Q(early2_match_fall3_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_255 ),
        .Q(early2_match_rise0_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_211 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 ),
        .Q(early2_match_rise2_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_249 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_264 ),
        .Q(early2_match_fall1_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_220 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ),
        .Q(early2_match_fall3_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_212 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ),
        .Q(early2_match_rise1_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_250 ),
        .Q(early2_match_rise3_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_228 ),
        .Q(early2_match_fall0_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_242 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ),
        .Q(early2_match_fall2_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_256 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ),
        .Q(early2_match_rise0_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_235 ),
        .Q(early2_match_rise2_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_228 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ),
        .Q(early1_match_fall0_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_264 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_242 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_220 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_256 ),
        .Q(early1_match_rise0_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_212 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_235 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_250 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_229 ),
        .Q(early1_match_fall0_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_265 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_243 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_221 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_257 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ),
        .Q(early1_match_rise0_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_213 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_236 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ),
        .Q(early2_match_rise2_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_251 ),
        .Q(early2_match_rise3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_229 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ),
        .Q(early2_match_fall0_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_265 ),
        .Q(early2_match_fall1_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_243 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ),
        .Q(early2_match_fall2_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_221 ),
        .Q(early2_match_fall3_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_257 ),
        .Q(early2_match_rise0_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_213 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ),
        .Q(early2_match_rise1_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_236 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_251 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_266 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_244 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ),
        .Q(early2_match_fall2_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_214 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_237 ),
        .Q(early2_match_rise2_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_230 ),
        .Q(early2_match_fall0_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_258 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ),
        .Q(early2_match_rise0_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_230 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ),
        .Q(early1_match_fall0_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_266 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ),
        .Q(early2_match_fall1_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_244 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_222 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ),
        .Q(early2_match_fall3_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_258 ),
        .Q(early1_match_rise0_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_214 ),
        .Q(early2_match_rise1_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_237 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 ),
        .Q(early2_match_rise3_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_231 ),
        .Q(early1_match_fall0_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_267 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ),
        .Q(early2_match_fall1_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_223 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_259 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ),
        .Q(early1_match_rise0_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_215 ),
        .Q(early2_match_rise1_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_245 ),
        .Q(early2_match_fall2_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_252 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ),
        .Q(early2_match_rise3_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_231 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ),
        .Q(early2_match_fall0_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_267 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_245 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_223 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ),
        .Q(early2_match_fall3_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_259 ),
        .Q(early2_match_rise0_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_215 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 ),
        .Q(early2_match_rise2_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_252 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_268 ),
        .Q(early2_match_fall1_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_224 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ),
        .Q(early2_match_fall3_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_216 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ),
        .Q(early2_match_rise1_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_253 ),
        .Q(early2_match_rise3_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_232 ),
        .Q(early2_match_fall0_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_246 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ),
        .Q(early2_match_fall2_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_260 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ),
        .Q(early2_match_rise0_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_238 ),
        .Q(early2_match_rise2_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_232 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ),
        .Q(early1_match_fall0_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_268 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_246 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_224 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_260 ),
        .Q(early1_match_rise0_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_216 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_238 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_253 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_233 ),
        .Q(early1_match_fall0_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_269 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_247 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_225 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_261 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ),
        .Q(early1_match_rise0_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_217 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_239 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ),
        .Q(early2_match_rise2_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_254 ),
        .Q(early2_match_rise3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_233 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ),
        .Q(early2_match_fall0_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_269 ),
        .Q(early2_match_fall1_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_247 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ),
        .Q(early2_match_fall2_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_225 ),
        .Q(early2_match_fall3_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_261 ),
        .Q(early2_match_rise0_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_217 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ),
        .Q(early2_match_rise1_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_239 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_254 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_270 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_248 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ),
        .Q(early2_match_fall2_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_218 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_240 ),
        .Q(early2_match_rise2_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_234 ),
        .Q(early2_match_fall0_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_262 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ),
        .Q(early2_match_rise0_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_234 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ),
        .Q(early1_match_fall0_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_270 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ),
        .Q(early2_match_fall1_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_248 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_226 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ),
        .Q(early2_match_fall3_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_262 ),
        .Q(early1_match_rise0_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_218 ),
        .Q(early2_match_rise1_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_240 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 ),
        .Q(early2_match_rise3_r[7]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat_data_match_r_i_1 
       (.I0(pat_match_fall0_and_r),
        .I1(pat_match_rise2_and_r),
        .I2(pat_match_rise1_and_r),
        .I3(pat_match_fall1_and_r),
        .I4(\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ),
        .O(pat_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.pat_data_match_r_i_2 
       (.I0(pat_match_rise0_and_r),
        .I1(pat_match_rise3_and_r),
        .I2(pat_match_fall3_and_r),
        .I3(pat_match_fall2_and_r),
        .O(\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat_data_match_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(pat_data_match_r0),
        .Q(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.pat_data_match_valid_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(rd_active_r3_reg_srl2_n_0),
        .Q(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair431" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat_match_fall0_and_r_i_1 
       (.I0(early2_match_fall0_r[2]),
        .I1(early2_match_fall0_r[0]),
        .I2(early2_match_fall0_r[6]),
        .I3(early2_match_fall0_r[4]),
        .I4(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_fall0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ),
        .Q(pat_match_fall0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ),
        .O(\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_fall1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ),
        .Q(pat_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_fall2_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ),
        .I3(early2_match_fall2_r[6]),
        .I4(early2_match_fall2_r[2]),
        .O(\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_fall2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ),
        .Q(pat_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ),
        .I3(early2_match_fall3_r[7]),
        .I4(early2_match_fall3_r[3]),
        .O(\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_fall3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ),
        .Q(pat_match_fall3_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair433" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat_match_rise0_and_r_i_1 
       (.I0(early2_match_rise0_r[2]),
        .I1(early2_match_rise0_r[0]),
        .I2(early2_match_rise0_r[6]),
        .I3(early2_match_rise0_r[4]),
        .I4(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_rise0_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ),
        .Q(pat_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg ),
        .O(\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_rise1_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ),
        .Q(pat_match_rise1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_rise2_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ),
        .O(\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_rise2_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ),
        .Q(pat_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_rise3_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ),
        .O(\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_rise3_and_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ),
        .Q(pat_match_rise3_and_r),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_227 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_263 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_241 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_219 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_255 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_211 ),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0] " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2 " *) 
  SRL16E \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg0 ),
        .Q(\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0]_srl2_n_0 ));
  FDRE \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_249 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_228 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_264 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_242 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_220 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_256 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_212 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_235 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_250 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_229 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_265 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_243 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_221 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_257 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_213 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_236 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_251 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_230 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_266 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_244 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_222 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_258 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_214 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_237 ),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3] " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2 " *) 
  SRL16E \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg0 ),
        .Q(\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0]_srl2_n_0 ));
  FDRE \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_231 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_267 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_245 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_223 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_259 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_215 ),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4] " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2 " *) 
  SRL16E \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg0 ),
        .Q(\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0]_srl2_n_0 ));
  FDRE \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_252 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_232 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_268 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_246 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_224 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_260 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_216 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_238 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_253 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_233 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_269 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_247 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_225 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_261 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_217 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_239 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_254 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_234 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_270 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_248 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_226 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_262 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_218 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_240 ),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7] " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2 " *) 
  SRL16E \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg0 ),
        .Q(\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0]_srl2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFCFF00000080)) 
    idelay_ld_done_i_1
       (.I0(idelay_ld_done_i_2_n_0),
        .I1(\cal2_state_r_reg_n_0_[0] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[3] ),
        .I5(idelay_ld_done_reg_n_0),
        .O(idelay_ld_done_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair438" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    idelay_ld_done_i_2
       (.I0(tap_inc_wait_cnt_reg[2]),
        .I1(tap_inc_wait_cnt_reg[0]),
        .I2(tap_inc_wait_cnt_reg[1]),
        .I3(tap_inc_wait_cnt_reg[3]),
        .O(idelay_ld_done_i_2_n_0));
  FDRE idelay_ld_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ld_done_i_1_n_0),
        .Q(idelay_ld_done_reg_n_0),
        .R(wrcal_sanity_chk_done_reg_2));
  LUT4 #(
    .INIT(16'h2F20)) 
    idelay_ld_i_1
       (.I0(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(idelay_ld_i_2_n_0),
        .I3(idelay_ld),
        .O(idelay_ld_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000540400000000)) 
    idelay_ld_i_2
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r[2]_i_2_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(idelay_ld_done_i_2_n_0),
        .I4(\cal2_state_r_reg_n_0_[1] ),
        .I5(\cal2_state_r_reg_n_0_[0] ),
        .O(idelay_ld_i_2_n_0));
  FDRE idelay_ld_reg
       (.C(CLK),
        .CE(1'b1),
        .D(idelay_ld_i_1_n_0),
        .Q(idelay_ld),
        .R(idelay_ld_reg_0));
  LUT3 #(
    .INIT(8'hFB)) 
    \idelay_tap_cnt_r[0][0][4]_i_2 
       (.I0(idelay_ce_int),
        .I1(idelay_ld),
        .I2(Q[1]),
        .O(cal1_dq_idel_ce_reg));
  LUT6 #(
    .INIT(64'hAAAAAEAAFFFFAEAA)) 
    \idelay_tap_cnt_r[0][1][4]_i_1 
       (.I0(\idelay_tap_cnt_r_reg[0][1][4] ),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(idelay_ld),
        .I4(idelay_ce_int),
        .I5(\idelay_tap_cnt_r_reg[0][1][4]_0 ),
        .O(\po_stg2_wrcal_cnt_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h5555555515555555)) 
    \init_state_r[0]_i_18 
       (.I0(wrcal_sanity_chk_done_reg_0),
        .I1(wrcal_done_reg_0),
        .I2(wrlvl_done_r1),
        .I3(D),
        .I4(pi_dqs_found_done),
        .I5(ddr3_lm_done_r),
        .O(wrcal_sanity_chk_done_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair437" *) 
  LUT4 #(
    .INIT(16'h7077)) 
    \init_state_r[1]_i_24 
       (.I0(D),
        .I1(mem_init_done_r),
        .I2(wrcal_done_reg_0),
        .I3(wrlvl_byte_redo),
        .O(rdlvl_stg1_done_int_reg));
  (* SOFT_HLUTNM = "soft_lutpair436" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \init_state_r[2]_i_31 
       (.I0(wrlvl_byte_redo),
        .I1(pi_dqs_found_done),
        .I2(wrlvl_done_r1),
        .O(wrlvl_byte_redo_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair443" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \init_state_r[2]_i_32 
       (.I0(wrlvl_byte_redo),
        .I1(wrcal_done_reg_0),
        .O(wrlvl_byte_redo_reg_2));
  (* SOFT_HLUTNM = "soft_lutpair443" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \init_state_r[4]_i_25 
       (.I0(wrlvl_byte_redo),
        .I1(\init_state_r[4]_i_15 ),
        .I2(wrcal_done_reg_0),
        .O(wrlvl_byte_redo_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair436" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \init_state_r[4]_i_28 
       (.I0(wrcal_done_reg_0),
        .I1(wrlvl_done_r1),
        .I2(D),
        .I3(pi_dqs_found_done),
        .O(wrcal_done_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair437" *) 
  LUT4 #(
    .INIT(16'hD0DD)) 
    \init_state_r[4]_i_34 
       (.I0(mem_init_done_r),
        .I1(D),
        .I2(wrcal_done_reg_0),
        .I3(wrlvl_byte_redo),
        .O(mem_init_done_r_reg));
  LUT6 #(
    .INIT(64'hFFFFFFFF45004400)) 
    \input_[0].iserdes_dq_.idelay_dq.idelaye2_i_2 
       (.I0(calib_zero_inputs),
        .I1(\input_[9].iserdes_dq_.idelay_dq.idelaye2 ),
        .I2(\input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ),
        .I3(idelay_ld),
        .I4(\input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ),
        .I5(idelay_ld_rst),
        .O(LD0));
  LUT6 #(
    .INIT(64'hFFFFFFFF54440000)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2 
       (.I0(calib_zero_inputs),
        .I1(\input_[9].iserdes_dq_.idelay_dq.idelaye2 ),
        .I2(\input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ),
        .I3(\input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ),
        .I4(idelay_ld),
        .I5(idelay_ld_rst),
        .O(LD0_0));
  (* SOFT_HLUTNM = "soft_lutpair445" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \not_empty_wait_cnt[0]_i_1 
       (.I0(\not_empty_wait_cnt_reg_n_0_[0] ),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair445" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_empty_wait_cnt[1]_i_1 
       (.I0(\not_empty_wait_cnt_reg_n_0_[0] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[1] ),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair441" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \not_empty_wait_cnt[2]_i_1 
       (.I0(\not_empty_wait_cnt_reg_n_0_[2] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[0] ),
        .I2(\not_empty_wait_cnt_reg_n_0_[1] ),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair441" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \not_empty_wait_cnt[3]_i_1 
       (.I0(\not_empty_wait_cnt_reg_n_0_[3] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[0] ),
        .I2(\not_empty_wait_cnt_reg_n_0_[1] ),
        .I3(\not_empty_wait_cnt_reg_n_0_[2] ),
        .O(p_0_in[3]));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFF)) 
    \not_empty_wait_cnt[4]_i_1 
       (.I0(wrcal_done_reg_2),
        .I1(\cal2_state_r_reg_n_0_[3] ),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(wrcal_rd_wait),
        .O(\not_empty_wait_cnt[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair435" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \not_empty_wait_cnt[4]_i_2 
       (.I0(\not_empty_wait_cnt_reg_n_0_[4] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[2] ),
        .I2(\not_empty_wait_cnt_reg_n_0_[1] ),
        .I3(\not_empty_wait_cnt_reg_n_0_[0] ),
        .I4(\not_empty_wait_cnt_reg_n_0_[3] ),
        .O(p_0_in[4]));
  FDRE \not_empty_wait_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(\not_empty_wait_cnt_reg_n_0_[0] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \not_empty_wait_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(\not_empty_wait_cnt_reg_n_0_[1] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \not_empty_wait_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(\not_empty_wait_cnt_reg_n_0_[2] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \not_empty_wait_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(\not_empty_wait_cnt_reg_n_0_[3] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \not_empty_wait_cnt_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in[4]),
        .Q(\not_empty_wait_cnt_reg_n_0_[4] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \po_stg2_wrcal_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \po_stg2_wrcal_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_dqs_cnt_r),
        .Q(Q[1]),
        .R(1'b0));
  FDRE rd_active_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(E),
        .Q(rd_active_r1),
        .R(1'b0));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/rd_active_r3_reg_srl2 " *) 
  SRL16E rd_active_r3_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(rd_active_r1),
        .Q(rd_active_r3_reg_srl2_n_0));
  FDRE rd_active_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_rddata_en),
        .Q(E),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair444" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \tap_inc_wait_cnt[0]_i_1 
       (.I0(tap_inc_wait_cnt_reg[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair444" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \tap_inc_wait_cnt[1]_i_1 
       (.I0(tap_inc_wait_cnt_reg[1]),
        .I1(tap_inc_wait_cnt_reg[0]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair442" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \tap_inc_wait_cnt[2]_i_1 
       (.I0(tap_inc_wait_cnt_reg[2]),
        .I1(tap_inc_wait_cnt_reg[1]),
        .I2(tap_inc_wait_cnt_reg[0]),
        .O(p_0_in__0[2]));
  LUT5 #(
    .INIT(32'hFFFFAFEF)) 
    \tap_inc_wait_cnt[3]_i_1 
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r_reg_n_0_[1] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r_reg_n_0_[0] ),
        .I4(wrcal_done_reg_2),
        .O(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair442" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \tap_inc_wait_cnt[3]_i_2 
       (.I0(tap_inc_wait_cnt_reg[3]),
        .I1(tap_inc_wait_cnt_reg[1]),
        .I2(tap_inc_wait_cnt_reg[0]),
        .I3(tap_inc_wait_cnt_reg[2]),
        .O(p_0_in__0[3]));
  FDRE \tap_inc_wait_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(tap_inc_wait_cnt_reg[0]),
        .R(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  FDRE \tap_inc_wait_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(tap_inc_wait_cnt_reg[1]),
        .R(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  FDRE \tap_inc_wait_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(tap_inc_wait_cnt_reg[2]),
        .R(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  FDRE \tap_inc_wait_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(tap_inc_wait_cnt_reg[3]),
        .R(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \wl_tap_count_r[5]_i_3 
       (.I0(wrlvl_byte_redo),
        .I1(wrlvl_byte_redo_r),
        .O(done_dqs_dec237_out));
  (* SOFT_HLUTNM = "soft_lutpair428" *) 
  LUT5 #(
    .INIT(32'h45454500)) 
    wrcal_done_i_1
       (.I0(wrcal_done_reg_2),
        .I1(wrcal_sanity_chk_r_reg_n_0),
        .I2(wrcal_sanity_chk),
        .I3(wrcal_done_reg_0),
        .I4(cal2_done_r),
        .O(wrcal_done_i_1_n_0));
  FDRE wrcal_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_done_i_1_n_0),
        .Q(wrcal_done_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFCFFF00001000)) 
    \wrcal_dqs_cnt_r[0]_i_1 
       (.I0(\cal2_state_r_reg_n_0_[2] ),
        .I1(\cal2_state_r_reg_n_0_[3] ),
        .I2(\wrcal_dqs_cnt_r[0]_i_2_n_0 ),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .O(\wrcal_dqs_cnt_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h33330033B8B888B8)) 
    \wrcal_dqs_cnt_r[0]_i_2 
       (.I0(wrcal_sanity_chk),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(prech_done),
        .I3(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I4(wrcal_dqs_cnt_r),
        .I5(wrcal_sanity_chk_r_reg_n_0),
        .O(\wrcal_dqs_cnt_r[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair439" *) 
  LUT4 #(
    .INIT(16'h1F20)) 
    \wrcal_dqs_cnt_r[1]_i_1 
       (.I0(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(\wrcal_dqs_cnt_r[1]_i_2_n_0 ),
        .I3(wrcal_dqs_cnt_r),
        .O(\wrcal_dqs_cnt_r[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0040)) 
    \wrcal_dqs_cnt_r[1]_i_2 
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\wrcal_dqs_cnt_r[0]_i_2_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(\cal2_state_r_reg_n_0_[0] ),
        .O(\wrcal_dqs_cnt_r[1]_i_2_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \wrcal_dqs_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrcal_dqs_cnt_r[0]_i_1_n_0 ),
        .Q(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .R(wrcal_sanity_chk_done_reg_2));
  (* syn_maxfan = "10" *) 
  FDRE \wrcal_dqs_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrcal_dqs_cnt_r[1]_i_1_n_0 ),
        .Q(wrcal_dqs_cnt_r),
        .R(wrcal_sanity_chk_done_reg_2));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_r2_reg_srl2 " *) 
  SRL16E wrcal_pat_resume_r2_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(wrcal_pat_resume_r),
        .Q(wrcal_pat_resume_r2_reg_srl2_n_0));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    wrcal_pat_resume_r_i_1
       (.I0(\cal2_state_r_reg_n_0_[2] ),
        .I1(idelay_ld_done_reg_n_0),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(wrcal_pat_resume_r_i_2_n_0),
        .I4(wrcal_pat_resume_r),
        .O(wrcal_pat_resume_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h08000800033C003C)) 
    wrcal_pat_resume_r_i_2
       (.I0(\cal2_state_r[3]_i_7_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[0] ),
        .I2(\cal2_state_r_reg_n_0_[3] ),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(wrcal_pat_resume_r_i_3_n_0),
        .I5(\cal2_state_r_reg_n_0_[1] ),
        .O(wrcal_pat_resume_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    wrcal_pat_resume_r_i_3
       (.I0(tap_inc_wait_cnt_reg[2]),
        .I1(idelay_ld_done_reg_n_0),
        .I2(tap_inc_wait_cnt_reg[0]),
        .I3(tap_inc_wait_cnt_reg[1]),
        .I4(wrcal_sanity_chk_r_reg_n_0),
        .I5(tap_inc_wait_cnt_reg[3]),
        .O(wrcal_pat_resume_r_i_3_n_0));
  FDRE wrcal_pat_resume_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_pat_resume_r_i_1_n_0),
        .Q(wrcal_pat_resume_r),
        .R(wrcal_sanity_chk_done_reg_2));
  FDRE wrcal_pat_resume_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_pat_resume_r2_reg_srl2_n_0),
        .Q(wrcal_resume_w),
        .R(1'b0));
  FDRE wrcal_prech_req_reg
       (.C(CLK),
        .CE(1'b1),
        .D(cal2_prech_req_r),
        .Q(wrcal_prech_req),
        .R(wrcal_sanity_chk_done_reg_2));
  LUT6 #(
    .INIT(64'hFFFFFFFF00004000)) 
    wrcal_sanity_chk_done_i_1
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(wrcal_sanity_chk_r_reg_n_0),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(wrcal_sanity_chk_done_reg_0),
        .O(wrcal_sanity_chk_done_i_1_n_0));
  FDRE wrcal_sanity_chk_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_sanity_chk_done_i_1_n_0),
        .Q(wrcal_sanity_chk_done_reg_0),
        .R(wrcal_sanity_chk_done_reg_2));
  FDRE wrcal_sanity_chk_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrcal_sanity_chk),
        .Q(wrcal_sanity_chk_r_reg_n_0),
        .R(1'b0));
  FDRE wrlvl_byte_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_byte_done),
        .Q(wrlvl_byte_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0EFFFFFF0E000000)) 
    wrlvl_byte_redo_i_1
       (.I0(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(wrlvl_byte_redo_i_2_n_0),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(wrlvl_byte_redo),
        .O(wrlvl_byte_redo_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000022222E22)) 
    wrlvl_byte_redo_i_2
       (.I0(wrlvl_byte_redo_i_3_n_0),
        .I1(\cal2_state_r_reg_n_0_[1] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(wrlvl_byte_done),
        .I4(wrlvl_byte_done_r),
        .I5(\cal2_state_r_reg_n_0_[3] ),
        .O(wrlvl_byte_redo_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000002220)) 
    wrlvl_byte_redo_i_3
       (.I0(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .I1(wrcal_sanity_chk_r_reg_n_0),
        .I2(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I3(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I4(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),
        .I5(\cal2_state_r_reg_n_0_[2] ),
        .O(wrlvl_byte_redo_i_3_n_0));
  FDRE wrlvl_byte_redo_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_byte_redo_i_1_n_0),
        .Q(wrlvl_byte_redo),
        .R(wrcal_sanity_chk_done_reg_2));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_wrlvl
   (wrlvl_byte_redo_r,
    dqs_po_dec_done_reg_0,
    dqs_po_en_stg2_f,
    po_cnt_dec_reg_0,
    wr_level_done_reg_0,
    wrlvl_rank_done,
    dqs_po_stg2_f_incdec,
    \gen_byte_sel_div2.calib_in_common_reg ,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    \gen_byte_sel_div2.calib_in_common_reg_1 ,
    dqs_wl_po_stg2_c_incdec_reg_0,
    \calib_sel_reg[1] ,
    \calib_sel_reg[1]_0 ,
    \gen_byte_sel_div2.calib_in_common_reg_2 ,
    \calib_sel_reg[0] ,
    \gen_byte_sel_div2.calib_in_common_reg_3 ,
    \final_coarse_tap_reg[1][1]_0 ,
    \final_coarse_tap_reg[1][0]_0 ,
    \final_coarse_tap_reg[0][0]_0 ,
    done_dqs_tap_inc,
    \gen_byte_sel_div2.byte_sel_cnt_reg[1] ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0] ,
    \gen_byte_sel_div2.ctl_lane_sel_reg[1] ,
    cmd_delay_start0,
    wrlvl_byte_done,
    Q,
    CLK,
    wrlvl_byte_redo,
    wr_level_start_r_reg_0,
    \smallest_reg[1][0]_0 ,
    \wl_dqs_tap_count_r_reg[0][0][2]_0 ,
    phaser_out,
    phaser_out_0,
    phaser_out_1,
    calib_zero_inputs,
    po_enstg2_f,
    ck_po_stg2_f_indec,
    wl_sm_start,
    done_dqs_dec237_out,
    dqs_po_stg2_f_incdec_reg_0,
    \dqs_count_r_reg[1]_0 ,
    \FSM_sequential_wl_state_r[4]_i_4_0 ,
    \po_rdval_cnt_reg[8]_0 ,
    \wrlvl_redo_corse_inc[1]_i_2_0 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]_1 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]_2 ,
    RSTB,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_1 ,
    \calib_sel_reg[0]_0 ,
    calib_sel15_out,
    \calib_sel_reg[0]_1 ,
    \calib_sel_reg[0]_2 ,
    calib_sel0,
    \calib_sel_reg[0]_3 ,
    in0,
    app_rd_data,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ,
    my_empty,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ,
    \single_rank.done_dqs_dec_reg_0 ,
    SS);
  output wrlvl_byte_redo_r;
  output dqs_po_dec_done_reg_0;
  output dqs_po_en_stg2_f;
  output po_cnt_dec_reg_0;
  output wr_level_done_reg_0;
  output wrlvl_rank_done;
  output dqs_po_stg2_f_incdec;
  output \gen_byte_sel_div2.calib_in_common_reg ;
  output \gen_byte_sel_div2.calib_in_common_reg_0 ;
  output \gen_byte_sel_div2.calib_in_common_reg_1 ;
  output dqs_wl_po_stg2_c_incdec_reg_0;
  output \calib_sel_reg[1] ;
  output \calib_sel_reg[1]_0 ;
  output \gen_byte_sel_div2.calib_in_common_reg_2 ;
  output \calib_sel_reg[0] ;
  output \gen_byte_sel_div2.calib_in_common_reg_3 ;
  output \final_coarse_tap_reg[1][1]_0 ;
  output [0:0]\final_coarse_tap_reg[1][0]_0 ;
  output [0:0]\final_coarse_tap_reg[0][0]_0 ;
  output done_dqs_tap_inc;
  output \gen_byte_sel_div2.byte_sel_cnt_reg[1] ;
  output \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  output \gen_byte_sel_div2.ctl_lane_sel_reg[1] ;
  output cmd_delay_start0;
  output wrlvl_byte_done;
  input [0:0]Q;
  input CLK;
  input wrlvl_byte_redo;
  input wr_level_start_r_reg_0;
  input [1:0]\smallest_reg[1][0]_0 ;
  input [0:0]\wl_dqs_tap_count_r_reg[0][0][2]_0 ;
  input phaser_out;
  input phaser_out_0;
  input phaser_out_1;
  input calib_zero_inputs;
  input [0:0]po_enstg2_f;
  input ck_po_stg2_f_indec;
  input wl_sm_start;
  input done_dqs_dec237_out;
  input dqs_po_stg2_f_incdec_reg_0;
  input [1:0]\dqs_count_r_reg[1]_0 ;
  input \FSM_sequential_wl_state_r[4]_i_4_0 ;
  input [8:0]\po_rdval_cnt_reg[8]_0 ;
  input \wrlvl_redo_corse_inc[1]_i_2_0 ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[1]_1 ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[1]_2 ;
  input RSTB;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[0]_1 ;
  input \calib_sel_reg[0]_0 ;
  input calib_sel15_out;
  input \calib_sel_reg[0]_1 ;
  input \calib_sel_reg[0]_2 ;
  input calib_sel0;
  input \calib_sel_reg[0]_3 ;
  input in0;
  input [13:0]app_rd_data;
  input [0:0]\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  input [0:0]\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  input [0:0]my_empty;
  input [0:0]\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  input [0:0]\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  input \single_rank.done_dqs_dec_reg_0 ;
  input [0:0]SS;

  wire CLK;
  wire \FSM_sequential_wl_state_r[0]_i_10_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_11_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_12_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_1_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_2_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_3_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_4_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_5_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_6_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_7_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_8_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_9_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_10_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_11_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_1_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_2_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_3_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_4_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_5_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_6_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_7_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_8_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_9_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_10_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_11_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_12_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_13_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_14_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_1_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_2_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_3_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_4_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_5_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_6_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_7_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_8_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_9_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_1_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_2_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_3_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_4_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_5_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_6_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_7_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_8_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_9_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_10_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_11_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_12_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_13_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_14_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_15_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_16_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_17_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_18_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_1_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_20_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_21_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_2_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_3_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_4_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_4_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_5_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_6_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_7_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_8_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_9_n_0 ;
  wire [0:0]Q;
  wire RSTB;
  wire [0:0]SS;
  wire [13:0]app_rd_data;
  wire calib_sel0;
  wire calib_sel15_out;
  wire \calib_sel_reg[0] ;
  wire \calib_sel_reg[0]_0 ;
  wire \calib_sel_reg[0]_1 ;
  wire \calib_sel_reg[0]_2 ;
  wire \calib_sel_reg[0]_3 ;
  wire \calib_sel_reg[1] ;
  wire \calib_sel_reg[1]_0 ;
  wire calib_zero_inputs;
  wire ck_po_stg2_f_indec;
  wire cmd_delay_start0;
  wire [2:0]corse_cnt;
  wire \corse_cnt[0][0]_i_1_n_0 ;
  wire \corse_cnt[0][0]_i_3_n_0 ;
  wire \corse_cnt[0][0]_i_4_n_0 ;
  wire \corse_cnt[0][0]_i_5_n_0 ;
  wire \corse_cnt[0][1]_i_1_n_0 ;
  wire \corse_cnt[0][1]_i_3_n_0 ;
  wire \corse_cnt[0][1]_i_4_n_0 ;
  wire \corse_cnt[0][2]_i_1_n_0 ;
  wire \corse_cnt[0][2]_i_3_n_0 ;
  wire \corse_cnt[0][2]_i_4_n_0 ;
  wire \corse_cnt[0][2]_i_5_n_0 ;
  wire \corse_cnt[0][2]_i_6_n_0 ;
  wire \corse_cnt[0][2]_i_7_n_0 ;
  wire \corse_cnt[0][2]_i_8_n_0 ;
  wire \corse_cnt[1][0]_i_1_n_0 ;
  wire \corse_cnt[1][1]_i_1_n_0 ;
  wire \corse_cnt[1][2]_i_1_n_0 ;
  wire \corse_cnt[1][2]_i_2_n_0 ;
  wire \corse_cnt[1][2]_i_3_n_0 ;
  wire \corse_cnt_reg_n_0_[0][0] ;
  wire \corse_cnt_reg_n_0_[0][1] ;
  wire \corse_cnt_reg_n_0_[0][2] ;
  wire \corse_cnt_reg_n_0_[1][0] ;
  wire \corse_cnt_reg_n_0_[1][1] ;
  wire \corse_cnt_reg_n_0_[1][2] ;
  wire [2:2]corse_dec;
  wire \corse_dec[0][0]_i_1_n_0 ;
  wire \corse_dec[0][1]_i_1_n_0 ;
  wire \corse_dec[0][2]_i_1_n_0 ;
  wire \corse_dec[0][2]_i_2_n_0 ;
  wire \corse_dec[1][0]_i_1_n_0 ;
  wire \corse_dec[1][1]_i_1_n_0 ;
  wire \corse_dec[1][1]_i_2_n_0 ;
  wire \corse_dec[1][1]_i_3_n_0 ;
  wire \corse_dec[1][2]_i_1_n_0 ;
  wire \corse_dec[1][2]_i_3_n_0 ;
  wire \corse_dec[1][2]_i_4_n_0 ;
  wire [2:0]\corse_dec_reg[0]_7 ;
  wire [2:0]\corse_dec_reg[1]_6 ;
  wire \corse_inc[0][0]_i_1_n_0 ;
  wire \corse_inc[0][1]_i_1_n_0 ;
  wire \corse_inc[0][2]_i_1_n_0 ;
  wire \corse_inc[0][2]_i_2_n_0 ;
  wire \corse_inc[1][0]_i_1_n_0 ;
  wire \corse_inc[1][0]_i_2_n_0 ;
  wire \corse_inc[1][1]_i_1_n_0 ;
  wire \corse_inc[1][1]_i_2_n_0 ;
  wire \corse_inc[1][2]_i_1_n_0 ;
  wire \corse_inc[1][2]_i_2_n_0 ;
  wire \corse_inc[1][2]_i_3_n_0 ;
  wire \corse_inc[1][2]_i_4_n_0 ;
  wire \corse_inc[1][2]_i_5_n_0 ;
  wire \corse_inc[1][2]_i_6_n_0 ;
  wire \corse_inc[1][2]_i_7_n_0 ;
  wire \corse_inc_reg_n_0_[0][0] ;
  wire \corse_inc_reg_n_0_[0][1] ;
  wire \corse_inc_reg_n_0_[0][2] ;
  wire \corse_inc_reg_n_0_[1][0] ;
  wire \corse_inc_reg_n_0_[1][1] ;
  wire \corse_inc_reg_n_0_[1][2] ;
  wire done_dqs_dec237_out;
  wire done_dqs_tap_inc;
  wire dq_cnt_inc_i_1_n_0;
  wire dq_cnt_inc_i_2_n_0;
  wire dq_cnt_inc_i_3_n_0;
  wire [1:0]dqs_count_r;
  wire \dqs_count_r[0]_i_1_n_0 ;
  wire \dqs_count_r[0]_i_2_n_0 ;
  wire \dqs_count_r[0]_i_3_n_0 ;
  wire \dqs_count_r[0]_i_4_n_0 ;
  wire \dqs_count_r[0]_i_5_n_0 ;
  wire \dqs_count_r[0]_i_6_n_0 ;
  wire \dqs_count_r[0]_i_7_n_0 ;
  wire \dqs_count_r[0]_i_8_n_0 ;
  wire \dqs_count_r[0]_i_9_n_0 ;
  wire \dqs_count_r[1]_i_10_n_0 ;
  wire \dqs_count_r[1]_i_1_n_0 ;
  wire \dqs_count_r[1]_i_2_n_0 ;
  wire \dqs_count_r[1]_i_3_n_0 ;
  wire \dqs_count_r[1]_i_4_n_0 ;
  wire \dqs_count_r[1]_i_5_n_0 ;
  wire \dqs_count_r[1]_i_6_n_0 ;
  wire \dqs_count_r[1]_i_7_n_0 ;
  wire \dqs_count_r[1]_i_8_n_0 ;
  wire \dqs_count_r[1]_i_9_n_0 ;
  wire \dqs_count_r_reg[0]_rep_n_0 ;
  wire [1:0]\dqs_count_r_reg[1]_0 ;
  wire dqs_po_dec_done_reg_0;
  wire dqs_po_en_stg2_f;
  wire dqs_po_en_stg2_f_i_1_n_0;
  wire dqs_po_stg2_f_incdec;
  wire dqs_po_stg2_f_incdec_i_1_n_0;
  wire dqs_po_stg2_f_incdec_i_2_n_0;
  wire dqs_po_stg2_f_incdec_reg_0;
  wire dqs_wl_po_stg2_c_incdec_i_1_n_0;
  wire dqs_wl_po_stg2_c_incdec_reg_0;
  wire [0:0]\final_coarse_tap_reg[0][0]_0 ;
  wire [0:0]\final_coarse_tap_reg[1][0]_0 ;
  wire \final_coarse_tap_reg[1][1]_0 ;
  wire \final_coarse_tap_reg_n_0_[0][1] ;
  wire \final_coarse_tap_reg_n_0_[0][2] ;
  wire \final_coarse_tap_reg_n_0_[1][1] ;
  wire \final_coarse_tap_reg_n_0_[1][2] ;
  wire [5:0]fine_dec_cnt;
  wire \fine_dec_cnt[3]_i_2_n_0 ;
  wire \fine_dec_cnt[4]_i_2_n_0 ;
  wire \fine_dec_cnt[5]_i_10_n_0 ;
  wire \fine_dec_cnt[5]_i_11_n_0 ;
  wire \fine_dec_cnt[5]_i_1_n_0 ;
  wire \fine_dec_cnt[5]_i_3_n_0 ;
  wire \fine_dec_cnt[5]_i_4_n_0 ;
  wire \fine_dec_cnt[5]_i_5_n_0 ;
  wire \fine_dec_cnt[5]_i_6_n_0 ;
  wire \fine_dec_cnt[5]_i_7_n_0 ;
  wire \fine_dec_cnt[5]_i_8_n_0 ;
  wire \fine_dec_cnt[5]_i_9_n_0 ;
  wire \fine_dec_cnt_reg_n_0_[0] ;
  wire \fine_dec_cnt_reg_n_0_[1] ;
  wire \fine_dec_cnt_reg_n_0_[2] ;
  wire \fine_dec_cnt_reg_n_0_[3] ;
  wire \fine_dec_cnt_reg_n_0_[4] ;
  wire \fine_dec_cnt_reg_n_0_[5] ;
  wire [4:0]fine_inc;
  wire \fine_inc[0][5]_i_1_n_0 ;
  wire \fine_inc[0][5]_i_2_n_0 ;
  wire \fine_inc[0][5]_i_3_n_0 ;
  wire \fine_inc[1][0]_i_1_n_0 ;
  wire \fine_inc[1][0]_i_2_n_0 ;
  wire \fine_inc[1][1]_i_1_n_0 ;
  wire \fine_inc[1][1]_i_2_n_0 ;
  wire \fine_inc[1][2]_i_1_n_0 ;
  wire \fine_inc[1][2]_i_2_n_0 ;
  wire \fine_inc[1][2]_i_3_n_0 ;
  wire \fine_inc[1][3]_i_1_n_0 ;
  wire \fine_inc[1][3]_i_2_n_0 ;
  wire \fine_inc[1][3]_i_3_n_0 ;
  wire \fine_inc[1][3]_i_4_n_0 ;
  wire \fine_inc[1][4]_i_1_n_0 ;
  wire \fine_inc[1][4]_i_2_n_0 ;
  wire \fine_inc[1][5]_i_1_n_0 ;
  wire \fine_inc[1][5]_i_2_n_0 ;
  wire \fine_inc[1][5]_i_3_n_0 ;
  wire \fine_inc[1][5]_i_4_n_0 ;
  wire \fine_inc[1][5]_i_5_n_0 ;
  wire \fine_inc[1][5]_i_6_n_0 ;
  wire \fine_inc[1][5]_i_7_n_0 ;
  wire \fine_inc[1][5]_i_8_n_0 ;
  wire [5:0]\fine_inc_reg[0]_3 ;
  wire [5:0]\fine_inc_reg[1]_2 ;
  wire flag_ck_negedge09_out;
  wire flag_ck_negedge_i_1_n_0;
  wire flag_ck_negedge_i_2_n_0;
  wire flag_ck_negedge_i_3_n_0;
  wire flag_ck_negedge_i_5_n_0;
  wire flag_ck_negedge_i_6_n_0;
  wire flag_ck_negedge_i_7_n_0;
  wire flag_ck_negedge_reg_n_0;
  wire flag_init;
  wire flag_init_i_1_n_0;
  wire flag_init_i_2_n_0;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0]_1 ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[1] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[1]_1 ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[1]_2 ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_1 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_2 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_3 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[1] ;
  wire \gen_final_tap[0].final_val_reg_n_0_[0][0] ;
  wire \gen_final_tap[0].final_val_reg_n_0_[0][1] ;
  wire \gen_final_tap[0].final_val_reg_n_0_[0][2] ;
  wire \gen_final_tap[0].final_val_reg_n_0_[0][3] ;
  wire \gen_final_tap[0].final_val_reg_n_0_[0][4] ;
  wire \gen_final_tap[0].final_val_reg_n_0_[0][5] ;
  wire \gen_final_tap[1].final_val_reg_n_0_[1][0] ;
  wire \gen_final_tap[1].final_val_reg_n_0_[1][1] ;
  wire \gen_final_tap[1].final_val_reg_n_0_[1][2] ;
  wire \gen_final_tap[1].final_val_reg_n_0_[1][3] ;
  wire \gen_final_tap[1].final_val_reg_n_0_[1][4] ;
  wire \gen_final_tap[1].final_val_reg_n_0_[1][5] ;
  wire \gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ;
  wire [0:0]\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  wire [0:0]\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ;
  wire \gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ;
  wire \gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ;
  wire [0:0]\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  wire [0:0]\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ;
  wire in0;
  wire \incdec_wait_cnt[3]_i_1_n_0 ;
  wire [3:0]incdec_wait_cnt_reg;
  wire inhibit_edge_detect_r_i_1_n_0;
  wire inhibit_edge_detect_r_i_2_n_0;
  wire inhibit_edge_detect_r_i_3_n_0;
  wire inhibit_edge_detect_r_i_4_n_0;
  wire inhibit_edge_detect_r_i_5_n_0;
  wire inhibit_edge_detect_r_i_6_n_0;
  wire inhibit_edge_detect_r_i_7_n_0;
  wire inhibit_edge_detect_r_i_8_n_0;
  wire inhibit_edge_detect_r_i_9_n_0;
  wire inhibit_edge_detect_r_reg_n_0;
  wire [5:0]largest;
  wire [0:0]my_empty;
  wire p_0_in;
  wire p_0_in__0;
  wire [3:0]p_0_in__0__0;
  wire [3:0]p_0_in__1;
  wire p_45_out;
  wire phaser_out;
  wire phaser_out_0;
  wire phaser_out_1;
  wire phy_ctl_ready_r4_reg_srl4_n_0;
  wire phy_ctl_ready_r5;
  wire phy_ctl_ready_r6_reg_n_0;
  wire po_cnt_dec_i_1_n_0;
  wire po_cnt_dec_i_2_n_0;
  wire po_cnt_dec_reg_0;
  wire po_dec_done;
  wire po_dec_done_i_1_n_0;
  wire po_dec_done_i_2_n_0;
  wire [0:0]po_enstg2_f;
  wire [8:0]po_rdval_cnt;
  wire \po_rdval_cnt[0]_i_1_n_0 ;
  wire \po_rdval_cnt[1]_i_1_n_0 ;
  wire \po_rdval_cnt[2]_i_1_n_0 ;
  wire \po_rdval_cnt[3]_i_1_n_0 ;
  wire \po_rdval_cnt[3]_i_2_n_0 ;
  wire \po_rdval_cnt[4]_i_1_n_0 ;
  wire \po_rdval_cnt[4]_i_2_n_0 ;
  wire \po_rdval_cnt[5]_i_1_n_0 ;
  wire \po_rdval_cnt[6]_i_1_n_0 ;
  wire \po_rdval_cnt[6]_i_2_n_0 ;
  wire \po_rdval_cnt[6]_i_3_n_0 ;
  wire \po_rdval_cnt[7]_i_1_n_0 ;
  wire \po_rdval_cnt[7]_i_2_n_0 ;
  wire \po_rdval_cnt[7]_i_3_n_0 ;
  wire \po_rdval_cnt[8]_i_1_n_0 ;
  wire \po_rdval_cnt[8]_i_2_n_0 ;
  wire \po_rdval_cnt[8]_i_3_n_0 ;
  wire \po_rdval_cnt[8]_i_4_n_0 ;
  wire [8:0]\po_rdval_cnt_reg[8]_0 ;
  wire [2:2]po_stg2_cincdec;
  wire rank_cnt_r;
  wire \rank_cnt_r[0]_i_1_n_0 ;
  wire \rank_cnt_r[1]_i_1_n_0 ;
  wire \rank_cnt_r_reg_n_0_[0] ;
  wire \rank_cnt_r_reg_n_0_[1] ;
  wire \rd_data_edge_detect_r[0]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[0]_i_2_n_0 ;
  wire \rd_data_edge_detect_r[1]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[1]_i_2_n_0 ;
  wire \rd_data_edge_detect_r[1]_i_3_n_0 ;
  wire \rd_data_edge_detect_r[1]_i_4_n_0 ;
  wire \rd_data_edge_detect_r[1]_i_5_n_0 ;
  wire \rd_data_edge_detect_r[1]_i_6_n_0 ;
  wire \rd_data_edge_detect_r_reg_n_0_[0] ;
  wire \rd_data_edge_detect_r_reg_n_0_[1] ;
  wire rd_data_previous_r0;
  wire \rd_data_previous_r[0]_i_1_n_0 ;
  wire \rd_data_previous_r[1]_i_1_n_0 ;
  wire \rd_data_previous_r_reg_n_0_[0] ;
  wire \rd_data_previous_r_reg_n_0_[1] ;
  wire \single_rank.done_dqs_dec_i_1_n_0 ;
  wire \single_rank.done_dqs_dec_reg_0 ;
  wire \smallest[0][5]_i_1_n_0 ;
  wire \smallest[1][5]_i_1_n_0 ;
  wire [5:0]\smallest_reg[0]_4 ;
  wire [1:0]\smallest_reg[1][0]_0 ;
  wire [5:0]\smallest_reg[1]_5 ;
  wire stable_cnt;
  wire stable_cnt0;
  wire \stable_cnt[3]_i_10_n_0 ;
  wire \stable_cnt[3]_i_4_n_0 ;
  wire \stable_cnt[3]_i_5_n_0 ;
  wire \stable_cnt[3]_i_6_n_0 ;
  wire \stable_cnt[3]_i_7_n_0 ;
  wire \stable_cnt[3]_i_8_n_0 ;
  wire \stable_cnt[3]_i_9_n_0 ;
  wire \stable_cnt_reg_n_0_[0] ;
  wire \stable_cnt_reg_n_0_[1] ;
  wire \stable_cnt_reg_n_0_[2] ;
  wire \stable_cnt_reg_n_0_[3] ;
  wire wait_cnt0;
  wire [3:0]wait_cnt0__0;
  wire \wait_cnt[1]_i_1_n_0 ;
  wire [3:0]wait_cnt_reg;
  wire \wl_corse_cnt[0][0][0]_i_1_n_0 ;
  wire \wl_corse_cnt[0][0][1]_i_1_n_0 ;
  wire \wl_corse_cnt[0][0][2]_i_1_n_0 ;
  wire [2:0]\wl_corse_cnt_reg[0][0]_8 ;
  wire [2:0]\wl_corse_cnt_reg[0][1]_9 ;
  wire \wl_dqs_tap_count_r[0][0][5]_i_1_n_0 ;
  wire \wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ;
  wire \wl_dqs_tap_count_r[0][0][5]_i_3_n_0 ;
  wire \wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ;
  wire [0:0]\wl_dqs_tap_count_r_reg[0][0][2]_0 ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][5] ;
  wire wl_edge_detect_valid_r;
  wire wl_edge_detect_valid_r_i_1_n_0;
  wire wl_edge_detect_valid_r_reg_n_0;
  wire wl_sm_start;
  wire \wl_state_r1[0]_i_1_n_0 ;
  wire \wl_state_r1[1]_i_1_n_0 ;
  wire \wl_state_r1[2]_i_1_n_0 ;
  wire \wl_state_r1[3]_i_1_n_0 ;
  wire \wl_state_r1[4]_i_1_n_0 ;
  wire \wl_state_r1_reg_n_0_[0] ;
  wire \wl_state_r1_reg_n_0_[1] ;
  wire \wl_state_r1_reg_n_0_[2] ;
  wire \wl_state_r1_reg_n_0_[3] ;
  wire \wl_state_r1_reg_n_0_[4] ;
  wire [4:0]wl_state_r__0;
  wire [5:0]wl_tap_count_r;
  wire \wl_tap_count_r[0]_i_2_n_0 ;
  wire \wl_tap_count_r[1]_i_2_n_0 ;
  wire \wl_tap_count_r[2]_i_2_n_0 ;
  wire \wl_tap_count_r[3]_i_2_n_0 ;
  wire \wl_tap_count_r[4]_i_2_n_0 ;
  wire \wl_tap_count_r[4]_i_3_n_0 ;
  wire \wl_tap_count_r[5]_i_1_n_0 ;
  wire \wl_tap_count_r[5]_i_4_n_0 ;
  wire \wl_tap_count_r[5]_i_5_n_0 ;
  wire \wl_tap_count_r[5]_i_6_n_0 ;
  wire \wl_tap_count_r_reg_n_0_[0] ;
  wire \wl_tap_count_r_reg_n_0_[1] ;
  wire \wl_tap_count_r_reg_n_0_[2] ;
  wire \wl_tap_count_r_reg_n_0_[3] ;
  wire \wl_tap_count_r_reg_n_0_[4] ;
  wire \wl_tap_count_r_reg_n_0_[5] ;
  wire wr_level_done_i_1_n_0;
  wire wr_level_done_r1;
  wire wr_level_done_r2;
  wire wr_level_done_r3;
  wire wr_level_done_r4;
  wire wr_level_done_r5;
  wire wr_level_done_r_i_1_n_0;
  wire wr_level_done_r_i_2_n_0;
  wire wr_level_done_r_reg_n_0;
  wire wr_level_done_reg_0;
  wire wr_level_start_r;
  wire wr_level_start_r_reg_0;
  wire wrlvl_byte_done;
  wire wrlvl_byte_done_i_1_n_0;
  wire wrlvl_byte_redo;
  wire wrlvl_byte_redo_r;
  wire wrlvl_rank_done;
  wire wrlvl_rank_done_r_i_1_n_0;
  wire wrlvl_rank_done_r_i_2_n_0;
  wire \wrlvl_redo_corse_inc[0]_i_1_n_0 ;
  wire \wrlvl_redo_corse_inc[1]_i_1_n_0 ;
  wire \wrlvl_redo_corse_inc[1]_i_2_0 ;
  wire \wrlvl_redo_corse_inc[1]_i_2_n_0 ;
  wire \wrlvl_redo_corse_inc[1]_i_3_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_1_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_2_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_3_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_4_n_0 ;
  wire \wrlvl_redo_corse_inc_reg_n_0_[0] ;
  wire \wrlvl_redo_corse_inc_reg_n_0_[1] ;
  wire \wrlvl_redo_corse_inc_reg_n_0_[2] ;

  LUT6 #(
    .INIT(64'h00000000FFFFEAAA)) 
    \FSM_sequential_wl_state_r[0]_i_1 
       (.I0(\FSM_sequential_wl_state_r[0]_i_2_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\FSM_sequential_wl_state_r[0]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r[0]_i_4_n_0 ),
        .I4(\FSM_sequential_wl_state_r[0]_i_5_n_0 ),
        .I5(\FSM_sequential_wl_state_r[0]_i_6_n_0 ),
        .O(\FSM_sequential_wl_state_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair276" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \FSM_sequential_wl_state_r[0]_i_10 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[0]),
        .I2(inhibit_edge_detect_r_i_3_n_0),
        .O(\FSM_sequential_wl_state_r[0]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair269" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_wl_state_r[0]_i_11 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[1]),
        .O(\FSM_sequential_wl_state_r[0]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair236" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \FSM_sequential_wl_state_r[0]_i_12 
       (.I0(\wl_tap_count_r_reg_n_0_[5] ),
        .I1(\wl_tap_count_r_reg_n_0_[4] ),
        .I2(\wl_tap_count_r_reg_n_0_[3] ),
        .O(\FSM_sequential_wl_state_r[0]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h2000022200000222)) 
    \FSM_sequential_wl_state_r[0]_i_2 
       (.I0(\FSM_sequential_wl_state_r[0]_i_7_n_0 ),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[3]),
        .I3(wl_state_r__0[2]),
        .I4(wl_state_r__0[0]),
        .I5(wr_level_done_r5),
        .O(\FSM_sequential_wl_state_r[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair287" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \FSM_sequential_wl_state_r[0]_i_3 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[2]),
        .O(\FSM_sequential_wl_state_r[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4000)) 
    \FSM_sequential_wl_state_r[0]_i_4 
       (.I0(wl_state_r__0[3]),
        .I1(wrlvl_byte_redo),
        .I2(\rd_data_edge_detect_r[1]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r[2]_i_10_n_0 ),
        .I4(\FSM_sequential_wl_state_r[0]_i_8_n_0 ),
        .O(\FSM_sequential_wl_state_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h000000000C0C0EFE)) 
    \FSM_sequential_wl_state_r[0]_i_5 
       (.I0(wl_state_r__0[3]),
        .I1(\FSM_sequential_wl_state_r[0]_i_9_n_0 ),
        .I2(\FSM_sequential_wl_state_r[0]_i_10_n_0 ),
        .I3(\FSM_sequential_wl_state_r[0]_i_3_n_0 ),
        .I4(wl_state_r__0[0]),
        .I5(wl_state_r__0[1]),
        .O(\FSM_sequential_wl_state_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000002C00)) 
    \FSM_sequential_wl_state_r[0]_i_6 
       (.I0(\FSM_sequential_wl_state_r[1]_i_6_n_0 ),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[3]),
        .I3(\fine_inc[1][5]_i_4_n_0 ),
        .I4(\FSM_sequential_wl_state_r[0]_i_11_n_0 ),
        .I5(\fine_inc[1][5]_i_5_n_0 ),
        .O(\FSM_sequential_wl_state_r[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFEFFFFFFFFFF)) 
    \FSM_sequential_wl_state_r[0]_i_7 
       (.I0(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I2(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .I3(wrlvl_byte_redo),
        .I4(wl_state_r__0[0]),
        .I5(wl_state_r__0[3]),
        .O(\FSM_sequential_wl_state_r[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFF44FFFF000F0000)) 
    \FSM_sequential_wl_state_r[0]_i_8 
       (.I0(\FSM_sequential_wl_state_r[3]_i_7_n_0 ),
        .I1(\FSM_sequential_wl_state_r[0]_i_12_n_0 ),
        .I2(\FSM_sequential_wl_state_r[4]_i_18_n_0 ),
        .I3(wl_state_r__0[2]),
        .I4(wl_state_r__0[3]),
        .I5(wl_state_r__0[0]),
        .O(\FSM_sequential_wl_state_r[0]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFBBF0FFFF00F0FF)) 
    \FSM_sequential_wl_state_r[0]_i_9 
       (.I0(\FSM_sequential_wl_state_r[2]_i_10_n_0 ),
        .I1(wrlvl_byte_redo),
        .I2(\fine_dec_cnt[5]_i_5_n_0 ),
        .I3(wl_state_r__0[3]),
        .I4(wl_state_r__0[4]),
        .I5(inhibit_edge_detect_r_i_3_n_0),
        .O(\FSM_sequential_wl_state_r[0]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF05C5)) 
    \FSM_sequential_wl_state_r[1]_i_1 
       (.I0(\FSM_sequential_wl_state_r[1]_i_2_n_0 ),
        .I1(wl_state_r__0[2]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(\FSM_sequential_wl_state_r[1]_i_3_n_0 ),
        .I5(\FSM_sequential_wl_state_r[1]_i_4_n_0 ),
        .O(\FSM_sequential_wl_state_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair289" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_wl_state_r[1]_i_10 
       (.I0(wl_state_r__0[0]),
        .I1(wl_state_r__0[2]),
        .O(\FSM_sequential_wl_state_r[1]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair267" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_wl_state_r[1]_i_11 
       (.I0(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .O(\FSM_sequential_wl_state_r[1]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFF4F4F4)) 
    \FSM_sequential_wl_state_r[1]_i_2 
       (.I0(\FSM_sequential_wl_state_r[4]_i_18_n_0 ),
        .I1(wl_state_r__0[4]),
        .I2(\FSM_sequential_wl_state_r[1]_i_5_n_0 ),
        .I3(\fine_inc[1][5]_i_5_n_0 ),
        .I4(\FSM_sequential_wl_state_r[1]_i_6_n_0 ),
        .I5(\FSM_sequential_wl_state_r[1]_i_7_n_0 ),
        .O(\FSM_sequential_wl_state_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0A0A0A0AC00000F0)) 
    \FSM_sequential_wl_state_r[1]_i_3 
       (.I0(inhibit_edge_detect_r_i_3_n_0),
        .I1(\FSM_sequential_wl_state_r[4]_i_12_n_0 ),
        .I2(wl_state_r__0[1]),
        .I3(wl_state_r__0[3]),
        .I4(wl_state_r__0[2]),
        .I5(wl_state_r__0[4]),
        .O(\FSM_sequential_wl_state_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEAE0000000000)) 
    \FSM_sequential_wl_state_r[1]_i_4 
       (.I0(\FSM_sequential_wl_state_r[1]_i_8_n_0 ),
        .I1(\FSM_sequential_wl_state_r[1]_i_9_n_0 ),
        .I2(\fine_inc[1][5]_i_5_n_0 ),
        .I3(wl_state_r__0[4]),
        .I4(\FSM_sequential_wl_state_r[3]_i_8_n_0 ),
        .I5(\FSM_sequential_wl_state_r[1]_i_10_n_0 ),
        .O(\FSM_sequential_wl_state_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h77777777777777F7)) 
    \FSM_sequential_wl_state_r[1]_i_5 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[3]),
        .I2(wrlvl_byte_redo),
        .I3(\FSM_sequential_wl_state_r[1]_i_11_n_0 ),
        .I4(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .I5(wl_state_r__0[4]),
        .O(\FSM_sequential_wl_state_r[1]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT5 #(
    .INIT(32'h0000000D)) 
    \FSM_sequential_wl_state_r[1]_i_6 
       (.I0(wl_sm_start),
        .I1(wr_level_done_r5),
        .I2(wrlvl_byte_redo),
        .I3(\FSM_sequential_wl_state_r[4]_i_12_n_0 ),
        .I4(wl_state_r__0[4]),
        .O(\FSM_sequential_wl_state_r[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h88888888FBBB8888)) 
    \FSM_sequential_wl_state_r[1]_i_7 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[1]),
        .I2(wrlvl_byte_redo),
        .I3(\rd_data_edge_detect_r[1]_i_3_n_0 ),
        .I4(wl_state_r__0[4]),
        .I5(wl_state_r__0[3]),
        .O(\FSM_sequential_wl_state_r[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h5D00FF000000FF00)) 
    \FSM_sequential_wl_state_r[1]_i_8 
       (.I0(wl_edge_detect_valid_r_reg_n_0),
        .I1(\fine_dec_cnt[5]_i_11_n_0 ),
        .I2(\fine_dec_cnt[5]_i_10_n_0 ),
        .I3(wl_state_r__0[3]),
        .I4(wl_state_r__0[1]),
        .I5(wl_state_r__0[4]),
        .O(\FSM_sequential_wl_state_r[1]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair268" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_wl_state_r[1]_i_9 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[3]),
        .O(\FSM_sequential_wl_state_r[1]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFAFAAAEAFAFAFAFA)) 
    \FSM_sequential_wl_state_r[2]_i_1 
       (.I0(\FSM_sequential_wl_state_r[2]_i_2_n_0 ),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(\FSM_sequential_wl_state_r[2]_i_3_n_0 ),
        .I4(\FSM_sequential_wl_state_r[2]_i_4_n_0 ),
        .I5(\FSM_sequential_wl_state_r[2]_i_5_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000017771777FFFF)) 
    \FSM_sequential_wl_state_r[2]_i_10 
       (.I0(\wl_corse_cnt[0][0][1]_i_1_n_0 ),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .I2(\wl_corse_cnt[0][0][0]_i_1_n_0 ),
        .I3(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I4(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .I5(\wl_corse_cnt[0][0][2]_i_1_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF4500)) 
    \FSM_sequential_wl_state_r[2]_i_11 
       (.I0(wrlvl_byte_redo),
        .I1(wr_level_done_r5),
        .I2(wl_sm_start),
        .I3(\FSM_sequential_wl_state_r[4]_i_12_n_0 ),
        .I4(\FSM_sequential_wl_state_r[2]_i_13_n_0 ),
        .I5(\FSM_sequential_wl_state_r[2]_i_14_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair288" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_wl_state_r[2]_i_12 
       (.I0(wl_state_r__0[3]),
        .I1(wl_state_r__0[0]),
        .O(\FSM_sequential_wl_state_r[2]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair267" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \FSM_sequential_wl_state_r[2]_i_13 
       (.I0(wrlvl_byte_redo),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .I2(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I3(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .O(\FSM_sequential_wl_state_r[2]_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair240" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_wl_state_r[2]_i_14 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[2]),
        .O(\FSM_sequential_wl_state_r[2]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h1F1F0F0F111F0000)) 
    \FSM_sequential_wl_state_r[2]_i_2 
       (.I0(\FSM_sequential_wl_state_r[2]_i_6_n_0 ),
        .I1(wl_state_r__0[3]),
        .I2(\FSM_sequential_wl_state_r[2]_i_7_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[0]),
        .I5(\FSM_sequential_wl_state_r[2]_i_8_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0F000F2F2FF0F)) 
    \FSM_sequential_wl_state_r[2]_i_3 
       (.I0(\FSM_sequential_wl_state_r[3]_i_6_n_0 ),
        .I1(\FSM_sequential_wl_state_r[3]_i_7_n_0 ),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r[4]_i_12_n_0 ),
        .I4(wl_state_r__0[4]),
        .I5(\FSM_sequential_wl_state_r[2]_i_9_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000030002000300)) 
    \FSM_sequential_wl_state_r[2]_i_4 
       (.I0(\rd_data_edge_detect_r[1]_i_3_n_0 ),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[3]),
        .I3(inhibit_edge_detect_r_i_2_n_0),
        .I4(wrlvl_byte_redo),
        .I5(\FSM_sequential_wl_state_r[2]_i_10_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hACAF0000FFFFFFFF)) 
    \FSM_sequential_wl_state_r[2]_i_5 
       (.I0(\FSM_sequential_wl_state_r[4]_i_18_n_0 ),
        .I1(\FSM_sequential_wl_state_r[4]_i_10_n_0 ),
        .I2(wl_state_r__0[4]),
        .I3(wl_state_r__0[2]),
        .I4(\FSM_sequential_wl_state_r[2]_i_11_n_0 ),
        .I5(\FSM_sequential_wl_state_r[2]_i_12_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair287" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_wl_state_r[2]_i_6 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[2]),
        .O(\FSM_sequential_wl_state_r[2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h000000DF00FF00FF)) 
    \FSM_sequential_wl_state_r[2]_i_7 
       (.I0(inhibit_edge_detect_r_i_3_n_0),
        .I1(\FSM_sequential_wl_state_r[2]_i_10_n_0 ),
        .I2(wrlvl_byte_redo),
        .I3(\FSM_sequential_wl_state_r[4]_i_16_n_0 ),
        .I4(wl_state_r__0[3]),
        .I5(wl_state_r__0[4]),
        .O(\FSM_sequential_wl_state_r[2]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair264" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \FSM_sequential_wl_state_r[2]_i_8 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[4]),
        .I2(inhibit_edge_detect_r_i_3_n_0),
        .I3(wl_state_r__0[3]),
        .O(\FSM_sequential_wl_state_r[2]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_sequential_wl_state_r[2]_i_9 
       (.I0(wl_state_r__0[3]),
        .I1(p_0_in),
        .O(\FSM_sequential_wl_state_r[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF04)) 
    \FSM_sequential_wl_state_r[3]_i_1 
       (.I0(\FSM_sequential_wl_state_r[3]_i_2_n_0 ),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r[3]_i_3_n_0 ),
        .I4(\FSM_sequential_wl_state_r[3]_i_4_n_0 ),
        .I5(\FSM_sequential_wl_state_r[3]_i_5_n_0 ),
        .O(\FSM_sequential_wl_state_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFACFF0CFFACFF0)) 
    \FSM_sequential_wl_state_r[3]_i_2 
       (.I0(inhibit_edge_detect_r_i_3_n_0),
        .I1(\FSM_sequential_wl_state_r[3]_i_6_n_0 ),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[3]),
        .I5(\FSM_sequential_wl_state_r[3]_i_7_n_0 ),
        .O(\FSM_sequential_wl_state_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000003700)) 
    \FSM_sequential_wl_state_r[3]_i_3 
       (.I0(\FSM_sequential_wl_state_r[3]_i_8_n_0 ),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(\wl_tap_count_r[5]_i_4_n_0 ),
        .I4(wl_state_r__0[2]),
        .I5(\FSM_sequential_wl_state_r[3]_i_9_n_0 ),
        .O(\FSM_sequential_wl_state_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hC07000C0C0700CC0)) 
    \FSM_sequential_wl_state_r[3]_i_4 
       (.I0(\FSM_sequential_wl_state_r[4]_i_10_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[3]),
        .I5(p_0_in),
        .O(\FSM_sequential_wl_state_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hC8CCC8CC44440000)) 
    \FSM_sequential_wl_state_r[3]_i_5 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_dec[1][1]_i_3_n_0 ),
        .I2(\rd_data_edge_detect_r[1]_i_3_n_0 ),
        .I3(wrlvl_byte_redo),
        .I4(inhibit_edge_detect_r_i_3_n_0),
        .I5(wl_state_r__0[1]),
        .O(\FSM_sequential_wl_state_r[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair236" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    \FSM_sequential_wl_state_r[3]_i_6 
       (.I0(\fine_dec_cnt[5]_i_11_n_0 ),
        .I1(wl_state_r__0[3]),
        .I2(\wl_tap_count_r_reg_n_0_[5] ),
        .I3(\wl_tap_count_r_reg_n_0_[4] ),
        .I4(\wl_tap_count_r_reg_n_0_[3] ),
        .O(\FSM_sequential_wl_state_r[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair266" *) 
  LUT4 #(
    .INIT(16'hE2FF)) 
    \FSM_sequential_wl_state_r[3]_i_7 
       (.I0(\rd_data_edge_detect_r_reg_n_0_[0] ),
        .I1(dqs_count_r[0]),
        .I2(\rd_data_edge_detect_r_reg_n_0_[1] ),
        .I3(wl_edge_detect_valid_r_reg_n_0),
        .O(\FSM_sequential_wl_state_r[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h1D00000000000000)) 
    \FSM_sequential_wl_state_r[3]_i_8 
       (.I0(\rd_data_previous_r_reg_n_0_[0] ),
        .I1(dqs_count_r[0]),
        .I2(\rd_data_previous_r_reg_n_0_[1] ),
        .I3(\stable_cnt_reg_n_0_[1] ),
        .I4(\stable_cnt_reg_n_0_[3] ),
        .I5(\stable_cnt_reg_n_0_[2] ),
        .O(\FSM_sequential_wl_state_r[3]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair268" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    \FSM_sequential_wl_state_r[3]_i_9 
       (.I0(wr_level_done_r5),
        .I1(wl_sm_start),
        .I2(wl_state_r__0[1]),
        .I3(wrlvl_byte_redo),
        .O(\FSM_sequential_wl_state_r[3]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF0FFF4F4)) 
    \FSM_sequential_wl_state_r[4]_i_1 
       (.I0(\FSM_sequential_wl_state_r[4]_i_3_n_0 ),
        .I1(\FSM_sequential_wl_state_r[4]_i_4_n_0 ),
        .I2(\FSM_sequential_wl_state_r[4]_i_5_n_0 ),
        .I3(\FSM_sequential_wl_state_r[4]_i_6_n_0 ),
        .I4(wl_state_r__0[4]),
        .I5(\FSM_sequential_wl_state_r[4]_i_7_n_0 ),
        .O(\FSM_sequential_wl_state_r[4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h08)) 
    \FSM_sequential_wl_state_r[4]_i_10 
       (.I0(wr_level_start_r),
        .I1(wl_sm_start),
        .I2(wr_level_done_r_reg_n_0),
        .O(\FSM_sequential_wl_state_r[4]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0008000800088088)) 
    \FSM_sequential_wl_state_r[4]_i_11 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[3]),
        .I2(wl_state_r__0[1]),
        .I3(inhibit_edge_detect_r_i_3_n_0),
        .I4(\FSM_sequential_wl_state_r[4]_i_18_n_0 ),
        .I5(wl_state_r__0[0]),
        .O(\FSM_sequential_wl_state_r[4]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFCFAFAFFFC)) 
    \FSM_sequential_wl_state_r[4]_i_12 
       (.I0(\corse_inc_reg_n_0_[1][1] ),
        .I1(\corse_inc_reg_n_0_[0][1] ),
        .I2(\corse_inc[1][0]_i_2_n_0 ),
        .I3(\corse_inc_reg_n_0_[0][2] ),
        .I4(\dqs_count_r_reg[0]_rep_n_0 ),
        .I5(\corse_inc_reg_n_0_[1][2] ),
        .O(\FSM_sequential_wl_state_r[4]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT5 #(
    .INIT(32'h7E7EFF7F)) 
    \FSM_sequential_wl_state_r[4]_i_13 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[3]),
        .I2(wl_state_r__0[1]),
        .I3(\FSM_sequential_wl_state_r[4]_i_10_n_0 ),
        .I4(wl_state_r__0[0]),
        .O(\FSM_sequential_wl_state_r[4]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h4440444444404040)) 
    \FSM_sequential_wl_state_r[4]_i_14 
       (.I0(wl_state_r__0[0]),
        .I1(done_dqs_dec237_out),
        .I2(\FSM_sequential_wl_state_r[4]_i_4_0 ),
        .I3(\final_coarse_tap_reg_n_0_[1][2] ),
        .I4(\dqs_count_r_reg[1]_0 [0]),
        .I5(\final_coarse_tap_reg_n_0_[0][2] ),
        .O(\FSM_sequential_wl_state_r[4]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair263" *) 
  LUT4 #(
    .INIT(16'hFFEF)) 
    \FSM_sequential_wl_state_r[4]_i_15 
       (.I0(incdec_wait_cnt_reg[0]),
        .I1(incdec_wait_cnt_reg[1]),
        .I2(incdec_wait_cnt_reg[3]),
        .I3(incdec_wait_cnt_reg[2]),
        .O(\FSM_sequential_wl_state_r[4]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair235" *) 
  LUT5 #(
    .INIT(32'h0FB0FFB0)) 
    \FSM_sequential_wl_state_r[4]_i_16 
       (.I0(\FSM_sequential_wl_state_r[4]_i_20_n_0 ),
        .I1(inhibit_edge_detect_r_i_6_n_0),
        .I2(wl_state_r__0[3]),
        .I3(wl_state_r__0[2]),
        .I4(wr_level_done_r5),
        .O(\FSM_sequential_wl_state_r[4]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF0000E0)) 
    \FSM_sequential_wl_state_r[4]_i_17 
       (.I0(wl_state_r__0[3]),
        .I1(p_0_in),
        .I2(wl_state_r__0[1]),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[2]),
        .I5(\FSM_sequential_wl_state_r[4]_i_21_n_0 ),
        .O(\FSM_sequential_wl_state_r[4]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h0000000305050003)) 
    \FSM_sequential_wl_state_r[4]_i_18 
       (.I0(\corse_dec_reg[1]_6 [2]),
        .I1(\corse_dec_reg[0]_7 [2]),
        .I2(\corse_dec[1][2]_i_4_n_0 ),
        .I3(\corse_dec_reg[0]_7 [0]),
        .I4(dqs_count_r[0]),
        .I5(\corse_dec_reg[1]_6 [0]),
        .O(\FSM_sequential_wl_state_r[4]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF444F4F4)) 
    \FSM_sequential_wl_state_r[4]_i_2 
       (.I0(\FSM_sequential_wl_state_r[4]_i_8_n_0 ),
        .I1(wl_state_r__0[0]),
        .I2(\FSM_sequential_wl_state_r[4]_i_9_n_0 ),
        .I3(\FSM_sequential_wl_state_r[4]_i_10_n_0 ),
        .I4(wl_state_r__0[3]),
        .I5(\FSM_sequential_wl_state_r[4]_i_11_n_0 ),
        .O(\FSM_sequential_wl_state_r[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair270" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \FSM_sequential_wl_state_r[4]_i_20 
       (.I0(\stable_cnt_reg_n_0_[2] ),
        .I1(\stable_cnt_reg_n_0_[3] ),
        .I2(\stable_cnt_reg_n_0_[1] ),
        .O(\FSM_sequential_wl_state_r[4]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hE200000000000000)) 
    \FSM_sequential_wl_state_r[4]_i_21 
       (.I0(\rd_data_edge_detect_r_reg_n_0_[0] ),
        .I1(dqs_count_r[0]),
        .I2(\rd_data_edge_detect_r_reg_n_0_[1] ),
        .I3(wl_state_r__0[3]),
        .I4(wl_state_r__0[4]),
        .I5(wl_edge_detect_valid_r_reg_n_0),
        .O(\FSM_sequential_wl_state_r[4]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'h00000FF00F100FF0)) 
    \FSM_sequential_wl_state_r[4]_i_3 
       (.I0(wr_level_done_r5),
        .I1(wrlvl_byte_redo),
        .I2(wl_state_r__0[3]),
        .I3(wl_state_r__0[2]),
        .I4(wl_state_r__0[1]),
        .I5(wl_sm_start),
        .O(\FSM_sequential_wl_state_r[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF8880)) 
    \FSM_sequential_wl_state_r[4]_i_4 
       (.I0(wr_level_done_r5),
        .I1(flag_ck_negedge_i_3_n_0),
        .I2(\fine_inc[1][5]_i_5_n_0 ),
        .I3(\FSM_sequential_wl_state_r[4]_i_12_n_0 ),
        .I4(\FSM_sequential_wl_state_r[4]_i_13_n_0 ),
        .I5(\FSM_sequential_wl_state_r[4]_i_14_n_0 ),
        .O(\FSM_sequential_wl_state_r[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF0E00000000)) 
    \FSM_sequential_wl_state_r[4]_i_5 
       (.I0(wrlvl_byte_redo),
        .I1(wl_sm_start),
        .I2(wl_state_r__0[3]),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[2]),
        .I5(wl_state_r__0[1]),
        .O(\FSM_sequential_wl_state_r[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF00708A8A7575)) 
    \FSM_sequential_wl_state_r[4]_i_6 
       (.I0(wl_state_r__0[0]),
        .I1(\FSM_sequential_wl_state_r[4]_i_15_n_0 ),
        .I2(wl_state_r__0[1]),
        .I3(wl_sm_start),
        .I4(wl_state_r__0[2]),
        .I5(wl_state_r__0[3]),
        .O(\FSM_sequential_wl_state_r[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0450000004550005)) 
    \FSM_sequential_wl_state_r[4]_i_7 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[3]),
        .I3(wl_state_r__0[2]),
        .I4(wl_sm_start),
        .I5(\FSM_sequential_wl_state_r[4]_i_15_n_0 ),
        .O(\FSM_sequential_wl_state_r[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h3032333233323332)) 
    \FSM_sequential_wl_state_r[4]_i_8 
       (.I0(\FSM_sequential_wl_state_r[4]_i_16_n_0 ),
        .I1(\FSM_sequential_wl_state_r[4]_i_17_n_0 ),
        .I2(wl_state_r__0[1]),
        .I3(wl_state_r__0[4]),
        .I4(inhibit_edge_detect_r_i_3_n_0),
        .I5(wl_state_r__0[3]),
        .O(\FSM_sequential_wl_state_r[4]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair276" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \FSM_sequential_wl_state_r[4]_i_9 
       (.I0(wl_state_r__0[0]),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[2]),
        .O(\FSM_sequential_wl_state_r[4]_i_9_n_0 ));
  (* FSM_ENCODED_STATES = "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001" *) 
  FDRE \FSM_sequential_wl_state_r_reg[0] 
       (.C(CLK),
        .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ),
        .D(\FSM_sequential_wl_state_r[0]_i_1_n_0 ),
        .Q(wl_state_r__0[0]),
        .R(\smallest_reg[1][0]_0 [1]));
  (* FSM_ENCODED_STATES = "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001" *) 
  FDSE \FSM_sequential_wl_state_r_reg[1] 
       (.C(CLK),
        .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ),
        .D(\FSM_sequential_wl_state_r[1]_i_1_n_0 ),
        .Q(wl_state_r__0[1]),
        .S(\smallest_reg[1][0]_0 [1]));
  (* FSM_ENCODED_STATES = "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001" *) 
  FDSE \FSM_sequential_wl_state_r_reg[2] 
       (.C(CLK),
        .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ),
        .D(\FSM_sequential_wl_state_r[2]_i_1_n_0 ),
        .Q(wl_state_r__0[2]),
        .S(\smallest_reg[1][0]_0 [1]));
  (* FSM_ENCODED_STATES = "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001" *) 
  FDSE \FSM_sequential_wl_state_r_reg[3] 
       (.C(CLK),
        .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ),
        .D(\FSM_sequential_wl_state_r[3]_i_1_n_0 ),
        .Q(wl_state_r__0[3]),
        .S(\smallest_reg[1][0]_0 [1]));
  (* FSM_ENCODED_STATES = "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001" *) 
  FDRE \FSM_sequential_wl_state_r_reg[4] 
       (.C(CLK),
        .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ),
        .D(\FSM_sequential_wl_state_r[4]_i_2_n_0 ),
        .Q(wl_state_r__0[4]),
        .R(\smallest_reg[1][0]_0 [1]));
  LUT6 #(
    .INIT(64'h000000002AEA2A2A)) 
    \calib_sel[0]_i_1 
       (.I0(\calib_sel_reg[0]_0 ),
        .I1(cmd_delay_start0),
        .I2(calib_sel15_out),
        .I3(\calib_sel_reg[0]_1 ),
        .I4(\calib_sel_reg[0]_2 ),
        .I5(calib_sel0),
        .O(\gen_byte_sel_div2.ctl_lane_sel_reg[1] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[0][0]_i_1 
       (.I0(corse_cnt[0]),
        .I1(\corse_cnt[0][2]_i_3_n_0 ),
        .I2(\corse_cnt_reg_n_0_[0][0] ),
        .O(\corse_cnt[0][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA88A88888)) 
    \corse_cnt[0][0]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(\corse_cnt[0][0]_i_3_n_0 ),
        .I2(\corse_cnt[0][0]_i_4_n_0 ),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[2]),
        .I5(\corse_cnt[0][0]_i_5_n_0 ),
        .O(corse_cnt[0]));
  LUT6 #(
    .INIT(64'hF4F444F4F4444444)) 
    \corse_cnt[0][0]_i_3 
       (.I0(\wl_corse_cnt[0][0][0]_i_1_n_0 ),
        .I1(wl_edge_detect_valid_r),
        .I2(inhibit_edge_detect_r_i_2_n_0),
        .I3(dqs_count_r[0]),
        .I4(\final_coarse_tap_reg[1][0]_0 ),
        .I5(\final_coarse_tap_reg[0][0]_0 ),
        .O(\corse_cnt[0][0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair271" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[0][0]_i_4 
       (.I0(\final_coarse_tap_reg[1][0]_0 ),
        .I1(\dqs_count_r_reg[1]_0 [0]),
        .I2(\final_coarse_tap_reg[0][0]_0 ),
        .O(\corse_cnt[0][0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair272" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \corse_cnt[0][0]_i_5 
       (.I0(p_0_in),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[3]),
        .O(\corse_cnt[0][0]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair235" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \corse_cnt[0][0]_i_6 
       (.I0(wl_state_r__0[3]),
        .I1(wl_state_r__0[2]),
        .O(wl_edge_detect_valid_r));
  (* SOFT_HLUTNM = "soft_lutpair281" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[0][1]_i_1 
       (.I0(corse_cnt[1]),
        .I1(\corse_cnt[0][2]_i_3_n_0 ),
        .I2(\corse_cnt_reg_n_0_[0][1] ),
        .O(\corse_cnt[0][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h888A8A8888888888)) 
    \corse_cnt[0][1]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(\corse_cnt[0][1]_i_3_n_0 ),
        .I2(wl_state_r__0[2]),
        .I3(\wl_corse_cnt[0][0][1]_i_1_n_0 ),
        .I4(\wl_corse_cnt[0][0][0]_i_1_n_0 ),
        .I5(wl_state_r__0[3]),
        .O(corse_cnt[1]));
  LUT6 #(
    .INIT(64'hAAEAAAEAAAFFAAEA)) 
    \corse_cnt[0][1]_i_3 
       (.I0(\corse_cnt[0][1]_i_4_n_0 ),
        .I1(\final_coarse_tap_reg[1][1]_0 ),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[4]),
        .I4(p_0_in),
        .I5(wl_state_r__0[3]),
        .O(\corse_cnt[0][1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair240" *) 
  LUT5 #(
    .INIT(32'h0000CA00)) 
    \corse_cnt[0][1]_i_4 
       (.I0(\final_coarse_tap_reg_n_0_[0][1] ),
        .I1(\final_coarse_tap_reg_n_0_[1][1] ),
        .I2(\dqs_count_r_reg[0]_rep_n_0 ),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[2]),
        .O(\corse_cnt[0][1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair271" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[0][1]_i_5 
       (.I0(\final_coarse_tap_reg_n_0_[1][1] ),
        .I1(\dqs_count_r_reg[1]_0 [0]),
        .I2(\final_coarse_tap_reg_n_0_[0][1] ),
        .O(\final_coarse_tap_reg[1][1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair281" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[0][2]_i_1 
       (.I0(corse_cnt[2]),
        .I1(\corse_cnt[0][2]_i_3_n_0 ),
        .I2(\corse_cnt_reg_n_0_[0][2] ),
        .O(\corse_cnt[0][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAA2000AAAA2A0A)) 
    \corse_cnt[0][2]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[2]),
        .I3(\corse_cnt[0][2]_i_4_n_0 ),
        .I4(\corse_cnt[0][2]_i_5_n_0 ),
        .I5(\corse_cnt[0][2]_i_6_n_0 ),
        .O(corse_cnt[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFF4040FF40)) 
    \corse_cnt[0][2]_i_3 
       (.I0(\corse_cnt[0][2]_i_7_n_0 ),
        .I1(done_dqs_dec237_out),
        .I2(wl_state_r__0[3]),
        .I3(\fine_inc[0][5]_i_3_n_0 ),
        .I4(\corse_cnt[0][2]_i_8_n_0 ),
        .I5(rank_cnt_r),
        .O(\corse_cnt[0][2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair249" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[0][2]_i_4 
       (.I0(\final_coarse_tap_reg_n_0_[1][2] ),
        .I1(\dqs_count_r_reg[1]_0 [0]),
        .I2(\final_coarse_tap_reg_n_0_[0][2] ),
        .O(\corse_cnt[0][2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAEFEAAAAA)) 
    \corse_cnt[0][2]_i_5 
       (.I0(\corse_cnt[0][0]_i_5_n_0 ),
        .I1(\final_coarse_tap_reg_n_0_[1][2] ),
        .I2(dqs_count_r[0]),
        .I3(\final_coarse_tap_reg_n_0_[0][2] ),
        .I4(wl_state_r__0[4]),
        .I5(wl_state_r__0[2]),
        .O(\corse_cnt[0][2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hA9595555FFFFFFFF)) 
    \corse_cnt[0][2]_i_6 
       (.I0(\wl_corse_cnt[0][0][2]_i_1_n_0 ),
        .I1(\corse_cnt_reg_n_0_[0][1] ),
        .I2(\dqs_count_r_reg[0]_rep_n_0 ),
        .I3(\corse_cnt_reg_n_0_[1][1] ),
        .I4(\wl_corse_cnt[0][0][0]_i_1_n_0 ),
        .I5(wl_state_r__0[3]),
        .O(\corse_cnt[0][2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFDFFFF)) 
    \corse_cnt[0][2]_i_7 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[0]),
        .I2(\dqs_count_r_reg[1]_0 [1]),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[2]),
        .I5(\dqs_count_r_reg[1]_0 [0]),
        .O(\corse_cnt[0][2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFDFFFDFFFFFFFDFF)) 
    \corse_cnt[0][2]_i_8 
       (.I0(flag_ck_negedge_i_3_n_0),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[3]),
        .I4(wr_level_done_r5),
        .I5(wrlvl_byte_redo),
        .O(\corse_cnt[0][2]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair273" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[1][0]_i_1 
       (.I0(corse_cnt[0]),
        .I1(\corse_cnt[1][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[1][0] ),
        .O(\corse_cnt[1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair280" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[1][1]_i_1 
       (.I0(corse_cnt[1]),
        .I1(\corse_cnt[1][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[1][1] ),
        .O(\corse_cnt[1][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair279" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[1][2]_i_1 
       (.I0(corse_cnt[2]),
        .I1(\corse_cnt[1][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[1][2] ),
        .O(\corse_cnt[1][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0404FF04)) 
    \corse_cnt[1][2]_i_2 
       (.I0(\corse_cnt[0][2]_i_8_n_0 ),
        .I1(dqs_count_r[0]),
        .I2(dqs_count_r[1]),
        .I3(\corse_inc[1][2]_i_3_n_0 ),
        .I4(\corse_cnt[1][2]_i_3_n_0 ),
        .I5(rank_cnt_r),
        .O(\corse_cnt[1][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFDFFFFFFFFFF)) 
    \corse_cnt[1][2]_i_3 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[0]),
        .I2(\dqs_count_r_reg[1]_0 [1]),
        .I3(wrlvl_byte_redo),
        .I4(wrlvl_byte_redo_r),
        .I5(\dqs_count_r_reg[1]_0 [0]),
        .O(\corse_cnt[1][2]_i_3_n_0 ));
  FDRE \corse_cnt_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[0][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[0][0] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_cnt_reg[0][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[0][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[0][1] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_cnt_reg[0][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[0][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[0][2] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_cnt_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[1][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[1][0] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_cnt_reg[1][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[1][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[1][1] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_cnt_reg[1][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_cnt[1][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[1][2] ),
        .R(\smallest_reg[1][0]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair253" *) 
  LUT5 #(
    .INIT(32'h20FF2000)) 
    \corse_dec[0][0]_i_1 
       (.I0(\corse_dec[1][1]_i_2_n_0 ),
        .I1(wl_state_r__0[3]),
        .I2(wl_state_r__0[4]),
        .I3(\corse_dec[0][2]_i_2_n_0 ),
        .I4(\corse_dec_reg[0]_7 [0]),
        .O(\corse_dec[0][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h6500FFFF6A000000)) 
    \corse_dec[0][1]_i_1 
       (.I0(\corse_dec[1][1]_i_2_n_0 ),
        .I1(\corse_dec_reg[1]_6 [1]),
        .I2(dqs_count_r[0]),
        .I3(\corse_dec[1][1]_i_3_n_0 ),
        .I4(\corse_dec[0][2]_i_2_n_0 ),
        .I5(\corse_dec_reg[0]_7 [1]),
        .O(\corse_dec[0][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair282" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_dec[0][2]_i_1 
       (.I0(corse_dec),
        .I1(\corse_dec[0][2]_i_2_n_0 ),
        .I2(\corse_dec_reg[0]_7 [2]),
        .O(\corse_dec[0][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \corse_dec[0][2]_i_2 
       (.I0(\fine_inc[0][5]_i_3_n_0 ),
        .I1(wl_state_r__0[2]),
        .I2(wl_state_r__0[4]),
        .I3(wl_state_r__0[3]),
        .I4(wl_state_r__0[1]),
        .I5(wl_state_r__0[0]),
        .O(\corse_dec[0][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair252" *) 
  LUT5 #(
    .INIT(32'h20FF2000)) 
    \corse_dec[1][0]_i_1 
       (.I0(\corse_dec[1][1]_i_2_n_0 ),
        .I1(wl_state_r__0[3]),
        .I2(wl_state_r__0[4]),
        .I3(\corse_dec[1][2]_i_3_n_0 ),
        .I4(\corse_dec_reg[1]_6 [0]),
        .O(\corse_dec[1][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5600FFFF9A000000)) 
    \corse_dec[1][1]_i_1 
       (.I0(\corse_dec[1][1]_i_2_n_0 ),
        .I1(dqs_count_r[0]),
        .I2(\corse_dec_reg[0]_7 [1]),
        .I3(\corse_dec[1][1]_i_3_n_0 ),
        .I4(\corse_dec[1][2]_i_3_n_0 ),
        .I5(\corse_dec_reg[1]_6 [1]),
        .O(\corse_dec[1][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000FCFAFA00FC)) 
    \corse_dec[1][1]_i_2 
       (.I0(\corse_dec_reg[1]_6 [2]),
        .I1(\corse_dec_reg[0]_7 [2]),
        .I2(\corse_dec[1][2]_i_4_n_0 ),
        .I3(\corse_dec_reg[0]_7 [0]),
        .I4(dqs_count_r[0]),
        .I5(\corse_dec_reg[1]_6 [0]),
        .O(\corse_dec[1][1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair253" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \corse_dec[1][1]_i_3 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[3]),
        .O(\corse_dec[1][1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair282" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_dec[1][2]_i_1 
       (.I0(corse_dec),
        .I1(\corse_dec[1][2]_i_3_n_0 ),
        .I2(\corse_dec_reg[1]_6 [2]),
        .O(\corse_dec[1][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hD000D0D0D0000000)) 
    \corse_dec[1][2]_i_2 
       (.I0(\corse_dec[1][1]_i_2_n_0 ),
        .I1(\corse_dec[1][2]_i_4_n_0 ),
        .I2(\corse_dec[1][1]_i_3_n_0 ),
        .I3(\corse_dec_reg[1]_6 [2]),
        .I4(dqs_count_r[0]),
        .I5(\corse_dec_reg[0]_7 [2]),
        .O(corse_dec));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \corse_dec[1][2]_i_3 
       (.I0(\fine_inc[1][5]_i_4_n_0 ),
        .I1(wl_state_r__0[2]),
        .I2(wl_state_r__0[4]),
        .I3(wl_state_r__0[3]),
        .I4(wl_state_r__0[1]),
        .I5(wl_state_r__0[0]),
        .O(\corse_dec[1][2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair278" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_dec[1][2]_i_4 
       (.I0(\corse_dec_reg[1]_6 [1]),
        .I1(dqs_count_r[0]),
        .I2(\corse_dec_reg[0]_7 [1]),
        .O(\corse_dec[1][2]_i_4_n_0 ));
  FDRE \corse_dec_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[0][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[0]_7 [0]),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_dec_reg[0][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[0][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[0]_7 [1]),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_dec_reg[0][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[0][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[0]_7 [2]),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_dec_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[1][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[1]_6 [0]),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_dec_reg[1][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[1][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[1]_6 [1]),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_dec_reg[1][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_dec[1][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[1]_6 [2]),
        .R(\smallest_reg[1][0]_0 [0]));
  LUT6 #(
    .INIT(64'h888FFFFF888F0000)) 
    \corse_inc[0][0]_i_1 
       (.I0(\corse_inc[1][2]_i_3_n_0 ),
        .I1(\final_coarse_tap_reg[0][0]_0 ),
        .I2(\corse_inc[1][0]_i_2_n_0 ),
        .I3(wl_state_r__0[2]),
        .I4(\corse_inc[0][2]_i_2_n_0 ),
        .I5(\corse_inc_reg_n_0_[0][0] ),
        .O(\corse_inc[0][0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \corse_inc[0][1]_i_1 
       (.I0(\corse_inc[1][2]_i_3_n_0 ),
        .I1(\final_coarse_tap_reg_n_0_[0][1] ),
        .I2(\corse_inc[1][1]_i_2_n_0 ),
        .I3(\corse_inc[0][2]_i_2_n_0 ),
        .I4(\corse_inc_reg_n_0_[0][1] ),
        .O(\corse_inc[0][1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    \corse_inc[0][2]_i_1 
       (.I0(\corse_inc[1][2]_i_3_n_0 ),
        .I1(\final_coarse_tap_reg_n_0_[0][2] ),
        .I2(\corse_inc[1][2]_i_2_n_0 ),
        .I3(\corse_inc[0][2]_i_2_n_0 ),
        .I4(\corse_inc_reg_n_0_[0][2] ),
        .O(\corse_inc[0][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0808AA0808080808)) 
    \corse_inc[0][2]_i_2 
       (.I0(\corse_inc[1][2]_i_6_n_0 ),
        .I1(\fine_inc[0][5]_i_3_n_0 ),
        .I2(\corse_inc[1][2]_i_7_n_0 ),
        .I3(wr_level_done_r4),
        .I4(wr_level_done_r5),
        .I5(wl_state_r__0[2]),
        .O(\corse_inc[0][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF111FFFFF1110000)) 
    \corse_inc[1][0]_i_1 
       (.I0(\corse_inc[1][0]_i_2_n_0 ),
        .I1(wl_state_r__0[2]),
        .I2(\corse_inc[1][2]_i_3_n_0 ),
        .I3(\final_coarse_tap_reg[1][0]_0 ),
        .I4(\corse_inc[1][2]_i_4_n_0 ),
        .I5(\corse_inc_reg_n_0_[1][0] ),
        .O(\corse_inc[1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair248" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_inc[1][0]_i_2 
       (.I0(\corse_inc_reg_n_0_[1][0] ),
        .I1(\dqs_count_r_reg[0]_rep_n_0 ),
        .I2(\corse_inc_reg_n_0_[0][0] ),
        .O(\corse_inc[1][0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hEAFFEA00)) 
    \corse_inc[1][1]_i_1 
       (.I0(\corse_inc[1][1]_i_2_n_0 ),
        .I1(\corse_inc[1][2]_i_3_n_0 ),
        .I2(\final_coarse_tap_reg_n_0_[1][1] ),
        .I3(\corse_inc[1][2]_i_4_n_0 ),
        .I4(\corse_inc_reg_n_0_[1][1] ),
        .O(\corse_inc[1][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4540151040451015)) 
    \corse_inc[1][1]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg_n_0_[1][1] ),
        .I2(\dqs_count_r_reg[0]_rep_n_0 ),
        .I3(\corse_inc_reg_n_0_[0][1] ),
        .I4(\corse_inc_reg_n_0_[1][0] ),
        .I5(\corse_inc_reg_n_0_[0][0] ),
        .O(\corse_inc[1][1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hEAFFEA00)) 
    \corse_inc[1][2]_i_1 
       (.I0(\corse_inc[1][2]_i_2_n_0 ),
        .I1(\corse_inc[1][2]_i_3_n_0 ),
        .I2(\final_coarse_tap_reg_n_0_[1][2] ),
        .I3(\corse_inc[1][2]_i_4_n_0 ),
        .I4(\corse_inc_reg_n_0_[1][2] ),
        .O(\corse_inc[1][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h45401015)) 
    \corse_inc[1][2]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg_n_0_[1][2] ),
        .I2(\dqs_count_r_reg[0]_rep_n_0 ),
        .I3(\corse_inc_reg_n_0_[0][2] ),
        .I4(\corse_inc[1][2]_i_5_n_0 ),
        .O(\corse_inc[1][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair272" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \corse_inc[1][2]_i_3 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[3]),
        .I2(wl_state_r__0[2]),
        .O(\corse_inc[1][2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0808AA0808080808)) 
    \corse_inc[1][2]_i_4 
       (.I0(\corse_inc[1][2]_i_6_n_0 ),
        .I1(\fine_inc[1][5]_i_4_n_0 ),
        .I2(\corse_inc[1][2]_i_7_n_0 ),
        .I3(wr_level_done_r4),
        .I4(wr_level_done_r5),
        .I5(wl_state_r__0[2]),
        .O(\corse_inc[1][2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair248" *) 
  LUT5 #(
    .INIT(32'hFFFACCFA)) 
    \corse_inc[1][2]_i_5 
       (.I0(\corse_inc_reg_n_0_[0][0] ),
        .I1(\corse_inc_reg_n_0_[1][0] ),
        .I2(\corse_inc_reg_n_0_[0][1] ),
        .I3(\dqs_count_r_reg[0]_rep_n_0 ),
        .I4(\corse_inc_reg_n_0_[1][1] ),
        .O(\corse_inc[1][2]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair260" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \corse_inc[1][2]_i_6 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[3]),
        .O(\corse_inc[1][2]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair262" *) 
  LUT4 #(
    .INIT(16'hFFDF)) 
    \corse_inc[1][2]_i_7 
       (.I0(\FSM_sequential_wl_state_r[4]_i_12_n_0 ),
        .I1(wl_state_r__0[2]),
        .I2(wr_level_done_r5),
        .I3(wrlvl_byte_redo),
        .O(\corse_inc[1][2]_i_7_n_0 ));
  FDRE \corse_inc_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[0][0]_i_1_n_0 ),
        .Q(\corse_inc_reg_n_0_[0][0] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_inc_reg[0][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[0][1]_i_1_n_0 ),
        .Q(\corse_inc_reg_n_0_[0][1] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_inc_reg[0][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[0][2]_i_1_n_0 ),
        .Q(\corse_inc_reg_n_0_[0][2] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_inc_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[1][0]_i_1_n_0 ),
        .Q(\corse_inc_reg_n_0_[1][0] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_inc_reg[1][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[1][1]_i_1_n_0 ),
        .Q(\corse_inc_reg_n_0_[1][1] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \corse_inc_reg[1][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\corse_inc[1][2]_i_1_n_0 ),
        .Q(\corse_inc_reg_n_0_[1][2] ),
        .R(\smallest_reg[1][0]_0 [0]));
  LUT2 #(
    .INIT(4'h8)) 
    delay_dec_done_i_3
       (.I0(dqs_po_dec_done_reg_0),
        .I1(\calib_sel_reg[0]_3 ),
        .O(cmd_delay_start0));
  LUT6 #(
    .INIT(64'hFFEFBFFF00208000)) 
    dq_cnt_inc_i_1
       (.I0(dq_cnt_inc_i_2_n_0),
        .I1(wl_state_r__0[2]),
        .I2(dq_cnt_inc_i_3_n_0),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[1]),
        .I5(p_0_in),
        .O(dq_cnt_inc_i_1_n_0));
  LUT6 #(
    .INIT(64'h00000B00BBBBBBBB)) 
    dq_cnt_inc_i_2
       (.I0(dqs_count_r[1]),
        .I1(dqs_count_r[0]),
        .I2(wl_state_r__0[3]),
        .I3(wl_state_r__0[4]),
        .I4(wrlvl_byte_redo),
        .I5(wl_state_r__0[2]),
        .O(dq_cnt_inc_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair289" *) 
  LUT2 #(
    .INIT(4'h1)) 
    dq_cnt_inc_i_3
       (.I0(wl_state_r__0[3]),
        .I1(wl_state_r__0[0]),
        .O(dq_cnt_inc_i_3_n_0));
  FDSE dq_cnt_inc_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dq_cnt_inc_i_1_n_0),
        .Q(p_0_in),
        .S(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFFFFFF40000)) 
    \dqs_count_r[0]_i_1 
       (.I0(\dqs_count_r[0]_i_2_n_0 ),
        .I1(\dqs_count_r[0]_i_3_n_0 ),
        .I2(\dqs_count_r[0]_i_4_n_0 ),
        .I3(\dqs_count_r[0]_i_5_n_0 ),
        .I4(\dqs_count_r[1]_i_5_n_0 ),
        .I5(\dqs_count_r_reg[0]_rep_n_0 ),
        .O(\dqs_count_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000015555555)) 
    \dqs_count_r[0]_i_2 
       (.I0(wl_state_r__0[4]),
        .I1(\dqs_count_r[1]_i_10_n_0 ),
        .I2(wl_state_r__0[1]),
        .I3(wl_state_r__0[0]),
        .I4(dqs_count_r[0]),
        .I5(\dqs_count_r[0]_i_6_n_0 ),
        .O(\dqs_count_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAA020A0A)) 
    \dqs_count_r[0]_i_3 
       (.I0(\dqs_count_r[0]_i_7_n_0 ),
        .I1(dqs_count_r[1]),
        .I2(\fine_inc[1][5]_i_5_n_0 ),
        .I3(\dqs_count_r[1]_i_7_n_0 ),
        .I4(dqs_count_r[0]),
        .I5(\dqs_count_r[0]_i_8_n_0 ),
        .O(\dqs_count_r[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair255" *) 
  LUT5 #(
    .INIT(32'h00010101)) 
    \dqs_count_r[0]_i_4 
       (.I0(wl_state_r__0[3]),
        .I1(wl_state_r__0[2]),
        .I2(wl_state_r__0[0]),
        .I3(dqs_count_r[0]),
        .I4(dqs_count_r[1]),
        .O(\dqs_count_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFF00F13300000000)) 
    \dqs_count_r[0]_i_5 
       (.I0(dqs_count_r[1]),
        .I1(\fine_inc[1][5]_i_5_n_0 ),
        .I2(\dqs_count_r[1]_i_7_n_0 ),
        .I3(dqs_count_r[0]),
        .I4(\dqs_count_r[1]_i_8_n_0 ),
        .I5(\dqs_count_r[0]_i_9_n_0 ),
        .O(\dqs_count_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0808080000000800)) 
    \dqs_count_r[0]_i_6 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[0]),
        .I3(dqs_count_r[0]),
        .I4(done_dqs_dec237_out),
        .I5(\dqs_count_r_reg[1]_0 [0]),
        .O(\dqs_count_r[0]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair288" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \dqs_count_r[0]_i_7 
       (.I0(wl_state_r__0[3]),
        .I1(wl_state_r__0[2]),
        .O(\dqs_count_r[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h40044404FFFFFFFF)) 
    \dqs_count_r[0]_i_8 
       (.I0(wl_state_r__0[3]),
        .I1(wl_state_r__0[2]),
        .I2(wrlvl_byte_redo),
        .I3(dqs_count_r[0]),
        .I4(dqs_count_r[1]),
        .I5(wl_state_r__0[4]),
        .O(\dqs_count_r[0]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair274" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \dqs_count_r[0]_i_9 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[3]),
        .I2(wl_state_r__0[0]),
        .O(\dqs_count_r[0]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hEEEFFFFFEEEF0000)) 
    \dqs_count_r[1]_i_1 
       (.I0(\dqs_count_r[1]_i_2_n_0 ),
        .I1(\dqs_count_r[1]_i_3_n_0 ),
        .I2(wl_state_r__0[4]),
        .I3(\dqs_count_r[1]_i_4_n_0 ),
        .I4(\dqs_count_r[1]_i_5_n_0 ),
        .I5(dqs_count_r[1]),
        .O(\dqs_count_r[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hBFBFBFB0)) 
    \dqs_count_r[1]_i_10 
       (.I0(wr_level_done_r5),
        .I1(wr_level_done_r4),
        .I2(wl_state_r__0[2]),
        .I3(wrlvl_byte_redo),
        .I4(p_0_in),
        .O(\dqs_count_r[1]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h1504000000000000)) 
    \dqs_count_r[1]_i_2 
       (.I0(wl_state_r__0[3]),
        .I1(wl_state_r__0[2]),
        .I2(\dqs_count_r[1]_i_6_n_0 ),
        .I3(\dqs_count_r[1]_i_7_n_0 ),
        .I4(dqs_count_r[1]),
        .I5(wl_state_r__0[4]),
        .O(\dqs_count_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hE000E0F000000000)) 
    \dqs_count_r[1]_i_3 
       (.I0(\dqs_count_r[1]_i_8_n_0 ),
        .I1(\dqs_count_r[1]_i_7_n_0 ),
        .I2(dqs_count_r[1]),
        .I3(wl_state_r__0[3]),
        .I4(dqs_count_r[0]),
        .I5(\dqs_count_r[1]_i_9_n_0 ),
        .O(\dqs_count_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h007F4F7F4F7F4F7F)) 
    \dqs_count_r[1]_i_4 
       (.I0(\dqs_count_r_reg[1]_0 [1]),
        .I1(done_dqs_dec237_out),
        .I2(\FSM_sequential_wl_state_r[4]_i_9_n_0 ),
        .I3(dqs_count_r[1]),
        .I4(flag_ck_negedge_i_3_n_0),
        .I5(\dqs_count_r[1]_i_10_n_0 ),
        .O(\dqs_count_r[1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair254" *) 
  LUT5 #(
    .INIT(32'h00C4180C)) 
    \dqs_count_r[1]_i_5 
       (.I0(wl_state_r__0[0]),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[3]),
        .O(\dqs_count_r[1]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair265" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dqs_count_r[1]_i_6 
       (.I0(\dqs_count_r_reg[0]_rep_n_0 ),
        .I1(wrlvl_byte_redo),
        .O(\dqs_count_r[1]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'hFFEF)) 
    \dqs_count_r[1]_i_7 
       (.I0(\fine_inc_reg[1]_2 [4]),
        .I1(\fine_inc[1][5]_i_7_n_0 ),
        .I2(\dqs_count_r_reg[0]_rep_n_0 ),
        .I3(\fine_inc_reg[1]_2 [5]),
        .O(\dqs_count_r[1]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \dqs_count_r[1]_i_8 
       (.I0(\FSM_sequential_wl_state_r[4]_i_12_n_0 ),
        .I1(wrlvl_byte_redo),
        .I2(wr_level_done_r5),
        .O(\dqs_count_r[1]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair262" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \dqs_count_r[1]_i_9 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[0]),
        .O(\dqs_count_r[1]_i_9_n_0 ));
  (* MAX_FANOUT = "50" *) 
  (* ORIG_CELL_NAME = "dqs_count_r_reg[0]" *) 
  FDRE \dqs_count_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqs_count_r[0]_i_1_n_0 ),
        .Q(dqs_count_r[0]),
        .R(\smallest_reg[1][0]_0 [1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* MAX_FANOUT = "50" *) 
  (* ORIG_CELL_NAME = "dqs_count_r_reg[0]" *) 
  FDRE \dqs_count_r_reg[0]_rep 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqs_count_r[0]_i_1_n_0 ),
        .Q(\dqs_count_r_reg[0]_rep_n_0 ),
        .R(in0));
  (* MAX_FANOUT = "50" *) 
  FDRE \dqs_count_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\dqs_count_r[1]_i_1_n_0 ),
        .Q(dqs_count_r[1]),
        .R(\smallest_reg[1][0]_0 [1]));
  (* syn_maxfan = "2" *) 
  FDRE dqs_po_dec_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(po_dec_done),
        .Q(dqs_po_dec_done_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAAAAABAAAEAEB)) 
    dqs_po_en_stg2_f_i_1
       (.I0(po_cnt_dec_reg_0),
        .I1(wl_state_r__0[2]),
        .I2(wl_state_r__0[3]),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[4]),
        .I5(wl_state_r__0[1]),
        .O(dqs_po_en_stg2_f_i_1_n_0));
  FDRE dqs_po_en_stg2_f_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_po_en_stg2_f_i_1_n_0),
        .Q(dqs_po_en_stg2_f),
        .R(\smallest_reg[1][0]_0 [0]));
  LUT6 #(
    .INIT(64'h0000000002000000)) 
    dqs_po_stg2_f_incdec_i_1
       (.I0(dqs_po_stg2_f_incdec_i_2_n_0),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[4]),
        .I3(wl_state_r__0[2]),
        .I4(wl_state_r__0[3]),
        .I5(dqs_po_stg2_f_incdec_reg_0),
        .O(dqs_po_stg2_f_incdec_i_1_n_0));
  LUT6 #(
    .INIT(64'h00000000FFFFBFFE)) 
    dqs_po_stg2_f_incdec_i_2
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[3]),
        .I4(wl_state_r__0[2]),
        .I5(po_cnt_dec_reg_0),
        .O(dqs_po_stg2_f_incdec_i_2_n_0));
  FDRE dqs_po_stg2_f_incdec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_po_stg2_f_incdec_i_1_n_0),
        .Q(dqs_po_stg2_f_incdec),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair260" *) 
  LUT5 #(
    .INIT(32'h00000080)) 
    dqs_wl_po_stg2_c_incdec_i_1
       (.I0(wl_state_r__0[3]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[2]),
        .O(dqs_wl_po_stg2_c_incdec_i_1_n_0));
  FDRE dqs_wl_po_stg2_c_incdec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(dqs_wl_po_stg2_c_incdec_i_1_n_0),
        .Q(po_stg2_cincdec),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \final_coarse_tap_reg[0][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][0]_8 [0]),
        .Q(\final_coarse_tap_reg[0][0]_0 ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[0][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][0]_8 [1]),
        .Q(\final_coarse_tap_reg_n_0_[0][1] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[0][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][0]_8 [2]),
        .Q(\final_coarse_tap_reg_n_0_[0][2] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[1][0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][1]_9 [0]),
        .Q(\final_coarse_tap_reg[1][0]_0 ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[1][1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][1]_9 [1]),
        .Q(\final_coarse_tap_reg_n_0_[1][1] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[1][2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][1]_9 [2]),
        .Q(\final_coarse_tap_reg_n_0_[1][2] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000CCCC55C5)) 
    \fine_dec_cnt[0]_i_1 
       (.I0(\fine_dec_cnt_reg_n_0_[0] ),
        .I1(\wl_tap_count_r_reg_n_0_[0] ),
        .I2(wl_state_r__0[3]),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[1]),
        .I5(wl_state_r__0[2]),
        .O(fine_dec_cnt[0]));
  LUT5 #(
    .INIT(32'h0000E22E)) 
    \fine_dec_cnt[1]_i_1 
       (.I0(\wl_tap_count_r_reg_n_0_[1] ),
        .I1(\fine_dec_cnt[5]_i_8_n_0 ),
        .I2(\fine_dec_cnt_reg_n_0_[0] ),
        .I3(\fine_dec_cnt_reg_n_0_[1] ),
        .I4(wl_state_r__0[2]),
        .O(fine_dec_cnt[1]));
  LUT6 #(
    .INIT(64'h00000000A9A9FF00)) 
    \fine_dec_cnt[2]_i_1 
       (.I0(\fine_dec_cnt_reg_n_0_[2] ),
        .I1(\fine_dec_cnt_reg_n_0_[0] ),
        .I2(\fine_dec_cnt_reg_n_0_[1] ),
        .I3(\wl_tap_count_r_reg_n_0_[2] ),
        .I4(\fine_dec_cnt[5]_i_8_n_0 ),
        .I5(wl_state_r__0[2]),
        .O(fine_dec_cnt[2]));
  LUT5 #(
    .INIT(32'h000099F0)) 
    \fine_dec_cnt[3]_i_1 
       (.I0(\fine_dec_cnt_reg_n_0_[3] ),
        .I1(\fine_dec_cnt[3]_i_2_n_0 ),
        .I2(\wl_tap_count_r_reg_n_0_[3] ),
        .I3(\fine_dec_cnt[5]_i_8_n_0 ),
        .I4(wl_state_r__0[2]),
        .O(fine_dec_cnt[3]));
  LUT3 #(
    .INIT(8'hFE)) 
    \fine_dec_cnt[3]_i_2 
       (.I0(\fine_dec_cnt_reg_n_0_[2] ),
        .I1(\fine_dec_cnt_reg_n_0_[0] ),
        .I2(\fine_dec_cnt_reg_n_0_[1] ),
        .O(\fine_dec_cnt[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h000099F0)) 
    \fine_dec_cnt[4]_i_1 
       (.I0(\fine_dec_cnt[4]_i_2_n_0 ),
        .I1(\fine_dec_cnt_reg_n_0_[4] ),
        .I2(\wl_tap_count_r_reg_n_0_[4] ),
        .I3(\fine_dec_cnt[5]_i_8_n_0 ),
        .I4(wl_state_r__0[2]),
        .O(fine_dec_cnt[4]));
  (* SOFT_HLUTNM = "soft_lutpair257" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \fine_dec_cnt[4]_i_2 
       (.I0(\fine_dec_cnt_reg_n_0_[3] ),
        .I1(\fine_dec_cnt_reg_n_0_[1] ),
        .I2(\fine_dec_cnt_reg_n_0_[0] ),
        .I3(\fine_dec_cnt_reg_n_0_[2] ),
        .O(\fine_dec_cnt[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEAAAAAAAAAAA)) 
    \fine_dec_cnt[5]_i_1 
       (.I0(\fine_dec_cnt[5]_i_3_n_0 ),
        .I1(\fine_dec_cnt[5]_i_4_n_0 ),
        .I2(\fine_dec_cnt[5]_i_5_n_0 ),
        .I3(wl_sm_start),
        .I4(wl_state_r__0[4]),
        .I5(\fine_dec_cnt[5]_i_6_n_0 ),
        .O(\fine_dec_cnt[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hE2FFFFFFFFFFFFFF)) 
    \fine_dec_cnt[5]_i_10 
       (.I0(\rd_data_edge_detect_r_reg_n_0_[0] ),
        .I1(\dqs_count_r_reg[0]_rep_n_0 ),
        .I2(\rd_data_edge_detect_r_reg_n_0_[1] ),
        .I3(\wl_tap_count_r_reg_n_0_[3] ),
        .I4(\wl_tap_count_r_reg_n_0_[4] ),
        .I5(\wl_tap_count_r_reg_n_0_[5] ),
        .O(\fine_dec_cnt[5]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hC000A0A0C0000000)) 
    \fine_dec_cnt[5]_i_11 
       (.I0(\corse_cnt_reg_n_0_[0][2] ),
        .I1(\corse_cnt_reg_n_0_[1][2] ),
        .I2(\wl_corse_cnt[0][0][0]_i_1_n_0 ),
        .I3(\corse_cnt_reg_n_0_[1][1] ),
        .I4(\dqs_count_r_reg[0]_rep_n_0 ),
        .I5(\corse_cnt_reg_n_0_[0][1] ),
        .O(\fine_dec_cnt[5]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'h000099F0)) 
    \fine_dec_cnt[5]_i_2 
       (.I0(\fine_dec_cnt_reg_n_0_[5] ),
        .I1(\fine_dec_cnt[5]_i_7_n_0 ),
        .I2(\wl_tap_count_r_reg_n_0_[5] ),
        .I3(\fine_dec_cnt[5]_i_8_n_0 ),
        .I4(wl_state_r__0[2]),
        .O(fine_dec_cnt[5]));
  LUT6 #(
    .INIT(64'h0002808200020002)) 
    \fine_dec_cnt[5]_i_3 
       (.I0(\fine_dec_cnt[5]_i_9_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[4]),
        .I3(inhibit_edge_detect_r_i_3_n_0),
        .I4(\rd_data_edge_detect_r[1]_i_3_n_0 ),
        .I5(wrlvl_byte_redo),
        .O(\fine_dec_cnt[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair255" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \fine_dec_cnt[5]_i_4 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[3]),
        .I2(wl_state_r__0[0]),
        .O(\fine_dec_cnt[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hE200000000000000)) 
    \fine_dec_cnt[5]_i_5 
       (.I0(\rd_data_previous_r_reg_n_0_[0] ),
        .I1(dqs_count_r[0]),
        .I2(\rd_data_previous_r_reg_n_0_[1] ),
        .I3(\stable_cnt_reg_n_0_[1] ),
        .I4(\stable_cnt_reg_n_0_[3] ),
        .I5(\stable_cnt_reg_n_0_[2] ),
        .O(\fine_dec_cnt[5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h020002FF00FF00FF)) 
    \fine_dec_cnt[5]_i_6 
       (.I0(wl_edge_detect_valid_r_reg_n_0),
        .I1(\fine_dec_cnt[5]_i_10_n_0 ),
        .I2(\fine_dec_cnt[5]_i_11_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(inhibit_edge_detect_r_i_3_n_0),
        .I5(wl_state_r__0[4]),
        .O(\fine_dec_cnt[5]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair257" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \fine_dec_cnt[5]_i_7 
       (.I0(\fine_dec_cnt_reg_n_0_[4] ),
        .I1(\fine_dec_cnt_reg_n_0_[2] ),
        .I2(\fine_dec_cnt_reg_n_0_[0] ),
        .I3(\fine_dec_cnt_reg_n_0_[1] ),
        .I4(\fine_dec_cnt_reg_n_0_[3] ),
        .O(\fine_dec_cnt[5]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair275" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \fine_dec_cnt[5]_i_8 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[3]),
        .O(\fine_dec_cnt[5]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair274" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \fine_dec_cnt[5]_i_9 
       (.I0(wl_state_r__0[0]),
        .I1(wl_state_r__0[2]),
        .I2(wl_state_r__0[3]),
        .O(\fine_dec_cnt[5]_i_9_n_0 ));
  FDRE \fine_dec_cnt_reg[0] 
       (.C(CLK),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(fine_dec_cnt[0]),
        .Q(\fine_dec_cnt_reg_n_0_[0] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \fine_dec_cnt_reg[1] 
       (.C(CLK),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(fine_dec_cnt[1]),
        .Q(\fine_dec_cnt_reg_n_0_[1] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \fine_dec_cnt_reg[2] 
       (.C(CLK),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(fine_dec_cnt[2]),
        .Q(\fine_dec_cnt_reg_n_0_[2] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \fine_dec_cnt_reg[3] 
       (.C(CLK),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(fine_dec_cnt[3]),
        .Q(\fine_dec_cnt_reg_n_0_[3] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \fine_dec_cnt_reg[4] 
       (.C(CLK),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(fine_dec_cnt[4]),
        .Q(\fine_dec_cnt_reg_n_0_[4] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \fine_dec_cnt_reg[5] 
       (.C(CLK),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(fine_dec_cnt[5]),
        .Q(\fine_dec_cnt_reg_n_0_[5] ),
        .R(\smallest_reg[1][0]_0 [0]));
  LUT6 #(
    .INIT(64'h888AAA8A00022202)) 
    \fine_inc[0][0]_i_1 
       (.I0(\fine_inc[1][0]_i_2_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\fine_inc_reg[0]_3 [0]),
        .I3(\dqs_count_r_reg[0]_rep_n_0 ),
        .I4(\fine_inc_reg[1]_2 [0]),
        .I5(\gen_final_tap[0].final_val_reg_n_0_[0][0] ),
        .O(fine_inc[0]));
  LUT5 #(
    .INIT(32'h44404040)) 
    \fine_inc[0][1]_i_1 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[0]),
        .I2(\fine_inc[1][1]_i_2_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(\gen_final_tap[0].final_val_reg_n_0_[0][1] ),
        .O(fine_inc[1]));
  LUT5 #(
    .INIT(32'h44404040)) 
    \fine_inc[0][2]_i_1 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[0]),
        .I2(\fine_inc[1][2]_i_2_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(\gen_final_tap[0].final_val_reg_n_0_[0][2] ),
        .O(fine_inc[2]));
  (* SOFT_HLUTNM = "soft_lutpair243" *) 
  LUT5 #(
    .INIT(32'h44404040)) 
    \fine_inc[0][3]_i_1 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[0]),
        .I2(\fine_inc[1][3]_i_2_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(\gen_final_tap[0].final_val_reg_n_0_[0][3] ),
        .O(fine_inc[3]));
  (* SOFT_HLUTNM = "soft_lutpair244" *) 
  LUT5 #(
    .INIT(32'h44404040)) 
    \fine_inc[0][4]_i_1 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[0]),
        .I2(\fine_inc[1][4]_i_2_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(\gen_final_tap[0].final_val_reg_n_0_[0][4] ),
        .O(fine_inc[4]));
  LUT6 #(
    .INIT(64'h0A800A0000800000)) 
    \fine_inc[0][5]_i_1 
       (.I0(\fine_inc[1][5]_i_3_n_0 ),
        .I1(\fine_inc[0][5]_i_3_n_0 ),
        .I2(wr_level_done_r5),
        .I3(wl_state_r__0[1]),
        .I4(\fine_inc[1][5]_i_5_n_0 ),
        .I5(wr_level_done_r4),
        .O(\fine_inc[0][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair232" *) 
  LUT5 #(
    .INIT(32'h00E20000)) 
    \fine_inc[0][5]_i_2 
       (.I0(\fine_inc[1][5]_i_6_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\gen_final_tap[0].final_val_reg_n_0_[0][5] ),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[0]),
        .O(\fine_inc[0][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair278" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \fine_inc[0][5]_i_3 
       (.I0(dqs_count_r[1]),
        .I1(dqs_count_r[0]),
        .O(\fine_inc[0][5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h888AAA8A00022202)) 
    \fine_inc[1][0]_i_1 
       (.I0(\fine_inc[1][0]_i_2_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\fine_inc_reg[0]_3 [0]),
        .I3(\dqs_count_r_reg[0]_rep_n_0 ),
        .I4(\fine_inc_reg[1]_2 [0]),
        .I5(\gen_final_tap[1].final_val_reg_n_0_[1][0] ),
        .O(\fine_inc[1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair241" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \fine_inc[1][0]_i_2 
       (.I0(wl_state_r__0[0]),
        .I1(wl_state_r__0[4]),
        .O(\fine_inc[1][0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h44404040)) 
    \fine_inc[1][1]_i_1 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[0]),
        .I2(\fine_inc[1][1]_i_2_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(\gen_final_tap[1].final_val_reg_n_0_[1][1] ),
        .O(\fine_inc[1][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4540151040451015)) 
    \fine_inc[1][1]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[1]_2 [1]),
        .I2(\dqs_count_r_reg[0]_rep_n_0 ),
        .I3(\fine_inc_reg[0]_3 [1]),
        .I4(\fine_inc_reg[1]_2 [0]),
        .I5(\fine_inc_reg[0]_3 [0]),
        .O(\fine_inc[1][1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h44404040)) 
    \fine_inc[1][2]_i_1 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[0]),
        .I2(\fine_inc[1][2]_i_2_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(\gen_final_tap[1].final_val_reg_n_0_[1][2] ),
        .O(\fine_inc[1][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h45401015)) 
    \fine_inc[1][2]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[1]_2 [2]),
        .I2(\dqs_count_r_reg[0]_rep_n_0 ),
        .I3(\fine_inc_reg[0]_3 [2]),
        .I4(\fine_inc[1][2]_i_3_n_0 ),
        .O(\fine_inc[1][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT5 #(
    .INIT(32'hFFFACCFA)) 
    \fine_inc[1][2]_i_3 
       (.I0(\fine_inc_reg[0]_3 [0]),
        .I1(\fine_inc_reg[1]_2 [0]),
        .I2(\fine_inc_reg[0]_3 [1]),
        .I3(\dqs_count_r_reg[0]_rep_n_0 ),
        .I4(\fine_inc_reg[1]_2 [1]),
        .O(\fine_inc[1][2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair241" *) 
  LUT5 #(
    .INIT(32'h44404040)) 
    \fine_inc[1][3]_i_1 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[0]),
        .I2(\fine_inc[1][3]_i_2_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(\gen_final_tap[1].final_val_reg_n_0_[1][3] ),
        .O(\fine_inc[1][3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h45401015)) 
    \fine_inc[1][3]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[1]_2 [3]),
        .I2(\dqs_count_r_reg[0]_rep_n_0 ),
        .I3(\fine_inc_reg[0]_3 [3]),
        .I4(\fine_inc[1][3]_i_3_n_0 ),
        .O(\fine_inc[1][3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFCFAFAFFFC)) 
    \fine_inc[1][3]_i_3 
       (.I0(\fine_inc_reg[1]_2 [1]),
        .I1(\fine_inc_reg[0]_3 [1]),
        .I2(\fine_inc[1][3]_i_4_n_0 ),
        .I3(\fine_inc_reg[0]_3 [2]),
        .I4(\dqs_count_r_reg[0]_rep_n_0 ),
        .I5(\fine_inc_reg[1]_2 [2]),
        .O(\fine_inc[1][3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \fine_inc[1][3]_i_4 
       (.I0(\fine_inc_reg[1]_2 [0]),
        .I1(\dqs_count_r_reg[0]_rep_n_0 ),
        .I2(\fine_inc_reg[0]_3 [0]),
        .O(\fine_inc[1][3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair242" *) 
  LUT5 #(
    .INIT(32'h44404040)) 
    \fine_inc[1][4]_i_1 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[0]),
        .I2(\fine_inc[1][4]_i_2_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(\gen_final_tap[1].final_val_reg_n_0_[1][4] ),
        .O(\fine_inc[1][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h45401015)) 
    \fine_inc[1][4]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[1]_2 [4]),
        .I2(\dqs_count_r_reg[0]_rep_n_0 ),
        .I3(\fine_inc_reg[0]_3 [4]),
        .I4(\fine_inc[1][5]_i_7_n_0 ),
        .O(\fine_inc[1][4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0A800A0000800000)) 
    \fine_inc[1][5]_i_1 
       (.I0(\fine_inc[1][5]_i_3_n_0 ),
        .I1(\fine_inc[1][5]_i_4_n_0 ),
        .I2(wr_level_done_r5),
        .I3(wl_state_r__0[1]),
        .I4(\fine_inc[1][5]_i_5_n_0 ),
        .I5(wr_level_done_r4),
        .O(\fine_inc[1][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair233" *) 
  LUT5 #(
    .INIT(32'h00E20000)) 
    \fine_inc[1][5]_i_2 
       (.I0(\fine_inc[1][5]_i_6_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\gen_final_tap[1].final_val_reg_n_0_[1][5] ),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[0]),
        .O(\fine_inc[1][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair261" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \fine_inc[1][5]_i_3 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[3]),
        .O(\fine_inc[1][5]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \fine_inc[1][5]_i_4 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .O(\fine_inc[1][5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFCFAFAFFFC)) 
    \fine_inc[1][5]_i_5 
       (.I0(\fine_inc_reg[1]_2 [4]),
        .I1(\fine_inc_reg[0]_3 [4]),
        .I2(\fine_inc[1][5]_i_7_n_0 ),
        .I3(\fine_inc_reg[0]_3 [5]),
        .I4(\dqs_count_r_reg[0]_rep_n_0 ),
        .I5(\fine_inc_reg[1]_2 [5]),
        .O(\fine_inc[1][5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair265" *) 
  LUT4 #(
    .INIT(16'hA965)) 
    \fine_inc[1][5]_i_6 
       (.I0(\fine_inc[1][5]_i_8_n_0 ),
        .I1(\dqs_count_r_reg[0]_rep_n_0 ),
        .I2(\fine_inc_reg[0]_3 [5]),
        .I3(\fine_inc_reg[1]_2 [5]),
        .O(\fine_inc[1][5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFCFAFAFFFC)) 
    \fine_inc[1][5]_i_7 
       (.I0(\fine_inc_reg[1]_2 [2]),
        .I1(\fine_inc_reg[0]_3 [2]),
        .I2(\fine_inc[1][2]_i_3_n_0 ),
        .I3(\fine_inc_reg[0]_3 [3]),
        .I4(\dqs_count_r_reg[0]_rep_n_0 ),
        .I5(\fine_inc_reg[1]_2 [3]),
        .O(\fine_inc[1][5]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFCFAFAFFFC)) 
    \fine_inc[1][5]_i_8 
       (.I0(\fine_inc_reg[1]_2 [3]),
        .I1(\fine_inc_reg[0]_3 [3]),
        .I2(\fine_inc[1][3]_i_3_n_0 ),
        .I3(\fine_inc_reg[0]_3 [4]),
        .I4(\dqs_count_r_reg[0]_rep_n_0 ),
        .I5(\fine_inc_reg[1]_2 [4]),
        .O(\fine_inc[1][5]_i_8_n_0 ));
  FDRE \fine_inc_reg[0][0] 
       (.C(CLK),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(fine_inc[0]),
        .Q(\fine_inc_reg[0]_3 [0]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \fine_inc_reg[0][1] 
       (.C(CLK),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(fine_inc[1]),
        .Q(\fine_inc_reg[0]_3 [1]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \fine_inc_reg[0][2] 
       (.C(CLK),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(fine_inc[2]),
        .Q(\fine_inc_reg[0]_3 [2]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \fine_inc_reg[0][3] 
       (.C(CLK),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(fine_inc[3]),
        .Q(\fine_inc_reg[0]_3 [3]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \fine_inc_reg[0][4] 
       (.C(CLK),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(fine_inc[4]),
        .Q(\fine_inc_reg[0]_3 [4]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \fine_inc_reg[0][5] 
       (.C(CLK),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(\fine_inc[0][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[0]_3 [5]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \fine_inc_reg[1][0] 
       (.C(CLK),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]_2 [0]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \fine_inc_reg[1][1] 
       (.C(CLK),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]_2 [1]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \fine_inc_reg[1][2] 
       (.C(CLK),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]_2 [2]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \fine_inc_reg[1][3] 
       (.C(CLK),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]_2 [3]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \fine_inc_reg[1][4] 
       (.C(CLK),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]_2 [4]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \fine_inc_reg[1][5] 
       (.C(CLK),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[1]_2 [5]),
        .R(\smallest_reg[1][0]_0 [1]));
  LUT6 #(
    .INIT(64'h2222222222222022)) 
    flag_ck_negedge_i_1
       (.I0(\stable_cnt[3]_i_4_n_0 ),
        .I1(flag_ck_negedge_i_2_n_0),
        .I2(wl_state_r__0[3]),
        .I3(flag_ck_negedge_i_3_n_0),
        .I4(wl_state_r__0[4]),
        .I5(wl_state_r__0[2]),
        .O(flag_ck_negedge_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair234" *) 
  LUT5 #(
    .INIT(32'hAAAABBFB)) 
    flag_ck_negedge_i_2
       (.I0(wr_level_done_r_reg_n_0),
        .I1(flag_ck_negedge_reg_n_0),
        .I2(\FSM_sequential_wl_state_r[3]_i_8_n_0 ),
        .I3(\stable_cnt_reg_n_0_[0] ),
        .I4(flag_ck_negedge09_out),
        .O(flag_ck_negedge_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair243" *) 
  LUT2 #(
    .INIT(4'h8)) 
    flag_ck_negedge_i_3
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[0]),
        .O(flag_ck_negedge_i_3_n_0));
  LUT6 #(
    .INIT(64'h4000FFFF40004000)) 
    flag_ck_negedge_i_4
       (.I0(wl_state_r__0[2]),
        .I1(\wrlvl_redo_corse_inc[2]_i_2_n_0 ),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[3]),
        .I4(flag_ck_negedge_i_5_n_0),
        .I5(inhibit_edge_detect_r_i_6_n_0),
        .O(flag_ck_negedge09_out));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    flag_ck_negedge_i_5
       (.I0(flag_ck_negedge_i_6_n_0),
        .I1(\stable_cnt_reg_n_0_[0] ),
        .I2(\stable_cnt_reg_n_0_[1] ),
        .I3(\stable_cnt_reg_n_0_[2] ),
        .I4(\stable_cnt_reg_n_0_[3] ),
        .I5(flag_ck_negedge_i_7_n_0),
        .O(flag_ck_negedge_i_5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT5 #(
    .INIT(32'hFFFFFBFE)) 
    flag_ck_negedge_i_6
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[3]),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[1]),
        .O(flag_ck_negedge_i_6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT5 #(
    .INIT(32'h00000004)) 
    flag_ck_negedge_i_7
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[3]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[4]),
        .O(flag_ck_negedge_i_7_n_0));
  FDRE flag_ck_negedge_reg
       (.C(CLK),
        .CE(1'b1),
        .D(flag_ck_negedge_i_1_n_0),
        .Q(flag_ck_negedge_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAA8AAAAAAAAAA)) 
    flag_init_i_1
       (.I0(flag_init),
        .I1(\wl_state_r1_reg_n_0_[0] ),
        .I2(\wl_state_r1_reg_n_0_[3] ),
        .I3(\wl_state_r1_reg_n_0_[2] ),
        .I4(\wl_state_r1_reg_n_0_[4] ),
        .I5(flag_init_i_2_n_0),
        .O(flag_init_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair254" *) 
  LUT5 #(
    .INIT(32'h00000008)) 
    flag_init_i_2
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[3]),
        .O(flag_init_i_2_n_0));
  FDSE flag_init_reg
       (.C(CLK),
        .CE(1'b1),
        .D(flag_init_i_1_n_0),
        .Q(flag_init),
        .S(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  LUT6 #(
    .INIT(64'h00000000EEE222E2)) 
    \gen_byte_sel_div2.byte_sel_cnt[0]_i_1 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[1]_1 ),
        .I2(\dqs_count_r_reg[0]_rep_n_0 ),
        .I3(wr_level_done_reg_0),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[0]_1 ),
        .I5(RSTB),
        .O(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ));
  LUT6 #(
    .INIT(64'h00000000EEE222E2)) 
    \gen_byte_sel_div2.byte_sel_cnt[1]_i_1 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[1]_1 ),
        .I2(dqs_count_r[1]),
        .I3(wr_level_done_reg_0),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[1]_2 ),
        .I5(RSTB),
        .O(\gen_byte_sel_div2.byte_sel_cnt_reg[1] ));
  LUT2 #(
    .INIT(4'h2)) 
    \gen_final_tap[0].final_val[0][5]_i_1 
       (.I0(wr_level_done_r2),
        .I1(wr_level_done_r3),
        .O(p_45_out));
  FDRE \gen_final_tap[0].final_val_reg[0][0] 
       (.C(CLK),
        .CE(p_45_out),
        .D(\smallest_reg[0]_4 [0]),
        .Q(\gen_final_tap[0].final_val_reg_n_0_[0][0] ),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \gen_final_tap[0].final_val_reg[0][1] 
       (.C(CLK),
        .CE(p_45_out),
        .D(\smallest_reg[0]_4 [1]),
        .Q(\gen_final_tap[0].final_val_reg_n_0_[0][1] ),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \gen_final_tap[0].final_val_reg[0][2] 
       (.C(CLK),
        .CE(p_45_out),
        .D(\smallest_reg[0]_4 [2]),
        .Q(\gen_final_tap[0].final_val_reg_n_0_[0][2] ),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \gen_final_tap[0].final_val_reg[0][3] 
       (.C(CLK),
        .CE(p_45_out),
        .D(\smallest_reg[0]_4 [3]),
        .Q(\gen_final_tap[0].final_val_reg_n_0_[0][3] ),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \gen_final_tap[0].final_val_reg[0][4] 
       (.C(CLK),
        .CE(p_45_out),
        .D(\smallest_reg[0]_4 [4]),
        .Q(\gen_final_tap[0].final_val_reg_n_0_[0][4] ),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \gen_final_tap[0].final_val_reg[0][5] 
       (.C(CLK),
        .CE(p_45_out),
        .D(\smallest_reg[0]_4 [5]),
        .Q(\gen_final_tap[0].final_val_reg_n_0_[0][5] ),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \gen_final_tap[1].final_val_reg[1][0] 
       (.C(CLK),
        .CE(p_45_out),
        .D(\smallest_reg[1]_5 [0]),
        .Q(\gen_final_tap[1].final_val_reg_n_0_[1][0] ),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \gen_final_tap[1].final_val_reg[1][1] 
       (.C(CLK),
        .CE(p_45_out),
        .D(\smallest_reg[1]_5 [1]),
        .Q(\gen_final_tap[1].final_val_reg_n_0_[1][1] ),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \gen_final_tap[1].final_val_reg[1][2] 
       (.C(CLK),
        .CE(p_45_out),
        .D(\smallest_reg[1]_5 [2]),
        .Q(\gen_final_tap[1].final_val_reg_n_0_[1][2] ),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \gen_final_tap[1].final_val_reg[1][3] 
       (.C(CLK),
        .CE(p_45_out),
        .D(\smallest_reg[1]_5 [3]),
        .Q(\gen_final_tap[1].final_val_reg_n_0_[1][3] ),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \gen_final_tap[1].final_val_reg[1][4] 
       (.C(CLK),
        .CE(p_45_out),
        .D(\smallest_reg[1]_5 [4]),
        .Q(\gen_final_tap[1].final_val_reg_n_0_[1][4] ),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \gen_final_tap[1].final_val_reg[1][5] 
       (.C(CLK),
        .CE(p_45_out),
        .D(\smallest_reg[1]_5 [5]),
        .Q(\gen_final_tap[1].final_val_reg_n_0_[1][5] ),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \gen_rd[0].rd_data_rise_wl_r[0]_i_1 
       (.I0(app_rd_data[2]),
        .I1(app_rd_data[3]),
        .I2(app_rd_data[0]),
        .I3(app_rd_data[1]),
        .I4(\gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ),
        .O(p_0_in__0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEEFA)) 
    \gen_rd[0].rd_data_rise_wl_r[0]_i_2 
       (.I0(app_rd_data[4]),
        .I1(\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ),
        .I2(\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ),
        .I3(my_empty),
        .I4(app_rd_data[6]),
        .I5(app_rd_data[5]),
        .O(\gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ));
  FDRE \gen_rd[0].rd_data_rise_wl_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0),
        .Q(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \gen_rd[1].rd_data_rise_wl_r[1]_i_1 
       (.I0(app_rd_data[9]),
        .I1(app_rd_data[10]),
        .I2(app_rd_data[7]),
        .I3(app_rd_data[8]),
        .I4(\gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ),
        .O(\gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEEFA)) 
    \gen_rd[1].rd_data_rise_wl_r[1]_i_2 
       (.I0(app_rd_data[11]),
        .I1(\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ),
        .I2(\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ),
        .I3(\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ),
        .I4(app_rd_data[13]),
        .I5(app_rd_data[12]),
        .O(\gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ));
  FDRE \gen_rd[1].rd_data_rise_wl_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ),
        .Q(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \incdec_wait_cnt[0]_i_1 
       (.I0(incdec_wait_cnt_reg[0]),
        .O(p_0_in__0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair285" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \incdec_wait_cnt[1]_i_1 
       (.I0(incdec_wait_cnt_reg[1]),
        .I1(incdec_wait_cnt_reg[0]),
        .O(p_0_in__0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair285" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \incdec_wait_cnt[2]_i_1 
       (.I0(incdec_wait_cnt_reg[2]),
        .I1(incdec_wait_cnt_reg[0]),
        .I2(incdec_wait_cnt_reg[1]),
        .O(p_0_in__0__0[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFBFFFFEFB)) 
    \incdec_wait_cnt[3]_i_1 
       (.I0(dqs_po_stg2_f_incdec_reg_0),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[1]),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[2]),
        .I5(wl_state_r__0[3]),
        .O(\incdec_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair263" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \incdec_wait_cnt[3]_i_2 
       (.I0(incdec_wait_cnt_reg[3]),
        .I1(incdec_wait_cnt_reg[1]),
        .I2(incdec_wait_cnt_reg[0]),
        .I3(incdec_wait_cnt_reg[2]),
        .O(p_0_in__0__0[3]));
  FDRE \incdec_wait_cnt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0__0[0]),
        .Q(incdec_wait_cnt_reg[0]),
        .R(\incdec_wait_cnt[3]_i_1_n_0 ));
  FDRE \incdec_wait_cnt_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0__0[1]),
        .Q(incdec_wait_cnt_reg[1]),
        .R(\incdec_wait_cnt[3]_i_1_n_0 ));
  FDRE \incdec_wait_cnt_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0__0[2]),
        .Q(incdec_wait_cnt_reg[2]),
        .R(\incdec_wait_cnt[3]_i_1_n_0 ));
  FDRE \incdec_wait_cnt_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_0_in__0__0[3]),
        .Q(incdec_wait_cnt_reg[3]),
        .R(\incdec_wait_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h007FFFFF007F0000)) 
    inhibit_edge_detect_r_i_1
       (.I0(inhibit_edge_detect_r_i_2_n_0),
        .I1(wl_state_r__0[3]),
        .I2(inhibit_edge_detect_r_i_3_n_0),
        .I3(inhibit_edge_detect_r_i_4_n_0),
        .I4(inhibit_edge_detect_r_i_5_n_0),
        .I5(inhibit_edge_detect_r_reg_n_0),
        .O(inhibit_edge_detect_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair251" *) 
  LUT2 #(
    .INIT(4'h2)) 
    inhibit_edge_detect_r_i_2
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[2]),
        .O(inhibit_edge_detect_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    inhibit_edge_detect_r_i_3
       (.I0(\fine_dec_cnt_reg_n_0_[5] ),
        .I1(\fine_dec_cnt_reg_n_0_[3] ),
        .I2(\fine_dec_cnt_reg_n_0_[1] ),
        .I3(\fine_dec_cnt_reg_n_0_[0] ),
        .I4(\fine_dec_cnt_reg_n_0_[2] ),
        .I5(\fine_dec_cnt_reg_n_0_[4] ),
        .O(inhibit_edge_detect_r_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair251" *) 
  LUT5 #(
    .INIT(32'h0000001D)) 
    inhibit_edge_detect_r_i_4
       (.I0(inhibit_edge_detect_r_i_6_n_0),
        .I1(wl_state_r__0[1]),
        .I2(wrlvl_byte_redo),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[2]),
        .O(inhibit_edge_detect_r_i_4_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF8000)) 
    inhibit_edge_detect_r_i_5
       (.I0(\FSM_sequential_wl_state_r[3]_i_8_n_0 ),
        .I1(inhibit_edge_detect_r_i_7_n_0),
        .I2(wl_sm_start),
        .I3(\fine_dec_cnt[5]_i_4_n_0 ),
        .I4(inhibit_edge_detect_r_i_8_n_0),
        .I5(inhibit_edge_detect_r_i_9_n_0),
        .O(inhibit_edge_detect_r_i_5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair239" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    inhibit_edge_detect_r_i_6
       (.I0(\rd_data_previous_r_reg_n_0_[1] ),
        .I1(dqs_count_r[0]),
        .I2(\rd_data_previous_r_reg_n_0_[0] ),
        .O(inhibit_edge_detect_r_i_6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair233" *) 
  LUT2 #(
    .INIT(4'h1)) 
    inhibit_edge_detect_r_i_7
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[1]),
        .O(inhibit_edge_detect_r_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair247" *) 
  LUT5 #(
    .INIT(32'h00002400)) 
    inhibit_edge_detect_r_i_8
       (.I0(wl_state_r__0[3]),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[0]),
        .O(inhibit_edge_detect_r_i_8_n_0));
  LUT6 #(
    .INIT(64'h0000555500300000)) 
    inhibit_edge_detect_r_i_9
       (.I0(\FSM_sequential_wl_state_r[0]_i_7_n_0 ),
        .I1(wl_state_r__0[2]),
        .I2(wl_state_r__0[3]),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[4]),
        .I5(wl_state_r__0[1]),
        .O(inhibit_edge_detect_r_i_9_n_0));
  FDSE inhibit_edge_detect_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(inhibit_edge_detect_r_i_1_n_0),
        .Q(inhibit_edge_detect_r_reg_n_0),
        .S(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair245" *) 
  LUT5 #(
    .INIT(32'h00000004)) 
    phaser_out_i_1
       (.I0(phaser_out),
        .I1(po_stg2_cincdec),
        .I2(phaser_out_0),
        .I3(phaser_out_1),
        .I4(calib_zero_inputs),
        .O(\gen_byte_sel_div2.calib_in_common_reg ));
  (* SOFT_HLUTNM = "soft_lutpair245" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    phaser_out_i_1__0
       (.I0(phaser_out),
        .I1(phaser_out_0),
        .I2(po_stg2_cincdec),
        .I3(phaser_out_1),
        .I4(calib_zero_inputs),
        .O(\gen_byte_sel_div2.calib_in_common_reg_1 ));
  (* SOFT_HLUTNM = "soft_lutpair246" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    phaser_out_i_1__1
       (.I0(po_stg2_cincdec),
        .I1(phaser_out_0),
        .I2(phaser_out_1),
        .I3(phaser_out),
        .I4(calib_zero_inputs),
        .O(dqs_wl_po_stg2_c_incdec_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair246" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    phaser_out_i_1__2
       (.I0(phaser_out_1),
        .I1(po_stg2_cincdec),
        .I2(phaser_out_0),
        .I3(phaser_out),
        .I4(calib_zero_inputs),
        .O(\calib_sel_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    phaser_out_i_2__0
       (.I0(phaser_out_1),
        .I1(po_enstg2_f),
        .I2(phaser_out_0),
        .I3(phaser_out),
        .I4(calib_zero_inputs),
        .O(\calib_sel_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    phaser_out_i_2__1
       (.I0(po_enstg2_f),
        .I1(phaser_out_0),
        .I2(phaser_out_1),
        .I3(phaser_out),
        .I4(calib_zero_inputs),
        .O(\calib_sel_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT5 #(
    .INIT(32'h00000004)) 
    phaser_out_i_3
       (.I0(phaser_out),
        .I1(po_enstg2_f),
        .I2(phaser_out_0),
        .I3(phaser_out_1),
        .I4(calib_zero_inputs),
        .O(\gen_byte_sel_div2.calib_in_common_reg_0 ));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    phaser_out_i_3__1
       (.I0(phaser_out),
        .I1(phaser_out_0),
        .I2(po_enstg2_f),
        .I3(phaser_out_1),
        .I4(calib_zero_inputs),
        .O(\gen_byte_sel_div2.calib_in_common_reg_2 ));
  LUT6 #(
    .INIT(64'h0000000000004440)) 
    phaser_out_i_4__0
       (.I0(phaser_out),
        .I1(phaser_out_0),
        .I2(dqs_po_stg2_f_incdec),
        .I3(ck_po_stg2_f_indec),
        .I4(phaser_out_1),
        .I5(calib_zero_inputs),
        .O(\gen_byte_sel_div2.calib_in_common_reg_3 ));
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r4_reg_srl4 " *) 
  SRL16E phy_ctl_ready_r4_reg_srl4
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(Q),
        .Q(phy_ctl_ready_r4_reg_srl4_n_0));
  FDRE phy_ctl_ready_r5_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_ready_r4_reg_srl4_n_0),
        .Q(phy_ctl_ready_r5),
        .R(1'b0));
  FDRE phy_ctl_ready_r6_reg
       (.C(CLK),
        .CE(1'b1),
        .D(phy_ctl_ready_r5),
        .Q(phy_ctl_ready_r6_reg_n_0),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    po_cnt_dec_i_1
       (.I0(\po_rdval_cnt[8]_i_3_n_0 ),
        .I1(po_cnt_dec_i_2_n_0),
        .O(po_cnt_dec_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEFFF)) 
    po_cnt_dec_i_2
       (.I0(wait_cnt_reg[3]),
        .I1(wait_cnt_reg[2]),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(wait_cnt_reg[0]),
        .I4(dqs_po_stg2_f_incdec_reg_0),
        .I5(wait_cnt_reg[1]),
        .O(po_cnt_dec_i_2_n_0));
  FDRE po_cnt_dec_reg
       (.C(CLK),
        .CE(1'b1),
        .D(po_cnt_dec_i_1_n_0),
        .Q(po_cnt_dec_reg_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFAE)) 
    po_dec_done_i_1
       (.I0(po_dec_done_i_2_n_0),
        .I1(phy_ctl_ready_r6_reg_n_0),
        .I2(\po_rdval_cnt[8]_i_3_n_0 ),
        .I3(po_dec_done),
        .O(po_dec_done_i_1_n_0));
  LUT5 #(
    .INIT(32'h00000080)) 
    po_dec_done_i_2
       (.I0(\po_rdval_cnt[7]_i_2_n_0 ),
        .I1(po_cnt_dec_reg_0),
        .I2(po_rdval_cnt[0]),
        .I3(po_rdval_cnt[6]),
        .I4(po_rdval_cnt[5]),
        .O(po_dec_done_i_2_n_0));
  FDRE po_dec_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(po_dec_done_i_1_n_0),
        .Q(po_dec_done),
        .R(\smallest_reg[1][0]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair237" *) 
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \po_rdval_cnt[0]_i_1 
       (.I0(\po_rdval_cnt_reg[8]_0 [0]),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(\po_rdval_cnt[8]_i_3_n_0 ),
        .I4(po_rdval_cnt[0]),
        .O(\po_rdval_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB0808080808FB08)) 
    \po_rdval_cnt[1]_i_1 
       (.I0(\po_rdval_cnt_reg[8]_0 [1]),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(\po_rdval_cnt[8]_i_3_n_0 ),
        .I4(po_rdval_cnt[1]),
        .I5(po_rdval_cnt[0]),
        .O(\po_rdval_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B888888888B8)) 
    \po_rdval_cnt[2]_i_1 
       (.I0(\po_rdval_cnt_reg[8]_0 [2]),
        .I1(\po_rdval_cnt[6]_i_3_n_0 ),
        .I2(\po_rdval_cnt[8]_i_3_n_0 ),
        .I3(po_rdval_cnt[0]),
        .I4(po_rdval_cnt[1]),
        .I5(po_rdval_cnt[2]),
        .O(\po_rdval_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B888888888B8)) 
    \po_rdval_cnt[3]_i_1 
       (.I0(\po_rdval_cnt_reg[8]_0 [3]),
        .I1(\po_rdval_cnt[6]_i_3_n_0 ),
        .I2(\po_rdval_cnt[8]_i_3_n_0 ),
        .I3(po_rdval_cnt[2]),
        .I4(\po_rdval_cnt[3]_i_2_n_0 ),
        .I5(po_rdval_cnt[3]),
        .O(\po_rdval_cnt[3]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \po_rdval_cnt[3]_i_2 
       (.I0(po_rdval_cnt[0]),
        .I1(po_rdval_cnt[1]),
        .O(\po_rdval_cnt[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFB0808080808FB08)) 
    \po_rdval_cnt[4]_i_1 
       (.I0(\po_rdval_cnt_reg[8]_0 [4]),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(\po_rdval_cnt[8]_i_3_n_0 ),
        .I4(\po_rdval_cnt[4]_i_2_n_0 ),
        .I5(po_rdval_cnt[4]),
        .O(\po_rdval_cnt[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \po_rdval_cnt[4]_i_2 
       (.I0(po_rdval_cnt[2]),
        .I1(po_rdval_cnt[3]),
        .I2(po_rdval_cnt[1]),
        .I3(po_rdval_cnt[0]),
        .O(\po_rdval_cnt[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0808FB08FB080808)) 
    \po_rdval_cnt[5]_i_1 
       (.I0(\po_rdval_cnt_reg[8]_0 [5]),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(\po_rdval_cnt[8]_i_3_n_0 ),
        .I4(\po_rdval_cnt[6]_i_2_n_0 ),
        .I5(po_rdval_cnt[5]),
        .O(\po_rdval_cnt[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFA6000000A600)) 
    \po_rdval_cnt[6]_i_1 
       (.I0(po_rdval_cnt[6]),
        .I1(\po_rdval_cnt[6]_i_2_n_0 ),
        .I2(po_rdval_cnt[5]),
        .I3(\po_rdval_cnt[8]_i_3_n_0 ),
        .I4(\po_rdval_cnt[6]_i_3_n_0 ),
        .I5(\po_rdval_cnt_reg[8]_0 [6]),
        .O(\po_rdval_cnt[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \po_rdval_cnt[6]_i_2 
       (.I0(po_rdval_cnt[4]),
        .I1(po_rdval_cnt[0]),
        .I2(po_rdval_cnt[1]),
        .I3(po_rdval_cnt[3]),
        .I4(po_rdval_cnt[2]),
        .O(\po_rdval_cnt[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair237" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \po_rdval_cnt[6]_i_3 
       (.I0(phy_ctl_ready_r5),
        .I1(phy_ctl_ready_r6_reg_n_0),
        .O(\po_rdval_cnt[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFBFB0808080808FB)) 
    \po_rdval_cnt[7]_i_1 
       (.I0(\po_rdval_cnt_reg[8]_0 [7]),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(\po_rdval_cnt[7]_i_2_n_0 ),
        .I4(\po_rdval_cnt[7]_i_3_n_0 ),
        .I5(po_rdval_cnt[7]),
        .O(\po_rdval_cnt[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \po_rdval_cnt[7]_i_2 
       (.I0(po_rdval_cnt[3]),
        .I1(po_rdval_cnt[2]),
        .I2(po_rdval_cnt[4]),
        .I3(po_rdval_cnt[7]),
        .I4(po_rdval_cnt[8]),
        .I5(po_rdval_cnt[1]),
        .O(\po_rdval_cnt[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \po_rdval_cnt[7]_i_3 
       (.I0(po_rdval_cnt[5]),
        .I1(po_rdval_cnt[6]),
        .I2(\po_rdval_cnt[6]_i_2_n_0 ),
        .O(\po_rdval_cnt[7]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hBBFB)) 
    \po_rdval_cnt[8]_i_1 
       (.I0(po_cnt_dec_reg_0),
        .I1(\po_rdval_cnt[8]_i_3_n_0 ),
        .I2(phy_ctl_ready_r5),
        .I3(phy_ctl_ready_r6_reg_n_0),
        .O(\po_rdval_cnt[8]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \po_rdval_cnt[8]_i_2 
       (.I0(\po_rdval_cnt_reg[8]_0 [8]),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(po_rdval_cnt[8]),
        .I4(\po_rdval_cnt[8]_i_4_n_0 ),
        .O(\po_rdval_cnt[8]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFD)) 
    \po_rdval_cnt[8]_i_3 
       (.I0(\po_rdval_cnt[6]_i_2_n_0 ),
        .I1(po_rdval_cnt[7]),
        .I2(po_rdval_cnt[8]),
        .I3(po_rdval_cnt[6]),
        .I4(po_rdval_cnt[5]),
        .O(\po_rdval_cnt[8]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h00010000)) 
    \po_rdval_cnt[8]_i_4 
       (.I0(po_rdval_cnt[7]),
        .I1(\po_rdval_cnt[7]_i_2_n_0 ),
        .I2(po_rdval_cnt[5]),
        .I3(po_rdval_cnt[6]),
        .I4(\po_rdval_cnt[6]_i_2_n_0 ),
        .O(\po_rdval_cnt[8]_i_4_n_0 ));
  FDRE \po_rdval_cnt_reg[0] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[0]_i_1_n_0 ),
        .Q(po_rdval_cnt[0]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \po_rdval_cnt_reg[1] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[1]_i_1_n_0 ),
        .Q(po_rdval_cnt[1]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \po_rdval_cnt_reg[2] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[2]_i_1_n_0 ),
        .Q(po_rdval_cnt[2]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \po_rdval_cnt_reg[3] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[3]_i_1_n_0 ),
        .Q(po_rdval_cnt[3]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \po_rdval_cnt_reg[4] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[4]_i_1_n_0 ),
        .Q(po_rdval_cnt[4]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \po_rdval_cnt_reg[5] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[5]_i_1_n_0 ),
        .Q(po_rdval_cnt[5]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \po_rdval_cnt_reg[6] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[6]_i_1_n_0 ),
        .Q(po_rdval_cnt[6]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \po_rdval_cnt_reg[7] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[7]_i_1_n_0 ),
        .Q(po_rdval_cnt[7]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \po_rdval_cnt_reg[8] 
       (.C(CLK),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[8]_i_2_n_0 ),
        .Q(po_rdval_cnt[8]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair283" *) 
  LUT3 #(
    .INIT(8'h38)) 
    \rank_cnt_r[0]_i_1 
       (.I0(\rank_cnt_r_reg_n_0_[1] ),
        .I1(rank_cnt_r),
        .I2(\rank_cnt_r_reg_n_0_[0] ),
        .O(\rank_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair283" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rank_cnt_r[1]_i_1 
       (.I0(\rank_cnt_r_reg_n_0_[0] ),
        .I1(rank_cnt_r),
        .I2(\rank_cnt_r_reg_n_0_[1] ),
        .O(\rank_cnt_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    \rank_cnt_r[1]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[3]),
        .I5(p_0_in),
        .O(rank_cnt_r));
  FDRE \rank_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_cnt_r[0]_i_1_n_0 ),
        .Q(\rank_cnt_r_reg_n_0_[0] ),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \rank_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rank_cnt_r[1]_i_1_n_0 ),
        .Q(\rank_cnt_r_reg_n_0_[1] ),
        .R(\smallest_reg[1][0]_0 [1]));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \rd_data_edge_detect_r[0]_i_1 
       (.I0(\rd_data_edge_detect_r[0]_i_2_n_0 ),
        .I1(inhibit_edge_detect_r_reg_n_0),
        .I2(dqs_po_stg2_f_incdec_reg_0),
        .I3(flag_ck_negedge_reg_n_0),
        .I4(flag_init),
        .I5(\rd_data_edge_detect_r[1]_i_3_n_0 ),
        .O(\rd_data_edge_detect_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF00202000002020)) 
    \rd_data_edge_detect_r[0]_i_2 
       (.I0(\rd_data_edge_detect_r[1]_i_4_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[0] ),
        .I2(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),
        .I3(\rd_data_edge_detect_r[1]_i_5_n_0 ),
        .I4(\rd_data_edge_detect_r[1]_i_6_n_0 ),
        .I5(\rd_data_edge_detect_r_reg_n_0_[0] ),
        .O(\rd_data_edge_detect_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \rd_data_edge_detect_r[1]_i_1 
       (.I0(\rd_data_edge_detect_r[1]_i_2_n_0 ),
        .I1(inhibit_edge_detect_r_reg_n_0),
        .I2(dqs_po_stg2_f_incdec_reg_0),
        .I3(flag_ck_negedge_reg_n_0),
        .I4(flag_init),
        .I5(\rd_data_edge_detect_r[1]_i_3_n_0 ),
        .O(\rd_data_edge_detect_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF00202000002020)) 
    \rd_data_edge_detect_r[1]_i_2 
       (.I0(\rd_data_edge_detect_r[1]_i_4_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[1] ),
        .I2(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),
        .I3(\rd_data_edge_detect_r[1]_i_5_n_0 ),
        .I4(\rd_data_edge_detect_r[1]_i_6_n_0 ),
        .I5(\rd_data_edge_detect_r_reg_n_0_[1] ),
        .O(\rd_data_edge_detect_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \rd_data_edge_detect_r[1]_i_3 
       (.I0(\wl_tap_count_r_reg_n_0_[0] ),
        .I1(\wl_tap_count_r_reg_n_0_[1] ),
        .I2(\wl_tap_count_r_reg_n_0_[2] ),
        .I3(\wl_tap_count_r_reg_n_0_[3] ),
        .I4(\wl_tap_count_r_reg_n_0_[4] ),
        .I5(\wl_tap_count_r_reg_n_0_[5] ),
        .O(\rd_data_edge_detect_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D1D1D1D1D1D1D)) 
    \rd_data_edge_detect_r[1]_i_4 
       (.I0(\rd_data_previous_r_reg_n_0_[0] ),
        .I1(dqs_count_r[0]),
        .I2(\rd_data_previous_r_reg_n_0_[1] ),
        .I3(\stable_cnt_reg_n_0_[1] ),
        .I4(\stable_cnt_reg_n_0_[3] ),
        .I5(\stable_cnt_reg_n_0_[2] ),
        .O(\rd_data_edge_detect_r[1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair247" *) 
  LUT5 #(
    .INIT(32'hFDFDCAFA)) 
    \rd_data_edge_detect_r[1]_i_5 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[3]),
        .O(\rd_data_edge_detect_r[1]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair266" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rd_data_edge_detect_r[1]_i_6 
       (.I0(\rd_data_edge_detect_r_reg_n_0_[1] ),
        .I1(\dqs_count_r_reg[0]_rep_n_0 ),
        .I2(\rd_data_edge_detect_r_reg_n_0_[0] ),
        .O(\rd_data_edge_detect_r[1]_i_6_n_0 ));
  FDRE \rd_data_edge_detect_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_data_edge_detect_r[0]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \rd_data_edge_detect_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_data_edge_detect_r[1]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[1] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair277" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rd_data_previous_r[0]_i_1 
       (.I0(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),
        .I1(rd_data_previous_r0),
        .I2(\rd_data_previous_r_reg_n_0_[0] ),
        .O(\rd_data_previous_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair277" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rd_data_previous_r[1]_i_1 
       (.I0(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),
        .I1(rd_data_previous_r0),
        .I2(\rd_data_previous_r_reg_n_0_[1] ),
        .O(\rd_data_previous_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAABABABBEAEBBAB)) 
    \rd_data_previous_r[1]_i_2 
       (.I0(\stable_cnt[3]_i_6_n_0 ),
        .I1(wl_state_r__0[3]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[1]),
        .I5(wl_state_r__0[4]),
        .O(rd_data_previous_r0));
  FDRE \rd_data_previous_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_data_previous_r[0]_i_1_n_0 ),
        .Q(\rd_data_previous_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_data_previous_r[1]_i_1_n_0 ),
        .Q(\rd_data_previous_r_reg_n_0_[1] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h000000BA)) 
    \single_rank.done_dqs_dec_i_1 
       (.I0(done_dqs_tap_inc),
        .I1(wr_level_done_r4),
        .I2(wr_level_done_r3),
        .I3(done_dqs_dec237_out),
        .I4(\single_rank.done_dqs_dec_reg_0 ),
        .O(\single_rank.done_dqs_dec_i_1_n_0 ));
  FDRE \single_rank.done_dqs_dec_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\single_rank.done_dqs_dec_i_1_n_0 ),
        .Q(done_dqs_tap_inc),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \smallest[0][5]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[3]),
        .I4(dqs_count_r[0]),
        .I5(dqs_count_r[1]),
        .O(\smallest[0][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000001000000000)) 
    \smallest[1][5]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[3]),
        .I4(dqs_count_r[1]),
        .I5(dqs_count_r[0]),
        .O(\smallest[1][5]_i_1_n_0 ));
  FDRE \smallest_reg[0][0] 
       (.C(CLK),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[0]),
        .Q(\smallest_reg[0]_4 [0]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \smallest_reg[0][1] 
       (.C(CLK),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[1]),
        .Q(\smallest_reg[0]_4 [1]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \smallest_reg[0][2] 
       (.C(CLK),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[2]),
        .Q(\smallest_reg[0]_4 [2]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \smallest_reg[0][3] 
       (.C(CLK),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[3]),
        .Q(\smallest_reg[0]_4 [3]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \smallest_reg[0][4] 
       (.C(CLK),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[4]),
        .Q(\smallest_reg[0]_4 [4]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \smallest_reg[0][5] 
       (.C(CLK),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[5]),
        .Q(\smallest_reg[0]_4 [5]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \smallest_reg[1][0] 
       (.C(CLK),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),
        .Q(\smallest_reg[1]_5 [0]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \smallest_reg[1][1] 
       (.C(CLK),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),
        .Q(\smallest_reg[1]_5 [1]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \smallest_reg[1][2] 
       (.C(CLK),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),
        .Q(\smallest_reg[1]_5 [2]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \smallest_reg[1][3] 
       (.C(CLK),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),
        .Q(\smallest_reg[1]_5 [3]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \smallest_reg[1][4] 
       (.C(CLK),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),
        .Q(\smallest_reg[1]_5 [4]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \smallest_reg[1][5] 
       (.C(CLK),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),
        .Q(\smallest_reg[1]_5 [5]),
        .R(\smallest_reg[1][0]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair234" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \stable_cnt[0]_i_1 
       (.I0(\stable_cnt_reg_n_0_[0] ),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair284" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \stable_cnt[1]_i_1 
       (.I0(\stable_cnt_reg_n_0_[1] ),
        .I1(\stable_cnt_reg_n_0_[0] ),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair284" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \stable_cnt[2]_i_1 
       (.I0(\stable_cnt_reg_n_0_[2] ),
        .I1(\stable_cnt_reg_n_0_[0] ),
        .I2(\stable_cnt_reg_n_0_[1] ),
        .O(p_0_in__1[2]));
  LUT6 #(
    .INIT(64'hDDDDDDDDDDDDDDDF)) 
    \stable_cnt[3]_i_1 
       (.I0(\stable_cnt[3]_i_4_n_0 ),
        .I1(\stable_cnt[3]_i_5_n_0 ),
        .I2(wl_state_r__0[4]),
        .I3(wl_state_r__0[3]),
        .I4(wl_state_r__0[0]),
        .I5(wl_state_r__0[1]),
        .O(stable_cnt0));
  (* SOFT_HLUTNM = "soft_lutpair242" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \stable_cnt[3]_i_10 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[0]),
        .O(\stable_cnt[3]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'h00002AAA)) 
    \stable_cnt[3]_i_2 
       (.I0(\stable_cnt[3]_i_6_n_0 ),
        .I1(\stable_cnt_reg_n_0_[1] ),
        .I2(\stable_cnt_reg_n_0_[3] ),
        .I3(\stable_cnt_reg_n_0_[2] ),
        .I4(\rd_data_edge_detect_r[1]_i_3_n_0 ),
        .O(stable_cnt));
  (* SOFT_HLUTNM = "soft_lutpair270" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \stable_cnt[3]_i_3 
       (.I0(\stable_cnt_reg_n_0_[3] ),
        .I1(\stable_cnt_reg_n_0_[1] ),
        .I2(\stable_cnt_reg_n_0_[0] ),
        .I3(\stable_cnt_reg_n_0_[2] ),
        .O(p_0_in__1[3]));
  LUT5 #(
    .INIT(32'h00000777)) 
    \stable_cnt[3]_i_4 
       (.I0(\stable_cnt[3]_i_7_n_0 ),
        .I1(\wl_state_r1_reg_n_0_[0] ),
        .I2(\stable_cnt[3]_i_8_n_0 ),
        .I3(wl_state_r__0[4]),
        .I4(dqs_po_stg2_f_incdec_reg_0),
        .O(\stable_cnt[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair239" *) 
  LUT5 #(
    .INIT(32'h335ACC5A)) 
    \stable_cnt[3]_i_5 
       (.I0(\rd_data_previous_r_reg_n_0_[0] ),
        .I1(\rd_data_previous_r_reg_n_0_[1] ),
        .I2(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),
        .I3(dqs_count_r[0]),
        .I4(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),
        .O(\stable_cnt[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h44F4444444444444)) 
    \stable_cnt[3]_i_6 
       (.I0(\stable_cnt[3]_i_9_n_0 ),
        .I1(\fine_dec_cnt[5]_i_4_n_0 ),
        .I2(\corse_inc[1][2]_i_3_n_0 ),
        .I3(\wl_state_r1_reg_n_0_[0] ),
        .I4(\stable_cnt[3]_i_10_n_0 ),
        .I5(\stable_cnt[3]_i_7_n_0 ),
        .O(\stable_cnt[3]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \stable_cnt[3]_i_7 
       (.I0(\wl_state_r1_reg_n_0_[1] ),
        .I1(\wl_state_r1_reg_n_0_[3] ),
        .I2(\wl_state_r1_reg_n_0_[2] ),
        .I3(\wl_state_r1_reg_n_0_[4] ),
        .O(\stable_cnt[3]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \stable_cnt[3]_i_8 
       (.I0(wl_state_r__0[3]),
        .I1(wl_state_r__0[2]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .O(\stable_cnt[3]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair275" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \stable_cnt[3]_i_9 
       (.I0(wl_state_r__0[1]),
        .I1(wl_edge_detect_valid_r_reg_n_0),
        .I2(wl_state_r__0[4]),
        .O(\stable_cnt[3]_i_9_n_0 ));
  FDRE \stable_cnt_reg[0] 
       (.C(CLK),
        .CE(stable_cnt),
        .D(p_0_in__1[0]),
        .Q(\stable_cnt_reg_n_0_[0] ),
        .R(stable_cnt0));
  FDRE \stable_cnt_reg[1] 
       (.C(CLK),
        .CE(stable_cnt),
        .D(p_0_in__1[1]),
        .Q(\stable_cnt_reg_n_0_[1] ),
        .R(stable_cnt0));
  FDRE \stable_cnt_reg[2] 
       (.C(CLK),
        .CE(stable_cnt),
        .D(p_0_in__1[2]),
        .Q(\stable_cnt_reg_n_0_[2] ),
        .R(stable_cnt0));
  FDRE \stable_cnt_reg[3] 
       (.C(CLK),
        .CE(stable_cnt),
        .D(p_0_in__1[3]),
        .Q(\stable_cnt_reg_n_0_[3] ),
        .R(stable_cnt0));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_cnt[0]_i_1 
       (.I0(wait_cnt_reg[0]),
        .O(wait_cnt0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair286" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wait_cnt[1]_i_1 
       (.I0(wait_cnt_reg[1]),
        .I1(wait_cnt_reg[0]),
        .O(\wait_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair286" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wait_cnt[2]_i_1 
       (.I0(wait_cnt_reg[2]),
        .I1(wait_cnt_reg[0]),
        .I2(wait_cnt_reg[1]),
        .O(wait_cnt0__0[2]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \wait_cnt[3]_i_2 
       (.I0(phy_ctl_ready_r6_reg_n_0),
        .I1(wait_cnt_reg[3]),
        .I2(wait_cnt_reg[0]),
        .I3(wait_cnt_reg[1]),
        .I4(wait_cnt_reg[2]),
        .O(wait_cnt0));
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wait_cnt[3]_i_3 
       (.I0(wait_cnt_reg[3]),
        .I1(wait_cnt_reg[2]),
        .I2(wait_cnt_reg[1]),
        .I3(wait_cnt_reg[0]),
        .O(wait_cnt0__0[3]));
  FDRE \wait_cnt_reg[0] 
       (.C(CLK),
        .CE(wait_cnt0),
        .D(wait_cnt0__0[0]),
        .Q(wait_cnt_reg[0]),
        .R(SS));
  FDRE \wait_cnt_reg[1] 
       (.C(CLK),
        .CE(wait_cnt0),
        .D(\wait_cnt[1]_i_1_n_0 ),
        .Q(wait_cnt_reg[1]),
        .R(SS));
  FDRE \wait_cnt_reg[2] 
       (.C(CLK),
        .CE(wait_cnt0),
        .D(wait_cnt0__0[2]),
        .Q(wait_cnt_reg[2]),
        .R(SS));
  FDSE \wait_cnt_reg[3] 
       (.C(CLK),
        .CE(wait_cnt0),
        .D(wait_cnt0__0[3]),
        .Q(wait_cnt_reg[3]),
        .S(SS));
  (* SOFT_HLUTNM = "soft_lutpair273" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \wl_corse_cnt[0][0][0]_i_1 
       (.I0(\corse_cnt_reg_n_0_[1][0] ),
        .I1(\dqs_count_r_reg[0]_rep_n_0 ),
        .I2(\corse_cnt_reg_n_0_[0][0] ),
        .O(\wl_corse_cnt[0][0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair280" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \wl_corse_cnt[0][0][1]_i_1 
       (.I0(\corse_cnt_reg_n_0_[1][1] ),
        .I1(\dqs_count_r_reg[0]_rep_n_0 ),
        .I2(\corse_cnt_reg_n_0_[0][1] ),
        .O(\wl_corse_cnt[0][0][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair279" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \wl_corse_cnt[0][0][2]_i_1 
       (.I0(\corse_cnt_reg_n_0_[1][2] ),
        .I1(\dqs_count_r_reg[0]_rep_n_0 ),
        .I2(\corse_cnt_reg_n_0_[0][2] ),
        .O(\wl_corse_cnt[0][0][2]_i_1_n_0 ));
  FDRE \wl_corse_cnt_reg[0][0][0] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][0][5]_i_1_n_0 ),
        .D(\wl_corse_cnt[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][0]_8 [0]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \wl_corse_cnt_reg[0][0][1] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][0][5]_i_1_n_0 ),
        .D(\wl_corse_cnt[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][0]_8 [1]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \wl_corse_cnt_reg[0][0][2] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][0][5]_i_1_n_0 ),
        .D(\wl_corse_cnt[0][0][2]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][0]_8 [2]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \wl_corse_cnt_reg[0][1][0] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_corse_cnt[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][1]_9 [0]),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \wl_corse_cnt_reg[0][1][1] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_corse_cnt[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][1]_9 [1]),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \wl_corse_cnt_reg[0][1][2] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_corse_cnt[0][0][2]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][1]_9 [2]),
        .R(\smallest_reg[1][0]_0 [0]));
  LUT3 #(
    .INIT(8'h02)) 
    \wl_dqs_tap_count_r[0][0][5]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ),
        .I1(dqs_count_r[0]),
        .I2(dqs_count_r[1]),
        .O(\wl_dqs_tap_count_r[0][0][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000800080028)) 
    \wl_dqs_tap_count_r[0][0][5]_i_2 
       (.I0(\wl_dqs_tap_count_r[0][0][5]_i_3_n_0 ),
        .I1(wl_state_r__0[2]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[3]),
        .I4(wl_state_r__0[1]),
        .I5(wl_state_r__0[4]),
        .O(\wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair238" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \wl_dqs_tap_count_r[0][0][5]_i_3 
       (.I0(\rank_cnt_r_reg_n_0_[1] ),
        .I1(\rank_cnt_r_reg_n_0_[0] ),
        .O(\wl_dqs_tap_count_r[0][0][5]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h20)) 
    \wl_dqs_tap_count_r[0][1][5]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ),
        .I1(dqs_count_r[1]),
        .I2(dqs_count_r[0]),
        .O(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][0][0] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][0][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(largest[0]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][0][1] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][0][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(largest[1]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][0][2] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][0][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(largest[2]),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][0][3] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][0][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(largest[3]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][0][4] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][0][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(largest[4]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][0][5] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][0][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(largest[5]),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][1][0] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][1][1] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][1][2] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][1][3] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][1][4] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][1][5] 
       (.C(CLK),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),
        .R(\smallest_reg[1][0]_0 [1]));
  LUT6 #(
    .INIT(64'hFF00BD00FC80FE00)) 
    wl_edge_detect_valid_r_i_1
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[3]),
        .I3(wl_edge_detect_valid_r_reg_n_0),
        .I4(wl_state_r__0[1]),
        .I5(wl_state_r__0[2]),
        .O(wl_edge_detect_valid_r_i_1_n_0));
  FDRE wl_edge_detect_valid_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wl_edge_detect_valid_r_i_1_n_0),
        .Q(wl_edge_detect_valid_r_reg_n_0),
        .R(\smallest_reg[1][0]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair258" *) 
  LUT5 #(
    .INIT(32'hF05A55B6)) 
    \wl_state_r1[0]_i_1 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[3]),
        .I2(wl_state_r__0[4]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[0]),
        .O(\wl_state_r1[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair258" *) 
  LUT5 #(
    .INIT(32'h50557F55)) 
    \wl_state_r1[1]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[3]),
        .O(\wl_state_r1[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair259" *) 
  LUT5 #(
    .INIT(32'h0E4EC099)) 
    \wl_state_r1[2]_i_1 
       (.I0(wl_state_r__0[3]),
        .I1(wl_state_r__0[4]),
        .I2(wl_state_r__0[1]),
        .I3(wl_state_r__0[2]),
        .I4(wl_state_r__0[0]),
        .O(\wl_state_r1[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair261" *) 
  LUT5 #(
    .INIT(32'hE91103B1)) 
    \wl_state_r1[3]_i_1 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[3]),
        .I2(wl_state_r__0[4]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[0]),
        .O(\wl_state_r1[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair259" *) 
  LUT5 #(
    .INIT(32'hFCD14998)) 
    \wl_state_r1[4]_i_1 
       (.I0(wl_state_r__0[3]),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[2]),
        .O(\wl_state_r1[4]_i_1_n_0 ));
  FDRE \wl_state_r1_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_state_r1[0]_i_1_n_0 ),
        .Q(\wl_state_r1_reg_n_0_[0] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \wl_state_r1_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_state_r1[1]_i_1_n_0 ),
        .Q(\wl_state_r1_reg_n_0_[1] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \wl_state_r1_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_state_r1[2]_i_1_n_0 ),
        .Q(\wl_state_r1_reg_n_0_[2] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \wl_state_r1_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_state_r1[3]_i_1_n_0 ),
        .Q(\wl_state_r1_reg_n_0_[3] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \wl_state_r1_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wl_state_r1[4]_i_1_n_0 ),
        .Q(\wl_state_r1_reg_n_0_[4] ),
        .R(\smallest_reg[1][0]_0 [0]));
  LUT6 #(
    .INIT(64'h88888888888A8A8A)) 
    \wl_tap_count_r[0]_i_1 
       (.I0(\wl_tap_count_r[5]_i_4_n_0 ),
        .I1(\wl_tap_count_r[0]_i_2_n_0 ),
        .I2(\wl_tap_count_r_reg_n_0_[0] ),
        .I3(wl_state_r__0[0]),
        .I4(wr_level_done_r5),
        .I5(wl_state_r__0[1]),
        .O(wl_tap_count_r[0]));
  (* SOFT_HLUTNM = "soft_lutpair269" *) 
  LUT4 #(
    .INIT(16'h8C80)) 
    \wl_tap_count_r[0]_i_2 
       (.I0(\smallest_reg[1]_5 [0]),
        .I1(wl_state_r__0[1]),
        .I2(\dqs_count_r_reg[1]_0 [0]),
        .I3(\smallest_reg[0]_4 [0]),
        .O(\wl_tap_count_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAA88A8888888A888)) 
    \wl_tap_count_r[1]_i_1 
       (.I0(\wl_tap_count_r[5]_i_4_n_0 ),
        .I1(\wl_tap_count_r[1]_i_2_n_0 ),
        .I2(\smallest_reg[0]_4 [1]),
        .I3(wl_state_r__0[1]),
        .I4(\dqs_count_r_reg[1]_0 [0]),
        .I5(\smallest_reg[1]_5 [1]),
        .O(wl_tap_count_r[1]));
  (* SOFT_HLUTNM = "soft_lutpair256" *) 
  LUT5 #(
    .INIT(32'h00000666)) 
    \wl_tap_count_r[1]_i_2 
       (.I0(\wl_tap_count_r_reg_n_0_[0] ),
        .I1(\wl_tap_count_r_reg_n_0_[1] ),
        .I2(wl_state_r__0[0]),
        .I3(wr_level_done_r5),
        .I4(wl_state_r__0[1]),
        .O(\wl_tap_count_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAA88A8888888A888)) 
    \wl_tap_count_r[2]_i_1 
       (.I0(\wl_tap_count_r[5]_i_4_n_0 ),
        .I1(\wl_tap_count_r[2]_i_2_n_0 ),
        .I2(\smallest_reg[0]_4 [2]),
        .I3(wl_state_r__0[1]),
        .I4(\dqs_count_r_reg[1]_0 [0]),
        .I5(\smallest_reg[1]_5 [2]),
        .O(wl_tap_count_r[2]));
  LUT6 #(
    .INIT(64'h0000000000787878)) 
    \wl_tap_count_r[2]_i_2 
       (.I0(\wl_tap_count_r_reg_n_0_[1] ),
        .I1(\wl_tap_count_r_reg_n_0_[0] ),
        .I2(\wl_tap_count_r_reg_n_0_[2] ),
        .I3(wl_state_r__0[0]),
        .I4(wr_level_done_r5),
        .I5(wl_state_r__0[1]),
        .O(\wl_tap_count_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h80A08000AAAAAAAA)) 
    \wl_tap_count_r[3]_i_1 
       (.I0(\wl_tap_count_r[5]_i_4_n_0 ),
        .I1(\smallest_reg[1]_5 [3]),
        .I2(wl_state_r__0[1]),
        .I3(\dqs_count_r_reg[1]_0 [0]),
        .I4(\smallest_reg[0]_4 [3]),
        .I5(\wl_tap_count_r[3]_i_2_n_0 ),
        .O(wl_tap_count_r[3]));
  (* SOFT_HLUTNM = "soft_lutpair250" *) 
  LUT5 #(
    .INIT(32'hFFFF9555)) 
    \wl_tap_count_r[3]_i_2 
       (.I0(\wl_tap_count_r_reg_n_0_[3] ),
        .I1(\wl_tap_count_r_reg_n_0_[2] ),
        .I2(\wl_tap_count_r_reg_n_0_[1] ),
        .I3(\wl_tap_count_r_reg_n_0_[0] ),
        .I4(\wl_tap_count_r[4]_i_3_n_0 ),
        .O(\wl_tap_count_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h80A08000AAAAAAAA)) 
    \wl_tap_count_r[4]_i_1 
       (.I0(\wl_tap_count_r[5]_i_4_n_0 ),
        .I1(\smallest_reg[1]_5 [4]),
        .I2(wl_state_r__0[1]),
        .I3(\dqs_count_r_reg[1]_0 [0]),
        .I4(\smallest_reg[0]_4 [4]),
        .I5(\wl_tap_count_r[4]_i_2_n_0 ),
        .O(wl_tap_count_r[4]));
  LUT6 #(
    .INIT(64'hFFFFFFFF95555555)) 
    \wl_tap_count_r[4]_i_2 
       (.I0(\wl_tap_count_r_reg_n_0_[4] ),
        .I1(\wl_tap_count_r_reg_n_0_[3] ),
        .I2(\wl_tap_count_r_reg_n_0_[0] ),
        .I3(\wl_tap_count_r_reg_n_0_[1] ),
        .I4(\wl_tap_count_r_reg_n_0_[2] ),
        .I5(\wl_tap_count_r[4]_i_3_n_0 ),
        .O(\wl_tap_count_r[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair256" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \wl_tap_count_r[4]_i_3 
       (.I0(wl_state_r__0[1]),
        .I1(wr_level_done_r5),
        .I2(wl_state_r__0[0]),
        .O(\wl_tap_count_r[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h003C080C03000003)) 
    \wl_tap_count_r[5]_i_1 
       (.I0(done_dqs_dec237_out),
        .I1(wl_state_r__0[2]),
        .I2(wl_state_r__0[4]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[0]),
        .I5(wl_state_r__0[3]),
        .O(\wl_tap_count_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAA88A8888888A888)) 
    \wl_tap_count_r[5]_i_2 
       (.I0(\wl_tap_count_r[5]_i_4_n_0 ),
        .I1(\wl_tap_count_r[5]_i_5_n_0 ),
        .I2(\smallest_reg[0]_4 [5]),
        .I3(wl_state_r__0[1]),
        .I4(\dqs_count_r_reg[1]_0 [0]),
        .I5(\smallest_reg[1]_5 [5]),
        .O(wl_tap_count_r[5]));
  (* SOFT_HLUTNM = "soft_lutpair252" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \wl_tap_count_r[5]_i_4 
       (.I0(wl_state_r__0[3]),
        .I1(wl_state_r__0[4]),
        .O(\wl_tap_count_r[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000787878)) 
    \wl_tap_count_r[5]_i_5 
       (.I0(\wl_tap_count_r[5]_i_6_n_0 ),
        .I1(\wl_tap_count_r_reg_n_0_[4] ),
        .I2(\wl_tap_count_r_reg_n_0_[5] ),
        .I3(wl_state_r__0[0]),
        .I4(wr_level_done_r5),
        .I5(wl_state_r__0[1]),
        .O(\wl_tap_count_r[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair250" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \wl_tap_count_r[5]_i_6 
       (.I0(\wl_tap_count_r_reg_n_0_[2] ),
        .I1(\wl_tap_count_r_reg_n_0_[1] ),
        .I2(\wl_tap_count_r_reg_n_0_[0] ),
        .I3(\wl_tap_count_r_reg_n_0_[3] ),
        .O(\wl_tap_count_r[5]_i_6_n_0 ));
  FDRE \wl_tap_count_r_reg[0] 
       (.C(CLK),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[0]),
        .Q(\wl_tap_count_r_reg_n_0_[0] ),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \wl_tap_count_r_reg[1] 
       (.C(CLK),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[1]),
        .Q(\wl_tap_count_r_reg_n_0_[1] ),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \wl_tap_count_r_reg[2] 
       (.C(CLK),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[2]),
        .Q(\wl_tap_count_r_reg_n_0_[2] ),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \wl_tap_count_r_reg[3] 
       (.C(CLK),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[3]),
        .Q(\wl_tap_count_r_reg_n_0_[3] ),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \wl_tap_count_r_reg[4] 
       (.C(CLK),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[4]),
        .Q(\wl_tap_count_r_reg_n_0_[4] ),
        .R(\smallest_reg[1][0]_0 [1]));
  FDRE \wl_tap_count_r_reg[5] 
       (.C(CLK),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[5]),
        .Q(\wl_tap_count_r_reg_n_0_[5] ),
        .R(\smallest_reg[1][0]_0 [1]));
  LUT3 #(
    .INIT(8'h8A)) 
    wr_level_done_i_1
       (.I0(done_dqs_tap_inc),
        .I1(wrlvl_byte_redo_r),
        .I2(wrlvl_byte_redo),
        .O(wr_level_done_i_1_n_0));
  FDRE wr_level_done_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_r_reg_n_0),
        .Q(wr_level_done_r1),
        .R(1'b0));
  FDRE wr_level_done_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_r1),
        .Q(wr_level_done_r2),
        .R(1'b0));
  FDRE wr_level_done_r3_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_r2),
        .Q(wr_level_done_r3),
        .R(1'b0));
  FDRE wr_level_done_r4_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_r3),
        .Q(wr_level_done_r4),
        .R(1'b0));
  FDRE wr_level_done_r5_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_r4),
        .Q(wr_level_done_r5),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair238" *) 
  LUT5 #(
    .INIT(32'h01FF0100)) 
    wr_level_done_r_i_1
       (.I0(\rank_cnt_r_reg_n_0_[0] ),
        .I1(\rank_cnt_r_reg_n_0_[1] ),
        .I2(wl_state_r__0[2]),
        .I3(wr_level_done_r_i_2_n_0),
        .I4(wr_level_done_r_reg_n_0),
        .O(wr_level_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h4000400000002020)) 
    wr_level_done_r_i_2
       (.I0(wl_state_r__0[0]),
        .I1(wl_state_r__0[2]),
        .I2(\wrlvl_redo_corse_inc[2]_i_2_n_0 ),
        .I3(done_dqs_dec237_out),
        .I4(p_0_in),
        .I5(wl_state_r__0[3]),
        .O(wr_level_done_r_i_2_n_0));
  FDRE wr_level_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_r_i_1_n_0),
        .Q(wr_level_done_r_reg_n_0),
        .R(\smallest_reg[1][0]_0 [0]));
  (* syn_maxfan = "2" *) 
  FDRE wr_level_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_done_i_1_n_0),
        .Q(wr_level_done_reg_0),
        .R(1'b0));
  FDRE wr_level_start_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wr_level_start_r_reg_0),
        .Q(wr_level_start_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000BAAA00AA)) 
    wrlvl_byte_done_i_1
       (.I0(wrlvl_byte_done),
        .I1(wr_level_done_r4),
        .I2(wr_level_done_r3),
        .I3(wrlvl_byte_redo),
        .I4(wrlvl_byte_redo_r),
        .I5(dqs_po_stg2_f_incdec_reg_0),
        .O(wrlvl_byte_done_i_1_n_0));
  FDRE wrlvl_byte_done_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_byte_done_i_1_n_0),
        .Q(wrlvl_byte_done),
        .R(1'b0));
  FDRE wrlvl_byte_redo_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_byte_redo),
        .Q(wrlvl_byte_redo_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h551F515F000A000A)) 
    wrlvl_rank_done_r_i_1
       (.I0(rank_cnt_r),
        .I1(wrlvl_rank_done_r_i_2_n_0),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[4]),
        .I4(wl_state_r__0[3]),
        .I5(wrlvl_rank_done),
        .O(wrlvl_rank_done_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair244" *) 
  LUT2 #(
    .INIT(4'h2)) 
    wrlvl_rank_done_r_i_2
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[0]),
        .O(wrlvl_rank_done_r_i_2_n_0));
  FDRE wrlvl_rank_done_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wrlvl_rank_done_r_i_1_n_0),
        .Q(wrlvl_rank_done),
        .R(\wl_dqs_tap_count_r_reg[0][0][2]_0 ));
  LUT6 #(
    .INIT(64'h0044FFFF04440000)) 
    \wrlvl_redo_corse_inc[0]_i_1 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[2]),
        .I3(\wrlvl_redo_corse_inc[1]_i_2_n_0 ),
        .I4(\wrlvl_redo_corse_inc[2]_i_3_n_0 ),
        .I5(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .O(\wrlvl_redo_corse_inc[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8880FFFF88080000)) 
    \wrlvl_redo_corse_inc[1]_i_1 
       (.I0(\wrlvl_redo_corse_inc[1]_i_2_n_0 ),
        .I1(\wrlvl_redo_corse_inc[2]_i_2_n_0 ),
        .I2(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I3(wl_state_r__0[2]),
        .I4(\wrlvl_redo_corse_inc[2]_i_3_n_0 ),
        .I5(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .O(\wrlvl_redo_corse_inc[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair249" *) 
  LUT5 #(
    .INIT(32'hDFD5FFFF)) 
    \wrlvl_redo_corse_inc[1]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\final_coarse_tap_reg_n_0_[1][2] ),
        .I2(\dqs_count_r_reg[1]_0 [0]),
        .I3(\final_coarse_tap_reg_n_0_[0][2] ),
        .I4(\wrlvl_redo_corse_inc[1]_i_3_n_0 ),
        .O(\wrlvl_redo_corse_inc[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h202AA0AA2A2AAAAA)) 
    \wrlvl_redo_corse_inc[1]_i_3 
       (.I0(\wrlvl_redo_corse_inc[1]_i_2_0 ),
        .I1(\final_coarse_tap_reg[1][0]_0 ),
        .I2(\dqs_count_r_reg[1]_0 [0]),
        .I3(\final_coarse_tap_reg[0][0]_0 ),
        .I4(\final_coarse_tap_reg_n_0_[1][1] ),
        .I5(\final_coarse_tap_reg_n_0_[0][1] ),
        .O(\wrlvl_redo_corse_inc[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAAA8FFFFAA020000)) 
    \wrlvl_redo_corse_inc[2]_i_1 
       (.I0(\wrlvl_redo_corse_inc[2]_i_2_n_0 ),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I2(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .I3(wl_state_r__0[2]),
        .I4(\wrlvl_redo_corse_inc[2]_i_3_n_0 ),
        .I5(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .O(\wrlvl_redo_corse_inc[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair232" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \wrlvl_redo_corse_inc[2]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[4]),
        .O(\wrlvl_redo_corse_inc[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair264" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    \wrlvl_redo_corse_inc[2]_i_3 
       (.I0(wl_state_r__0[4]),
        .I1(wl_state_r__0[3]),
        .I2(wl_state_r__0[1]),
        .I3(\wrlvl_redo_corse_inc[2]_i_4_n_0 ),
        .O(\wrlvl_redo_corse_inc[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF5F5FFCFF5F5F)) 
    \wrlvl_redo_corse_inc[2]_i_4 
       (.I0(\FSM_sequential_wl_state_r[2]_i_13_n_0 ),
        .I1(\FSM_sequential_wl_state_r[4]_i_4_0 ),
        .I2(wl_state_r__0[0]),
        .I3(done_dqs_dec237_out),
        .I4(wl_state_r__0[2]),
        .I5(\corse_cnt[0][2]_i_4_n_0 ),
        .O(\wrlvl_redo_corse_inc[2]_i_4_n_0 ));
  FDRE \wrlvl_redo_corse_inc_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrlvl_redo_corse_inc[0]_i_1_n_0 ),
        .Q(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \wrlvl_redo_corse_inc_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrlvl_redo_corse_inc[1]_i_1_n_0 ),
        .Q(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .R(\smallest_reg[1][0]_0 [0]));
  FDRE \wrlvl_redo_corse_inc_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wrlvl_redo_corse_inc[2]_i_1_n_0 ),
        .Q(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .R(\smallest_reg[1][0]_0 [0]));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_infrastructure
   (\gen_mmcm.mmcm_i_i_1_0 ,
    CLK,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    RST0,
    in0,
    SR,
    rstdiv0_sync_r1_reg_rep__1_0,
    rstdiv0_sync_r1_reg_rep__2_0,
    rstdiv0_sync_r1_reg_rep__4_0,
    rstdiv0_sync_r1_reg_rep__6_0,
    rstdiv0_sync_r1_reg_rep__7_0,
    rstdiv0_sync_r1_reg_rep__8_0,
    rstdiv0_sync_r1_reg_rep__9_0,
    rstdiv0_sync_r1_reg_rep__10_0,
    rstdiv0_sync_r1_reg_rep__14_0,
    rstdiv0_sync_r1_reg_rep__15_0,
    rstdiv0_sync_r1_reg_rep__16_0,
    rstdiv0_sync_r1_reg_rep__17_0,
    rstdiv0_sync_r1_reg_rep__18_0,
    pll_locked,
    bm_end_r1_reg,
    bm_end_r1_reg_0,
    bm_end_r1_reg_1,
    bm_end_r1_reg_2,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    SS,
    po_cnt_dec_reg,
    new_cnt_cpt_r_reg,
    rdlvl_stg1_start_reg,
    samp_edge_cnt0_en_r_reg,
    pi_cnt_dec_reg,
    rstdiv0_sync_r1_reg_rep__15_1,
    prbs_rdlvl_done_pulse_reg,
    mmcm_clk,
    AS,
    rst_tmp,
    bm_end_r1,
    bm_end_r1_0,
    bm_end_r1_1,
    bm_end_r1_2,
    insert_maint_r,
    po_cnt_dec,
    po_cnt_dec_3,
    \tap_cnt_cpt_r_reg[5] ,
    \cnt_shift_r_reg[0] ,
    samp_edge_cnt0_en_r,
    pi_cnt_dec,
    \en_cnt_div4.enable_wrlvl_cnt_reg[4] ,
    prbs_rdlvl_done_pulse);
  output \gen_mmcm.mmcm_i_i_1_0 ;
  output CLK;
  output freq_refclk;
  output mem_refclk;
  output sync_pulse;
  output RST0;
  output in0;
  output [0:0]SR;
  output rstdiv0_sync_r1_reg_rep__1_0;
  output [0:0]rstdiv0_sync_r1_reg_rep__2_0;
  output [1:0]rstdiv0_sync_r1_reg_rep__4_0;
  output [1:0]rstdiv0_sync_r1_reg_rep__6_0;
  output rstdiv0_sync_r1_reg_rep__7_0;
  output rstdiv0_sync_r1_reg_rep__8_0;
  output rstdiv0_sync_r1_reg_rep__9_0;
  output [3:0]rstdiv0_sync_r1_reg_rep__10_0;
  output rstdiv0_sync_r1_reg_rep__14_0;
  output rstdiv0_sync_r1_reg_rep__15_0;
  output rstdiv0_sync_r1_reg_rep__16_0;
  output rstdiv0_sync_r1_reg_rep__17_0;
  output rstdiv0_sync_r1_reg_rep__18_0;
  output pll_locked;
  output bm_end_r1_reg;
  output bm_end_r1_reg_0;
  output bm_end_r1_reg_1;
  output bm_end_r1_reg_2;
  output \generate_maint_cmds.insert_maint_r_lcl_reg ;
  output [0:0]SS;
  output [0:0]po_cnt_dec_reg;
  output [0:0]new_cnt_cpt_r_reg;
  output [0:0]rdlvl_stg1_start_reg;
  output samp_edge_cnt0_en_r_reg;
  output [0:0]pi_cnt_dec_reg;
  output rstdiv0_sync_r1_reg_rep__15_1;
  output prbs_rdlvl_done_pulse_reg;
  input mmcm_clk;
  input [0:0]AS;
  input rst_tmp;
  input bm_end_r1;
  input bm_end_r1_0;
  input bm_end_r1_1;
  input bm_end_r1_2;
  input insert_maint_r;
  input po_cnt_dec;
  input po_cnt_dec_3;
  input \tap_cnt_cpt_r_reg[5] ;
  input \cnt_shift_r_reg[0] ;
  input samp_edge_cnt0_en_r;
  input pi_cnt_dec;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  input prbs_rdlvl_done_pulse;

  wire [0:0]AS;
  wire CLK;
  wire RST0;
  wire RST0_0;
  wire [0:0]SR;
  wire [0:0]SS;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire bm_end_r1_1;
  wire bm_end_r1_2;
  wire bm_end_r1_reg;
  wire bm_end_r1_reg_0;
  wire bm_end_r1_reg_1;
  wire bm_end_r1_reg_2;
  wire clk_div2_bufg_in;
  wire clk_pll_i;
  wire \cnt_shift_r_reg[0] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  wire freq_refclk;
  wire \gen_mmcm.mmcm_i_i_1_0 ;
  wire \gen_mmcm.mmcm_i_n_17 ;
  wire \gen_mmcm.u_bufg_clk_div2_n_0 ;
  wire \gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire in0;
  wire insert_maint_r;
  wire mem_refclk;
  wire mmcm_clk;
  wire mmcm_ps_clk_bufg_in;
  wire [0:0]new_cnt_cpt_r_reg;
  wire pi_cnt_dec;
  wire [0:0]pi_cnt_dec_reg;
  wire pll_clk3;
  wire pll_clk3_out;
  wire pll_clkfbout;
  wire pll_locked;
  wire pll_locked_i;
  wire po_cnt_dec;
  wire po_cnt_dec_3;
  wire [0:0]po_cnt_dec_reg;
  wire prbs_rdlvl_done_pulse;
  wire prbs_rdlvl_done_pulse_reg;
  wire [0:0]rdlvl_stg1_start_reg;
  wire [11:0]rst_sync_r;
  (* MAX_FANOUT = "10" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire rst_sync_r1;
  wire rst_tmp;
  wire [11:0]rstdiv0_sync_r;
  wire rstdiv0_sync_r1_reg_rep__0_n_0;
  wire [3:0]rstdiv0_sync_r1_reg_rep__10_0;
  wire rstdiv0_sync_r1_reg_rep__10_n_0;
  wire rstdiv0_sync_r1_reg_rep__11_n_0;
  wire rstdiv0_sync_r1_reg_rep__12_n_0;
  wire rstdiv0_sync_r1_reg_rep__13_n_0;
  wire rstdiv0_sync_r1_reg_rep__14_0;
  wire rstdiv0_sync_r1_reg_rep__14_n_0;
  wire rstdiv0_sync_r1_reg_rep__15_0;
  wire rstdiv0_sync_r1_reg_rep__15_1;
  wire rstdiv0_sync_r1_reg_rep__15_n_0;
  wire rstdiv0_sync_r1_reg_rep__16_0;
  wire rstdiv0_sync_r1_reg_rep__16_n_0;
  wire rstdiv0_sync_r1_reg_rep__17_0;
  wire rstdiv0_sync_r1_reg_rep__17_n_0;
  wire rstdiv0_sync_r1_reg_rep__18_0;
  wire rstdiv0_sync_r1_reg_rep__18_n_0;
  wire rstdiv0_sync_r1_reg_rep__1_0;
  wire rstdiv0_sync_r1_reg_rep__1_n_0;
  wire [0:0]rstdiv0_sync_r1_reg_rep__2_0;
  wire rstdiv0_sync_r1_reg_rep__2_n_0;
  wire rstdiv0_sync_r1_reg_rep__3_n_0;
  wire [1:0]rstdiv0_sync_r1_reg_rep__4_0;
  wire rstdiv0_sync_r1_reg_rep__4_n_0;
  wire rstdiv0_sync_r1_reg_rep__5_n_0;
  wire [1:0]rstdiv0_sync_r1_reg_rep__6_0;
  wire rstdiv0_sync_r1_reg_rep__6_n_0;
  wire rstdiv0_sync_r1_reg_rep__7_0;
  wire rstdiv0_sync_r1_reg_rep__7_n_0;
  wire rstdiv0_sync_r1_reg_rep__8_0;
  wire rstdiv0_sync_r1_reg_rep__8_n_0;
  wire rstdiv0_sync_r1_reg_rep__9_0;
  wire rstdiv0_sync_r1_reg_rep__9_n_0;
  wire rstdiv0_sync_r1_reg_rep_n_0;
  wire [11:0]rstdiv2_sync_r;
  (* MAX_FANOUT = "10" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire rstdiv2_sync_r1;
  wire samp_edge_cnt0_en_r;
  wire samp_edge_cnt0_en_r_reg;
  wire sync_pulse;
  wire \tap_cnt_cpt_r_reg[5] ;
  wire \NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ;
  wire [15:0]\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED ;
  wire NLW_plle2_i_CLKOUT4_UNCONNECTED;
  wire NLW_plle2_i_CLKOUT5_UNCONNECTED;
  wire NLW_plle2_i_DRDY_UNCONNECTED;
  wire [15:0]NLW_plle2_i_DO_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \cnt_shift_r[3]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__15_0),
        .I1(\cnt_shift_r_reg[0] ),
        .O(rdlvl_stg1_start_reg));
  LUT2 #(
    .INIT(4'h1)) 
    complex_row0_rd_done_i_2
       (.I0(rstdiv0_sync_r1_reg_rep__14_0),
        .I1(prbs_rdlvl_done_pulse),
        .O(prbs_rdlvl_done_pulse_reg));
  LUT2 #(
    .INIT(4'hE)) 
    \en_cnt_div4.enable_wrlvl_cnt[4]_i_2 
       (.I0(rstdiv0_sync_r1_reg_rep__15_0),
        .I1(\en_cnt_div4.enable_wrlvl_cnt_reg[4] ),
        .O(rstdiv0_sync_r1_reg_rep__15_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  MMCME2_ADV #(
    .BANDWIDTH("HIGH"),
    .CLKFBOUT_MULT_F(8.000000),
    .CLKFBOUT_PHASE(0.000000),
    .CLKFBOUT_USE_FINE_PS("FALSE"),
    .CLKIN1_PERIOD(12.304000),
    .CLKIN2_PERIOD(0.000000),
    .CLKOUT0_DIVIDE_F(16.000000),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT0_USE_FINE_PS("TRUE"),
    .CLKOUT1_DIVIDE(4),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUT1_USE_FINE_PS("FALSE"),
    .CLKOUT2_DIVIDE(1),
    .CLKOUT2_DUTY_CYCLE(0.500000),
    .CLKOUT2_PHASE(0.000000),
    .CLKOUT2_USE_FINE_PS("FALSE"),
    .CLKOUT3_DIVIDE(1),
    .CLKOUT3_DUTY_CYCLE(0.500000),
    .CLKOUT3_PHASE(0.000000),
    .CLKOUT3_USE_FINE_PS("FALSE"),
    .CLKOUT4_CASCADE("FALSE"),
    .CLKOUT4_DIVIDE(1),
    .CLKOUT4_DUTY_CYCLE(0.500000),
    .CLKOUT4_PHASE(0.000000),
    .CLKOUT4_USE_FINE_PS("FALSE"),
    .CLKOUT5_DIVIDE(1),
    .CLKOUT5_DUTY_CYCLE(0.500000),
    .CLKOUT5_PHASE(0.000000),
    .CLKOUT5_USE_FINE_PS("FALSE"),
    .CLKOUT6_DIVIDE(1),
    .CLKOUT6_DUTY_CYCLE(0.500000),
    .CLKOUT6_PHASE(0.000000),
    .CLKOUT6_USE_FINE_PS("FALSE"),
    .COMPENSATION("BUF_IN"),
    .DIVCLK_DIVIDE(1),
    .IS_CLKINSEL_INVERTED(1'b0),
    .IS_PSEN_INVERTED(1'b0),
    .IS_PSINCDEC_INVERTED(1'b0),
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .REF_JITTER1(0.000000),
    .REF_JITTER2(0.010000),
    .SS_EN("FALSE"),
    .SS_MODE("CENTER_HIGH"),
    .SS_MOD_PERIOD(10000),
    .STARTUP_WAIT("FALSE")) 
    \gen_mmcm.mmcm_i 
       (.CLKFBIN(CLK),
        .CLKFBOUT(clk_pll_i),
        .CLKFBOUTB(\NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ),
        .CLKFBSTOPPED(\NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ),
        .CLKIN1(pll_clk3),
        .CLKIN2(1'b0),
        .CLKINSEL(1'b1),
        .CLKINSTOPPED(\NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ),
        .CLKOUT0(mmcm_ps_clk_bufg_in),
        .CLKOUT0B(\NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ),
        .CLKOUT1(clk_div2_bufg_in),
        .CLKOUT1B(\NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ),
        .CLKOUT2(\NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ),
        .CLKOUT2B(\NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ),
        .CLKOUT3(\NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ),
        .CLKOUT3B(\NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ),
        .CLKOUT4(\NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ),
        .CLKOUT5(\NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ),
        .CLKOUT6(\NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED [15:0]),
        .DRDY(\NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ),
        .DWE(1'b0),
        .LOCKED(\gen_mmcm.mmcm_i_i_1_0 ),
        .PSCLK(CLK),
        .PSDONE(\gen_mmcm.mmcm_i_n_17 ),
        .PSEN(1'b0),
        .PSINCDEC(1'b0),
        .PWRDWN(1'b0),
        .RST(RST0_0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_mmcm.mmcm_i_i_1 
       (.I0(pll_locked_i),
        .O(RST0_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFG \gen_mmcm.u_bufg_clk_div2 
       (.I(clk_div2_bufg_in),
        .O(\gen_mmcm.u_bufg_clk_div2_n_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFG \gen_mmcm.u_bufg_mmcm_ps_clk 
       (.I(mmcm_ps_clk_bufg_in),
        .O(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT2 #(
    .INIT(4'h7)) 
    phaser_ref_i_i_1
       (.I0(\gen_mmcm.mmcm_i_i_1_0 ),
        .I1(pll_locked_i),
        .O(RST0));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phy_control_i_i_1
       (.I0(pll_locked_i),
        .I1(\gen_mmcm.mmcm_i_i_1_0 ),
        .O(pll_locked));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PLLE2_ADV #(
    .BANDWIDTH("OPTIMIZED"),
    .CLKFBOUT_MULT(13),
    .CLKFBOUT_PHASE(0.000000),
    .CLKIN1_PERIOD(10.000000),
    .CLKIN2_PERIOD(0.000000),
    .CLKOUT0_DIVIDE(2),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT1_DIVIDE(4),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUT2_DIVIDE(64),
    .CLKOUT2_DUTY_CYCLE(0.062500),
    .CLKOUT2_PHASE(9.843750),
    .CLKOUT3_DIVIDE(16),
    .CLKOUT3_DUTY_CYCLE(0.500000),
    .CLKOUT3_PHASE(0.000000),
    .CLKOUT4_DIVIDE(8),
    .CLKOUT4_DUTY_CYCLE(0.500000),
    .CLKOUT4_PHASE(168.750000),
    .CLKOUT5_DIVIDE(1),
    .CLKOUT5_DUTY_CYCLE(0.500000),
    .CLKOUT5_PHASE(0.000000),
    .COMPENSATION("INTERNAL"),
    .DIVCLK_DIVIDE(1),
    .IS_CLKINSEL_INVERTED(1'b0),
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .REF_JITTER1(0.010000),
    .REF_JITTER2(0.010000),
    .STARTUP_WAIT("FALSE")) 
    plle2_i
       (.CLKFBIN(pll_clkfbout),
        .CLKFBOUT(pll_clkfbout),
        .CLKIN1(mmcm_clk),
        .CLKIN2(1'b0),
        .CLKINSEL(1'b1),
        .CLKOUT0(freq_refclk),
        .CLKOUT1(mem_refclk),
        .CLKOUT2(sync_pulse),
        .CLKOUT3(pll_clk3_out),
        .CLKOUT4(NLW_plle2_i_CLKOUT4_UNCONNECTED),
        .CLKOUT5(NLW_plle2_i_CLKOUT5_UNCONNECTED),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(NLW_plle2_i_DO_UNCONNECTED[15:0]),
        .DRDY(NLW_plle2_i_DRDY_UNCONNECTED),
        .DWE(1'b0),
        .LOCKED(pll_locked_i),
        .PWRDWN(1'b0),
        .RST(AS));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \ras_timer_r[0]_i_4 
       (.I0(rstdiv0_sync_r1_reg_rep__17_0),
        .I1(bm_end_r1),
        .O(bm_end_r1_reg));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \ras_timer_r[0]_i_4__0 
       (.I0(rstdiv0_sync_r1_reg_rep__17_0),
        .I1(bm_end_r1_0),
        .O(bm_end_r1_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \ras_timer_r[0]_i_4__1 
       (.I0(rstdiv0_sync_r1_reg_rep__17_0),
        .I1(bm_end_r1_1),
        .O(bm_end_r1_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT2 #(
    .INIT(4'hE)) 
    ras_timer_zero_r_i_3
       (.I0(rstdiv0_sync_r1_reg_rep__17_0),
        .I1(bm_end_r1_2),
        .O(bm_end_r1_reg_2));
  LUT2 #(
    .INIT(4'h1)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_3 
       (.I0(rstdiv0_sync_r1_reg_rep__16_0),
        .I1(insert_maint_r),
        .O(\generate_maint_cmds.insert_maint_r_lcl_reg ));
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDPE rst_sync_r1_reg
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rst_sync_r1));
  FDPE \rst_sync_r_reg[0] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(1'b0),
        .PRE(rst_tmp),
        .Q(rst_sync_r[0]));
  FDPE \rst_sync_r_reg[10] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[9]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[10]));
  FDPE \rst_sync_r_reg[11] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[10]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[11]));
  FDPE \rst_sync_r_reg[1] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[0]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[1]));
  FDPE \rst_sync_r_reg[2] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[1]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[2]));
  FDPE \rst_sync_r_reg[3] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[2]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[3]));
  FDPE \rst_sync_r_reg[4] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[3]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[4]));
  FDPE \rst_sync_r_reg[5] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[4]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[5]));
  FDPE \rst_sync_r_reg[6] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[5]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[6]));
  FDPE \rst_sync_r_reg[7] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[6]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[7]));
  FDPE \rst_sync_r_reg[8] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[7]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[8]));
  FDPE \rst_sync_r_reg[9] 
       (.C(\gen_mmcm.u_bufg_mmcm_ps_clk_n_0 ),
        .CE(1'b1),
        .D(rst_sync_r[8]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[9]));
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst
       (.I0(rstdiv0_sync_r1_reg_rep_n_0),
        .O(in0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep
       (.I0(rstdiv0_sync_r1_reg_rep__0_n_0),
        .O(SR));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__0
       (.I0(rstdiv0_sync_r1_reg_rep__1_n_0),
        .O(rstdiv0_sync_r1_reg_rep__1_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__1
       (.I0(rstdiv0_sync_r1_reg_rep__2_n_0),
        .O(rstdiv0_sync_r1_reg_rep__2_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__10
       (.I0(rstdiv0_sync_r1_reg_rep__11_n_0),
        .O(rstdiv0_sync_r1_reg_rep__10_0[2]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__11
       (.I0(rstdiv0_sync_r1_reg_rep__12_n_0),
        .O(rstdiv0_sync_r1_reg_rep__10_0[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__12
       (.I0(rstdiv0_sync_r1_reg_rep__13_n_0),
        .O(rstdiv0_sync_r1_reg_rep__10_0[0]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__13
       (.I0(rstdiv0_sync_r1_reg_rep__14_n_0),
        .O(rstdiv0_sync_r1_reg_rep__14_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__14
       (.I0(rstdiv0_sync_r1_reg_rep__15_n_0),
        .O(rstdiv0_sync_r1_reg_rep__15_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__15
       (.I0(rstdiv0_sync_r1_reg_rep__16_n_0),
        .O(rstdiv0_sync_r1_reg_rep__16_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__16
       (.I0(rstdiv0_sync_r1_reg_rep__17_n_0),
        .O(rstdiv0_sync_r1_reg_rep__17_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__17
       (.I0(rstdiv0_sync_r1_reg_rep__18_n_0),
        .O(rstdiv0_sync_r1_reg_rep__18_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__2
       (.I0(rstdiv0_sync_r1_reg_rep__3_n_0),
        .O(rstdiv0_sync_r1_reg_rep__4_0[0]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__3
       (.I0(rstdiv0_sync_r1_reg_rep__4_n_0),
        .O(rstdiv0_sync_r1_reg_rep__4_0[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__4
       (.I0(rstdiv0_sync_r1_reg_rep__5_n_0),
        .O(rstdiv0_sync_r1_reg_rep__6_0[0]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__5
       (.I0(rstdiv0_sync_r1_reg_rep__6_n_0),
        .O(rstdiv0_sync_r1_reg_rep__6_0[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__6
       (.I0(rstdiv0_sync_r1_reg_rep__7_n_0),
        .O(rstdiv0_sync_r1_reg_rep__7_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__7
       (.I0(rstdiv0_sync_r1_reg_rep__8_n_0),
        .O(rstdiv0_sync_r1_reg_rep__8_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__8
       (.I0(rstdiv0_sync_r1_reg_rep__9_n_0),
        .O(rstdiv0_sync_r1_reg_rep__9_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__9
       (.I0(rstdiv0_sync_r1_reg_rep__10_n_0),
        .O(rstdiv0_sync_r1_reg_rep__10_0[3]));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__0
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__0_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__1
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__1_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__10
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__10_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__11
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__11_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__12
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__12_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__13
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__13_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__14
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__14_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__15
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__15_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__16
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__16_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__17
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__17_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__18
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__18_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__2
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__2_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__3
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__3_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__4
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__4_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__5
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__5_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__6
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__6_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__7
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__7_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__8
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__8_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__9
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__9_n_0));
  FDPE \rstdiv0_sync_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(1'b0),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[0]));
  FDPE \rstdiv0_sync_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[9]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[10]));
  FDPE \rstdiv0_sync_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[10]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[11]));
  FDPE \rstdiv0_sync_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[0]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[1]));
  FDPE \rstdiv0_sync_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[1]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[2]));
  FDPE \rstdiv0_sync_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[2]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[3]));
  FDPE \rstdiv0_sync_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[3]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[4]));
  FDPE \rstdiv0_sync_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[4]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[5]));
  FDPE \rstdiv0_sync_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[5]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[6]));
  FDPE \rstdiv0_sync_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[6]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[7]));
  FDPE \rstdiv0_sync_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[7]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[8]));
  FDPE \rstdiv0_sync_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(rstdiv0_sync_r[8]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[9]));
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDPE rstdiv2_sync_r1_reg
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(rstdiv2_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r1));
  FDPE \rstdiv2_sync_r_reg[0] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(1'b0),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r[0]));
  FDPE \rstdiv2_sync_r_reg[10] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(rstdiv2_sync_r[9]),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r[10]));
  FDPE \rstdiv2_sync_r_reg[11] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(rstdiv2_sync_r[10]),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r[11]));
  FDPE \rstdiv2_sync_r_reg[1] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(rstdiv2_sync_r[0]),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r[1]));
  FDPE \rstdiv2_sync_r_reg[2] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(rstdiv2_sync_r[1]),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r[2]));
  FDPE \rstdiv2_sync_r_reg[3] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(rstdiv2_sync_r[2]),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r[3]));
  FDPE \rstdiv2_sync_r_reg[4] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(rstdiv2_sync_r[3]),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r[4]));
  FDPE \rstdiv2_sync_r_reg[5] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(rstdiv2_sync_r[4]),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r[5]));
  FDPE \rstdiv2_sync_r_reg[6] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(rstdiv2_sync_r[5]),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r[6]));
  FDPE \rstdiv2_sync_r_reg[7] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(rstdiv2_sync_r[6]),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r[7]));
  FDPE \rstdiv2_sync_r_reg[8] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(rstdiv2_sync_r[7]),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r[8]));
  FDPE \rstdiv2_sync_r_reg[9] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(rstdiv2_sync_r[8]),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r[9]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \samp_edge_cnt0_r[0]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__15_0),
        .I1(samp_edge_cnt0_en_r),
        .O(samp_edge_cnt0_en_r_reg));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \tap_cnt_cpt_r[5]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__15_0),
        .I1(\tap_cnt_cpt_r_reg[5] ),
        .O(new_cnt_cpt_r_reg));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFG u_bufg_clkdiv0
       (.I(clk_pll_i),
        .O(CLK));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFH u_bufh_pll_clk3
       (.I(pll_clk3_out),
        .O(pll_clk3));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \wait_cnt[3]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__16_0),
        .I1(po_cnt_dec),
        .O(SS));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \wait_cnt_r[3]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__16_0),
        .I1(po_cnt_dec_3),
        .O(po_cnt_dec_reg));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \wait_cnt_r[3]_i_1__0 
       (.I0(rstdiv0_sync_r1_reg_rep__15_0),
        .I1(pi_cnt_dec),
        .O(pi_cnt_dec_reg));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_iodelay_ctrl
   (AS,
    rst_tmp,
    clk_ref_i,
    sys_rst,
    \rstdiv2_sync_r_reg[11] ,
    ref_dll_lock);
  output [0:0]AS;
  output rst_tmp;
  input clk_ref_i;
  input sys_rst;
  input \rstdiv2_sync_r_reg[11] ;
  input ref_dll_lock;

  wire clk_ref_i;
  wire [0:0]iodelay_ctrl_rdy;
  wire ref_dll_lock;
  wire [0:0]rst_ref;
  wire \rst_ref_sync_r_reg_n_0_[0][0] ;
  wire \rst_ref_sync_r_reg_n_0_[0][10] ;
  wire \rst_ref_sync_r_reg_n_0_[0][11] ;
  wire \rst_ref_sync_r_reg_n_0_[0][12] ;
  wire \rst_ref_sync_r_reg_n_0_[0][13] ;
  wire \rst_ref_sync_r_reg_n_0_[0][1] ;
  wire \rst_ref_sync_r_reg_n_0_[0][2] ;
  wire \rst_ref_sync_r_reg_n_0_[0][3] ;
  wire \rst_ref_sync_r_reg_n_0_[0][4] ;
  wire \rst_ref_sync_r_reg_n_0_[0][5] ;
  wire \rst_ref_sync_r_reg_n_0_[0][6] ;
  wire \rst_ref_sync_r_reg_n_0_[0][7] ;
  wire \rst_ref_sync_r_reg_n_0_[0][8] ;
  wire \rst_ref_sync_r_reg_n_0_[0][9] ;
  wire rst_tmp;
  wire \rstdiv2_sync_r_reg[11] ;
  (* RTL_KEEP = "true" *) wire sys_rst_i;

  assign AS[0] = sys_rst_i;
  assign sys_rst_i = sys_rst;
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][0] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(1'b0),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][0] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][10] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][9] ),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][10] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][11] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][10] ),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][11] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][12] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][11] ),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][12] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][13] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][12] ),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][13] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][14] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][13] ),
        .PRE(sys_rst_i),
        .Q(rst_ref));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][1] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][0] ),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][1] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][2] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][1] ),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][2] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][3] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][2] ),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][3] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][4] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][3] ),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][4] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][5] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][4] ),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][5] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][6] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][5] ),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][6] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][7] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][6] ),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][7] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][8] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][7] ),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][8] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][9] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][8] ),
        .PRE(sys_rst_i),
        .Q(\rst_ref_sync_r_reg_n_0_[0][9] ));
  LUT4 #(
    .INIT(16'hDFFF)) 
    \rstdiv2_sync_r[11]_i_1 
       (.I0(\rstdiv2_sync_r_reg[11] ),
        .I1(sys_rst_i),
        .I2(iodelay_ctrl_rdy),
        .I3(ref_dll_lock),
        .O(rst_tmp));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_7SERIES_0_IODELAY_MIG0" *) 
  IDELAYCTRL #(
    .SIM_DEVICE("7SERIES")) 
    u_idelayctrl_200
       (.RDY(iodelay_ctrl_rdy),
        .REFCLK(clk_ref_i),
        .RST(rst_ref));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_mc
   (\periodic_read_request.periodic_rd_r_lcl_reg ,
    app_ref_ack,
    app_zq_ack,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    bm_end_r1,
    bm_end_r1_0,
    bm_end_r1_1,
    bm_end_r1_2,
    periodic_rd_ack_r_lcl_reg,
    accept_ns,
    mc_cmd,
    app_sr_active,
    periodic_rd_cntr_r_reg,
    head_r_lcl_reg,
    head_r_lcl_reg_0,
    head_r_lcl_reg_1,
    head_r_lcl_reg_2,
    \read_fifo.tail_r_reg[0] ,
    phy_dout,
    mc_cas_n,
    mc_cs_n,
    mc_ras_n,
    Q,
    \req_row_r_lcl_reg[13] ,
    \req_bank_r_lcl_reg[2] ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_bank_r_lcl_reg[2]_1 ,
    \req_bank_r_lcl_reg[2]_2 ,
    \pointer_ram.pointer_we ,
    wr_data_en,
    \read_fifo.fifo_out_data_r_reg[7] ,
    wr_data_addr,
    mc_ref_zq_wip,
    \cmd_pipe_plus.mc_address_reg[41]_0 ,
    \cmd_pipe_plus.mc_bank_reg[8]_0 ,
    mc_odt,
    mc_cke,
    mc_wrdata_en,
    \cmd_pipe_plus.mc_data_offset_reg[3]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[5]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[4]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[2]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[1]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[0]_0 ,
    CLK,
    SR,
    req_wr_r_lcl0,
    rb_hit_busy_r_reg,
    rb_hit_busy_r_reg_0,
    rb_hit_busy_r_reg_1,
    rb_hit_busy_r_reg_2,
    phy_mc_ctl_full,
    in0,
    phy_mc_cmd_full,
    was_wr0,
    \cmd_pipe_plus.mc_data_offset_reg[5]_1 ,
    S,
    row_hit_r_reg,
    row_hit_r_reg_0,
    row_hit_r_reg_1,
    row_hit_r_reg_2,
    \grant_r_reg[0] ,
    \last_master_r_reg[0] ,
    app_zq_req,
    app_sr_req,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ,
    was_priority_reg,
    app_en_r2,
    \inhbt_act_faw.faw_cnt_r_reg[2] ,
    \read_fifo.tail_r_reg[1] ,
    \read_fifo.fifo_out_data_r_reg[7]_0 ,
    \periodic_rd_generation.periodic_rd_timer_r_reg[2] ,
    \rtp_timer_r_reg[0] ,
    app_ref_req,
    rd_wr_r_lcl_reg,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ,
    row,
    ras_timer_zero_r_reg,
    ras_timer_zero_r_reg_0,
    ras_timer_zero_r_reg_1,
    ras_timer_zero_r_reg_2,
    phy_mc_data_full,
    E,
    D,
    bank,
    \req_col_r_reg[9] ,
    \read_fifo.tail_r_reg[0]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[0]_1 );
  output \periodic_read_request.periodic_rd_r_lcl_reg ;
  output app_ref_ack;
  output app_zq_ack;
  output \generate_maint_cmds.insert_maint_r_lcl_reg ;
  output bm_end_r1;
  output bm_end_r1_0;
  output bm_end_r1_1;
  output bm_end_r1_2;
  output periodic_rd_ack_r_lcl_reg;
  output accept_ns;
  output [1:0]mc_cmd;
  output app_sr_active;
  output periodic_rd_cntr_r_reg;
  output head_r_lcl_reg;
  output head_r_lcl_reg_0;
  output head_r_lcl_reg_1;
  output head_r_lcl_reg_2;
  output [0:0]\read_fifo.tail_r_reg[0] ;
  output [6:0]phy_dout;
  output [2:0]mc_cas_n;
  output [0:0]mc_cs_n;
  output [2:0]mc_ras_n;
  output [2:0]Q;
  output [16:0]\req_row_r_lcl_reg[13] ;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [2:0]\req_bank_r_lcl_reg[2]_0 ;
  output [2:0]\req_bank_r_lcl_reg[2]_1 ;
  output [2:0]\req_bank_r_lcl_reg[2]_2 ;
  output \pointer_ram.pointer_we ;
  output wr_data_en;
  output [1:0]\read_fifo.fifo_out_data_r_reg[7] ;
  output [3:0]wr_data_addr;
  output mc_ref_zq_wip;
  output [38:0]\cmd_pipe_plus.mc_address_reg[41]_0 ;
  output [8:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  output [0:0]mc_odt;
  output [0:0]mc_cke;
  output mc_wrdata_en;
  output [0:0]\cmd_pipe_plus.mc_data_offset_reg[3]_0 ;
  output \cmd_pipe_plus.mc_data_offset_reg[5]_0 ;
  output \cmd_pipe_plus.mc_data_offset_reg[4]_0 ;
  output \cmd_pipe_plus.mc_data_offset_reg[2]_0 ;
  output \cmd_pipe_plus.mc_data_offset_reg[1]_0 ;
  output \cmd_pipe_plus.mc_data_offset_reg[0]_0 ;
  input CLK;
  input [0:0]SR;
  input req_wr_r_lcl0;
  input rb_hit_busy_r_reg;
  input rb_hit_busy_r_reg_0;
  input rb_hit_busy_r_reg_1;
  input rb_hit_busy_r_reg_2;
  input phy_mc_ctl_full;
  input in0;
  input phy_mc_cmd_full;
  input was_wr0;
  input [5:0]\cmd_pipe_plus.mc_data_offset_reg[5]_1 ;
  input [2:0]S;
  input [0:0]row_hit_r_reg;
  input [0:0]row_hit_r_reg_0;
  input [0:0]row_hit_r_reg_1;
  input [0:0]row_hit_r_reg_2;
  input \grant_r_reg[0] ;
  input \last_master_r_reg[0] ;
  input app_zq_req;
  input app_sr_req;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  input was_priority_reg;
  input app_en_r2;
  input \inhbt_act_faw.faw_cnt_r_reg[2] ;
  input \read_fifo.tail_r_reg[1] ;
  input \read_fifo.fifo_out_data_r_reg[7]_0 ;
  input \periodic_rd_generation.periodic_rd_timer_r_reg[2] ;
  input \rtp_timer_r_reg[0] ;
  input app_ref_req;
  input rd_wr_r_lcl_reg;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  input [13:0]row;
  input ras_timer_zero_r_reg;
  input ras_timer_zero_r_reg_0;
  input ras_timer_zero_r_reg_1;
  input ras_timer_zero_r_reg_2;
  input phy_mc_data_full;
  input [0:0]E;
  input [3:0]D;
  input [2:0]bank;
  input [9:0]\req_col_r_reg[9] ;
  input \read_fifo.tail_r_reg[0]_0 ;
  input \cmd_pipe_plus.mc_data_offset_reg[0]_1 ;

  wire CLK;
  wire [3:0]D;
  wire [0:0]E;
  wire [2:0]Q;
  wire [2:0]S;
  wire [0:0]SR;
  wire accept_ns;
  wire app_en_r2;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire app_zq_ack;
  wire app_zq_req;
  wire \arb_mux0/arb_select0/cke_r ;
  wire [5:1]\arb_mux0/arb_select0/mc_data_offset1 ;
  wire [2:0]bank;
  wire \bank_cntrl[0].bank0/bank_queue0/set_order_q ;
  wire \bank_cntrl[0].bank0/wait_for_maint_r ;
  wire \bank_cntrl[1].bank0/bank_queue0/set_order_q ;
  wire \bank_cntrl[1].bank0/wait_for_maint_r ;
  wire \bank_cntrl[2].bank0/bank_queue0/set_order_q ;
  wire \bank_cntrl[2].bank0/wait_for_maint_r ;
  wire \bank_cntrl[3].bank0/bank_queue0/set_order_q ;
  wire \bank_cntrl[3].bank0/wait_for_maint_r ;
  wire [0:0]\bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r ;
  wire bank_mach0_n_133;
  wire bank_mach0_n_134;
  wire bank_mach0_n_26;
  wire bank_mach0_n_27;
  wire bank_mach0_n_29;
  wire bank_mach0_n_36;
  wire bank_mach0_n_37;
  wire bank_mach0_n_38;
  wire bank_mach0_n_41;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire bm_end_r1_1;
  wire bm_end_r1_2;
  wire clear_periodic_rd_request;
  wire [38:0]\cmd_pipe_plus.mc_address_reg[41]_0 ;
  wire \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1] ;
  wire [8:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[0]_1 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[1]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[2]_0 ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_reg[3]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[4]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[5]_0 ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5]_1 ;
  wire col_periodic_rd;
  wire col_rd_wr;
  wire [3:0]col_wr_data_buf_addr;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire \grant_r_reg[0] ;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire in0;
  wire \inhbt_act_faw.faw_cnt_r_reg[2] ;
  wire inhbt_act_faw_r;
  wire insert_maint_r1;
  wire \last_master_r_reg[0] ;
  wire maint_rank_r;
  wire maint_ref_zq_wip;
  wire maint_req_r;
  wire maint_srx_r;
  wire maint_wip_r;
  wire maint_zq_r;
  wire [41:0]mc_address_ns;
  wire [8:0]mc_bank_ns;
  wire [2:0]mc_cas_n;
  wire [2:0]mc_cas_n_ns;
  wire [0:0]mc_cke;
  wire [1:1]mc_cke_ns;
  wire [1:0]mc_cmd;
  wire [1:1]mc_cmd_ns;
  wire [0:0]mc_cs_n;
  wire [0:0]mc_cs_n_ns;
  wire [3:3]mc_data_offset_ns;
  wire [0:0]mc_odt;
  wire [0:0]mc_odt_ns;
  wire [2:0]mc_ras_n;
  wire [2:0]mc_ras_n_ns;
  wire mc_ref_zq_wip;
  wire mc_ref_zq_wip_ns;
  wire [2:0]mc_we_n_ns;
  wire mc_wrdata_en;
  wire mc_wrdata_en_ns;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_cntr_r_reg;
  wire \periodic_rd_generation.periodic_rd_timer_r_reg[2] ;
  wire \periodic_read_request.periodic_rd_r_lcl_reg ;
  wire [6:0]phy_dout;
  wire phy_mc_cmd_full;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire \pointer_ram.pointer_we ;
  wire \rank_cntrl[0].rank_cntrl0/act_this_rank ;
  wire \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank ;
  wire \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r ;
  wire \rank_common0/periodic_read_request.periodic_rd_grant_r ;
  wire rank_mach0_n_13;
  wire rank_mach0_n_14;
  wire rank_mach0_n_15;
  wire rank_mach0_n_17;
  wire rank_mach0_n_18;
  wire rank_mach0_n_19;
  wire rank_mach0_n_20;
  wire rank_mach0_n_21;
  wire rank_mach0_n_22;
  wire rank_mach0_n_23;
  wire rank_mach0_n_24;
  wire rank_mach0_n_25;
  wire rank_mach0_n_26;
  wire rank_mach0_n_27;
  wire rank_mach0_n_28;
  wire rank_mach0_n_29;
  wire rank_mach0_n_30;
  wire rank_mach0_n_31;
  wire rank_mach0_n_32;
  wire rank_mach0_n_33;
  wire rank_mach0_n_34;
  wire rank_mach0_n_35;
  wire rank_mach0_n_36;
  wire rank_mach0_n_37;
  wire rank_mach0_n_38;
  wire rank_mach0_n_41;
  wire rank_mach0_n_42;
  wire rank_mach0_n_43;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire ras_timer_zero_r_reg_2;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rb_hit_busy_r_reg_2;
  wire rd_wr_r_lcl_reg;
  wire [1:0]\read_fifo.fifo_out_data_r_reg[7] ;
  wire \read_fifo.fifo_out_data_r_reg[7]_0 ;
  wire [0:0]\read_fifo.tail_r_reg[0] ;
  wire \read_fifo.tail_r_reg[0]_0 ;
  wire \read_fifo.tail_r_reg[1] ;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_2 ;
  wire [9:0]\req_col_r_reg[9] ;
  wire [16:0]\req_row_r_lcl_reg[13] ;
  wire req_wr_r_lcl0;
  wire [7:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  wire [13:0]row;
  wire [0:0]row_hit_r_reg;
  wire [0:0]row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire [0:0]row_hit_r_reg_2;
  wire \rtp_timer_r_reg[0] ;
  wire sent_col;
  wire was_priority_reg;
  wire was_wr0;
  wire [3:0]wr_data_addr;
  wire [3:0]wr_data_addr_ns;
  wire wr_data_en;
  wire wr_data_en_ns;
  wire [1:1]\wtr_timer.wtr_cnt_r ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 ;
  wire [3:3]\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_bank_mach bank_mach0
       (.CLK(CLK),
        .D({mc_we_n_ns[2],bank_mach0_n_29,mc_we_n_ns[0]}),
        .DIC(col_periodic_rd),
        .E(mc_cmd_ns),
        .I118(mc_cs_n_ns),
        .I119(mc_odt_ns),
        .I120(mc_cke_ns),
        .Q(\bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r ),
        .S(S),
        .SR(SR),
        .accept_internal_r_reg(\grant_r_reg[0] ),
        .accept_ns(accept_ns),
        .act_this_rank(\rank_cntrl[0].rank_cntrl0/act_this_rank ),
        .app_en_r2(app_en_r2),
        .bank(bank),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_0(bm_end_r1_0),
        .bm_end_r1_1(bm_end_r1_1),
        .bm_end_r1_2(bm_end_r1_2),
        .cke_r(\arb_mux0/arb_select0/cke_r ),
        .clear_periodic_rd_request(clear_periodic_rd_request),
        .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5]_1 ),
        .\cmd_pipe_plus.mc_odt_reg[0] (\cmd_pipe_plus.mc_aux_out0_reg_n_0_[1] ),
        .col_rd_wr(col_rd_wr),
        .col_wr_data_buf_addr(col_wr_data_buf_addr),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (wr_data_addr_ns),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .\grant_r[2]_i_3 (\wtr_timer.wtr_cnt_r ),
        .\grant_r_reg[0] (bank_mach0_n_133),
        .\grant_r_reg[1] (bank_mach0_n_26),
        .\grant_r_reg[3] ({mc_address_ns[41:28],mc_address_ns[24:0]}),
        .\grant_r_reg[3]_0 (mc_bank_ns),
        .granted_col_r_reg(bank_mach0_n_27),
        .granted_col_r_reg_0(bank_mach0_n_38),
        .granted_col_r_reg_1(mc_data_offset_ns),
        .head_r_lcl_reg(head_r_lcl_reg),
        .head_r_lcl_reg_0(head_r_lcl_reg_0),
        .head_r_lcl_reg_1(head_r_lcl_reg_1),
        .head_r_lcl_reg_2(head_r_lcl_reg_2),
        .in0(in0),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .insert_maint_r1(insert_maint_r1),
        .\maint_controller.maint_hit_busies_r_reg[3] (rank_mach0_n_38),
        .maint_rank_r(maint_rank_r),
        .maint_req_r(maint_req_r),
        .maint_srx_r(maint_srx_r),
        .maint_wip_r(maint_wip_r),
        .maint_zq_r(maint_zq_r),
        .mc_cas_n_ns(mc_cas_n_ns),
        .mc_ras_n_ns({mc_ras_n_ns[2],mc_ras_n_ns[0]}),
        .pass_open_bank_r_lcl_reg(rank_mach0_n_43),
        .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r_lcl_reg),
        .periodic_rd_cntr_r_reg(periodic_rd_cntr_r_reg),
        .periodic_rd_cntr_r_reg_0(\periodic_read_request.periodic_rd_r_lcl_reg ),
        .\periodic_rd_generation.read_this_rank (\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank ),
        .\periodic_rd_generation.read_this_rank_r (\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r ),
        .\periodic_rd_generation.read_this_rank_r_reg (bank_mach0_n_41),
        .\periodic_read_request.periodic_rd_grant_r (\rank_common0/periodic_read_request.periodic_rd_grant_r ),
        .phy_mc_cmd_full(phy_mc_cmd_full),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .q_has_rd_r_reg(rank_mach0_n_42),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ({\arb_mux0/arb_select0/mc_data_offset1 [5:4],\arb_mux0/arb_select0/mc_data_offset1 [2:1]}),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_1),
        .ras_timer_zero_r_reg_2(ras_timer_zero_r_reg_2),
        .rb_hit_busy_r_reg(rb_hit_busy_r_reg),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0),
        .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_1),
        .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg_2),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ),
        .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_1 ),
        .\req_bank_r_lcl_reg[2]_2 (\req_bank_r_lcl_reg[2]_2 ),
        .\req_col_r_reg[9] (\req_col_r_reg[9] ),
        .\req_data_buf_addr_r_reg[3] (D),
        .\req_row_r_lcl_reg[13] (\req_row_r_lcl_reg[13] ),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (rank_mach0_n_41),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] (\inhbt_act_faw.faw_cnt_r_reg[2] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (bank_mach0_n_134),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ({\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [7],\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [0]}),
        .row(row),
        .row_hit_r_reg(row_hit_r_reg),
        .row_hit_r_reg_0(row_hit_r_reg_0),
        .row_hit_r_reg_1(row_hit_r_reg_1),
        .row_hit_r_reg_2(row_hit_r_reg_2),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1] (\last_master_r_reg[0] ),
        .sent_col(sent_col),
        .set_order_q(\bank_cntrl[0].bank0/bank_queue0/set_order_q ),
        .set_order_q_3(\bank_cntrl[1].bank0/bank_queue0/set_order_q ),
        .set_order_q_4(\bank_cntrl[2].bank0/bank_queue0/set_order_q ),
        .set_order_q_5(\bank_cntrl[3].bank0/bank_queue0/set_order_q ),
        .wait_for_maint_r(\bank_cntrl[0].bank0/wait_for_maint_r ),
        .wait_for_maint_r_0(\bank_cntrl[1].bank0/wait_for_maint_r ),
        .wait_for_maint_r_1(\bank_cntrl[2].bank0/wait_for_maint_r ),
        .wait_for_maint_r_2(\bank_cntrl[3].bank0/wait_for_maint_r ),
        .wait_for_maint_r_lcl_reg(rank_mach0_n_37),
        .wait_for_maint_r_lcl_reg_0(rank_mach0_n_13),
        .wait_for_maint_r_lcl_reg_1(rank_mach0_n_14),
        .wait_for_maint_r_lcl_reg_2(rank_mach0_n_15),
        .was_priority_reg(was_priority_reg),
        .was_wr0(was_wr0),
        .\wr_this_rank_r_reg[0] (bank_mach0_n_36),
        .\wr_this_rank_r_reg[0]_0 (bank_mach0_n_37));
  FDRE \cmd_pipe_plus.mc_address_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[0]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[10]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [10]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[11]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [11]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[12]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [12]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[13]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [13]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[14]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [14]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[15]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [15]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[16]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [16]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[17]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [17]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[18]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [18]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[19]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [19]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[1]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[20]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [20]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[21]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [21]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[22]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [22]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[23]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [23]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[24]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [24]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[28]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [25]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[29]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [26]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[2]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[30]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [27]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[31]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [28]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[32]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [29]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[33]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [30]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[34]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [31]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[35]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [32]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[36]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [33]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[37]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [34]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[38]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [35]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[39]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [36]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[3]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [3]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[40]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [37]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[41]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [38]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[4]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [4]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[5]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [5]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[6]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [6]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[7]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [7]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[8]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [8]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_address_ns[9]),
        .Q(\cmd_pipe_plus.mc_address_reg[41]_0 [9]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_aux_out0_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_mach0_n_27),
        .Q(\cmd_pipe_plus.mc_aux_out0_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[0]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[1]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[2]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[3]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [3]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[4]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [4]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[5]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [5]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[6]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [6]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[7]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [7]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_bank_ns[8]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [8]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cas_n_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_cas_n_ns[0]),
        .Q(mc_cas_n[0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cas_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_cas_n_ns[1]),
        .Q(mc_cas_n[1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cas_n_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_cas_n_ns[2]),
        .Q(mc_cas_n[2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cke_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_cke_ns),
        .Q(mc_cke),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cmd_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(sent_col),
        .Q(mc_cmd[0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cmd_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_cmd_ns),
        .Q(mc_cmd[1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cs_n_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_cs_n_ns),
        .Q(mc_cs_n),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_reg[0]_1 ),
        .Q(\cmd_pipe_plus.mc_data_offset_reg[0]_0 ),
        .R(bank_mach0_n_38));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset1 [1]),
        .Q(\cmd_pipe_plus.mc_data_offset_reg[1]_0 ),
        .R(bank_mach0_n_38));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset1 [2]),
        .Q(\cmd_pipe_plus.mc_data_offset_reg[2]_0 ),
        .R(bank_mach0_n_38));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_data_offset_ns),
        .Q(\cmd_pipe_plus.mc_data_offset_reg[3]_0 ),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset1 [4]),
        .Q(\cmd_pipe_plus.mc_data_offset_reg[4]_0 ),
        .R(bank_mach0_n_38));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset1 [5]),
        .Q(\cmd_pipe_plus.mc_data_offset_reg[5]_0 ),
        .R(bank_mach0_n_38));
  FDRE \cmd_pipe_plus.mc_odt_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_odt_ns),
        .Q(mc_odt),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_ras_n_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_ras_n_ns[0]),
        .Q(mc_ras_n[0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_ras_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_mach0_n_26),
        .Q(mc_ras_n[1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_ras_n_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_ras_n_ns[2]),
        .Q(mc_ras_n[2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_we_n_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_we_n_ns[0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_we_n_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(bank_mach0_n_29),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_we_n_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_we_n_ns[2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_wrdata_en_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(mc_wrdata_en_ns),
        .Q(mc_wrdata_en),
        .R(1'b0));
  (* syn_maxfan = "30" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_data_addr_ns[0]),
        .Q(wr_data_addr[0]),
        .R(1'b0));
  (* syn_maxfan = "30" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_data_addr_ns[1]),
        .Q(wr_data_addr[1]),
        .R(1'b0));
  (* syn_maxfan = "30" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_data_addr_ns[2]),
        .Q(wr_data_addr[2]),
        .R(1'b0));
  (* syn_maxfan = "30" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_data_addr_ns[3]),
        .Q(wr_data_addr[3]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.wr_data_en_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_data_en_ns),
        .Q(wr_data_en),
        .R(1'b0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_col_mach col_mach0
       (.CLK(CLK),
        .D(wr_data_addr_ns),
        .DIC(col_periodic_rd),
        .E(mc_cmd_ns),
        .col_rd_wr(col_rd_wr),
        .col_wr_data_buf_addr(col_wr_data_buf_addr),
        .in0(in0),
        .maint_ref_zq_wip(maint_ref_zq_wip),
        .mc_cmd(mc_cmd[0]),
        .mc_ref_zq_wip_ns(mc_ref_zq_wip_ns),
        .mc_wrdata_en_ns(mc_wrdata_en_ns),
        .\read_fifo.fifo_out_data_r_reg[7]_0 (\read_fifo.fifo_out_data_r_reg[7] ),
        .\read_fifo.fifo_out_data_r_reg[7]_1 (\inhbt_act_faw.faw_cnt_r_reg[2] ),
        .\read_fifo.fifo_out_data_r_reg[7]_2 (\read_fifo.fifo_out_data_r_reg[7]_0 ),
        .\read_fifo.tail_r_reg[0]_0 (\read_fifo.tail_r_reg[0] ),
        .\read_fifo.tail_r_reg[0]_1 (\read_fifo.tail_r_reg[0]_0 ),
        .\read_fifo.tail_r_reg[1]_0 (\read_fifo.tail_r_reg[1] ),
        .wr_data_en_ns(wr_data_en_ns));
  FDRE mc_ref_zq_wip_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(mc_ref_zq_wip_ns),
        .Q(mc_ref_zq_wip),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_12_17_i_2__2
       (.I0(mc_cs_n),
        .I1(\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),
        .O(phy_dout[0]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_1__2
       (.I0(mc_ras_n[2]),
        .I1(\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),
        .O(phy_dout[2]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_2__2
       (.I0(mc_ras_n[0]),
        .I1(\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),
        .O(phy_dout[1]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_4__2
       (.I0(mc_cas_n[0]),
        .I1(\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),
        .O(phy_dout[3]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_1__2
       (.I0(mc_cas_n[2]),
        .I1(\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),
        .O(phy_dout[4]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_3__2
       (.I0(Q[0]),
        .I1(\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),
        .O(phy_dout[5]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_4__2
       (.I0(Q[2]),
        .I1(\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),
        .O(phy_dout[6]));
  LUT2 #(
    .INIT(4'hE)) 
    \pointer_ram.rams[0].RAM32M0_i_1 
       (.I0(wr_data_en),
        .I1(E),
        .O(\pointer_ram.pointer_we ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_rank_mach rank_mach0
       (.CLK(CLK),
        .I120(mc_cke_ns),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 }),
        .Q(\wtr_timer.wtr_cnt_r ),
        .S({rank_mach0_n_17,rank_mach0_n_18,rank_mach0_n_19,rank_mach0_n_20}),
        .SR(SR),
        .act_this_rank(\rank_cntrl[0].rank_cntrl0/act_this_rank ),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .cke_r(\arb_mux0/arb_select0/cke_r ),
        .clear_periodic_rd_request(clear_periodic_rd_request),
        .\grant_r_reg[0] (\grant_r_reg[0] ),
        .in0(in0),
        .\inhbt_act_faw.faw_cnt_r_reg[2] (\inhbt_act_faw.faw_cnt_r_reg[2] ),
        .\inhbt_act_faw.faw_cnt_r_reg[2]_0 (bank_mach0_n_133),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .insert_maint_r1(insert_maint_r1),
        .\last_master_r_reg[0] (\last_master_r_reg[0] ),
        .\maint_controller.maint_hit_busies_r_reg[3] (periodic_rd_cntr_r_reg),
        .maint_rank_r(maint_rank_r),
        .maint_ref_zq_wip(maint_ref_zq_wip),
        .maint_req_r(maint_req_r),
        .maint_srx_r(maint_srx_r),
        .maint_wip_r(maint_wip_r),
        .maint_zq_r(maint_zq_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0] (rank_mach0_n_43),
        .\maintenance_request.maint_sre_r_lcl_reg (rank_mach0_n_38),
        .\maintenance_request.maint_sre_r_lcl_reg_0 (rank_mach0_n_42),
        .\maintenance_request.maint_srx_r_lcl_reg (rank_mach0_n_41),
        .\maintenance_request.maint_zq_r_lcl_reg ({\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [7],\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [0]}),
        .\periodic_rd_generation.periodic_rd_timer_r_reg[2] (bank_mach0_n_41),
        .\periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 (\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),
        .\periodic_rd_generation.read_this_rank (\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank ),
        .\periodic_rd_generation.read_this_rank_r (\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r ),
        .\periodic_read_request.periodic_rd_grant_r (\rank_common0/periodic_read_request.periodic_rd_grant_r ),
        .\periodic_read_request.periodic_rd_r_lcl_reg (\periodic_read_request.periodic_rd_r_lcl_reg ),
        .\periodic_read_request.periodic_rd_r_lcl_reg_0 (periodic_rd_ack_r_lcl_reg),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (\bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 (bank_mach0_n_134),
        .set_order_q(\bank_cntrl[1].bank0/bank_queue0/set_order_q ),
        .set_order_q_1(\bank_cntrl[2].bank0/bank_queue0/set_order_q ),
        .set_order_q_3(\bank_cntrl[3].bank0/bank_queue0/set_order_q ),
        .set_order_q_5(\bank_cntrl[0].bank0/bank_queue0/set_order_q ),
        .wait_for_maint_r(\bank_cntrl[1].bank0/wait_for_maint_r ),
        .wait_for_maint_r_0(\bank_cntrl[2].bank0/wait_for_maint_r ),
        .wait_for_maint_r_2(\bank_cntrl[3].bank0/wait_for_maint_r ),
        .wait_for_maint_r_4(\bank_cntrl[0].bank0/wait_for_maint_r ),
        .wait_for_maint_r_lcl_reg(rank_mach0_n_13),
        .wait_for_maint_r_lcl_reg_0(rank_mach0_n_14),
        .wait_for_maint_r_lcl_reg_1(rank_mach0_n_15),
        .wait_for_maint_r_lcl_reg_2(rank_mach0_n_37),
        .\wtr_timer.wtr_cnt_r_reg[0] (bank_mach0_n_36),
        .\wtr_timer.wtr_cnt_r_reg[0]_0 (bank_mach0_n_37),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[11] ({rank_mach0_n_25,rank_mach0_n_26,rank_mach0_n_27,rank_mach0_n_28}),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 }),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[15] ({rank_mach0_n_29,rank_mach0_n_30,rank_mach0_n_31,rank_mach0_n_32}),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 }),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[19] ({rank_mach0_n_33,rank_mach0_n_34,rank_mach0_n_35,rank_mach0_n_36}),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 }),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[7] ({rank_mach0_n_21,rank_mach0_n_22,rank_mach0_n_23,rank_mach0_n_24}),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 }));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3 
       (.CI(1'b0),
        .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 }),
        .S({rank_mach0_n_17,rank_mach0_n_18,rank_mach0_n_19,rank_mach0_n_20}));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1 
       (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ),
        .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 }),
        .S({rank_mach0_n_29,rank_mach0_n_30,rank_mach0_n_31,rank_mach0_n_32}));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1 
       (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ),
        .CO({\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED [3],\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 }),
        .S({rank_mach0_n_33,rank_mach0_n_34,rank_mach0_n_35,rank_mach0_n_36}));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1 
       (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ),
        .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 }),
        .S({rank_mach0_n_21,rank_mach0_n_22,rank_mach0_n_23,rank_mach0_n_24}));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1 
       (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ),
        .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 }),
        .S({rank_mach0_n_25,rank_mach0_n_26,rank_mach0_n_27,rank_mach0_n_28}));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_mem_intfc
   (periodic_rd_r,
    app_ref_ack,
    app_zq_ack,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    bm_end_r1,
    bm_end_r1_0,
    bm_end_r1_1,
    bm_end_r1_2,
    periodic_rd_ack_r,
    accept_ns,
    \rd_ptr_reg[0] ,
    \rd_ptr_reg[1] ,
    \rd_ptr_reg[2] ,
    \rd_ptr_reg[3] ,
    out,
    A_rst_primitives_reg,
    \rd_ptr_reg[0]_0 ,
    \rd_ptr_reg[1]_0 ,
    \rd_ptr_reg[2]_0 ,
    \rd_ptr_reg[3]_0 ,
    \rd_ptr_timing_reg[1] ,
    A_rst_primitives_reg_0,
    \rd_ptr_reg[0]_1 ,
    \rd_ptr_reg[1]_1 ,
    \rd_ptr_reg[2]_1 ,
    \rd_ptr_reg[3]_1 ,
    ref_dll_lock,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_reset_n,
    ddr3_dm,
    ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    app_sr_active,
    periodic_rd_cntr_r,
    po_cnt_dec_reg,
    po_cnt_dec_3,
    new_cnt_cpt_r_reg,
    rdlvl_stg1_start_reg,
    samp_edge_cnt0_en_r,
    pi_cnt_dec_reg,
    prbs_rdlvl_done_pulse_reg,
    init_calib_complete,
    init_calib_complete_reg_rep__0,
    init_calib_complete_reg_rep__1,
    init_calib_complete_reg_rep__2,
    head_r_lcl_reg,
    head_r_lcl_reg_0,
    head_r_lcl_reg_1,
    head_r_lcl_reg_2,
    phy_dout,
    init_calib_complete_reg_rep__0_0,
    \write_buffer.wr_buf_out_data_reg[122] ,
    \req_row_r_lcl_reg[13] ,
    req_bank_r,
    app_rd_data_valid,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    app_rd_data,
    \init_state_r_reg[2] ,
    \pointer_ram.pointer_we ,
    wr_data_en,
    app_rd_data_end,
    \wr_ptr_reg[3] ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_reg[3]_1 ,
    p_1_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    wr_data_addr,
    wr_en,
    wr_en_2,
    wr_en_3,
    ddr_ck_out,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    CLK,
    SR,
    req_wr_r_lcl0,
    rb_hit_busy_r_reg,
    rb_hit_busy_r_reg_0,
    rb_hit_busy_r_reg_1,
    rb_hit_busy_r_reg_2,
    in0,
    was_wr0,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    CLKB0,
    CLKB0_4,
    pll_locked,
    RST0,
    S,
    row_hit_r_reg,
    row_hit_r_reg_0,
    row_hit_r_reg_1,
    row_hit_r_reg_2,
    \smallest_reg[1][0] ,
    \rdlvl_dqs_tap_cnt_r_reg[0][1][4] ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[2] ,
    \samp_edge_cnt1_r_reg[0] ,
    init_calib_complete_reg,
    pi_f_dec_reg,
    \cnt_pwron_ce_r_reg[9] ,
    \last_master_r_reg[0] ,
    app_zq_req,
    app_sr_req,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ,
    was_priority_reg,
    app_en_r2,
    \inhbt_act_faw.faw_cnt_r_reg[2] ,
    mem_out,
    \idelay_tap_cnt_r_reg[0][1][4] ,
    \rtp_timer_r_reg[0] ,
    complex_row0_rd_done_reg,
    Q,
    app_ref_req,
    rd_wr_r_lcl_reg,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ,
    row,
    ras_timer_zero_r_reg,
    ras_timer_zero_r_reg_0,
    ras_timer_zero_r_reg_1,
    ras_timer_zero_r_reg_2,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    E,
    D,
    bank,
    \req_col_r_reg[9] ,
    \rd_ptr_reg[0]_2 ,
    \wr_ptr_timing_reg[2] ,
    \app_rd_data[112] ,
    SS,
    \wait_cnt_r_reg[0] ,
    \tap_cnt_cpt_r_reg[5] ,
    \cnt_shift_r_reg[0] ,
    \wait_cnt_r_reg[0]_0 ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[4] ,
    \device_temp_101_reg[11] ,
    out_fifo,
    out_fifo_0);
  output periodic_rd_r;
  output app_ref_ack;
  output app_zq_ack;
  output \generate_maint_cmds.insert_maint_r_lcl_reg ;
  output bm_end_r1;
  output bm_end_r1_0;
  output bm_end_r1_1;
  output bm_end_r1_2;
  output periodic_rd_ack_r;
  output accept_ns;
  output \rd_ptr_reg[0] ;
  output \rd_ptr_reg[1] ;
  output \rd_ptr_reg[2] ;
  output \rd_ptr_reg[3] ;
  output [1:0]out;
  output A_rst_primitives_reg;
  output \rd_ptr_reg[0]_0 ;
  output \rd_ptr_reg[1]_0 ;
  output \rd_ptr_reg[2]_0 ;
  output \rd_ptr_reg[3]_0 ;
  output [1:0]\rd_ptr_timing_reg[1] ;
  output A_rst_primitives_reg_0;
  output \rd_ptr_reg[0]_1 ;
  output \rd_ptr_reg[1]_1 ;
  output \rd_ptr_reg[2]_1 ;
  output \rd_ptr_reg[3]_1 ;
  output ref_dll_lock;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output ddr3_reset_n;
  output [1:0]ddr3_dm;
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output app_sr_active;
  output periodic_rd_cntr_r;
  output po_cnt_dec_reg;
  output po_cnt_dec_3;
  output new_cnt_cpt_r_reg;
  output rdlvl_stg1_start_reg;
  output samp_edge_cnt0_en_r;
  output pi_cnt_dec_reg;
  output prbs_rdlvl_done_pulse_reg;
  output init_calib_complete;
  output init_calib_complete_reg_rep__0;
  output init_calib_complete_reg_rep__1;
  output init_calib_complete_reg_rep__2;
  output head_r_lcl_reg;
  output head_r_lcl_reg_0;
  output head_r_lcl_reg_1;
  output head_r_lcl_reg_2;
  output [39:0]phy_dout;
  output [59:0]init_calib_complete_reg_rep__0_0;
  output [59:0]\write_buffer.wr_buf_out_data_reg[122] ;
  output [16:0]\req_row_r_lcl_reg[13] ;
  output [11:0]req_bank_r;
  output app_rd_data_valid;
  output [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output [127:0]app_rd_data;
  output \init_state_r_reg[2] ;
  output \pointer_ram.pointer_we ;
  output wr_data_en;
  output app_rd_data_end;
  output [3:0]\wr_ptr_reg[3] ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1] ;
  output [3:0]\wr_ptr_reg[3]_0 ;
  output [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_0 ;
  output [3:0]\wr_ptr_reg[3]_1 ;
  output p_1_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output [3:0]wr_data_addr;
  output wr_en;
  output wr_en_2;
  output wr_en_3;
  output [1:0]ddr_ck_out;
  inout [15:0]ddr3_dq;
  inout [1:0]ddr3_dqs_p;
  inout [1:0]ddr3_dqs_n;
  input CLK;
  input [0:0]SR;
  input req_wr_r_lcl0;
  input rb_hit_busy_r_reg;
  input rb_hit_busy_r_reg_0;
  input rb_hit_busy_r_reg_1;
  input rb_hit_busy_r_reg_2;
  input in0;
  input was_wr0;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input CLKB0;
  input CLKB0_4;
  input pll_locked;
  input RST0;
  input [2:0]S;
  input [0:0]row_hit_r_reg;
  input [0:0]row_hit_r_reg_0;
  input [0:0]row_hit_r_reg_1;
  input [0:0]row_hit_r_reg_2;
  input [1:0]\smallest_reg[1][0] ;
  input [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][1][4] ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  input \samp_edge_cnt1_r_reg[0] ;
  input init_calib_complete_reg;
  input pi_f_dec_reg;
  input [3:0]\cnt_pwron_ce_r_reg[9] ;
  input \last_master_r_reg[0] ;
  input app_zq_req;
  input app_sr_req;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  input was_priority_reg;
  input app_en_r2;
  input \inhbt_act_faw.faw_cnt_r_reg[2] ;
  input [47:0]mem_out;
  input \idelay_tap_cnt_r_reg[0][1][4] ;
  input \rtp_timer_r_reg[0] ;
  input complex_row0_rd_done_reg;
  input [143:0]Q;
  input app_ref_req;
  input rd_wr_r_lcl_reg;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  input [13:0]row;
  input ras_timer_zero_r_reg;
  input ras_timer_zero_r_reg_0;
  input ras_timer_zero_r_reg_1;
  input ras_timer_zero_r_reg_2;
  input [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input [0:0]E;
  input [3:0]D;
  input [2:0]bank;
  input [9:0]\req_col_r_reg[9] ;
  input \rd_ptr_reg[0]_2 ;
  input [0:0]\wr_ptr_timing_reg[2] ;
  input [63:0]\app_rd_data[112] ;
  input [0:0]SS;
  input [0:0]\wait_cnt_r_reg[0] ;
  input [0:0]\tap_cnt_cpt_r_reg[5] ;
  input [0:0]\cnt_shift_r_reg[0] ;
  input [0:0]\wait_cnt_r_reg[0]_0 ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  input [11:0]\device_temp_101_reg[11] ;
  input [71:0]out_fifo;
  input [71:0]out_fifo_0;

  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire CLK;
  wire CLKB0;
  wire CLKB0_4;
  wire [3:0]D;
  wire [0:0]E;
  wire [143:0]Q;
  wire RST0;
  wire [2:0]S;
  wire [0:0]SR;
  wire [0:0]SS;
  wire accept_ns;
  wire app_en_r2;
  wire [127:0]app_rd_data;
  wire [63:0]\app_rd_data[112] ;
  wire app_rd_data_end;
  wire app_rd_data_valid;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire app_zq_ack;
  wire app_zq_req;
  wire [2:0]bank;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire bm_end_r1_1;
  wire bm_end_r1_2;
  wire [3:0]\cnt_pwron_ce_r_reg[9] ;
  wire [0:0]\cnt_shift_r_reg[0] ;
  wire \col_mach0/p_0_in ;
  wire [0:0]\col_mach0/read_fifo.tail_r_reg ;
  wire complex_row0_rd_done_reg;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [1:0]ddr3_dm;
  wire [15:0]ddr3_dq;
  wire [1:0]ddr3_dqs_n;
  wire [1:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire ddr_phy_top0_n_214;
  wire ddr_phy_top0_n_215;
  wire ddr_phy_top0_n_216;
  wire ddr_phy_top0_n_217;
  wire ddr_phy_top0_n_218;
  wire ddr_phy_top0_n_219;
  wire ddr_phy_top0_n_220;
  wire ddr_phy_top0_n_221;
  wire ddr_phy_top0_n_222;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire ddr_phy_top0_n_54;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire ddr_phy_top0_n_58;
  wire ddr_phy_top0_n_59;
  wire [11:0]\device_temp_101_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire [67:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  wire freq_refclk;
  wire [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire \idelay_tap_cnt_r_reg[0][1][4] ;
  wire in0;
  wire \inhbt_act_faw.faw_cnt_r_reg[2] ;
  wire init_calib_complete;
  wire init_calib_complete_reg;
  wire init_calib_complete_reg_rep__0;
  wire [59:0]init_calib_complete_reg_rep__0_0;
  wire init_calib_complete_reg_rep__1;
  wire init_calib_complete_reg_rep__2;
  wire \init_state_r_reg[2] ;
  wire \last_master_r_reg[0] ;
  wire mc0_n_125;
  wire mc0_n_126;
  wire mc0_n_127;
  wire mc0_n_128;
  wire mc0_n_129;
  wire mc0_n_130;
  wire [41:0]mc_address;
  wire [8:0]mc_bank;
  wire [2:0]mc_cas_n;
  wire [3:3]mc_cke;
  wire [1:0]mc_cmd;
  wire [0:0]mc_cs_n;
  wire [0:0]mc_odt;
  wire [2:0]mc_ras_n;
  wire [2:0]mc_we_n;
  wire mc_wrdata_en;
  wire [47:0]mem_out;
  wire mem_refclk;
  wire new_cnt_cpt_r_reg;
  wire [1:0]out;
  wire [71:0]out_fifo;
  wire [71:0]out_fifo_0;
  wire p_1_in;
  wire periodic_rd_ack_r;
  wire periodic_rd_cntr_r;
  wire periodic_rd_r;
  wire [39:0]phy_dout;
  wire phy_mc_cmd_full;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire pi_cnt_dec_reg;
  wire pi_f_dec_reg;
  wire pll_locked;
  wire po_cnt_dec_3;
  wire po_cnt_dec_reg;
  wire \pointer_ram.pointer_we ;
  wire prbs_rdlvl_done_pulse_reg;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire ras_timer_zero_r_reg_2;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rb_hit_busy_r_reg_2;
  wire \rd_ptr_reg[0] ;
  wire \rd_ptr_reg[0]_0 ;
  wire \rd_ptr_reg[0]_1 ;
  wire \rd_ptr_reg[0]_2 ;
  wire \rd_ptr_reg[1] ;
  wire \rd_ptr_reg[1]_0 ;
  wire \rd_ptr_reg[1]_1 ;
  wire \rd_ptr_reg[2] ;
  wire \rd_ptr_reg[2]_0 ;
  wire \rd_ptr_reg[2]_1 ;
  wire \rd_ptr_reg[3] ;
  wire \rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg[3]_1 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire rd_wr_r_lcl_reg;
  wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][1][4] ;
  wire rdlvl_stg1_start_reg;
  wire ref_dll_lock;
  wire [11:0]req_bank_r;
  wire [9:0]\req_col_r_reg[9] ;
  wire [16:0]\req_row_r_lcl_reg[13] ;
  wire req_wr_r_lcl0;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  wire [13:0]row;
  wire [0:0]row_hit_r_reg;
  wire [0:0]row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire [0:0]row_hit_r_reg_2;
  wire \rtp_timer_r_reg[0] ;
  wire samp_edge_cnt0_en_r;
  wire \samp_edge_cnt1_r_reg[0] ;
  wire [1:0]\smallest_reg[1][0] ;
  wire sync_pulse;
  wire [0:0]\tap_cnt_cpt_r_reg[5] ;
  wire tempmon_sample_en;
  wire [0:0]\wait_cnt_r_reg[0] ;
  wire [0:0]\wait_cnt_r_reg[0]_0 ;
  wire was_priority_reg;
  wire was_wr0;
  wire [3:0]wr_data_addr;
  wire wr_data_en;
  wire wr_en;
  wire wr_en_2;
  wire wr_en_3;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire [3:0]\wr_ptr_reg[3] ;
  wire [3:0]\wr_ptr_reg[3]_0 ;
  wire [3:0]\wr_ptr_reg[3]_1 ;
  wire [0:0]\wr_ptr_timing_reg[2] ;
  wire [59:0]\write_buffer.wr_buf_out_data_reg[122] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ddr_phy_top ddr_phy_top0
       (.A_rst_primitives_reg(A_rst_primitives_reg),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .CLK(CLK),
        .CLKB0(CLKB0),
        .CLKB0_4(CLKB0_4),
        .Q(Q),
        .RST0(RST0),
        .SR(SR),
        .SS(SS),
        .app_rd_data(app_rd_data),
        .\app_rd_data[112] (\app_rd_data[112] ),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rd_data_valid_0(\col_mach0/p_0_in ),
        .\cnt_pwron_ce_r_reg[9] (\cnt_pwron_ce_r_reg[9] ),
        .\cnt_shift_r_reg[0] (\cnt_shift_r_reg[0] ),
        .complex_row0_rd_done_reg(complex_row0_rd_done_reg),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out(ddr_ck_out),
        .\device_temp_101_reg[11] (\device_temp_101_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .dqs_po_stg2_f_incdec_reg(\inhbt_act_faw.faw_cnt_r_reg[2] ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[2] (\en_cnt_div4.enable_wrlvl_cnt_reg[2] ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[4] (\en_cnt_div4.enable_wrlvl_cnt_reg[4] ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\idelay_tap_cnt_r_reg[0][1][4] (\idelay_tap_cnt_r_reg[0][1][4] ),
        .in0(in0),
        .init_calib_complete(init_calib_complete),
        .init_calib_complete_reg(init_calib_complete_reg),
        .init_calib_complete_reg_rep(ddr_phy_top0_n_54),
        .init_calib_complete_reg_rep__0(init_calib_complete_reg_rep__0),
        .init_calib_complete_reg_rep__0_0(init_calib_complete_reg_rep__0_0),
        .init_calib_complete_reg_rep__1(init_calib_complete_reg_rep__1),
        .init_calib_complete_reg_rep__2(init_calib_complete_reg_rep__2),
        .init_calib_complete_reg_rep__9(ddr_phy_top0_n_58),
        .init_complete_r1_timing_reg(ddr_phy_top0_n_59),
        .\init_state_r_reg[2] (\init_state_r_reg[2] ),
        .mc_address({mc_address[41:28],mc_address[24:0]}),
        .mc_bank(mc_bank),
        .mc_cas_n(mc_cas_n),
        .mc_cke(mc_cke),
        .mc_cmd(mc_cmd),
        .mc_cs_n(mc_cs_n),
        .mc_data_offset(mc0_n_125),
        .mc_odt(mc_odt),
        .mc_ras_n(mc_ras_n),
        .mc_ref_zq_wip(tempmon_sample_en),
        .mc_we_n(mc_we_n),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[0] (ddr_phy_top0_n_214),
        .\my_empty_reg[0]_0 (ddr_phy_top0_n_215),
        .\my_full_reg[5] (\rtp_timer_r_reg[0] ),
        .new_cnt_cpt_r_reg(new_cnt_cpt_r_reg),
        .out(out),
        .out_fifo(out_fifo),
        .out_fifo_0(out_fifo_0),
        .p_1_in(p_1_in),
        .\phy_ctl_wd_i1_reg[17] (mc0_n_130),
        .\phy_ctl_wd_i1_reg[18] (mc0_n_129),
        .\phy_ctl_wd_i1_reg[19] (mc0_n_128),
        .\phy_ctl_wd_i1_reg[21] (mc0_n_127),
        .\phy_ctl_wd_i1_reg[22] (mc0_n_126),
        .phy_dout({phy_dout[39:32],phy_dout[30],phy_dout[27],phy_dout[24],phy_dout[22:9],phy_dout[7:0]}),
        .phy_mc_cmd_full(phy_mc_cmd_full),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .pi_cnt_dec_reg(pi_cnt_dec_reg),
        .pi_f_dec_reg(pi_f_dec_reg),
        .pll_locked(pll_locked),
        .po_cnt_dec_3(po_cnt_dec_3),
        .po_cnt_dec_reg(po_cnt_dec_reg),
        .prbs_rdlvl_done_pulse_reg(prbs_rdlvl_done_pulse_reg),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] (ddr_phy_top0_n_216),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ({ddr_phy_top0_n_217,ddr_phy_top0_n_218,ddr_phy_top0_n_219,ddr_phy_top0_n_220,ddr_phy_top0_n_221,ddr_phy_top0_n_222}),
        .\rd_ptr_reg[0] (\rd_ptr_reg[0] ),
        .\rd_ptr_reg[0]_0 (\rd_ptr_reg[0]_0 ),
        .\rd_ptr_reg[0]_1 (\rd_ptr_reg[0]_1 ),
        .\rd_ptr_reg[0]_2 (\rd_ptr_reg[0]_2 ),
        .\rd_ptr_reg[1] (\rd_ptr_reg[1] ),
        .\rd_ptr_reg[1]_0 (\rd_ptr_reg[1]_0 ),
        .\rd_ptr_reg[1]_1 (\rd_ptr_reg[1]_1 ),
        .\rd_ptr_reg[2] (\rd_ptr_reg[2] ),
        .\rd_ptr_reg[2]_0 (\rd_ptr_reg[2]_0 ),
        .\rd_ptr_reg[2]_1 (\rd_ptr_reg[2]_1 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3] ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ),
        .\rd_ptr_reg[3]_1 (\rd_ptr_reg[3]_1 ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .\rdlvl_dqs_tap_cnt_r_reg[0][1][4] (\rdlvl_dqs_tap_cnt_r_reg[0][1][4] ),
        .rdlvl_stg1_start_reg(rdlvl_stg1_start_reg),
        .\read_fifo.tail_r_reg (\col_mach0/read_fifo.tail_r_reg ),
        .ref_dll_lock(ref_dll_lock),
        .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),
        .\samp_edge_cnt1_r_reg[0] (\samp_edge_cnt1_r_reg[0] ),
        .\smallest_reg[1][0] (\smallest_reg[1][0] ),
        .sync_pulse(sync_pulse),
        .\tap_cnt_cpt_r_reg[5] (\tap_cnt_cpt_r_reg[5] ),
        .\wait_cnt_r_reg[0] (\wait_cnt_r_reg[0] ),
        .\wait_cnt_r_reg[0]_0 (\wait_cnt_r_reg[0]_0 ),
        .wr_en(wr_en),
        .wr_en_2(wr_en_2),
        .wr_en_3(wr_en_3),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0]_0 ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_reg[3] (\wr_ptr_reg[3] ),
        .\wr_ptr_reg[3]_0 (\wr_ptr_reg[3]_0 ),
        .\wr_ptr_reg[3]_1 (\wr_ptr_reg[3]_1 ),
        .\wr_ptr_timing_reg[2] (\wr_ptr_timing_reg[2] ),
        .\write_buffer.wr_buf_out_data_reg[122] (\write_buffer.wr_buf_out_data_reg[122] ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_mc mc0
       (.CLK(CLK),
        .D(D),
        .E(E),
        .Q(mc_we_n),
        .S(S),
        .SR(SR),
        .accept_ns(accept_ns),
        .app_en_r2(app_en_r2),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .bank(bank),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_0(bm_end_r1_0),
        .bm_end_r1_1(bm_end_r1_1),
        .bm_end_r1_2(bm_end_r1_2),
        .\cmd_pipe_plus.mc_address_reg[41]_0 ({mc_address[41:28],mc_address[24:0]}),
        .\cmd_pipe_plus.mc_bank_reg[8]_0 (mc_bank),
        .\cmd_pipe_plus.mc_data_offset_reg[0]_0 (mc0_n_130),
        .\cmd_pipe_plus.mc_data_offset_reg[0]_1 (ddr_phy_top0_n_216),
        .\cmd_pipe_plus.mc_data_offset_reg[1]_0 (mc0_n_129),
        .\cmd_pipe_plus.mc_data_offset_reg[2]_0 (mc0_n_128),
        .\cmd_pipe_plus.mc_data_offset_reg[3]_0 (mc0_n_125),
        .\cmd_pipe_plus.mc_data_offset_reg[4]_0 (mc0_n_127),
        .\cmd_pipe_plus.mc_data_offset_reg[5]_0 (mc0_n_126),
        .\cmd_pipe_plus.mc_data_offset_reg[5]_1 ({ddr_phy_top0_n_217,ddr_phy_top0_n_218,ddr_phy_top0_n_219,ddr_phy_top0_n_220,ddr_phy_top0_n_221,ddr_phy_top0_n_222}),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .\grant_r_reg[0] (ddr_phy_top0_n_58),
        .head_r_lcl_reg(head_r_lcl_reg),
        .head_r_lcl_reg_0(head_r_lcl_reg_0),
        .head_r_lcl_reg_1(head_r_lcl_reg_1),
        .head_r_lcl_reg_2(head_r_lcl_reg_2),
        .in0(in0),
        .\inhbt_act_faw.faw_cnt_r_reg[2] (\inhbt_act_faw.faw_cnt_r_reg[2] ),
        .\last_master_r_reg[0] (\last_master_r_reg[0] ),
        .mc_cas_n(mc_cas_n),
        .mc_cke(mc_cke),
        .mc_cmd(mc_cmd),
        .mc_cs_n(mc_cs_n),
        .mc_odt(mc_odt),
        .mc_ras_n(mc_ras_n),
        .mc_ref_zq_wip(tempmon_sample_en),
        .mc_wrdata_en(mc_wrdata_en),
        .periodic_rd_ack_r_lcl_reg(periodic_rd_ack_r),
        .periodic_rd_cntr_r_reg(periodic_rd_cntr_r),
        .\periodic_rd_generation.periodic_rd_timer_r_reg[2] (ddr_phy_top0_n_54),
        .\periodic_read_request.periodic_rd_r_lcl_reg (periodic_rd_r),
        .phy_dout({phy_dout[31],phy_dout[29:28],phy_dout[26:25],phy_dout[23],phy_dout[8]}),
        .phy_mc_cmd_full(phy_mc_cmd_full),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .\pointer_ram.pointer_we (\pointer_ram.pointer_we ),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_1),
        .ras_timer_zero_r_reg_2(ras_timer_zero_r_reg_2),
        .rb_hit_busy_r_reg(rb_hit_busy_r_reg),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0),
        .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_1),
        .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg_2),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),
        .\read_fifo.fifo_out_data_r_reg[7] ({app_rd_data_end,\col_mach0/p_0_in }),
        .\read_fifo.fifo_out_data_r_reg[7]_0 (ddr_phy_top0_n_214),
        .\read_fifo.tail_r_reg[0] (\col_mach0/read_fifo.tail_r_reg ),
        .\read_fifo.tail_r_reg[0]_0 (ddr_phy_top0_n_215),
        .\read_fifo.tail_r_reg[1] (ddr_phy_top0_n_59),
        .\req_bank_r_lcl_reg[2] (req_bank_r[5:3]),
        .\req_bank_r_lcl_reg[2]_0 (req_bank_r[2:0]),
        .\req_bank_r_lcl_reg[2]_1 (req_bank_r[8:6]),
        .\req_bank_r_lcl_reg[2]_2 (req_bank_r[11:9]),
        .\req_col_r_reg[9] (\req_col_r_reg[9] ),
        .\req_row_r_lcl_reg[13] (\req_row_r_lcl_reg[13] ),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ),
        .row(row),
        .row_hit_r_reg(row_hit_r_reg),
        .row_hit_r_reg_0(row_hit_r_reg_0),
        .row_hit_r_reg_1(row_hit_r_reg_1),
        .row_hit_r_reg_2(row_hit_r_reg_2),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .was_priority_reg(was_priority_reg),
        .was_wr0(was_wr0),
        .wr_data_addr(wr_data_addr),
        .wr_data_en(wr_data_en));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_memc_ui_top_std
   (app_ref_ack,
    app_zq_ack,
    insert_maint_r,
    bm_end_r1,
    bm_end_r1_0,
    bm_end_r1_1,
    bm_end_r1_2,
    \rd_ptr_reg[0] ,
    \rd_ptr_reg[1] ,
    \rd_ptr_reg[2] ,
    \rd_ptr_reg[3] ,
    out,
    A_rst_primitives_reg,
    \rd_ptr_reg[0]_0 ,
    \rd_ptr_reg[1]_0 ,
    \rd_ptr_reg[2]_0 ,
    \rd_ptr_reg[3]_0 ,
    \rd_ptr_timing_reg[1] ,
    A_rst_primitives_reg_0,
    \rd_ptr_reg[0]_1 ,
    \rd_ptr_reg[1]_1 ,
    \rd_ptr_reg[2]_1 ,
    \rd_ptr_reg[3]_1 ,
    ref_dll_lock,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_reset_n,
    ddr3_dm,
    ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    app_sr_active,
    E,
    app_wdf_rdy,
    po_cnt_dec,
    po_cnt_dec_3,
    new_cnt_cpt_r_reg,
    rdlvl_stg1_start_reg,
    samp_edge_cnt0_en_r,
    pi_cnt_dec,
    prbs_rdlvl_done_pulse,
    init_calib_complete,
    phy_dout,
    init_calib_complete_reg_rep__0,
    \write_buffer.wr_buf_out_data_reg[122] ,
    app_rd_data_valid,
    Q,
    app_rd_data,
    \init_state_r_reg[2] ,
    app_rd_data_end,
    \wr_ptr_reg[3] ,
    \wr_ptr_reg[0] ,
    \wr_ptr_reg[1] ,
    \wr_ptr_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \wr_ptr_reg[0]_0 ,
    \wr_ptr_reg[1]_0 ,
    \wr_ptr_reg[3]_1 ,
    p_1_in,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    wr_en,
    wr_en_2,
    wr_en_3,
    ddr_ck_out,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    CLK,
    SR,
    in0,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    CLKB0,
    CLKB0_4,
    pll_locked,
    RST0,
    reset_reg_0,
    \smallest_reg[1][0] ,
    \rdlvl_dqs_tap_cnt_r_reg[0][1][4] ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[2] ,
    \samp_edge_cnt1_r_reg[0] ,
    init_calib_complete_reg,
    pi_f_dec_reg,
    \cnt_pwron_ce_r_reg[9] ,
    app_zq_req,
    app_sr_req,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ,
    \inhbt_act_faw.faw_cnt_r_reg[2] ,
    mem_out,
    \idelay_tap_cnt_r_reg[0][1][4] ,
    \rtp_timer_r_reg[0] ,
    complex_row0_rd_done_reg,
    app_ref_req,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ,
    ras_timer_zero_r_reg,
    ras_timer_zero_r_reg_0,
    ras_timer_zero_r_reg_1,
    ras_timer_zero_r_reg_2,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \rd_ptr_reg[0]_2 ,
    \wr_ptr_timing_reg[2] ,
    app_addr,
    app_cmd,
    app_wdf_data,
    app_wdf_mask,
    \app_rd_data[112] ,
    SS,
    \wait_cnt_r_reg[0] ,
    \tap_cnt_cpt_r_reg[5] ,
    \cnt_shift_r_reg[0] ,
    \wait_cnt_r_reg[0]_0 ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[4] ,
    D,
    out_fifo,
    out_fifo_0,
    app_en,
    app_wdf_wren,
    app_wdf_end);
  output app_ref_ack;
  output app_zq_ack;
  output insert_maint_r;
  output bm_end_r1;
  output bm_end_r1_0;
  output bm_end_r1_1;
  output bm_end_r1_2;
  output \rd_ptr_reg[0] ;
  output \rd_ptr_reg[1] ;
  output \rd_ptr_reg[2] ;
  output \rd_ptr_reg[3] ;
  output [1:0]out;
  output A_rst_primitives_reg;
  output \rd_ptr_reg[0]_0 ;
  output \rd_ptr_reg[1]_0 ;
  output \rd_ptr_reg[2]_0 ;
  output \rd_ptr_reg[3]_0 ;
  output [1:0]\rd_ptr_timing_reg[1] ;
  output A_rst_primitives_reg_0;
  output \rd_ptr_reg[0]_1 ;
  output \rd_ptr_reg[1]_1 ;
  output \rd_ptr_reg[2]_1 ;
  output \rd_ptr_reg[3]_1 ;
  output ref_dll_lock;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output ddr3_reset_n;
  output [1:0]ddr3_dm;
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output app_sr_active;
  output [0:0]E;
  output app_wdf_rdy;
  output po_cnt_dec;
  output po_cnt_dec_3;
  output new_cnt_cpt_r_reg;
  output rdlvl_stg1_start_reg;
  output samp_edge_cnt0_en_r;
  output pi_cnt_dec;
  output prbs_rdlvl_done_pulse;
  output init_calib_complete;
  output [39:0]phy_dout;
  output [71:0]init_calib_complete_reg_rep__0;
  output [71:0]\write_buffer.wr_buf_out_data_reg[122] ;
  output app_rd_data_valid;
  output [67:0]Q;
  output [127:0]app_rd_data;
  output \init_state_r_reg[2] ;
  output app_rd_data_end;
  output [3:0]\wr_ptr_reg[3] ;
  output \wr_ptr_reg[0] ;
  output \wr_ptr_reg[1] ;
  output [3:0]\wr_ptr_reg[3]_0 ;
  output [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \wr_ptr_reg[0]_0 ;
  output \wr_ptr_reg[1]_0 ;
  output [3:0]\wr_ptr_reg[3]_1 ;
  output p_1_in;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output wr_en;
  output wr_en_2;
  output wr_en_3;
  output [1:0]ddr_ck_out;
  inout [15:0]ddr3_dq;
  inout [1:0]ddr3_dqs_p;
  inout [1:0]ddr3_dqs_n;
  input CLK;
  input [0:0]SR;
  input in0;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input CLKB0;
  input CLKB0_4;
  input pll_locked;
  input RST0;
  input reset_reg_0;
  input [1:0]\smallest_reg[1][0] ;
  input [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][1][4] ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  input \samp_edge_cnt1_r_reg[0] ;
  input init_calib_complete_reg;
  input pi_f_dec_reg;
  input [3:0]\cnt_pwron_ce_r_reg[9] ;
  input app_zq_req;
  input app_sr_req;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  input \inhbt_act_faw.faw_cnt_r_reg[2] ;
  input [47:0]mem_out;
  input \idelay_tap_cnt_r_reg[0][1][4] ;
  input \rtp_timer_r_reg[0] ;
  input complex_row0_rd_done_reg;
  input app_ref_req;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  input ras_timer_zero_r_reg;
  input ras_timer_zero_r_reg_0;
  input ras_timer_zero_r_reg_1;
  input ras_timer_zero_r_reg_2;
  input [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \rd_ptr_reg[0]_2 ;
  input [0:0]\wr_ptr_timing_reg[2] ;
  input [26:0]app_addr;
  input [1:0]app_cmd;
  input [127:0]app_wdf_data;
  input [15:0]app_wdf_mask;
  input [63:0]\app_rd_data[112] ;
  input [0:0]SS;
  input [0:0]\wait_cnt_r_reg[0] ;
  input [0:0]\tap_cnt_cpt_r_reg[5] ;
  input [0:0]\cnt_shift_r_reg[0] ;
  input [0:0]\wait_cnt_r_reg[0]_0 ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  input [11:0]D;
  input [71:0]out_fifo;
  input [71:0]out_fifo_0;
  input app_en;
  input app_wdf_wren;
  input app_wdf_end;

  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire CLK;
  wire CLKB0;
  wire CLKB0_4;
  wire [11:0]D;
  wire [0:0]E;
  wire [67:0]Q;
  wire RST0;
  wire [0:0]SR;
  wire [0:0]SS;
  wire accept_ns;
  wire [26:0]app_addr;
  wire [1:0]app_cmd;
  wire app_en;
  wire [127:0]app_rd_data;
  wire [63:0]\app_rd_data[112] ;
  wire app_rd_data_end;
  wire app_rd_data_valid;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire [127:0]app_wdf_data;
  wire app_wdf_end;
  wire [15:0]app_wdf_mask;
  wire app_wdf_rdy;
  wire app_wdf_wren;
  wire app_zq_ack;
  wire app_zq_req;
  wire [2:0]bank;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire bm_end_r1_1;
  wire bm_end_r1_2;
  wire [3:0]\cnt_pwron_ce_r_reg[9] ;
  wire [0:0]\cnt_shift_r_reg[0] ;
  wire [9:0]col;
  wire complex_row0_rd_done_reg;
  wire [3:0]data_buf_addr;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [1:0]ddr3_dm;
  wire [15:0]ddr3_dq;
  wire [1:0]ddr3_dqs_n;
  wire [1:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire [73:0]\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  wire freq_refclk;
  wire [63:0]\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \idelay_tap_cnt_r_reg[0][1][4] ;
  wire in0;
  wire \inhbt_act_faw.faw_cnt_r_reg[2] ;
  wire init_calib_complete;
  wire init_calib_complete_reg;
  wire [71:0]init_calib_complete_reg_rep__0;
  wire \init_state_r_reg[2] ;
  wire insert_maint_r;
  wire \mc0/bank_mach0/bank_cntrl[0].bank0/bank_compare0/req_wr_r_lcl0 ;
  wire \mc0/bank_mach0/bank_common0/periodic_rd_cntr_r ;
  wire \mc0/bank_mach0/bank_common0/was_wr0 ;
  wire [11:0]\mc0/bank_mach0/req_bank_r ;
  wire [55:0]\mc0/bank_mach0/req_row_r ;
  wire \mc0/periodic_rd_ack_r ;
  wire \mc0/periodic_rd_r ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire mem_intfc0_n_65;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire mem_intfc0_n_66;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire mem_intfc0_n_67;
  wire mem_intfc0_n_68;
  wire mem_intfc0_n_69;
  wire mem_intfc0_n_70;
  wire mem_intfc0_n_71;
  wire [47:0]mem_out;
  wire mem_refclk;
  wire new_cnt_cpt_r_reg;
  wire [1:0]out;
  wire [71:0]out_fifo;
  wire [71:0]out_fifo_0;
  wire p_1_in;
  wire [39:0]phy_dout;
  wire pi_cnt_dec;
  wire pi_f_dec_reg;
  wire pll_locked;
  wire po_cnt_dec;
  wire po_cnt_dec_3;
  wire prbs_rdlvl_done_pulse;
  wire ram_init_done_r;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire ras_timer_zero_r_reg_2;
  wire \rd_ptr_reg[0] ;
  wire \rd_ptr_reg[0]_0 ;
  wire \rd_ptr_reg[0]_1 ;
  wire \rd_ptr_reg[0]_2 ;
  wire \rd_ptr_reg[1] ;
  wire \rd_ptr_reg[1]_0 ;
  wire \rd_ptr_reg[1]_1 ;
  wire \rd_ptr_reg[2] ;
  wire \rd_ptr_reg[2]_0 ;
  wire \rd_ptr_reg[2]_1 ;
  wire \rd_ptr_reg[3] ;
  wire \rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg[3]_1 ;
  wire [1:0]\rd_ptr_timing_reg[1] ;
  wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][1][4] ;
  wire rdlvl_stg1_start_reg;
  wire ref_dll_lock;
  wire reset_reg_0;
  wire reset_reg_n_0;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  wire [13:0]row;
  wire \rtp_timer_r_reg[0] ;
  wire samp_edge_cnt0_en_r;
  wire \samp_edge_cnt1_r_reg[0] ;
  wire [1:0]\smallest_reg[1][0] ;
  wire sync_pulse;
  wire [0:0]\tap_cnt_cpt_r_reg[5] ;
  wire u_ui_top_n_10;
  wire u_ui_top_n_11;
  wire u_ui_top_n_26;
  wire u_ui_top_n_27;
  wire u_ui_top_n_28;
  wire u_ui_top_n_29;
  wire u_ui_top_n_4;
  wire u_ui_top_n_5;
  wire u_ui_top_n_6;
  wire u_ui_top_n_7;
  wire u_ui_top_n_8;
  wire u_ui_top_n_9;
  wire \ui_cmd0/app_en_r2 ;
  wire \ui_wr_data0/pointer_ram.pointer_we ;
  wire [0:0]\wait_cnt_r_reg[0] ;
  wire [0:0]\wait_cnt_r_reg[0]_0 ;
  wire [127:0]wr_data;
  wire [3:0]wr_data_addr;
  wire wr_data_en;
  wire [15:0]wr_data_mask;
  wire wr_en;
  wire wr_en_2;
  wire wr_en_3;
  wire \wr_ptr_reg[0] ;
  wire \wr_ptr_reg[0]_0 ;
  wire \wr_ptr_reg[1] ;
  wire \wr_ptr_reg[1]_0 ;
  wire [3:0]\wr_ptr_reg[3] ;
  wire [3:0]\wr_ptr_reg[3]_0 ;
  wire [3:0]\wr_ptr_reg[3]_1 ;
  wire [0:0]\wr_ptr_timing_reg[2] ;
  wire [71:0]\write_buffer.wr_buf_out_data_reg[122] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_mem_intfc mem_intfc0
       (.A_rst_primitives_reg(A_rst_primitives_reg),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .CLK(CLK),
        .CLKB0(CLKB0),
        .CLKB0_4(CLKB0_4),
        .D(data_buf_addr),
        .E(ram_init_done_r),
        .Q({wr_data_mask,wr_data}),
        .RST0(RST0),
        .S({u_ui_top_n_9,u_ui_top_n_10,u_ui_top_n_11}),
        .SR(SR),
        .SS(SS),
        .accept_ns(accept_ns),
        .app_en_r2(\ui_cmd0/app_en_r2 ),
        .app_rd_data(app_rd_data),
        .\app_rd_data[112] (\app_rd_data[112] ),
        .app_rd_data_end(app_rd_data_end),
        .app_rd_data_valid(app_rd_data_valid),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .bank(bank),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_0(bm_end_r1_0),
        .bm_end_r1_1(bm_end_r1_1),
        .bm_end_r1_2(bm_end_r1_2),
        .\cnt_pwron_ce_r_reg[9] (\cnt_pwron_ce_r_reg[9] ),
        .\cnt_shift_r_reg[0] (\cnt_shift_r_reg[0] ),
        .complex_row0_rd_done_reg(complex_row0_rd_done_reg),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out(ddr_ck_out),
        .\device_temp_101_reg[11] (D),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (Q),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[2] (\en_cnt_div4.enable_wrlvl_cnt_reg[2] ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[4] (\en_cnt_div4.enable_wrlvl_cnt_reg[4] ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (insert_maint_r),
        .head_r_lcl_reg(mem_intfc0_n_68),
        .head_r_lcl_reg_0(mem_intfc0_n_69),
        .head_r_lcl_reg_1(mem_intfc0_n_70),
        .head_r_lcl_reg_2(mem_intfc0_n_71),
        .\idelay_tap_cnt_r_reg[0][1][4] (\idelay_tap_cnt_r_reg[0][1][4] ),
        .in0(in0),
        .\inhbt_act_faw.faw_cnt_r_reg[2] (\inhbt_act_faw.faw_cnt_r_reg[2] ),
        .init_calib_complete(init_calib_complete),
        .init_calib_complete_reg(init_calib_complete_reg),
        .init_calib_complete_reg_rep__0(mem_intfc0_n_65),
        .init_calib_complete_reg_rep__0_0({init_calib_complete_reg_rep__0[71:65],init_calib_complete_reg_rep__0[63:54],init_calib_complete_reg_rep__0[52:49],init_calib_complete_reg_rep__0[47:45],init_calib_complete_reg_rep__0[42:35],init_calib_complete_reg_rep__0[33:27],init_calib_complete_reg_rep__0[25:22],init_calib_complete_reg_rep__0[20:17],init_calib_complete_reg_rep__0[15:13],init_calib_complete_reg_rep__0[10:1]}),
        .init_calib_complete_reg_rep__1(mem_intfc0_n_66),
        .init_calib_complete_reg_rep__2(mem_intfc0_n_67),
        .\init_state_r_reg[2] (\init_state_r_reg[2] ),
        .\last_master_r_reg[0] (reset_reg_0),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .new_cnt_cpt_r_reg(new_cnt_cpt_r_reg),
        .out(out),
        .out_fifo(out_fifo),
        .out_fifo_0(out_fifo_0),
        .p_1_in(p_1_in),
        .periodic_rd_ack_r(\mc0/periodic_rd_ack_r ),
        .periodic_rd_cntr_r(\mc0/bank_mach0/bank_common0/periodic_rd_cntr_r ),
        .periodic_rd_r(\mc0/periodic_rd_r ),
        .phy_dout(phy_dout),
        .pi_cnt_dec_reg(pi_cnt_dec),
        .pi_f_dec_reg(pi_f_dec_reg),
        .pll_locked(pll_locked),
        .po_cnt_dec_3(po_cnt_dec_3),
        .po_cnt_dec_reg(po_cnt_dec),
        .\pointer_ram.pointer_we (\ui_wr_data0/pointer_ram.pointer_we ),
        .prbs_rdlvl_done_pulse_reg(prbs_rdlvl_done_pulse),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_1),
        .ras_timer_zero_r_reg_2(ras_timer_zero_r_reg_2),
        .rb_hit_busy_r_reg(u_ui_top_n_4),
        .rb_hit_busy_r_reg_0(u_ui_top_n_5),
        .rb_hit_busy_r_reg_1(u_ui_top_n_6),
        .rb_hit_busy_r_reg_2(u_ui_top_n_7),
        .\rd_ptr_reg[0] (\rd_ptr_reg[0] ),
        .\rd_ptr_reg[0]_0 (\rd_ptr_reg[0]_0 ),
        .\rd_ptr_reg[0]_1 (\rd_ptr_reg[0]_1 ),
        .\rd_ptr_reg[0]_2 (\rd_ptr_reg[0]_2 ),
        .\rd_ptr_reg[1] (\rd_ptr_reg[1] ),
        .\rd_ptr_reg[1]_0 (\rd_ptr_reg[1]_0 ),
        .\rd_ptr_reg[1]_1 (\rd_ptr_reg[1]_1 ),
        .\rd_ptr_reg[2] (\rd_ptr_reg[2] ),
        .\rd_ptr_reg[2]_0 (\rd_ptr_reg[2]_0 ),
        .\rd_ptr_reg[2]_1 (\rd_ptr_reg[2]_1 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3] ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ),
        .\rd_ptr_reg[3]_1 (\rd_ptr_reg[3]_1 ),
        .\rd_ptr_timing_reg[1] (\rd_ptr_timing_reg[1] ),
        .rd_wr_r_lcl_reg(u_ui_top_n_8),
        .\rdlvl_dqs_tap_cnt_r_reg[0][1][4] (\rdlvl_dqs_tap_cnt_r_reg[0][1][4] ),
        .rdlvl_stg1_start_reg(rdlvl_stg1_start_reg),
        .ref_dll_lock(ref_dll_lock),
        .req_bank_r(\mc0/bank_mach0/req_bank_r ),
        .\req_col_r_reg[9] (col),
        .\req_row_r_lcl_reg[13] ({\mc0/bank_mach0/req_row_r [55:54],\mc0/bank_mach0/req_row_r [41:40],\mc0/bank_mach0/req_row_r [27:26],\mc0/bank_mach0/req_row_r [13:12],\mc0/bank_mach0/req_row_r [8:0]}),
        .req_wr_r_lcl0(\mc0/bank_mach0/bank_cntrl[0].bank0/bank_compare0/req_wr_r_lcl0 ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ),
        .row(row),
        .row_hit_r_reg(u_ui_top_n_26),
        .row_hit_r_reg_0(u_ui_top_n_27),
        .row_hit_r_reg_1(u_ui_top_n_28),
        .row_hit_r_reg_2(u_ui_top_n_29),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),
        .\samp_edge_cnt1_r_reg[0] (\samp_edge_cnt1_r_reg[0] ),
        .\smallest_reg[1][0] (\smallest_reg[1][0] ),
        .sync_pulse(sync_pulse),
        .\tap_cnt_cpt_r_reg[5] (\tap_cnt_cpt_r_reg[5] ),
        .\wait_cnt_r_reg[0] (\wait_cnt_r_reg[0] ),
        .\wait_cnt_r_reg[0]_0 (\wait_cnt_r_reg[0]_0 ),
        .was_priority_reg(E),
        .was_wr0(\mc0/bank_mach0/bank_common0/was_wr0 ),
        .wr_data_addr(wr_data_addr),
        .wr_data_en(wr_data_en),
        .wr_en(wr_en),
        .wr_en_2(wr_en_2),
        .wr_en_3(wr_en_3),
        .\wr_ptr_reg[0] (\wr_ptr_reg[0] ),
        .\wr_ptr_reg[0]_0 (\wr_ptr_reg[0]_0 ),
        .\wr_ptr_reg[1] (\wr_ptr_reg[1] ),
        .\wr_ptr_reg[1]_0 (\wr_ptr_reg[1]_0 ),
        .\wr_ptr_reg[3] (\wr_ptr_reg[3] ),
        .\wr_ptr_reg[3]_0 (\wr_ptr_reg[3]_0 ),
        .\wr_ptr_reg[3]_1 (\wr_ptr_reg[3]_1 ),
        .\wr_ptr_timing_reg[2] (\wr_ptr_timing_reg[2] ),
        .\write_buffer.wr_buf_out_data_reg[122] ({\write_buffer.wr_buf_out_data_reg[122] [71:69],\write_buffer.wr_buf_out_data_reg[122] [66:51],\write_buffer.wr_buf_out_data_reg[122] [49:46],\write_buffer.wr_buf_out_data_reg[122] [44:41],\write_buffer.wr_buf_out_data_reg[122] [39:38],\write_buffer.wr_buf_out_data_reg[122] [36:33],\write_buffer.wr_buf_out_data_reg[122] [31:27],\write_buffer.wr_buf_out_data_reg[122] [25:21],\write_buffer.wr_buf_out_data_reg[122] [18:9],\write_buffer.wr_buf_out_data_reg[122] [7:1]}));
  (* syn_maxfan = "10" *) 
  FDRE reset_reg
       (.C(CLK),
        .CE(1'b1),
        .D(reset_reg_0),
        .Q(reset_reg_n_0),
        .R(1'b0));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ui_top u_ui_top
       (.CLK(CLK),
        .D(data_buf_addr),
        .E(wr_data_en),
        .Q({wr_data_mask,wr_data}),
        .S({u_ui_top_n_9,u_ui_top_n_10,u_ui_top_n_11}),
        .accept_ns(accept_ns),
        .app_addr(app_addr),
        .\app_addr_r1_reg[22] (u_ui_top_n_26),
        .\app_addr_r1_reg[9] (col),
        .\app_addr_r2_reg[24] (u_ui_top_n_4),
        .\app_addr_r2_reg[24]_0 (u_ui_top_n_7),
        .\app_addr_r2_reg[26] (u_ui_top_n_6),
        .app_cmd(app_cmd),
        .\app_cmd_r2_reg[0] (u_ui_top_n_8),
        .app_en(app_en),
        .app_en_r2(\ui_cmd0/app_en_r2 ),
        .app_rdy_r_reg(E),
        .app_wdf_data(app_wdf_data),
        .app_wdf_end(app_wdf_end),
        .app_wdf_mask(app_wdf_mask),
        .app_wdf_rdy(app_wdf_rdy),
        .app_wdf_wren(app_wdf_wren),
        .bank(bank),
        .\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 (mem_intfc0_n_66),
        .\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 (mem_intfc0_n_67),
        .\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 (mem_intfc0_n_65),
        .periodic_rd_ack_r(\mc0/periodic_rd_ack_r ),
        .periodic_rd_cntr_r(\mc0/bank_mach0/bank_common0/periodic_rd_cntr_r ),
        .periodic_rd_r(\mc0/periodic_rd_r ),
        .\pointer_ram.pointer_we (\ui_wr_data0/pointer_ram.pointer_we ),
        .rb_hit_busy_r_reg(mem_intfc0_n_68),
        .rb_hit_busy_r_reg_0(mem_intfc0_n_69),
        .rb_hit_busy_r_reg_1(mem_intfc0_n_70),
        .rb_hit_busy_r_reg_2(mem_intfc0_n_71),
        .\rd_buf_indx.ram_init_done_r_lcl_reg_inv (ram_init_done_r),
        .req_bank_r(\mc0/bank_mach0/req_bank_r ),
        .\req_bank_r_lcl_reg[0] (u_ui_top_n_5),
        .\req_row_r_lcl_reg[12] (u_ui_top_n_27),
        .\req_row_r_lcl_reg[12]_0 (u_ui_top_n_28),
        .\req_row_r_lcl_reg[12]_1 (u_ui_top_n_29),
        .req_wr_r_lcl0(\mc0/bank_mach0/bank_cntrl[0].bank0/bank_compare0/req_wr_r_lcl0 ),
        .row(row),
        .row_hit_r_reg({\mc0/bank_mach0/req_row_r [55:54],\mc0/bank_mach0/req_row_r [41:40],\mc0/bank_mach0/req_row_r [27:26],\mc0/bank_mach0/req_row_r [13:12],\mc0/bank_mach0/req_row_r [8:0]}),
        .was_wr0(\mc0/bank_mach0/bank_common0/was_wr0 ),
        .wr_data_addr(wr_data_addr),
        .\wr_req_counter.wr_req_cnt_r_reg[0] (reset_reg_n_0),
        .\write_buffer.wr_buf_out_data_reg[0] ({init_calib_complete_reg_rep__0[64],init_calib_complete_reg_rep__0[53],init_calib_complete_reg_rep__0[48],init_calib_complete_reg_rep__0[44:43],init_calib_complete_reg_rep__0[34],init_calib_complete_reg_rep__0[26],init_calib_complete_reg_rep__0[21],init_calib_complete_reg_rep__0[16],init_calib_complete_reg_rep__0[12:11],init_calib_complete_reg_rep__0[0]}),
        .\write_buffer.wr_buf_out_data_reg[74] ({\write_buffer.wr_buf_out_data_reg[122] [68:67],\write_buffer.wr_buf_out_data_reg[122] [50],\write_buffer.wr_buf_out_data_reg[122] [45],\write_buffer.wr_buf_out_data_reg[122] [40],\write_buffer.wr_buf_out_data_reg[122] [37],\write_buffer.wr_buf_out_data_reg[122] [32],\write_buffer.wr_buf_out_data_reg[122] [26],\write_buffer.wr_buf_out_data_reg[122] [20:19],\write_buffer.wr_buf_out_data_reg[122] [8],\write_buffer.wr_buf_out_data_reg[122] [0]}));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_rank_cntrl
   (\periodic_rd_generation.read_this_rank_r ,
    inhbt_act_faw_r,
    \periodic_rd_generation.periodic_rd_request_r ,
    \periodic_rd_generation.periodic_rd_cntr1_r ,
    \refresh_generation.refresh_bank_r ,
    Q,
    act_this_rank,
    CLK,
    \periodic_rd_generation.read_this_rank ,
    in0,
    SR,
    \periodic_rd_generation.periodic_rd_cntr1_r_reg_0 ,
    \refresh_generation.refresh_bank_r_reg[0]_0 ,
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ,
    clear_periodic_rd_request,
    \periodic_rd_generation.periodic_rd_request_r_reg_0 ,
    \wtr_timer.wtr_cnt_r_reg[0]_0 ,
    \wtr_timer.wtr_cnt_r_reg[0]_1 ,
    \wtr_timer.wtr_cnt_r_reg[0]_2 ,
    \inhbt_act_faw.faw_cnt_r_reg[2]_0 ,
    \inhbt_act_faw.faw_cnt_r_reg[2]_1 ,
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ,
    maint_prescaler_tick_r);
  output \periodic_rd_generation.read_this_rank_r ;
  output inhbt_act_faw_r;
  output \periodic_rd_generation.periodic_rd_request_r ;
  output \periodic_rd_generation.periodic_rd_cntr1_r ;
  output \refresh_generation.refresh_bank_r ;
  output [0:0]Q;
  input act_this_rank;
  input CLK;
  input \periodic_rd_generation.read_this_rank ;
  input in0;
  input [0:0]SR;
  input \periodic_rd_generation.periodic_rd_cntr1_r_reg_0 ;
  input \refresh_generation.refresh_bank_r_reg[0]_0 ;
  input \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ;
  input clear_periodic_rd_request;
  input \periodic_rd_generation.periodic_rd_request_r_reg_0 ;
  input \wtr_timer.wtr_cnt_r_reg[0]_0 ;
  input \wtr_timer.wtr_cnt_r_reg[0]_1 ;
  input \wtr_timer.wtr_cnt_r_reg[0]_2 ;
  input \inhbt_act_faw.faw_cnt_r_reg[2]_0 ;
  input \inhbt_act_faw.faw_cnt_r_reg[2]_1 ;
  input \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ;
  input maint_prescaler_tick_r;

  wire CLK;
  wire [0:0]Q;
  wire [0:0]SR;
  wire act_this_rank;
  wire clear_periodic_rd_request;
  wire in0;
  wire \inhbt_act_faw.act_delayed ;
  wire [2:0]\inhbt_act_faw.faw_cnt_r ;
  wire \inhbt_act_faw.faw_cnt_r[0]_i_1_n_0 ;
  wire \inhbt_act_faw.faw_cnt_r[1]_i_1_n_0 ;
  wire \inhbt_act_faw.faw_cnt_r[2]_i_1_n_0 ;
  wire \inhbt_act_faw.faw_cnt_r_reg[2]_0 ;
  wire \inhbt_act_faw.faw_cnt_r_reg[2]_1 ;
  wire \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ;
  wire inhbt_act_faw_r;
  wire maint_prescaler_tick_r;
  wire \periodic_rd_generation.periodic_rd_cntr1_r ;
  wire \periodic_rd_generation.periodic_rd_cntr1_r_reg_0 ;
  wire \periodic_rd_generation.periodic_rd_request_r ;
  wire \periodic_rd_generation.periodic_rd_request_r_i_1_n_0 ;
  wire \periodic_rd_generation.periodic_rd_request_r_i_2_n_0 ;
  wire \periodic_rd_generation.periodic_rd_request_r_reg_0 ;
  wire [2:0]\periodic_rd_generation.periodic_rd_timer_r ;
  wire \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ;
  wire \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ;
  wire \periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ;
  wire \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ;
  wire \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ;
  wire \periodic_rd_generation.read_this_rank ;
  wire \periodic_rd_generation.read_this_rank_r ;
  wire \refresh_generation.refresh_bank_r ;
  wire \refresh_generation.refresh_bank_r_reg[0]_0 ;
  wire [0:0]\wtr_timer.wtr_cnt_r ;
  wire \wtr_timer.wtr_cnt_r[0]_i_1_n_0 ;
  wire \wtr_timer.wtr_cnt_r[1]_i_1_n_0 ;
  wire \wtr_timer.wtr_cnt_r_reg[0]_0 ;
  wire \wtr_timer.wtr_cnt_r_reg[0]_1 ;
  wire \wtr_timer.wtr_cnt_r_reg[0]_2 ;
  wire \NLW_inhbt_act_faw.SRLC32E0_Q31_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* srl_bus_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl " *) 
  (* srl_name = "\u_mig_7series_0_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/inhbt_act_faw.SRLC32E0 " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \inhbt_act_faw.SRLC32E0 
       (.A({1'b0,1'b0,1'b0,1'b0,1'b1}),
        .CE(1'b1),
        .CLK(CLK),
        .D(act_this_rank),
        .Q(\inhbt_act_faw.act_delayed ),
        .Q31(\NLW_inhbt_act_faw.SRLC32E0_Q31_UNCONNECTED ));
  (* SOFT_HLUTNM = "soft_lutpair614" *) 
  LUT4 #(
    .INIT(16'h1441)) 
    \inhbt_act_faw.faw_cnt_r[0]_i_1 
       (.I0(\inhbt_act_faw.faw_cnt_r_reg[2]_0 ),
        .I1(\inhbt_act_faw.act_delayed ),
        .I2(\inhbt_act_faw.faw_cnt_r_reg[2]_1 ),
        .I3(\inhbt_act_faw.faw_cnt_r [0]),
        .O(\inhbt_act_faw.faw_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair614" *) 
  LUT5 #(
    .INIT(32'h44411444)) 
    \inhbt_act_faw.faw_cnt_r[1]_i_1 
       (.I0(\inhbt_act_faw.faw_cnt_r_reg[2]_0 ),
        .I1(\inhbt_act_faw.faw_cnt_r [1]),
        .I2(\inhbt_act_faw.faw_cnt_r_reg[2]_1 ),
        .I3(\inhbt_act_faw.act_delayed ),
        .I4(\inhbt_act_faw.faw_cnt_r [0]),
        .O(\inhbt_act_faw.faw_cnt_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5050501441505050)) 
    \inhbt_act_faw.faw_cnt_r[2]_i_1 
       (.I0(\inhbt_act_faw.faw_cnt_r_reg[2]_0 ),
        .I1(\inhbt_act_faw.faw_cnt_r [1]),
        .I2(\inhbt_act_faw.faw_cnt_r [2]),
        .I3(\inhbt_act_faw.act_delayed ),
        .I4(\inhbt_act_faw.faw_cnt_r_reg[2]_1 ),
        .I5(\inhbt_act_faw.faw_cnt_r [0]),
        .O(\inhbt_act_faw.faw_cnt_r[2]_i_1_n_0 ));
  FDRE \inhbt_act_faw.faw_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\inhbt_act_faw.faw_cnt_r[0]_i_1_n_0 ),
        .Q(\inhbt_act_faw.faw_cnt_r [0]),
        .R(1'b0));
  FDRE \inhbt_act_faw.faw_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\inhbt_act_faw.faw_cnt_r[1]_i_1_n_0 ),
        .Q(\inhbt_act_faw.faw_cnt_r [1]),
        .R(1'b0));
  FDRE \inhbt_act_faw.faw_cnt_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\inhbt_act_faw.faw_cnt_r[2]_i_1_n_0 ),
        .Q(\inhbt_act_faw.faw_cnt_r [2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0001000020000220)) 
    \inhbt_act_faw.inhbt_act_faw_r_i_1 
       (.I0(\inhbt_act_faw.faw_cnt_r [2]),
        .I1(\inhbt_act_faw.faw_cnt_r_reg[2]_0 ),
        .I2(\inhbt_act_faw.act_delayed ),
        .I3(\inhbt_act_faw.faw_cnt_r_reg[2]_1 ),
        .I4(\inhbt_act_faw.faw_cnt_r [0]),
        .I5(\inhbt_act_faw.faw_cnt_r [1]),
        .O(\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ));
  FDRE \inhbt_act_faw.inhbt_act_faw_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ),
        .Q(inhbt_act_faw_r),
        .R(1'b0));
  FDRE \periodic_rd_generation.periodic_rd_cntr1_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_cntr1_r_reg_0 ),
        .Q(\periodic_rd_generation.periodic_rd_cntr1_r ),
        .R(SR));
  LUT6 #(
    .INIT(64'h00545454FFFFFFFF)) 
    \periodic_rd_generation.periodic_rd_request_r_i_1 
       (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ),
        .I1(\periodic_rd_generation.periodic_rd_request_r_i_2_n_0 ),
        .I2(\periodic_rd_generation.periodic_rd_request_r ),
        .I3(clear_periodic_rd_request),
        .I4(\periodic_rd_generation.periodic_rd_cntr1_r ),
        .I5(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .O(\periodic_rd_generation.periodic_rd_request_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0040)) 
    \periodic_rd_generation.periodic_rd_request_r_i_2 
       (.I0(\periodic_rd_generation.periodic_rd_timer_r [1]),
        .I1(maint_prescaler_tick_r),
        .I2(\periodic_rd_generation.periodic_rd_timer_r [0]),
        .I3(\periodic_rd_generation.periodic_rd_timer_r [2]),
        .O(\periodic_rd_generation.periodic_rd_request_r_i_2_n_0 ));
  FDRE \periodic_rd_generation.periodic_rd_request_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_request_r_i_1_n_0 ),
        .Q(\periodic_rd_generation.periodic_rd_request_r ),
        .R(in0));
  LUT6 #(
    .INIT(64'hBBFFFFBBBFFFFBBB)) 
    \periodic_rd_generation.periodic_rd_timer_r[0]_i_1 
       (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ),
        .I1(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ),
        .I2(\periodic_rd_generation.periodic_rd_timer_r [1]),
        .I3(maint_prescaler_tick_r),
        .I4(\periodic_rd_generation.periodic_rd_timer_r [0]),
        .I5(\periodic_rd_generation.periodic_rd_timer_r [2]),
        .O(\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4040044040400040)) 
    \periodic_rd_generation.periodic_rd_timer_r[1]_i_1 
       (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ),
        .I1(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ),
        .I2(\periodic_rd_generation.periodic_rd_timer_r [1]),
        .I3(maint_prescaler_tick_r),
        .I4(\periodic_rd_generation.periodic_rd_timer_r [0]),
        .I5(\periodic_rd_generation.periodic_rd_timer_r [2]),
        .O(\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFBFFBFBBBBBB)) 
    \periodic_rd_generation.periodic_rd_timer_r[2]_i_1 
       (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ),
        .I1(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ),
        .I2(\periodic_rd_generation.periodic_rd_timer_r [1]),
        .I3(maint_prescaler_tick_r),
        .I4(\periodic_rd_generation.periodic_rd_timer_r [0]),
        .I5(\periodic_rd_generation.periodic_rd_timer_r [2]),
        .O(\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ));
  FDRE \periodic_rd_generation.periodic_rd_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ),
        .Q(\periodic_rd_generation.periodic_rd_timer_r [0]),
        .R(1'b0));
  FDRE \periodic_rd_generation.periodic_rd_timer_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ),
        .Q(\periodic_rd_generation.periodic_rd_timer_r [1]),
        .R(1'b0));
  FDRE \periodic_rd_generation.periodic_rd_timer_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ),
        .Q(\periodic_rd_generation.periodic_rd_timer_r [2]),
        .R(1'b0));
  FDRE \periodic_rd_generation.read_this_rank_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_rd_generation.read_this_rank ),
        .Q(\periodic_rd_generation.read_this_rank_r ),
        .R(1'b0));
  FDRE \refresh_generation.refresh_bank_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\refresh_generation.refresh_bank_r_reg[0]_0 ),
        .Q(\refresh_generation.refresh_bank_r ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair615" *) 
  LUT5 #(
    .INIT(32'h55550455)) 
    \wtr_timer.wtr_cnt_r[0]_i_1 
       (.I0(\wtr_timer.wtr_cnt_r_reg[0]_0 ),
        .I1(Q),
        .I2(\wtr_timer.wtr_cnt_r ),
        .I3(\wtr_timer.wtr_cnt_r_reg[0]_1 ),
        .I4(\wtr_timer.wtr_cnt_r_reg[0]_2 ),
        .O(\wtr_timer.wtr_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair615" *) 
  LUT5 #(
    .INIT(32'h55554055)) 
    \wtr_timer.wtr_cnt_r[1]_i_1 
       (.I0(\wtr_timer.wtr_cnt_r_reg[0]_0 ),
        .I1(Q),
        .I2(\wtr_timer.wtr_cnt_r ),
        .I3(\wtr_timer.wtr_cnt_r_reg[0]_1 ),
        .I4(\wtr_timer.wtr_cnt_r_reg[0]_2 ),
        .O(\wtr_timer.wtr_cnt_r[1]_i_1_n_0 ));
  FDRE \wtr_timer.wtr_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wtr_timer.wtr_cnt_r[0]_i_1_n_0 ),
        .Q(\wtr_timer.wtr_cnt_r ),
        .R(1'b0));
  FDRE \wtr_timer.wtr_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wtr_timer.wtr_cnt_r[1]_i_1_n_0 ),
        .Q(Q),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_rank_common
   (maint_prescaler_tick_r,
    maint_req_r,
    \periodic_read_request.periodic_rd_r_lcl_reg_0 ,
    app_ref_ack,
    app_zq_ack,
    \maintenance_request.maint_srx_r_lcl_reg_0 ,
    \maintenance_request.maint_zq_r_lcl_reg_0 ,
    \maintenance_request.maint_rank_r_lcl_reg[0]_0 ,
    \periodic_read_request.periodic_rd_grant_r ,
    app_sr_active,
    maint_ref_zq_wip,
    \periodic_read_request.periodic_rd_grant_r_reg[0]_0 ,
    wait_for_maint_r_lcl_reg,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    init_calib_complete_reg_rep__9,
    I120,
    S,
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ,
    wait_for_maint_r_lcl_reg_2,
    \maintenance_request.maint_sre_r_lcl_reg_0 ,
    \maintenance_request.maint_zq_r_lcl_reg_1 ,
    \maintenance_request.maint_srx_r_lcl_reg_1 ,
    \maintenance_request.maint_sre_r_lcl_reg_1 ,
    \maintenance_request.maint_rank_r_lcl_reg[0]_1 ,
    CLK,
    in0,
    SR,
    O,
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ,
    \grant_r_reg[0] ,
    \periodic_rd_generation.periodic_rd_request_r ,
    insert_maint_r1,
    \refresh_generation.refresh_bank_r ,
    maint_wip_r,
    \periodic_read_request.periodic_rd_r_lcl_reg_1 ,
    \periodic_rd_generation.periodic_rd_cntr1_r ,
    app_zq_req,
    app_sr_req,
    \last_master_r_reg[0] ,
    wait_for_maint_r,
    set_order_q,
    wait_for_maint_r_0,
    set_order_q_1,
    wait_for_maint_r_2,
    set_order_q_3,
    app_ref_req,
    cke_r,
    wait_for_maint_r_4,
    set_order_q_5,
    \maint_controller.maint_hit_busies_r_reg[3] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 );
  output maint_prescaler_tick_r;
  output maint_req_r;
  output \periodic_read_request.periodic_rd_r_lcl_reg_0 ;
  output app_ref_ack;
  output app_zq_ack;
  output \maintenance_request.maint_srx_r_lcl_reg_0 ;
  output \maintenance_request.maint_zq_r_lcl_reg_0 ;
  output \maintenance_request.maint_rank_r_lcl_reg[0]_0 ;
  output \periodic_read_request.periodic_rd_grant_r ;
  output app_sr_active;
  output maint_ref_zq_wip;
  output \periodic_read_request.periodic_rd_grant_r_reg[0]_0 ;
  output wait_for_maint_r_lcl_reg;
  output wait_for_maint_r_lcl_reg_0;
  output wait_for_maint_r_lcl_reg_1;
  output init_calib_complete_reg_rep__9;
  output [0:0]I120;
  output [3:0]S;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;
  output wait_for_maint_r_lcl_reg_2;
  output \maintenance_request.maint_sre_r_lcl_reg_0 ;
  output [1:0]\maintenance_request.maint_zq_r_lcl_reg_1 ;
  output \maintenance_request.maint_srx_r_lcl_reg_1 ;
  output \maintenance_request.maint_sre_r_lcl_reg_1 ;
  output \maintenance_request.maint_rank_r_lcl_reg[0]_1 ;
  input CLK;
  input in0;
  input [0:0]SR;
  input [3:0]O;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ;
  input \grant_r_reg[0] ;
  input \periodic_rd_generation.periodic_rd_request_r ;
  input insert_maint_r1;
  input \refresh_generation.refresh_bank_r ;
  input maint_wip_r;
  input \periodic_read_request.periodic_rd_r_lcl_reg_1 ;
  input \periodic_rd_generation.periodic_rd_cntr1_r ;
  input app_zq_req;
  input app_sr_req;
  input \last_master_r_reg[0] ;
  input wait_for_maint_r;
  input set_order_q;
  input wait_for_maint_r_0;
  input set_order_q_1;
  input wait_for_maint_r_2;
  input set_order_q_3;
  input app_ref_req;
  input cke_r;
  input wait_for_maint_r_4;
  input set_order_q_5;
  input \maint_controller.maint_hit_busies_r_reg[3] ;
  input [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ;

  wire CLK;
  wire [0:0]I120;
  wire [3:0]O;
  wire [3:0]S;
  wire [0:0]SR;
  wire app_ref_ack;
  wire app_ref_ack_ns;
  wire app_ref_ns;
  wire app_ref_r;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_active_r_i_1_n_0;
  wire app_sr_req;
  wire app_zq_ack;
  wire app_zq_ack_ns;
  wire app_zq_ns;
  wire app_zq_r;
  wire app_zq_req;
  wire cke_r;
  wire \grant_r_reg[0] ;
  wire in0;
  wire init_calib_complete_reg_rep__9;
  wire insert_maint_r1;
  wire \last_master_r_reg[0] ;
  wire \maint_controller.maint_hit_busies_r_reg[3] ;
  wire [4:0]\maint_prescaler.maint_prescaler_r0 ;
  wire \maint_prescaler.maint_prescaler_r[1]_i_1_n_0 ;
  wire \maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ;
  wire [4:0]\maint_prescaler.maint_prescaler_r_reg ;
  wire \maint_prescaler.maint_prescaler_tick_ns ;
  wire maint_prescaler_tick_r;
  wire maint_ref_zq_wip;
  wire maint_ref_zq_wip_r_i_1_n_0;
  wire maint_req_r;
  wire maint_sre_r;
  wire maint_wip_r;
  wire \maintenance_request.maint_arb0_n_0 ;
  wire \maintenance_request.maint_arb0_n_2 ;
  wire \maintenance_request.maint_arb0_n_3 ;
  wire \maintenance_request.maint_rank_r_lcl_reg[0]_0 ;
  wire \maintenance_request.maint_rank_r_lcl_reg[0]_1 ;
  wire \maintenance_request.maint_sre_ns ;
  wire \maintenance_request.maint_sre_r_lcl_reg_0 ;
  wire \maintenance_request.maint_sre_r_lcl_reg_1 ;
  wire \maintenance_request.maint_srx_r_lcl_reg_0 ;
  wire \maintenance_request.maint_srx_r_lcl_reg_1 ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire [1:0]\maintenance_request.maint_zq_r_lcl_reg_1 ;
  wire \maintenance_request.new_maint_rank_r ;
  wire \maintenance_request.upd_last_master_r ;
  wire \maintenance_request.upd_last_master_r_i_1_n_0 ;
  wire \periodic_rd_generation.periodic_rd_cntr1_r ;
  wire \periodic_rd_generation.periodic_rd_request_r ;
  wire \periodic_read_request.periodic_rd_grant_r ;
  wire \periodic_read_request.periodic_rd_grant_r[0]_i_1_n_0 ;
  wire \periodic_read_request.periodic_rd_grant_r_reg[0]_0 ;
  wire \periodic_read_request.periodic_rd_ns ;
  wire \periodic_read_request.periodic_rd_r_cnt ;
  wire \periodic_read_request.periodic_rd_r_cnt_i_1_n_0 ;
  wire \periodic_read_request.periodic_rd_r_lcl_reg_0 ;
  wire \periodic_read_request.periodic_rd_r_lcl_reg_1 ;
  wire \periodic_read_request.upd_last_master_ns ;
  wire \periodic_read_request.upd_last_master_r ;
  wire \refresh_generation.refresh_bank_r ;
  wire \refresh_generation.refresh_bank_r[0]_i_2_n_0 ;
  wire [5:0]\refresh_timer.refresh_timer_r0 ;
  wire \refresh_timer.refresh_timer_r0_0 ;
  wire \refresh_timer.refresh_timer_r[1]_i_1_n_0 ;
  wire \refresh_timer.refresh_timer_r[4]_i_1_n_0 ;
  wire \refresh_timer.refresh_timer_r[5]_i_1_n_0 ;
  wire \refresh_timer.refresh_timer_r[5]_i_4_n_0 ;
  wire \refresh_timer.refresh_timer_r[5]_i_5_n_0 ;
  wire \refresh_timer.refresh_timer_r[5]_i_6_n_0 ;
  wire [5:0]\refresh_timer.refresh_timer_r_reg ;
  wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ;
  wire sel;
  wire set_order_q;
  wire set_order_q_1;
  wire set_order_q_3;
  wire set_order_q_5;
  wire \sr_cntrl.ckesr_timer.ckesr_timer_r ;
  wire \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ;
  wire \sr_cntrl.sre_request_logic.sre_request_r ;
  wire \sr_cntrl.sre_request_logic.sre_request_r_i_1_n_0 ;
  wire wait_for_maint_r;
  wire wait_for_maint_r_0;
  wire wait_for_maint_r_2;
  wire wait_for_maint_r_4;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire wait_for_maint_r_lcl_reg_2;
  wire \zq_cntrl.zq_request_logic.zq_request_r ;
  wire \zq_cntrl.zq_request_logic.zq_request_r_i_1_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ;
  wire [19:0]\zq_cntrl.zq_timer.zq_timer_r_reg ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ;

  (* SOFT_HLUTNM = "soft_lutpair625" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    app_ref_ack_r_i_1
       (.I0(app_ref_r),
        .I1(\refresh_generation.refresh_bank_r ),
        .I2(\grant_r_reg[0] ),
        .O(app_ref_ack_ns));
  FDRE #(
    .INIT(1'b0)) 
    app_ref_ack_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_ref_ack_ns),
        .Q(app_ref_ack),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair625" *) 
  LUT4 #(
    .INIT(16'hAA08)) 
    app_ref_r_i_1
       (.I0(\grant_r_reg[0] ),
        .I1(app_ref_r),
        .I2(\refresh_generation.refresh_bank_r ),
        .I3(app_ref_req),
        .O(app_ref_ns));
  FDRE #(
    .INIT(1'b0)) 
    app_ref_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_ref_ns),
        .Q(app_ref_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair623" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    app_sr_active_r_i_1
       (.I0(maint_sre_r),
        .I1(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I2(insert_maint_r1),
        .I3(app_sr_active),
        .O(app_sr_active_r_i_1_n_0));
  FDRE app_sr_active_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_sr_active_r_i_1_n_0),
        .Q(app_sr_active),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair626" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    app_zq_ack_r_i_1
       (.I0(app_zq_r),
        .I1(\zq_cntrl.zq_request_logic.zq_request_r ),
        .I2(\grant_r_reg[0] ),
        .O(app_zq_ack_ns));
  FDRE #(
    .INIT(1'b0)) 
    app_zq_ack_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_zq_ack_ns),
        .Q(app_zq_ack),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair626" *) 
  LUT4 #(
    .INIT(16'hA888)) 
    app_zq_r_i_1
       (.I0(\grant_r_reg[0] ),
        .I1(app_zq_req),
        .I2(\zq_cntrl.zq_request_logic.zq_request_r ),
        .I3(app_zq_r),
        .O(app_zq_ns));
  FDRE #(
    .INIT(1'b0)) 
    app_zq_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_zq_ns),
        .Q(app_zq_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair623" *) 
  LUT4 #(
    .INIT(16'h0CEC)) 
    cke_r_i_1
       (.I0(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I1(cke_r),
        .I2(insert_maint_r1),
        .I3(maint_sre_r),
        .O(I120));
  LUT6 #(
    .INIT(64'hFFFFFFFF1010FF10)) 
    \maint_controller.maint_hit_busies_r[3]_i_2 
       (.I0(maint_sre_r),
        .I1(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I2(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I3(maint_req_r),
        .I4(\maint_controller.maint_hit_busies_r_reg[3] ),
        .I5(maint_wip_r),
        .O(\maintenance_request.maint_sre_r_lcl_reg_0 ));
  (* SOFT_HLUTNM = "soft_lutpair629" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \maint_prescaler.maint_prescaler_r[0]_i_1 
       (.I0(\maint_prescaler.maint_prescaler_r_reg [0]),
        .O(\maint_prescaler.maint_prescaler_r0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair629" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \maint_prescaler.maint_prescaler_r[1]_i_1 
       (.I0(\maint_prescaler.maint_prescaler_r_reg [0]),
        .I1(\maint_prescaler.maint_prescaler_r_reg [1]),
        .O(\maint_prescaler.maint_prescaler_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair624" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \maint_prescaler.maint_prescaler_r[2]_i_1 
       (.I0(\maint_prescaler.maint_prescaler_r_reg [2]),
        .I1(\maint_prescaler.maint_prescaler_r_reg [1]),
        .I2(\maint_prescaler.maint_prescaler_r_reg [0]),
        .O(\maint_prescaler.maint_prescaler_r0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair624" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \maint_prescaler.maint_prescaler_r[3]_i_1 
       (.I0(\maint_prescaler.maint_prescaler_r_reg [3]),
        .I1(\maint_prescaler.maint_prescaler_r_reg [0]),
        .I2(\maint_prescaler.maint_prescaler_r_reg [1]),
        .I3(\maint_prescaler.maint_prescaler_r_reg [2]),
        .O(\maint_prescaler.maint_prescaler_r0 [3]));
  LUT6 #(
    .INIT(64'h00000004FFFFFFFF)) 
    \maint_prescaler.maint_prescaler_r[4]_i_1 
       (.I0(\maint_prescaler.maint_prescaler_r_reg [3]),
        .I1(\maint_prescaler.maint_prescaler_r_reg [0]),
        .I2(\maint_prescaler.maint_prescaler_r_reg [4]),
        .I3(\maint_prescaler.maint_prescaler_r_reg [1]),
        .I4(\maint_prescaler.maint_prescaler_r_reg [2]),
        .I5(\grant_r_reg[0] ),
        .O(\maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \maint_prescaler.maint_prescaler_r[4]_i_2 
       (.I0(\maint_prescaler.maint_prescaler_r_reg [4]),
        .I1(\maint_prescaler.maint_prescaler_r_reg [3]),
        .I2(\maint_prescaler.maint_prescaler_r_reg [2]),
        .I3(\maint_prescaler.maint_prescaler_r_reg [1]),
        .I4(\maint_prescaler.maint_prescaler_r_reg [0]),
        .O(sel));
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \maint_prescaler.maint_prescaler_r[4]_i_3 
       (.I0(\maint_prescaler.maint_prescaler_r_reg [4]),
        .I1(\maint_prescaler.maint_prescaler_r_reg [3]),
        .I2(\maint_prescaler.maint_prescaler_r_reg [2]),
        .I3(\maint_prescaler.maint_prescaler_r_reg [1]),
        .I4(\maint_prescaler.maint_prescaler_r_reg [0]),
        .O(\maint_prescaler.maint_prescaler_r0 [4]));
  FDRE \maint_prescaler.maint_prescaler_r_reg[0] 
       (.C(CLK),
        .CE(sel),
        .D(\maint_prescaler.maint_prescaler_r0 [0]),
        .Q(\maint_prescaler.maint_prescaler_r_reg [0]),
        .R(\maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ));
  FDRE \maint_prescaler.maint_prescaler_r_reg[1] 
       (.C(CLK),
        .CE(sel),
        .D(\maint_prescaler.maint_prescaler_r[1]_i_1_n_0 ),
        .Q(\maint_prescaler.maint_prescaler_r_reg [1]),
        .R(\maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ));
  FDRE \maint_prescaler.maint_prescaler_r_reg[2] 
       (.C(CLK),
        .CE(sel),
        .D(\maint_prescaler.maint_prescaler_r0 [2]),
        .Q(\maint_prescaler.maint_prescaler_r_reg [2]),
        .R(\maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ));
  FDRE \maint_prescaler.maint_prescaler_r_reg[3] 
       (.C(CLK),
        .CE(sel),
        .D(\maint_prescaler.maint_prescaler_r0 [3]),
        .Q(\maint_prescaler.maint_prescaler_r_reg [3]),
        .R(\maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ));
  FDSE \maint_prescaler.maint_prescaler_r_reg[4] 
       (.C(CLK),
        .CE(sel),
        .D(\maint_prescaler.maint_prescaler_r0 [4]),
        .Q(\maint_prescaler.maint_prescaler_r_reg [4]),
        .S(\maint_prescaler.maint_prescaler_r[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000100)) 
    \maint_prescaler.maint_prescaler_tick_r_lcl_i_1 
       (.I0(\maint_prescaler.maint_prescaler_r_reg [2]),
        .I1(\maint_prescaler.maint_prescaler_r_reg [1]),
        .I2(\maint_prescaler.maint_prescaler_r_reg [4]),
        .I3(\maint_prescaler.maint_prescaler_r_reg [0]),
        .I4(\maint_prescaler.maint_prescaler_r_reg [3]),
        .O(\maint_prescaler.maint_prescaler_tick_ns ));
  FDRE \maint_prescaler.maint_prescaler_tick_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\maint_prescaler.maint_prescaler_tick_ns ),
        .Q(maint_prescaler_tick_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFD000D000D000)) 
    maint_ref_zq_wip_r_i_1
       (.I0(\refresh_generation.refresh_bank_r ),
        .I1(\zq_cntrl.zq_request_logic.zq_request_r ),
        .I2(\grant_r_reg[0] ),
        .I3(insert_maint_r1),
        .I4(maint_wip_r),
        .I5(maint_ref_zq_wip),
        .O(maint_ref_zq_wip_r_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    maint_ref_zq_wip_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(maint_ref_zq_wip_r_i_1_n_0),
        .Q(maint_ref_zq_wip),
        .R(SR));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_round_robin_arb \maintenance_request.maint_arb0 
       (.CLK(CLK),
        .app_sr_req(app_sr_req),
        .\grant_r_reg[0]_0 (\grant_r_reg[0] ),
        .\last_master_r_reg[0]_0 (\last_master_r_reg[0] ),
        .maint_sre_r(maint_sre_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0] (\maintenance_request.maint_arb0_n_0 ),
        .\maintenance_request.maint_rank_r_lcl_reg[0]_0 (\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .\maintenance_request.maint_sre_ns (\maintenance_request.maint_sre_ns ),
        .\maintenance_request.maint_srx_r_lcl_reg (\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_arb0_n_3 ),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .\maintenance_request.new_maint_rank_r (\maintenance_request.new_maint_rank_r ),
        .\maintenance_request.upd_last_master_r (\maintenance_request.upd_last_master_r ),
        .\refresh_generation.refresh_bank_r (\refresh_generation.refresh_bank_r ),
        .\sr_cntrl.ckesr_timer.ckesr_timer_r (\sr_cntrl.ckesr_timer.ckesr_timer_r ),
        .\sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0] (\maintenance_request.maint_arb0_n_2 ),
        .\sr_cntrl.sre_request_logic.sre_request_r (\sr_cntrl.sre_request_logic.sre_request_r ),
        .\zq_cntrl.zq_request_logic.zq_request_r (\zq_cntrl.zq_request_logic.zq_request_r ));
  FDRE \maintenance_request.maint_rank_r_lcl_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\maintenance_request.maint_arb0_n_0 ),
        .Q(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .R(1'b0));
  FDRE \maintenance_request.maint_req_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\maintenance_request.new_maint_rank_r ),
        .Q(maint_req_r),
        .R(1'b0));
  FDRE \maintenance_request.maint_sre_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\maintenance_request.maint_sre_ns ),
        .Q(maint_sre_r),
        .R(1'b0));
  FDRE \maintenance_request.maint_srx_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\maintenance_request.maint_arb0_n_2 ),
        .Q(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .R(in0));
  FDRE \maintenance_request.maint_zq_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\maintenance_request.maint_arb0_n_3 ),
        .Q(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .R(in0));
  FDRE \maintenance_request.new_maint_rank_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\maintenance_request.upd_last_master_r ),
        .Q(\maintenance_request.new_maint_rank_r ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h44444044)) 
    \maintenance_request.upd_last_master_r_i_1 
       (.I0(maint_wip_r),
        .I1(\grant_r_reg[0] ),
        .I2(\sr_cntrl.sre_request_logic.sre_request_r ),
        .I3(\refresh_generation.refresh_bank_r ),
        .I4(\zq_cntrl.zq_request_logic.zq_request_r ),
        .O(\maintenance_request.upd_last_master_r_i_1_n_0 ));
  FDRE \maintenance_request.upd_last_master_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\maintenance_request.upd_last_master_r_i_1_n_0 ),
        .Q(\maintenance_request.upd_last_master_r ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair619" *) 
  LUT3 #(
    .INIT(8'h02)) 
    pass_open_bank_r_lcl_i_4
       (.I0(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I1(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I2(maint_sre_r),
        .O(\maintenance_request.maint_rank_r_lcl_reg[0]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair627" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \periodic_rd_generation.periodic_rd_cntr1_r_i_1 
       (.I0(\periodic_read_request.periodic_rd_grant_r ),
        .I1(\periodic_read_request.periodic_rd_r_lcl_reg_1 ),
        .I2(\periodic_rd_generation.periodic_rd_cntr1_r ),
        .O(\periodic_read_request.periodic_rd_grant_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair621" *) 
  LUT5 #(
    .INIT(32'hFFFF0008)) 
    \periodic_read_request.periodic_rd_grant_r[0]_i_1 
       (.I0(\grant_r_reg[0] ),
        .I1(\periodic_rd_generation.periodic_rd_request_r ),
        .I2(\periodic_read_request.upd_last_master_r ),
        .I3(\periodic_read_request.periodic_rd_r_lcl_reg_0 ),
        .I4(\periodic_read_request.periodic_rd_grant_r ),
        .O(\periodic_read_request.periodic_rd_grant_r[0]_i_1_n_0 ));
  FDRE \periodic_read_request.periodic_rd_grant_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_read_request.periodic_rd_grant_r[0]_i_1_n_0 ),
        .Q(\periodic_read_request.periodic_rd_grant_r ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair627" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \periodic_read_request.periodic_rd_r_cnt_i_1 
       (.I0(\periodic_read_request.periodic_rd_r_lcl_reg_0 ),
        .I1(\periodic_read_request.periodic_rd_r_lcl_reg_1 ),
        .I2(\periodic_read_request.periodic_rd_r_cnt ),
        .O(\periodic_read_request.periodic_rd_r_cnt_i_1_n_0 ));
  FDRE \periodic_read_request.periodic_rd_r_cnt_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_read_request.periodic_rd_r_cnt_i_1_n_0 ),
        .Q(\periodic_read_request.periodic_rd_r_cnt ),
        .R(SR));
  LUT5 #(
    .INIT(32'hF0F07000)) 
    \periodic_read_request.periodic_rd_r_lcl_i_1 
       (.I0(\periodic_read_request.periodic_rd_r_cnt ),
        .I1(\periodic_read_request.periodic_rd_r_lcl_reg_1 ),
        .I2(\grant_r_reg[0] ),
        .I3(\periodic_read_request.periodic_rd_r_lcl_reg_0 ),
        .I4(\periodic_read_request.upd_last_master_r ),
        .O(\periodic_read_request.periodic_rd_ns ));
  FDRE \periodic_read_request.periodic_rd_r_lcl_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_read_request.periodic_rd_ns ),
        .Q(\periodic_read_request.periodic_rd_r_lcl_reg_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair621" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    \periodic_read_request.upd_last_master_r_i_1 
       (.I0(\grant_r_reg[0] ),
        .I1(\periodic_rd_generation.periodic_rd_request_r ),
        .I2(\periodic_read_request.upd_last_master_r ),
        .I3(\periodic_read_request.periodic_rd_r_lcl_reg_0 ),
        .O(\periodic_read_request.upd_last_master_ns ));
  FDRE \periodic_read_request.upd_last_master_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\periodic_read_request.upd_last_master_ns ),
        .Q(\periodic_read_request.upd_last_master_r ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h10FF)) 
    q_has_rd_r_i_2
       (.I0(maint_sre_r),
        .I1(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I2(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I3(maint_req_r),
        .O(\maintenance_request.maint_sre_r_lcl_reg_1 ));
  LUT5 #(
    .INIT(32'h88820008)) 
    \refresh_generation.refresh_bank_r[0]_i_1 
       (.I0(\grant_r_reg[0] ),
        .I1(\refresh_generation.refresh_bank_r ),
        .I2(app_ref_req),
        .I3(\refresh_timer.refresh_timer_r[5]_i_4_n_0 ),
        .I4(\refresh_generation.refresh_bank_r[0]_i_2_n_0 ),
        .O(init_calib_complete_reg_rep__9));
  (* SOFT_HLUTNM = "soft_lutpair620" *) 
  LUT5 #(
    .INIT(32'h00000004)) 
    \refresh_generation.refresh_bank_r[0]_i_2 
       (.I0(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I1(insert_maint_r1),
        .I2(maint_sre_r),
        .I3(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I4(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .O(\refresh_generation.refresh_bank_r[0]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \refresh_timer.refresh_timer_r[0]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg [0]),
        .O(\refresh_timer.refresh_timer_r0 [0]));
  LUT2 #(
    .INIT(4'h9)) 
    \refresh_timer.refresh_timer_r[1]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg [0]),
        .I1(\refresh_timer.refresh_timer_r_reg [1]),
        .O(\refresh_timer.refresh_timer_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair628" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \refresh_timer.refresh_timer_r[2]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg [2]),
        .I1(\refresh_timer.refresh_timer_r_reg [1]),
        .I2(\refresh_timer.refresh_timer_r_reg [0]),
        .O(\refresh_timer.refresh_timer_r0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair622" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \refresh_timer.refresh_timer_r[3]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg [3]),
        .I1(\refresh_timer.refresh_timer_r_reg [2]),
        .I2(\refresh_timer.refresh_timer_r_reg [0]),
        .I3(\refresh_timer.refresh_timer_r_reg [1]),
        .O(\refresh_timer.refresh_timer_r0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair622" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \refresh_timer.refresh_timer_r[4]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg [4]),
        .I1(\refresh_timer.refresh_timer_r_reg [0]),
        .I2(\refresh_timer.refresh_timer_r_reg [1]),
        .I3(\refresh_timer.refresh_timer_r_reg [3]),
        .I4(\refresh_timer.refresh_timer_r_reg [2]),
        .O(\refresh_timer.refresh_timer_r[4]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \refresh_timer.refresh_timer_r[5]_i_1 
       (.I0(\refresh_timer.refresh_timer_r[5]_i_4_n_0 ),
        .I1(\grant_r_reg[0] ),
        .O(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAA8AA)) 
    \refresh_timer.refresh_timer_r[5]_i_2 
       (.I0(maint_prescaler_tick_r),
        .I1(\refresh_timer.refresh_timer_r_reg [5]),
        .I2(\refresh_timer.refresh_timer_r_reg [4]),
        .I3(\refresh_timer.refresh_timer_r[5]_i_5_n_0 ),
        .I4(\refresh_timer.refresh_timer_r_reg [3]),
        .I5(\refresh_timer.refresh_timer_r_reg [2]),
        .O(\refresh_timer.refresh_timer_r0_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \refresh_timer.refresh_timer_r[5]_i_3 
       (.I0(\refresh_timer.refresh_timer_r_reg [5]),
        .I1(\refresh_timer.refresh_timer_r_reg [2]),
        .I2(\refresh_timer.refresh_timer_r_reg [3]),
        .I3(\refresh_timer.refresh_timer_r_reg [1]),
        .I4(\refresh_timer.refresh_timer_r_reg [0]),
        .I5(\refresh_timer.refresh_timer_r_reg [4]),
        .O(\refresh_timer.refresh_timer_r0 [5]));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    \refresh_timer.refresh_timer_r[5]_i_4 
       (.I0(\refresh_timer.refresh_timer_r_reg [4]),
        .I1(\refresh_timer.refresh_timer_r_reg [1]),
        .I2(\refresh_timer.refresh_timer_r[5]_i_6_n_0 ),
        .I3(maint_prescaler_tick_r),
        .I4(\refresh_timer.refresh_timer_r_reg [0]),
        .I5(\refresh_timer.refresh_timer_r_reg [5]),
        .O(\refresh_timer.refresh_timer_r[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair628" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \refresh_timer.refresh_timer_r[5]_i_5 
       (.I0(\refresh_timer.refresh_timer_r_reg [0]),
        .I1(\refresh_timer.refresh_timer_r_reg [1]),
        .O(\refresh_timer.refresh_timer_r[5]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \refresh_timer.refresh_timer_r[5]_i_6 
       (.I0(\refresh_timer.refresh_timer_r_reg [3]),
        .I1(\refresh_timer.refresh_timer_r_reg [2]),
        .O(\refresh_timer.refresh_timer_r[5]_i_6_n_0 ));
  FDSE \refresh_timer.refresh_timer_r_reg[0] 
       (.C(CLK),
        .CE(\refresh_timer.refresh_timer_r0_0 ),
        .D(\refresh_timer.refresh_timer_r0 [0]),
        .Q(\refresh_timer.refresh_timer_r_reg [0]),
        .S(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  FDRE \refresh_timer.refresh_timer_r_reg[1] 
       (.C(CLK),
        .CE(\refresh_timer.refresh_timer_r0_0 ),
        .D(\refresh_timer.refresh_timer_r[1]_i_1_n_0 ),
        .Q(\refresh_timer.refresh_timer_r_reg [1]),
        .R(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  FDSE \refresh_timer.refresh_timer_r_reg[2] 
       (.C(CLK),
        .CE(\refresh_timer.refresh_timer_r0_0 ),
        .D(\refresh_timer.refresh_timer_r0 [2]),
        .Q(\refresh_timer.refresh_timer_r_reg [2]),
        .S(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  FDRE \refresh_timer.refresh_timer_r_reg[3] 
       (.C(CLK),
        .CE(\refresh_timer.refresh_timer_r0_0 ),
        .D(\refresh_timer.refresh_timer_r0 [3]),
        .Q(\refresh_timer.refresh_timer_r_reg [3]),
        .R(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  FDRE \refresh_timer.refresh_timer_r_reg[4] 
       (.C(CLK),
        .CE(\refresh_timer.refresh_timer_r0_0 ),
        .D(\refresh_timer.refresh_timer_r[4]_i_1_n_0 ),
        .Q(\refresh_timer.refresh_timer_r_reg [4]),
        .R(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  FDSE \refresh_timer.refresh_timer_r_reg[5] 
       (.C(CLK),
        .CE(\refresh_timer.refresh_timer_r0_0 ),
        .D(\refresh_timer.refresh_timer_r0 [5]),
        .Q(\refresh_timer.refresh_timer_r_reg [5]),
        .S(\refresh_timer.refresh_timer_r[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000101000000FF)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1 
       (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I1(maint_sre_r),
        .I2(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ),
        .I5(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),
        .O(\maintenance_request.maint_zq_r_lcl_reg_1 [0]));
  LUT5 #(
    .INIT(32'h00000010)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2 
       (.I0(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ),
        .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),
        .I3(maint_sre_r),
        .I4(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .O(\maintenance_request.maint_srx_r_lcl_reg_1 ));
  LUT6 #(
    .INIT(64'h0000035500000055)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_2 
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ),
        .I1(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I2(maint_sre_r),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ),
        .I5(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .O(\maintenance_request.maint_zq_r_lcl_reg_1 [1]));
  (* SOFT_HLUTNM = "soft_lutpair620" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1 
       (.I0(maint_sre_r),
        .I1(insert_maint_r1),
        .O(\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ),
        .Q(\sr_cntrl.ckesr_timer.ckesr_timer_r ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00F8F0F8)) 
    \sr_cntrl.sre_request_logic.sre_request_r_i_1 
       (.I0(app_sr_req),
        .I1(\grant_r_reg[0] ),
        .I2(\sr_cntrl.sre_request_logic.sre_request_r ),
        .I3(maint_sre_r),
        .I4(insert_maint_r1),
        .O(\sr_cntrl.sre_request_logic.sre_request_r_i_1_n_0 ));
  FDRE \sr_cntrl.sre_request_logic.sre_request_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\sr_cntrl.sre_request_logic.sre_request_r_i_1_n_0 ),
        .Q(\sr_cntrl.sre_request_logic.sre_request_r ),
        .R(in0));
  (* SOFT_HLUTNM = "soft_lutpair619" *) 
  LUT5 #(
    .INIT(32'hFFFBAAAA)) 
    wait_for_maint_r_lcl_i_1
       (.I0(wait_for_maint_r),
        .I1(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I2(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I3(maint_sre_r),
        .I4(set_order_q),
        .O(wait_for_maint_r_lcl_reg));
  LUT5 #(
    .INIT(32'hFFFBAAAA)) 
    wait_for_maint_r_lcl_i_1__0
       (.I0(wait_for_maint_r_0),
        .I1(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I2(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I3(maint_sre_r),
        .I4(set_order_q_1),
        .O(wait_for_maint_r_lcl_reg_0));
  LUT5 #(
    .INIT(32'hFFFBAAAA)) 
    wait_for_maint_r_lcl_i_1__1
       (.I0(wait_for_maint_r_2),
        .I1(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I2(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I3(maint_sre_r),
        .I4(set_order_q_3),
        .O(wait_for_maint_r_lcl_reg_1));
  LUT5 #(
    .INIT(32'hFFFBAAAA)) 
    wait_for_maint_r_lcl_i_2
       (.I0(wait_for_maint_r_4),
        .I1(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I2(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I3(maint_sre_r),
        .I4(set_order_q_5),
        .O(wait_for_maint_r_lcl_reg_2));
  LUT5 #(
    .INIT(32'hFF2AFFFF)) 
    \zq_cntrl.zq_request_logic.zq_request_r_i_1 
       (.I0(\zq_cntrl.zq_request_logic.zq_request_r ),
        .I1(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I2(insert_maint_r1),
        .I3(app_zq_req),
        .I4(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ),
        .O(\zq_cntrl.zq_request_logic.zq_request_r_i_1_n_0 ));
  FDRE \zq_cntrl.zq_request_logic.zq_request_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\zq_cntrl.zq_request_logic.zq_request_r_i_1_n_0 ),
        .Q(\zq_cntrl.zq_request_logic.zq_request_r ),
        .R(in0));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_1 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ),
        .O(\zq_cntrl.zq_timer.zq_timer_r0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_10 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [12]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [4]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [15]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [10]),
        .I4(\zq_cntrl.zq_timer.zq_timer_r_reg [19]),
        .I5(\zq_cntrl.zq_timer.zq_timer_r_reg [3]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_11 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [9]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [8]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [13]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [2]),
        .I4(\zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_12 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [17]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [11]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [5]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [14]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ));
  LUT4 #(
    .INIT(16'hA8AA)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_2 
       (.I0(maint_prescaler_tick_r),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [1]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [0]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h8AAAAAAA)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_4 
       (.I0(\grant_r_reg[0] ),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [1]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [0]),
        .I3(maint_prescaler_tick_r),
        .I4(\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0 ),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [16]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [18]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [7]),
        .I4(\zq_cntrl.zq_timer.zq_timer_r_reg [6]),
        .I5(\zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_6 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [3]),
        .O(S[3]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_7 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [2]),
        .O(S[2]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_8 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [1]),
        .O(S[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_9 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [0]),
        .O(S[0]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[12]_i_2 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [15]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [3]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[12]_i_3 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [14]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [2]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[12]_i_4 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [13]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[12]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [12]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [0]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[16]_i_2 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [19]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [3]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[16]_i_3 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [18]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [2]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[16]_i_4 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [17]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[16]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [16]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [0]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[4]_i_2 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [7]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [3]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[4]_i_3 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [6]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [2]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[4]_i_4 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [5]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[4]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [4]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [0]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[8]_i_2 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [11]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [3]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[8]_i_3 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [10]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [2]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[8]_i_4 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [9]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[8]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [8]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [0]));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[0] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(O[0]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [0]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[10] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [2]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [10]),
        .S(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[11] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [3]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [11]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[12] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [0]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [12]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[13] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [1]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [13]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[14] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [2]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [14]),
        .S(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[15] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [3]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [15]),
        .S(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[16] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [0]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [16]),
        .S(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[17] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [1]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [17]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[18] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [2]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [18]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[19] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [3]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [19]),
        .S(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[1] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(O[1]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [1]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[2] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(O[2]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [2]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[3] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(O[3]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [3]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[4] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [0]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [4]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[5] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [1]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [5]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[6] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [2]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [6]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[7] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [3]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [7]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[8] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [0]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [8]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[9] 
       (.C(CLK),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [1]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [9]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_rank_mach
   (\periodic_rd_generation.read_this_rank_r ,
    inhbt_act_faw_r,
    maint_req_r,
    \periodic_read_request.periodic_rd_r_lcl_reg ,
    app_ref_ack,
    app_zq_ack,
    maint_srx_r,
    maint_zq_r,
    maint_rank_r,
    \periodic_read_request.periodic_rd_grant_r ,
    app_sr_active,
    maint_ref_zq_wip,
    Q,
    wait_for_maint_r_lcl_reg,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    I120,
    S,
    \zq_cntrl.zq_timer.zq_timer_r_reg[7] ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[11] ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[15] ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[19] ,
    wait_for_maint_r_lcl_reg_2,
    \maintenance_request.maint_sre_r_lcl_reg ,
    \maintenance_request.maint_zq_r_lcl_reg ,
    \maintenance_request.maint_srx_r_lcl_reg ,
    \maintenance_request.maint_sre_r_lcl_reg_0 ,
    \maintenance_request.maint_rank_r_lcl_reg[0] ,
    act_this_rank,
    CLK,
    \periodic_rd_generation.read_this_rank ,
    in0,
    SR,
    O,
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ,
    \grant_r_reg[0] ,
    insert_maint_r1,
    maint_wip_r,
    \periodic_read_request.periodic_rd_r_lcl_reg_0 ,
    \periodic_rd_generation.periodic_rd_timer_r_reg[2] ,
    clear_periodic_rd_request,
    app_zq_req,
    app_sr_req,
    \last_master_r_reg[0] ,
    \wtr_timer.wtr_cnt_r_reg[0] ,
    \wtr_timer.wtr_cnt_r_reg[0]_0 ,
    wait_for_maint_r,
    set_order_q,
    wait_for_maint_r_0,
    set_order_q_1,
    wait_for_maint_r_2,
    set_order_q_3,
    \inhbt_act_faw.faw_cnt_r_reg[2] ,
    \inhbt_act_faw.faw_cnt_r_reg[2]_0 ,
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ,
    app_ref_req,
    cke_r,
    wait_for_maint_r_4,
    set_order_q_5,
    \maint_controller.maint_hit_busies_r_reg[3] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 );
  output \periodic_rd_generation.read_this_rank_r ;
  output inhbt_act_faw_r;
  output maint_req_r;
  output \periodic_read_request.periodic_rd_r_lcl_reg ;
  output app_ref_ack;
  output app_zq_ack;
  output maint_srx_r;
  output maint_zq_r;
  output maint_rank_r;
  output \periodic_read_request.periodic_rd_grant_r ;
  output app_sr_active;
  output maint_ref_zq_wip;
  output [0:0]Q;
  output wait_for_maint_r_lcl_reg;
  output wait_for_maint_r_lcl_reg_0;
  output wait_for_maint_r_lcl_reg_1;
  output [0:0]I120;
  output [3:0]S;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7] ;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11] ;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15] ;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19] ;
  output wait_for_maint_r_lcl_reg_2;
  output \maintenance_request.maint_sre_r_lcl_reg ;
  output [1:0]\maintenance_request.maint_zq_r_lcl_reg ;
  output \maintenance_request.maint_srx_r_lcl_reg ;
  output \maintenance_request.maint_sre_r_lcl_reg_0 ;
  output \maintenance_request.maint_rank_r_lcl_reg[0] ;
  input act_this_rank;
  input CLK;
  input \periodic_rd_generation.read_this_rank ;
  input in0;
  input [0:0]SR;
  input [3:0]O;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;
  input \grant_r_reg[0] ;
  input insert_maint_r1;
  input maint_wip_r;
  input \periodic_read_request.periodic_rd_r_lcl_reg_0 ;
  input \periodic_rd_generation.periodic_rd_timer_r_reg[2] ;
  input clear_periodic_rd_request;
  input app_zq_req;
  input app_sr_req;
  input \last_master_r_reg[0] ;
  input \wtr_timer.wtr_cnt_r_reg[0] ;
  input \wtr_timer.wtr_cnt_r_reg[0]_0 ;
  input wait_for_maint_r;
  input set_order_q;
  input wait_for_maint_r_0;
  input set_order_q_1;
  input wait_for_maint_r_2;
  input set_order_q_3;
  input \inhbt_act_faw.faw_cnt_r_reg[2] ;
  input \inhbt_act_faw.faw_cnt_r_reg[2]_0 ;
  input \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ;
  input app_ref_req;
  input cke_r;
  input wait_for_maint_r_4;
  input set_order_q_5;
  input \maint_controller.maint_hit_busies_r_reg[3] ;
  input [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ;

  wire CLK;
  wire [0:0]I120;
  wire [3:0]O;
  wire [0:0]Q;
  wire [3:0]S;
  wire [0:0]SR;
  wire act_this_rank;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire app_zq_ack;
  wire app_zq_req;
  wire cke_r;
  wire clear_periodic_rd_request;
  wire \grant_r_reg[0] ;
  wire in0;
  wire \inhbt_act_faw.faw_cnt_r_reg[2] ;
  wire \inhbt_act_faw.faw_cnt_r_reg[2]_0 ;
  wire inhbt_act_faw_r;
  wire insert_maint_r1;
  wire \last_master_r_reg[0] ;
  wire \maint_controller.maint_hit_busies_r_reg[3] ;
  wire maint_prescaler_tick_r;
  wire maint_rank_r;
  wire maint_ref_zq_wip;
  wire maint_req_r;
  wire maint_srx_r;
  wire maint_wip_r;
  wire maint_zq_r;
  wire \maintenance_request.maint_rank_r_lcl_reg[0] ;
  wire \maintenance_request.maint_sre_r_lcl_reg ;
  wire \maintenance_request.maint_sre_r_lcl_reg_0 ;
  wire \maintenance_request.maint_srx_r_lcl_reg ;
  wire [1:0]\maintenance_request.maint_zq_r_lcl_reg ;
  wire \periodic_rd_generation.periodic_rd_cntr1_r ;
  wire \periodic_rd_generation.periodic_rd_request_r ;
  wire \periodic_rd_generation.periodic_rd_timer_r_reg[2] ;
  wire \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ;
  wire \periodic_rd_generation.read_this_rank ;
  wire \periodic_rd_generation.read_this_rank_r ;
  wire \periodic_read_request.periodic_rd_grant_r ;
  wire \periodic_read_request.periodic_rd_r_lcl_reg ;
  wire \periodic_read_request.periodic_rd_r_lcl_reg_0 ;
  wire rank_common0_n_11;
  wire rank_common0_n_15;
  wire \refresh_generation.refresh_bank_r ;
  wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ;
  wire set_order_q;
  wire set_order_q_1;
  wire set_order_q_3;
  wire set_order_q_5;
  wire wait_for_maint_r;
  wire wait_for_maint_r_0;
  wire wait_for_maint_r_2;
  wire wait_for_maint_r_4;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire wait_for_maint_r_lcl_reg_2;
  wire \wtr_timer.wtr_cnt_r_reg[0] ;
  wire \wtr_timer.wtr_cnt_r_reg[0]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11] ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15] ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19] ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7] ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_rank_cntrl \rank_cntrl[0].rank_cntrl0 
       (.CLK(CLK),
        .Q(Q),
        .SR(SR),
        .act_this_rank(act_this_rank),
        .clear_periodic_rd_request(clear_periodic_rd_request),
        .in0(in0),
        .\inhbt_act_faw.faw_cnt_r_reg[2]_0 (\inhbt_act_faw.faw_cnt_r_reg[2] ),
        .\inhbt_act_faw.faw_cnt_r_reg[2]_1 (\inhbt_act_faw.faw_cnt_r_reg[2]_0 ),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .maint_prescaler_tick_r(maint_prescaler_tick_r),
        .\periodic_rd_generation.periodic_rd_cntr1_r (\periodic_rd_generation.periodic_rd_cntr1_r ),
        .\periodic_rd_generation.periodic_rd_cntr1_r_reg_0 (rank_common0_n_11),
        .\periodic_rd_generation.periodic_rd_request_r (\periodic_rd_generation.periodic_rd_request_r ),
        .\periodic_rd_generation.periodic_rd_request_r_reg_0 (\grant_r_reg[0] ),
        .\periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 (\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),
        .\periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 (\periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ),
        .\periodic_rd_generation.read_this_rank (\periodic_rd_generation.read_this_rank ),
        .\periodic_rd_generation.read_this_rank_r (\periodic_rd_generation.read_this_rank_r ),
        .\refresh_generation.refresh_bank_r (\refresh_generation.refresh_bank_r ),
        .\refresh_generation.refresh_bank_r_reg[0]_0 (rank_common0_n_15),
        .\wtr_timer.wtr_cnt_r_reg[0]_0 (\last_master_r_reg[0] ),
        .\wtr_timer.wtr_cnt_r_reg[0]_1 (\wtr_timer.wtr_cnt_r_reg[0] ),
        .\wtr_timer.wtr_cnt_r_reg[0]_2 (\wtr_timer.wtr_cnt_r_reg[0]_0 ));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_rank_common rank_common0
       (.CLK(CLK),
        .I120(I120),
        .O(O),
        .S(S),
        .SR(SR),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .cke_r(cke_r),
        .\grant_r_reg[0] (\grant_r_reg[0] ),
        .in0(in0),
        .init_calib_complete_reg_rep__9(rank_common0_n_15),
        .insert_maint_r1(insert_maint_r1),
        .\last_master_r_reg[0] (\last_master_r_reg[0] ),
        .\maint_controller.maint_hit_busies_r_reg[3] (\maint_controller.maint_hit_busies_r_reg[3] ),
        .maint_prescaler_tick_r(maint_prescaler_tick_r),
        .maint_ref_zq_wip(maint_ref_zq_wip),
        .maint_req_r(maint_req_r),
        .maint_wip_r(maint_wip_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0]_0 (maint_rank_r),
        .\maintenance_request.maint_rank_r_lcl_reg[0]_1 (\maintenance_request.maint_rank_r_lcl_reg[0] ),
        .\maintenance_request.maint_sre_r_lcl_reg_0 (\maintenance_request.maint_sre_r_lcl_reg ),
        .\maintenance_request.maint_sre_r_lcl_reg_1 (\maintenance_request.maint_sre_r_lcl_reg_0 ),
        .\maintenance_request.maint_srx_r_lcl_reg_0 (maint_srx_r),
        .\maintenance_request.maint_srx_r_lcl_reg_1 (\maintenance_request.maint_srx_r_lcl_reg ),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (maint_zq_r),
        .\maintenance_request.maint_zq_r_lcl_reg_1 (\maintenance_request.maint_zq_r_lcl_reg ),
        .\periodic_rd_generation.periodic_rd_cntr1_r (\periodic_rd_generation.periodic_rd_cntr1_r ),
        .\periodic_rd_generation.periodic_rd_request_r (\periodic_rd_generation.periodic_rd_request_r ),
        .\periodic_read_request.periodic_rd_grant_r (\periodic_read_request.periodic_rd_grant_r ),
        .\periodic_read_request.periodic_rd_grant_r_reg[0]_0 (rank_common0_n_11),
        .\periodic_read_request.periodic_rd_r_lcl_reg_0 (\periodic_read_request.periodic_rd_r_lcl_reg ),
        .\periodic_read_request.periodic_rd_r_lcl_reg_1 (\periodic_read_request.periodic_rd_r_lcl_reg_0 ),
        .\refresh_generation.refresh_bank_r (\refresh_generation.refresh_bank_r ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ),
        .set_order_q(set_order_q),
        .set_order_q_1(set_order_q_1),
        .set_order_q_3(set_order_q_3),
        .set_order_q_5(set_order_q_5),
        .wait_for_maint_r(wait_for_maint_r),
        .wait_for_maint_r_0(wait_for_maint_r_0),
        .wait_for_maint_r_2(wait_for_maint_r_2),
        .wait_for_maint_r_4(wait_for_maint_r_4),
        .wait_for_maint_r_lcl_reg(wait_for_maint_r_lcl_reg),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg_0),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_1),
        .wait_for_maint_r_lcl_reg_2(wait_for_maint_r_lcl_reg_2),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[11] ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[15] ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[19] ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[7] ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_round_robin_arb
   (\maintenance_request.maint_rank_r_lcl_reg[0] ,
    \maintenance_request.maint_sre_ns ,
    \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0] ,
    \maintenance_request.maint_zq_r_lcl_reg ,
    \last_master_r_reg[0]_0 ,
    \maintenance_request.new_maint_rank_r ,
    \maintenance_request.upd_last_master_r ,
    \maintenance_request.maint_rank_r_lcl_reg[0]_0 ,
    \zq_cntrl.zq_request_logic.zq_request_r ,
    \refresh_generation.refresh_bank_r ,
    \grant_r_reg[0]_0 ,
    \sr_cntrl.sre_request_logic.sre_request_r ,
    \maintenance_request.maint_zq_r_lcl_reg_0 ,
    maint_sre_r,
    app_sr_req,
    \sr_cntrl.ckesr_timer.ckesr_timer_r ,
    \maintenance_request.maint_srx_r_lcl_reg ,
    CLK);
  output \maintenance_request.maint_rank_r_lcl_reg[0] ;
  output \maintenance_request.maint_sre_ns ;
  output \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0] ;
  output \maintenance_request.maint_zq_r_lcl_reg ;
  input \last_master_r_reg[0]_0 ;
  input \maintenance_request.new_maint_rank_r ;
  input \maintenance_request.upd_last_master_r ;
  input \maintenance_request.maint_rank_r_lcl_reg[0]_0 ;
  input \zq_cntrl.zq_request_logic.zq_request_r ;
  input \refresh_generation.refresh_bank_r ;
  input \grant_r_reg[0]_0 ;
  input \sr_cntrl.sre_request_logic.sre_request_r ;
  input \maintenance_request.maint_zq_r_lcl_reg_0 ;
  input maint_sre_r;
  input app_sr_req;
  input \sr_cntrl.ckesr_timer.ckesr_timer_r ;
  input \maintenance_request.maint_srx_r_lcl_reg ;
  input CLK;

  wire CLK;
  wire app_sr_req;
  wire \grant_r[0]_i_1__0_n_0 ;
  wire \grant_r[1]_i_1__0_n_0 ;
  wire \grant_r[1]_i_2__0_n_0 ;
  wire \grant_r[1]_i_3_n_0 ;
  wire \grant_r[2]_i_1__0_n_0 ;
  wire \grant_r[2]_i_2__3_n_0 ;
  wire \grant_r_reg[0]_0 ;
  wire [2:0]last_master_r;
  wire \last_master_r[0]_i_1__3_n_0 ;
  wire \last_master_r[1]_i_1__3_n_0 ;
  wire \last_master_r[2]_i_1_n_0 ;
  wire \last_master_r_reg[0]_0 ;
  wire maint_sre_r;
  wire [2:0]\maintenance_request.maint_grant_r ;
  wire \maintenance_request.maint_rank_r_lcl[0]_i_2_n_0 ;
  wire \maintenance_request.maint_rank_r_lcl_reg[0] ;
  wire \maintenance_request.maint_rank_r_lcl_reg[0]_0 ;
  wire \maintenance_request.maint_sre_ns ;
  wire \maintenance_request.maint_sre_r_lcl_i_2_n_0 ;
  wire \maintenance_request.maint_srx_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire \maintenance_request.new_maint_rank_r ;
  wire \maintenance_request.upd_last_master_r ;
  wire \refresh_generation.refresh_bank_r ;
  wire \sr_cntrl.ckesr_timer.ckesr_timer_r ;
  wire \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0] ;
  wire \sr_cntrl.sre_request_logic.sre_request_r ;
  wire \zq_cntrl.zq_request_logic.zq_request_r ;

  LUT6 #(
    .INIT(64'h0003000007070000)) 
    \grant_r[0]_i_1__0 
       (.I0(\zq_cntrl.zq_request_logic.zq_request_r ),
        .I1(\last_master_r[0]_i_1__3_n_0 ),
        .I2(\refresh_generation.refresh_bank_r ),
        .I3(\last_master_r[1]_i_1__3_n_0 ),
        .I4(\grant_r_reg[0]_0 ),
        .I5(\sr_cntrl.sre_request_logic.sre_request_r ),
        .O(\grant_r[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h80800000AA800000)) 
    \grant_r[1]_i_1__0 
       (.I0(\zq_cntrl.zq_request_logic.zq_request_r ),
        .I1(\grant_r[2]_i_2__3_n_0 ),
        .I2(\grant_r[1]_i_2__0_n_0 ),
        .I3(\refresh_generation.refresh_bank_r ),
        .I4(\grant_r_reg[0]_0 ),
        .I5(\grant_r[1]_i_3_n_0 ),
        .O(\grant_r[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair617" *) 
  LUT4 #(
    .INIT(16'h04F7)) 
    \grant_r[1]_i_2__0 
       (.I0(\maintenance_request.maint_grant_r [1]),
        .I1(\maintenance_request.upd_last_master_r ),
        .I2(\maintenance_request.new_maint_rank_r ),
        .I3(last_master_r[1]),
        .O(\grant_r[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000080888000)) 
    \grant_r[1]_i_3 
       (.I0(\sr_cntrl.sre_request_logic.sre_request_r ),
        .I1(\grant_r_reg[0]_0 ),
        .I2(\maintenance_request.maint_grant_r [1]),
        .I3(\maintenance_request.maint_sre_r_lcl_i_2_n_0 ),
        .I4(last_master_r[1]),
        .I5(\last_master_r_reg[0]_0 ),
        .O(\grant_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h4C4C0C0000000000)) 
    \grant_r[2]_i_1__0 
       (.I0(\last_master_r[0]_i_1__3_n_0 ),
        .I1(\grant_r_reg[0]_0 ),
        .I2(\zq_cntrl.zq_request_logic.zq_request_r ),
        .I3(\refresh_generation.refresh_bank_r ),
        .I4(\grant_r[2]_i_2__3_n_0 ),
        .I5(\sr_cntrl.sre_request_logic.sre_request_r ),
        .O(\grant_r[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair618" *) 
  LUT5 #(
    .INIT(32'h10111511)) 
    \grant_r[2]_i_2__3 
       (.I0(\last_master_r_reg[0]_0 ),
        .I1(last_master_r[2]),
        .I2(\maintenance_request.new_maint_rank_r ),
        .I3(\maintenance_request.upd_last_master_r ),
        .I4(\maintenance_request.maint_grant_r [2]),
        .O(\grant_r[2]_i_2__3_n_0 ));
  FDRE \grant_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[0]_i_1__0_n_0 ),
        .Q(\maintenance_request.maint_grant_r [0]),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[1]_i_1__0_n_0 ),
        .Q(\maintenance_request.maint_grant_r [1]),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[2]_i_1__0_n_0 ),
        .Q(\maintenance_request.maint_grant_r [2]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair616" *) 
  LUT5 #(
    .INIT(32'h54550400)) 
    \last_master_r[0]_i_1__3 
       (.I0(\last_master_r_reg[0]_0 ),
        .I1(\maintenance_request.maint_grant_r [0]),
        .I2(\maintenance_request.new_maint_rank_r ),
        .I3(\maintenance_request.upd_last_master_r ),
        .I4(last_master_r[0]),
        .O(\last_master_r[0]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair617" *) 
  LUT5 #(
    .INIT(32'h45444044)) 
    \last_master_r[1]_i_1__3 
       (.I0(\last_master_r_reg[0]_0 ),
        .I1(last_master_r[1]),
        .I2(\maintenance_request.new_maint_rank_r ),
        .I3(\maintenance_request.upd_last_master_r ),
        .I4(\maintenance_request.maint_grant_r [1]),
        .O(\last_master_r[1]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair618" *) 
  LUT5 #(
    .INIT(32'hFFFFFB08)) 
    \last_master_r[2]_i_1 
       (.I0(\maintenance_request.maint_grant_r [2]),
        .I1(\maintenance_request.upd_last_master_r ),
        .I2(\maintenance_request.new_maint_rank_r ),
        .I3(last_master_r[2]),
        .I4(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[2]_i_1_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[0]_i_1__3_n_0 ),
        .Q(last_master_r[0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[1]_i_1__3_n_0 ),
        .Q(last_master_r[1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[2]_i_1_n_0 ),
        .Q(last_master_r[2]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0002)) 
    \maintenance_request.maint_rank_r_lcl[0]_i_1 
       (.I0(\maintenance_request.maint_rank_r_lcl_reg[0]_0 ),
        .I1(\maintenance_request.maint_sre_ns ),
        .I2(\maintenance_request.maint_rank_r_lcl[0]_i_2_n_0 ),
        .I3(\sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0] ),
        .O(\maintenance_request.maint_rank_r_lcl_reg[0] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAFCAAAA)) 
    \maintenance_request.maint_rank_r_lcl[0]_i_2 
       (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I1(\maintenance_request.maint_grant_r [1]),
        .I2(\maintenance_request.maint_grant_r [0]),
        .I3(\maintenance_request.new_maint_rank_r ),
        .I4(\maintenance_request.upd_last_master_r ),
        .I5(\last_master_r_reg[0]_0 ),
        .O(\maintenance_request.maint_rank_r_lcl[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFA800A8)) 
    \maintenance_request.maint_sre_r_lcl_i_1 
       (.I0(maint_sre_r),
        .I1(app_sr_req),
        .I2(\sr_cntrl.ckesr_timer.ckesr_timer_r ),
        .I3(\maintenance_request.maint_sre_r_lcl_i_2_n_0 ),
        .I4(\maintenance_request.maint_grant_r [2]),
        .I5(\last_master_r_reg[0]_0 ),
        .O(\maintenance_request.maint_sre_ns ));
  (* SOFT_HLUTNM = "soft_lutpair616" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \maintenance_request.maint_sre_r_lcl_i_2 
       (.I0(\maintenance_request.upd_last_master_r ),
        .I1(\maintenance_request.new_maint_rank_r ),
        .O(\maintenance_request.maint_sre_r_lcl_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h1F1010101F101F10)) 
    \maintenance_request.maint_srx_r_lcl_i_1 
       (.I0(\sr_cntrl.ckesr_timer.ckesr_timer_r ),
        .I1(app_sr_req),
        .I2(maint_sre_r),
        .I3(\maintenance_request.maint_srx_r_lcl_reg ),
        .I4(\maintenance_request.maint_grant_r [2]),
        .I5(\maintenance_request.maint_sre_r_lcl_i_2_n_0 ),
        .O(\sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0] ));
  LUT4 #(
    .INIT(16'hBA8A)) 
    \maintenance_request.maint_zq_r_lcl_i_1 
       (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I1(\maintenance_request.new_maint_rank_r ),
        .I2(\maintenance_request.upd_last_master_r ),
        .I3(\maintenance_request.maint_grant_r [1]),
        .O(\maintenance_request.maint_zq_r_lcl_reg ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_round_robin_arb" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_round_robin_arb__parameterized1
   (\grant_r_reg[1]_0 ,
    Q,
    granted_col_r_reg,
    D,
    \wr_this_rank_r_reg[0] ,
    \wr_this_rank_r_reg[0]_0 ,
    granted_col_r_reg_0,
    I119,
    granted_col_r_reg_1,
    \periodic_rd_generation.read_this_rank_r_reg ,
    \periodic_rd_generation.read_this_rank ,
    DIC,
    E,
    col_rd_wr,
    granted_col_ns,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    \last_master_r_reg[1]_0 ,
    rd_wr_r_lcl_reg,
    \wtr_timer.wtr_cnt_r_reg[1]_0 ,
    \grant_r_reg[2]_0 ,
    \genblk3[1].rnk_config_strobe_r_reg[1] ,
    col_wr_data_buf_addr,
    \grant_r_reg[3]_0 ,
    \grant_r_reg[3]_1 ,
    \grant_r_reg[3]_2 ,
    \cmd_pipe_plus.mc_data_offset_reg[3] ,
    rd_wr_r,
    \col_mux.col_periodic_rd_r_reg ,
    \last_master_r_reg[0]_0 ,
    \grant_r[2]_i_3 ,
    \grant_r[2]_i_3_0 ,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    O,
    \periodic_rd_generation.read_this_rank_r ,
    rd_this_rank_r,
    req_periodic_rd_r,
    col_rd_wr_r,
    granted_col_r_reg_2,
    granted_col_r_reg_3,
    \grant_r_reg[0]_0 ,
    \grant_r_reg[1]_1 ,
    granted_col_r_reg_4,
    granted_col_r_reg_5,
    granted_col_r_reg_6,
    granted_col_r_reg_7,
    \grant_r_reg[3]_3 ,
    \grant_r_reg[3]_4 ,
    col_wait_r,
    \grant_r_reg[3]_5 ,
    col_wait_r_0,
    \grant_r_reg[3]_6 ,
    \col_mux.col_periodic_rd_r ,
    wr_this_rank_r,
    ofs_rdy_r_3,
    \grant_r[3]_i_2_0 ,
    \grant_r[3]_i_2_1 ,
    override_demand_r,
    \genblk3[1].rnk_config_strobe_r_reg ,
    \genblk3[2].rnk_config_strobe_r_reg ,
    rnk_config_strobe,
    req_data_buf_addr_r,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,
    \cmd_pipe_plus.mc_address_reg[23] ,
    \cmd_pipe_plus.mc_address_reg[23]_0 ,
    \cmd_pipe_plus.mc_address_reg[23]_1 ,
    \cmd_pipe_plus.mc_address_reg[23]_2 ,
    auto_pre_r,
    auto_pre_r_9,
    auto_pre_r_10,
    auto_pre_r_11,
    \cmd_pipe_plus.mc_bank_reg[5] ,
    \cmd_pipe_plus.mc_bank_reg[5]_0 ,
    \cmd_pipe_plus.mc_bank_reg[5]_1 ,
    \cmd_pipe_plus.mc_bank_reg[5]_2 ,
    CLK);
  output \grant_r_reg[1]_0 ;
  output [3:0]Q;
  output granted_col_r_reg;
  output [0:0]D;
  output \wr_this_rank_r_reg[0] ;
  output \wr_this_rank_r_reg[0]_0 ;
  output granted_col_r_reg_0;
  output [0:0]I119;
  output [0:0]granted_col_r_reg_1;
  output \periodic_rd_generation.read_this_rank_r_reg ;
  output \periodic_rd_generation.read_this_rank ;
  output [0:0]DIC;
  output [0:0]E;
  output col_rd_wr;
  output granted_col_ns;
  output \wtr_timer.wtr_cnt_r_reg[1] ;
  output [0:0]\last_master_r_reg[1]_0 ;
  output rd_wr_r_lcl_reg;
  output \wtr_timer.wtr_cnt_r_reg[1]_0 ;
  output \grant_r_reg[2]_0 ;
  output \genblk3[1].rnk_config_strobe_r_reg[1] ;
  output [3:0]col_wr_data_buf_addr;
  output [10:0]\grant_r_reg[3]_0 ;
  output [2:0]\grant_r_reg[3]_1 ;
  output \grant_r_reg[3]_2 ;
  input \cmd_pipe_plus.mc_data_offset_reg[3] ;
  input [3:0]rd_wr_r;
  input \col_mux.col_periodic_rd_r_reg ;
  input \last_master_r_reg[0]_0 ;
  input \grant_r[2]_i_3 ;
  input [0:0]\grant_r[2]_i_3_0 ;
  input \cmd_pipe_plus.mc_odt_reg[0] ;
  input [0:0]O;
  input \periodic_rd_generation.read_this_rank_r ;
  input [3:0]rd_this_rank_r;
  input [3:0]req_periodic_rd_r;
  input col_rd_wr_r;
  input granted_col_r_reg_2;
  input granted_col_r_reg_3;
  input \grant_r_reg[0]_0 ;
  input \grant_r_reg[1]_1 ;
  input granted_col_r_reg_4;
  input granted_col_r_reg_5;
  input granted_col_r_reg_6;
  input granted_col_r_reg_7;
  input \grant_r_reg[3]_3 ;
  input \grant_r_reg[3]_4 ;
  input col_wait_r;
  input \grant_r_reg[3]_5 ;
  input col_wait_r_0;
  input \grant_r_reg[3]_6 ;
  input \col_mux.col_periodic_rd_r ;
  input [3:0]wr_this_rank_r;
  input ofs_rdy_r_3;
  input \grant_r[3]_i_2_0 ;
  input \grant_r[3]_i_2_1 ;
  input override_demand_r;
  input \genblk3[1].rnk_config_strobe_r_reg ;
  input \genblk3[2].rnk_config_strobe_r_reg ;
  input rnk_config_strobe;
  input [15:0]req_data_buf_addr_r;
  input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_0 ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_1 ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_2 ;
  input auto_pre_r;
  input auto_pre_r_9;
  input auto_pre_r_10;
  input auto_pre_r_11;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[5] ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[5]_0 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[5]_1 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[5]_2 ;
  input CLK;

  wire CLK;
  wire [0:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire [0:0]I119;
  wire [0:0]O;
  wire [3:0]Q;
  wire auto_pre_r;
  wire auto_pre_r_10;
  wire auto_pre_r_11;
  wire auto_pre_r_9;
  wire \cmd_pipe_plus.mc_address[14]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[15]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[16]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[17]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[18]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[19]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[20]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[21]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[22]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[23]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[24]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[24]_i_3_n_0 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_0 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_1 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_2 ;
  wire \cmd_pipe_plus.mc_bank[3]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[4]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[5]_i_2_n_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[5] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[5]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[5]_1 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[5]_2 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[3] ;
  wire \cmd_pipe_plus.mc_odt_reg[0] ;
  wire \cmd_pipe_plus.mc_we_n[1]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_we_n[1]_i_3_n_0 ;
  wire \col_mux.col_periodic_rd_r ;
  wire \col_mux.col_periodic_rd_r_i_2_n_0 ;
  wire \col_mux.col_periodic_rd_r_reg ;
  wire \col_mux.col_rd_wr_r_i_2_n_0 ;
  wire col_rd_wr;
  wire col_rd_wr_r;
  wire col_wait_r;
  wire col_wait_r_0;
  wire [3:0]col_wr_data_buf_addr;
  wire \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2_n_0 ;
  wire \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2_n_0 ;
  wire \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2_n_0 ;
  wire \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2_n_0 ;
  wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  wire \genblk3[1].rnk_config_strobe_r_reg ;
  wire \genblk3[1].rnk_config_strobe_r_reg[1] ;
  wire \genblk3[2].rnk_config_strobe_r_reg ;
  wire \grant_r[0]_i_1_n_0 ;
  wire \grant_r[1]_i_1_n_0 ;
  wire \grant_r[1]_i_3__1_n_0 ;
  wire \grant_r[1]_i_4_n_0 ;
  wire \grant_r[2]_i_1_n_0 ;
  wire \grant_r[2]_i_2_n_0 ;
  wire \grant_r[2]_i_3 ;
  wire [0:0]\grant_r[2]_i_3_0 ;
  wire \grant_r[2]_i_4__0_n_0 ;
  wire \grant_r[3]_i_14__0_n_0 ;
  wire \grant_r[3]_i_15__0_n_0 ;
  wire \grant_r[3]_i_1_n_0 ;
  wire \grant_r[3]_i_2_0 ;
  wire \grant_r[3]_i_2_1 ;
  wire \grant_r[3]_i_2_n_0 ;
  wire \grant_r[3]_i_3__2_n_0 ;
  wire \grant_r[3]_i_4_n_0 ;
  wire \grant_r[3]_i_7__1_n_0 ;
  wire \grant_r[3]_i_9_n_0 ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[1]_1 ;
  wire \grant_r_reg[2]_0 ;
  wire [10:0]\grant_r_reg[3]_0 ;
  wire [2:0]\grant_r_reg[3]_1 ;
  wire \grant_r_reg[3]_2 ;
  wire \grant_r_reg[3]_3 ;
  wire \grant_r_reg[3]_4 ;
  wire \grant_r_reg[3]_5 ;
  wire \grant_r_reg[3]_6 ;
  wire granted_col_ns;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire [0:0]granted_col_r_reg_1;
  wire granted_col_r_reg_2;
  wire granted_col_r_reg_3;
  wire granted_col_r_reg_4;
  wire granted_col_r_reg_5;
  wire granted_col_r_reg_6;
  wire granted_col_r_reg_7;
  wire [3:0]last_master_r;
  wire \last_master_r[0]_i_1_n_0 ;
  wire \last_master_r[2]_i_1__0_n_0 ;
  wire \last_master_r[3]_i_1_n_0 ;
  wire \last_master_r_reg[0]_0 ;
  wire [0:0]\last_master_r_reg[1]_0 ;
  wire ofs_rdy_r_3;
  wire override_demand_r;
  wire \periodic_rd_generation.read_this_rank ;
  wire \periodic_rd_generation.read_this_rank_r ;
  wire \periodic_rd_generation.read_this_rank_r_i_2_n_0 ;
  wire \periodic_rd_generation.read_this_rank_r_reg ;
  wire [3:0]rd_this_rank_r;
  wire [3:0]rd_wr_r;
  wire rd_wr_r_lcl_reg;
  wire [15:0]req_data_buf_addr_r;
  wire [3:0]req_periodic_rd_r;
  wire rnk_config_strobe;
  wire [3:0]wr_this_rank_r;
  wire \wr_this_rank_r_reg[0] ;
  wire \wr_this_rank_r_reg[0]_0 ;
  wire \wtr_timer.wtr_cnt_r_reg[1] ;
  wire \wtr_timer.wtr_cnt_r_reg[1]_0 ;

  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[14]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_address_reg[23] [0]),
        .I3(\cmd_pipe_plus.mc_address[14]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_0 [0]),
        .O(\grant_r_reg[3]_0 [0]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[14]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_address_reg[23]_1 [0]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_address_reg[23]_2 [0]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(\cmd_pipe_plus.mc_address[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[15]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_address_reg[23] [1]),
        .I3(\cmd_pipe_plus.mc_address[15]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_0 [1]),
        .O(\grant_r_reg[3]_0 [1]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[15]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_address_reg[23]_1 [1]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_address_reg[23]_2 [1]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(\cmd_pipe_plus.mc_address[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[16]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_address_reg[23] [2]),
        .I3(\cmd_pipe_plus.mc_address[16]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_0 [2]),
        .O(\grant_r_reg[3]_0 [2]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[16]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_address_reg[23]_1 [2]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_address_reg[23]_2 [2]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(\cmd_pipe_plus.mc_address[16]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[17]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_address_reg[23] [3]),
        .I3(\cmd_pipe_plus.mc_address[17]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_0 [3]),
        .O(\grant_r_reg[3]_0 [3]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[17]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_address_reg[23]_1 [3]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_address_reg[23]_2 [3]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(\cmd_pipe_plus.mc_address[17]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[18]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_address_reg[23] [4]),
        .I3(\cmd_pipe_plus.mc_address[18]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_0 [4]),
        .O(\grant_r_reg[3]_0 [4]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[18]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_address_reg[23]_1 [4]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_address_reg[23]_2 [4]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(\cmd_pipe_plus.mc_address[18]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[19]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_address_reg[23] [5]),
        .I3(\cmd_pipe_plus.mc_address[19]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_0 [5]),
        .O(\grant_r_reg[3]_0 [5]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[19]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_address_reg[23]_1 [5]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_address_reg[23]_2 [5]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(\cmd_pipe_plus.mc_address[19]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[20]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_address_reg[23] [6]),
        .I3(\cmd_pipe_plus.mc_address[20]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_0 [6]),
        .O(\grant_r_reg[3]_0 [6]));
  LUT6 #(
    .INIT(64'hFFFFFDDDDDDDFDDD)) 
    \cmd_pipe_plus.mc_address[20]_i_2 
       (.I0(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I1(Q[3]),
        .I2(\cmd_pipe_plus.mc_address_reg[23]_1 [6]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_2 [6]),
        .O(\cmd_pipe_plus.mc_address[20]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[21]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_address_reg[23] [7]),
        .I3(\cmd_pipe_plus.mc_address[21]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_0 [7]),
        .O(\grant_r_reg[3]_0 [7]));
  LUT6 #(
    .INIT(64'hFFFFFDDDDDDDFDDD)) 
    \cmd_pipe_plus.mc_address[21]_i_2 
       (.I0(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I1(Q[3]),
        .I2(\cmd_pipe_plus.mc_address_reg[23]_1 [7]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_2 [7]),
        .O(\cmd_pipe_plus.mc_address[21]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[22]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_address_reg[23] [8]),
        .I3(\cmd_pipe_plus.mc_address[22]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_0 [8]),
        .O(\grant_r_reg[3]_0 [8]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[22]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_address_reg[23]_1 [8]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_address_reg[23]_2 [8]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(\cmd_pipe_plus.mc_address[22]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[23]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_address_reg[23] [9]),
        .I3(\cmd_pipe_plus.mc_address[23]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_0 [9]),
        .O(\grant_r_reg[3]_0 [9]));
  LUT6 #(
    .INIT(64'hFFFFFDDDDDDDFDDD)) 
    \cmd_pipe_plus.mc_address[23]_i_2 
       (.I0(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I1(Q[3]),
        .I2(\cmd_pipe_plus.mc_address_reg[23]_1 [9]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_2 [9]),
        .O(\cmd_pipe_plus.mc_address[23]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[24]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(auto_pre_r),
        .I3(\cmd_pipe_plus.mc_address[24]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(auto_pre_r_9),
        .O(\grant_r_reg[3]_0 [10]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[24]_i_2 
       (.I0(Q[1]),
        .I1(auto_pre_r_10),
        .I2(Q[2]),
        .I3(auto_pre_r_11),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(\cmd_pipe_plus.mc_address[24]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair560" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \cmd_pipe_plus.mc_address[24]_i_3 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .O(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair565" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \cmd_pipe_plus.mc_aux_out0[1]_i_1 
       (.I0(\col_mux.col_rd_wr_r_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(granted_col_r_reg));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_bank[3]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_bank_reg[5] [0]),
        .I3(\cmd_pipe_plus.mc_bank[3]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_bank_reg[5]_0 [0]),
        .O(\grant_r_reg[3]_1 [0]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_bank[3]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_bank_reg[5]_1 [0]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_bank_reg[5]_2 [0]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(\cmd_pipe_plus.mc_bank[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_bank[4]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_bank_reg[5] [1]),
        .I3(\cmd_pipe_plus.mc_bank[4]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_bank_reg[5]_0 [1]),
        .O(\grant_r_reg[3]_1 [1]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_bank[4]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_bank_reg[5]_1 [1]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_bank_reg[5]_2 [1]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(\cmd_pipe_plus.mc_bank[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_bank[5]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_bank_reg[5] [2]),
        .I3(\cmd_pipe_plus.mc_bank[5]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address[24]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_bank_reg[5]_0 [2]),
        .O(\grant_r_reg[3]_1 [2]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_bank[5]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_bank_reg[5]_1 [2]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_bank_reg[5]_2 [2]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(\cmd_pipe_plus.mc_bank[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair562" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \cmd_pipe_plus.mc_cmd[1]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I1(\col_mux.col_rd_wr_r_i_2_n_0 ),
        .O(E));
  (* SOFT_HLUTNM = "soft_lutpair567" *) 
  LUT3 #(
    .INIT(8'hC8)) 
    \cmd_pipe_plus.mc_data_offset[3]_i_1 
       (.I0(\col_mux.col_rd_wr_r_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(O),
        .O(granted_col_r_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair564" *) 
  LUT2 #(
    .INIT(4'hD)) 
    \cmd_pipe_plus.mc_data_offset[5]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I1(\col_mux.col_rd_wr_r_i_2_n_0 ),
        .O(granted_col_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair567" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \cmd_pipe_plus.mc_odt[0]_i_1 
       (.I0(\col_mux.col_rd_wr_r_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(\cmd_pipe_plus.mc_odt_reg[0] ),
        .O(I119));
  (* SOFT_HLUTNM = "soft_lutpair560" *) 
  LUT5 #(
    .INIT(32'hFFFEFFFF)) 
    \cmd_pipe_plus.mc_ras_n[1]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(\grant_r_reg[1]_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \cmd_pipe_plus.mc_we_n[1]_i_1 
       (.I0(\cmd_pipe_plus.mc_we_n[1]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(D));
  LUT5 #(
    .INIT(32'hFE0EF202)) 
    \cmd_pipe_plus.mc_we_n[1]_i_2 
       (.I0(\cmd_pipe_plus.mc_we_n[1]_i_3_n_0 ),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(rd_wr_r[3]),
        .I4(rd_wr_r[2]),
        .O(\cmd_pipe_plus.mc_we_n[1]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hCCA0)) 
    \cmd_pipe_plus.mc_we_n[1]_i_3 
       (.I0(rd_wr_r[0]),
        .I1(rd_wr_r[1]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\cmd_pipe_plus.mc_we_n[1]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFC500C5)) 
    \col_mux.col_periodic_rd_r_i_1 
       (.I0(\col_mux.col_periodic_rd_r_i_2_n_0 ),
        .I1(req_periodic_rd_r[2]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(req_periodic_rd_r[3]),
        .O(DIC));
  LUT6 #(
    .INIT(64'h1D3F1D3F1D0C1D3F)) 
    \col_mux.col_periodic_rd_r_i_2 
       (.I0(req_periodic_rd_r[0]),
        .I1(Q[1]),
        .I2(req_periodic_rd_r[1]),
        .I3(Q[0]),
        .I4(\col_mux.col_periodic_rd_r ),
        .I5(\col_mux.col_periodic_rd_r_reg ),
        .O(\col_mux.col_periodic_rd_r_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \col_mux.col_rd_wr_r_i_1 
       (.I0(\col_mux.col_rd_wr_r_i_2_n_0 ),
        .O(col_rd_wr));
  LUT6 #(
    .INIT(64'h00000000FFFEFFFF)) 
    \col_mux.col_rd_wr_r_i_2 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(col_rd_wr_r),
        .I5(\cmd_pipe_plus.mc_we_n[1]_i_2_n_0 ),
        .O(\col_mux.col_rd_wr_r_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_1 
       (.I0(req_data_buf_addr_r[12]),
        .I1(Q[3]),
        .I2(req_data_buf_addr_r[8]),
        .I3(Q[2]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2_n_0 ),
        .O(col_wr_data_buf_addr[0]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2 
       (.I0(req_data_buf_addr_r[4]),
        .I1(Q[1]),
        .I2(req_data_buf_addr_r[0]),
        .I3(Q[0]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [0]),
        .O(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_1 
       (.I0(req_data_buf_addr_r[13]),
        .I1(Q[3]),
        .I2(req_data_buf_addr_r[9]),
        .I3(Q[2]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2_n_0 ),
        .O(col_wr_data_buf_addr[1]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2 
       (.I0(req_data_buf_addr_r[5]),
        .I1(Q[1]),
        .I2(req_data_buf_addr_r[1]),
        .I3(Q[0]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [1]),
        .O(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_1 
       (.I0(req_data_buf_addr_r[14]),
        .I1(Q[3]),
        .I2(req_data_buf_addr_r[10]),
        .I3(Q[2]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2_n_0 ),
        .O(col_wr_data_buf_addr[2]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2 
       (.I0(req_data_buf_addr_r[6]),
        .I1(Q[1]),
        .I2(req_data_buf_addr_r[2]),
        .I3(Q[0]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [2]),
        .O(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_1 
       (.I0(req_data_buf_addr_r[15]),
        .I1(Q[3]),
        .I2(req_data_buf_addr_r[11]),
        .I3(Q[2]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2_n_0 ),
        .O(col_wr_data_buf_addr[3]));
  LUT5 #(
    .INIT(32'hFF00B8B8)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2 
       (.I0(req_data_buf_addr_r[3]),
        .I1(Q[0]),
        .I2(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [3]),
        .I3(req_data_buf_addr_r[7]),
        .I4(Q[1]),
        .O(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000004050455)) 
    \grant_r[0]_i_1 
       (.I0(\grant_r[2]_i_2_n_0 ),
        .I1(\grant_r[3]_i_4_n_0 ),
        .I2(\grant_r_reg[0]_0 ),
        .I3(\last_master_r[0]_i_1_n_0 ),
        .I4(\last_master_r_reg[1]_0 ),
        .I5(granted_col_r_reg_2),
        .O(\grant_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000055050404)) 
    \grant_r[1]_i_1 
       (.I0(\grant_r_reg[1]_1 ),
        .I1(\grant_r[1]_i_3__1_n_0 ),
        .I2(\grant_r[1]_i_4_n_0 ),
        .I3(\wtr_timer.wtr_cnt_r_reg[1] ),
        .I4(granted_col_r_reg_2),
        .I5(\grant_r[3]_i_4_n_0 ),
        .O(\grant_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair561" *) 
  LUT4 #(
    .INIT(16'h0151)) 
    \grant_r[1]_i_3__1 
       (.I0(\last_master_r_reg[0]_0 ),
        .I1(last_master_r[3]),
        .I2(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I3(Q[3]),
        .O(\grant_r[1]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'h0F0A0F0F0F0A0C0C)) 
    \grant_r[1]_i_4 
       (.I0(Q[2]),
        .I1(last_master_r[2]),
        .I2(\last_master_r_reg[0]_0 ),
        .I3(Q[1]),
        .I4(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I5(last_master_r[1]),
        .O(\grant_r[1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair566" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \grant_r[1]_i_5 
       (.I0(\wtr_timer.wtr_cnt_r_reg[1]_0 ),
        .I1(rd_wr_r[2]),
        .I2(\grant_r_reg[2]_0 ),
        .O(rd_wr_r_lcl_reg));
  LUT6 #(
    .INIT(64'h0000000051515000)) 
    \grant_r[2]_i_1 
       (.I0(\grant_r[2]_i_2_n_0 ),
        .I1(\last_master_r[0]_i_1_n_0 ),
        .I2(\grant_r[3]_i_4_n_0 ),
        .I3(granted_col_r_reg_2),
        .I4(\grant_r[2]_i_4__0_n_0 ),
        .I5(granted_col_r_reg_3),
        .O(\grant_r[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \grant_r[2]_i_2 
       (.I0(\col_mux.col_periodic_rd_r_reg ),
        .I1(Q[2]),
        .I2(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I3(last_master_r[2]),
        .I4(\wtr_timer.wtr_cnt_r_reg[1] ),
        .O(\grant_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0005000000050303)) 
    \grant_r[2]_i_4__0 
       (.I0(Q[3]),
        .I1(last_master_r[3]),
        .I2(\last_master_r_reg[0]_0 ),
        .I3(Q[2]),
        .I4(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I5(last_master_r[2]),
        .O(\grant_r[2]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000CC0C0404)) 
    \grant_r[3]_i_1 
       (.I0(\last_master_r_reg[1]_0 ),
        .I1(\grant_r[3]_i_2_n_0 ),
        .I2(\grant_r[3]_i_3__2_n_0 ),
        .I3(\grant_r[3]_i_4_n_0 ),
        .I4(granted_col_r_reg_3),
        .I5(\wtr_timer.wtr_cnt_r_reg[1] ),
        .O(\grant_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair559" *) 
  LUT4 #(
    .INIT(16'h00FB)) 
    \grant_r[3]_i_10__1 
       (.I0(\wr_this_rank_r_reg[0]_0 ),
        .I1(\wr_this_rank_r_reg[0] ),
        .I2(\grant_r[2]_i_3_0 ),
        .I3(\grant_r[2]_i_3 ),
        .O(\wtr_timer.wtr_cnt_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h00000000FE0EF202)) 
    \grant_r[3]_i_11 
       (.I0(\cmd_pipe_plus.mc_we_n[1]_i_3_n_0 ),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(rd_wr_r[3]),
        .I4(rd_wr_r[2]),
        .I5(\col_mux.col_periodic_rd_r_reg ),
        .O(\grant_r_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair559" *) 
  LUT5 #(
    .INIT(32'h55450000)) 
    \grant_r[3]_i_14__0 
       (.I0(\grant_r[2]_i_3 ),
        .I1(\grant_r[2]_i_3_0 ),
        .I2(\wr_this_rank_r_reg[0] ),
        .I3(\wr_this_rank_r_reg[0]_0 ),
        .I4(rd_wr_r[3]),
        .O(\grant_r[3]_i_14__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000000E0002)) 
    \grant_r[3]_i_15__0 
       (.I0(\cmd_pipe_plus.mc_we_n[1]_i_3_n_0 ),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(rd_wr_r[3]),
        .I4(rd_wr_r[2]),
        .I5(\col_mux.col_periodic_rd_r_reg ),
        .O(\grant_r[3]_i_15__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFEFFFEFFFF)) 
    \grant_r[3]_i_2 
       (.I0(\grant_r[1]_i_3__1_n_0 ),
        .I1(\grant_r[3]_i_7__1_n_0 ),
        .I2(\grant_r_reg[3]_5 ),
        .I3(\grant_r[3]_i_9_n_0 ),
        .I4(col_wait_r_0),
        .I5(\grant_r_reg[3]_6 ),
        .O(\grant_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFAFFFACC)) 
    \grant_r[3]_i_3__2 
       (.I0(Q[0]),
        .I1(last_master_r[0]),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I4(last_master_r[3]),
        .I5(\last_master_r_reg[0]_0 ),
        .O(\grant_r[3]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFB8FFB8FFB8FFFF)) 
    \grant_r[3]_i_4 
       (.I0(\wtr_timer.wtr_cnt_r_reg[1]_0 ),
        .I1(rd_wr_r[1]),
        .I2(\grant_r_reg[2]_0 ),
        .I3(\grant_r_reg[3]_3 ),
        .I4(\grant_r_reg[3]_4 ),
        .I5(col_wait_r),
        .O(\grant_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFFFFFF)) 
    \grant_r[3]_i_6 
       (.I0(\grant_r[3]_i_14__0_n_0 ),
        .I1(\grant_r[3]_i_15__0_n_0 ),
        .I2(granted_col_r_reg_4),
        .I3(granted_col_r_reg_5),
        .I4(granted_col_r_reg_6),
        .I5(granted_col_r_reg_7),
        .O(\wtr_timer.wtr_cnt_r_reg[1] ));
  LUT6 #(
    .INIT(64'hFFFBFFFBFFFBFFFF)) 
    \grant_r[3]_i_7__1 
       (.I0(\genblk3[1].rnk_config_strobe_r_reg[1] ),
        .I1(ofs_rdy_r_3),
        .I2(Q[0]),
        .I3(\grant_r[3]_i_2_0 ),
        .I4(\grant_r[3]_i_2_1 ),
        .I5(override_demand_r),
        .O(\grant_r[3]_i_7__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair566" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \grant_r[3]_i_9 
       (.I0(\wtr_timer.wtr_cnt_r_reg[1]_0 ),
        .I1(rd_wr_r[0]),
        .I2(\grant_r_reg[2]_0 ),
        .O(\grant_r[3]_i_9_n_0 ));
  FDRE \grant_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[0]_i_1_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[1]_i_1_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[2]_i_1_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \grant_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[3]_i_1_n_0 ),
        .Q(Q[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    granted_col_r_i_1
       (.I0(\grant_r[3]_i_4_n_0 ),
        .I1(granted_col_r_reg_2),
        .I2(\wtr_timer.wtr_cnt_r_reg[1] ),
        .I3(granted_col_r_reg_3),
        .O(granted_col_ns));
  (* SOFT_HLUTNM = "soft_lutpair564" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[0]_i_1 
       (.I0(last_master_r[0]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(Q[0]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair562" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[1]_i_1 
       (.I0(last_master_r[1]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(Q[1]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair565" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[2]_i_1__0 
       (.I0(last_master_r[2]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(Q[2]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair561" *) 
  LUT4 #(
    .INIT(16'hFFB8)) 
    \last_master_r[3]_i_1 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .I2(last_master_r[3]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[3]_i_1_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[0]_i_1_n_0 ),
        .Q(last_master_r[0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r_reg[1]_0 ),
        .Q(last_master_r[1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[2]_i_1__0_n_0 ),
        .Q(last_master_r[2]),
        .R(1'b0));
  FDRE \last_master_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[3]_i_1_n_0 ),
        .Q(last_master_r[3]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hFE)) 
    override_demand_r_i_1
       (.I0(\genblk3[1].rnk_config_strobe_r_reg ),
        .I1(\genblk3[2].rnk_config_strobe_r_reg ),
        .I2(rnk_config_strobe),
        .O(\genblk3[1].rnk_config_strobe_r_reg[1] ));
  LUT6 #(
    .INIT(64'hAAAAA888A888A888)) 
    \periodic_rd_generation.periodic_rd_timer_r[2]_i_2 
       (.I0(\periodic_rd_generation.read_this_rank_r ),
        .I1(\periodic_rd_generation.read_this_rank_r_i_2_n_0 ),
        .I2(rd_this_rank_r[1]),
        .I3(Q[1]),
        .I4(rd_this_rank_r[0]),
        .I5(Q[0]),
        .O(\periodic_rd_generation.read_this_rank_r_reg ));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \periodic_rd_generation.read_this_rank_r_i_1 
       (.I0(\periodic_rd_generation.read_this_rank_r_i_2_n_0 ),
        .I1(rd_this_rank_r[1]),
        .I2(Q[1]),
        .I3(rd_this_rank_r[0]),
        .I4(Q[0]),
        .O(\periodic_rd_generation.read_this_rank ));
  LUT4 #(
    .INIT(16'hF888)) 
    \periodic_rd_generation.read_this_rank_r_i_2 
       (.I0(rd_this_rank_r[3]),
        .I1(Q[3]),
        .I2(rd_this_rank_r[2]),
        .I3(Q[2]),
        .O(\periodic_rd_generation.read_this_rank_r_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair563" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \starve_limit_cntr_r[2]_i_2__2 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(\grant_r_reg[3]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair563" *) 
  LUT4 #(
    .INIT(16'h0777)) 
    \wtr_timer.wtr_cnt_r[1]_i_2 
       (.I0(wr_this_rank_r[3]),
        .I1(Q[3]),
        .I2(wr_this_rank_r[0]),
        .I3(Q[0]),
        .O(\wr_this_rank_r_reg[0] ));
  LUT4 #(
    .INIT(16'hF888)) 
    \wtr_timer.wtr_cnt_r[1]_i_3 
       (.I0(wr_this_rank_r[1]),
        .I1(Q[1]),
        .I2(wr_this_rank_r[2]),
        .I3(Q[2]),
        .O(\wr_this_rank_r_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_round_robin_arb" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_round_robin_arb__parameterized1_3
   (\rnk_config_r_reg[0] ,
    \rnk_config_strobe_r_reg[0] ,
    \grant_r_reg[1]_0 ,
    \grant_r_reg[0]_0 ,
    rnk_config_valid_r_lcl_reg,
    rnk_config_0,
    \last_master_r_reg[3]_0 ,
    rnk_config_r,
    rnk_config_strobe,
    rnk_config_valid_r,
    \grant_r_reg[0]_1 ,
    \grant_r_reg[0]_2 ,
    \grant_r_reg[0]_3 ,
    \grant_r_reg[1]_1 ,
    \grant_r_reg[2]_0 ,
    req_bank_rdy_ns,
    req_bank_rdy_ns_1,
    \grant_r_reg[1]_2 ,
    \grant_r[3]_i_4 ,
    Q,
    ofs_rdy_r,
    \grant_r[3]_i_6 ,
    \grant_r[3]_i_4_0 ,
    \grant_r_reg[0]_4 ,
    req_bank_rdy_ns_2,
    \grant_r[2]_i_3 ,
    \grant_r[2]_i_3_0 ,
    ofs_rdy_r_3,
    req_bank_rdy_ns_4,
    \grant_r_reg[3]_0 ,
    \genblk3[2].rnk_config_strobe_r_reg ,
    \genblk3[1].rnk_config_strobe_r_reg ,
    ofs_rdy_r_7,
    \last_master_r_reg[0]_0 ,
    CLK);
  output \rnk_config_r_reg[0] ;
  output \rnk_config_strobe_r_reg[0] ;
  output \grant_r_reg[1]_0 ;
  output \grant_r_reg[0]_0 ;
  output rnk_config_valid_r_lcl_reg;
  output rnk_config_0;
  input \last_master_r_reg[3]_0 ;
  input rnk_config_r;
  input rnk_config_strobe;
  input rnk_config_valid_r;
  input \grant_r_reg[0]_1 ;
  input \grant_r_reg[0]_2 ;
  input \grant_r_reg[0]_3 ;
  input \grant_r_reg[1]_1 ;
  input \grant_r_reg[2]_0 ;
  input req_bank_rdy_ns;
  input req_bank_rdy_ns_1;
  input \grant_r_reg[1]_2 ;
  input \grant_r[3]_i_4 ;
  input [2:0]Q;
  input ofs_rdy_r;
  input \grant_r[3]_i_6 ;
  input \grant_r[3]_i_4_0 ;
  input \grant_r_reg[0]_4 ;
  input req_bank_rdy_ns_2;
  input \grant_r[2]_i_3 ;
  input \grant_r[2]_i_3_0 ;
  input ofs_rdy_r_3;
  input req_bank_rdy_ns_4;
  input \grant_r_reg[3]_0 ;
  input \genblk3[2].rnk_config_strobe_r_reg ;
  input \genblk3[1].rnk_config_strobe_r_reg ;
  input ofs_rdy_r_7;
  input \last_master_r_reg[0]_0 ;
  input CLK;

  wire CLK;
  wire [2:0]Q;
  wire \genblk3[1].rnk_config_strobe_r_reg ;
  wire \genblk3[2].rnk_config_strobe_r_reg ;
  wire [3:0]grant_config_r;
  wire \grant_r[0]_i_1__1_n_0 ;
  wire \grant_r[0]_i_2__0_n_0 ;
  wire \grant_r[0]_i_3_n_0 ;
  wire \grant_r[1]_i_1__1_n_0 ;
  wire \grant_r[1]_i_2__1_n_0 ;
  wire \grant_r[1]_i_3__0_n_0 ;
  wire \grant_r[2]_i_1__1_n_0 ;
  wire \grant_r[2]_i_2__0_n_0 ;
  wire \grant_r[2]_i_3 ;
  wire \grant_r[2]_i_3_0 ;
  wire \grant_r[2]_i_3__2_n_0 ;
  wire \grant_r[3]_i_1__0_n_0 ;
  wire \grant_r[3]_i_23_n_0 ;
  wire \grant_r[3]_i_2__0_n_0 ;
  wire \grant_r[3]_i_4 ;
  wire \grant_r[3]_i_4_0 ;
  wire \grant_r[3]_i_6 ;
  wire \grant_r[3]_i_6__1_n_0 ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[0]_2 ;
  wire \grant_r_reg[0]_3 ;
  wire \grant_r_reg[0]_4 ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[1]_1 ;
  wire \grant_r_reg[1]_2 ;
  wire \grant_r_reg[2]_0 ;
  wire \grant_r_reg[3]_0 ;
  wire [3:0]last_master_r;
  wire \last_master_r[0]_i_1__0_n_0 ;
  wire \last_master_r[1]_i_1__0_n_0 ;
  wire \last_master_r[2]_i_1__1_n_0 ;
  wire \last_master_r[3]_i_1__0_n_0 ;
  wire \last_master_r_reg[0]_0 ;
  wire \last_master_r_reg[3]_0 ;
  wire ofs_rdy_r;
  wire ofs_rdy_r_3;
  wire ofs_rdy_r_7;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_ns_1;
  wire req_bank_rdy_ns_2;
  wire req_bank_rdy_ns_4;
  wire rnk_config_0;
  wire rnk_config_r;
  wire \rnk_config_r[0]_i_2_n_0 ;
  wire \rnk_config_r_reg[0] ;
  wire rnk_config_strobe;
  wire \rnk_config_strobe_r_reg[0] ;
  wire rnk_config_valid_r;
  wire rnk_config_valid_r_lcl_reg;

  LUT6 #(
    .INIT(64'h0000000004CC040C)) 
    \grant_r[0]_i_1__1 
       (.I0(\last_master_r[2]_i_1__1_n_0 ),
        .I1(\grant_r[0]_i_2__0_n_0 ),
        .I2(\grant_r[0]_i_3_n_0 ),
        .I3(\grant_r_reg[0]_1 ),
        .I4(\grant_r_reg[0]_2 ),
        .I5(\grant_r_reg[0]_3 ),
        .O(\grant_r[0]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hDFFF)) 
    \grant_r[0]_i_2__0 
       (.I0(\last_master_r[0]_i_1__0_n_0 ),
        .I1(\rnk_config_strobe_r_reg[0] ),
        .I2(\grant_r_reg[0]_4 ),
        .I3(req_bank_rdy_ns_2),
        .O(\grant_r[0]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0F0A0F0F0F0A0C0C)) 
    \grant_r[0]_i_3 
       (.I0(grant_config_r[1]),
        .I1(last_master_r[1]),
        .I2(\last_master_r_reg[0]_0 ),
        .I3(grant_config_r[0]),
        .I4(rnk_config_strobe),
        .I5(last_master_r[0]),
        .O(\grant_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hC040CC4000000000)) 
    \grant_r[1]_i_1__1 
       (.I0(\last_master_r[3]_i_1__0_n_0 ),
        .I1(\grant_r[1]_i_2__1_n_0 ),
        .I2(\grant_r[1]_i_3__0_n_0 ),
        .I3(\grant_r_reg[0]_3 ),
        .I4(\grant_r_reg[0]_1 ),
        .I5(\grant_r_reg[1]_1 ),
        .O(\grant_r[1]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hDFFF)) 
    \grant_r[1]_i_2__1 
       (.I0(req_bank_rdy_ns_1),
        .I1(\rnk_config_strobe_r_reg[0] ),
        .I2(\grant_r_reg[1]_2 ),
        .I3(\last_master_r[1]_i_1__0_n_0 ),
        .O(\grant_r[1]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0F5F0F0F0F5F3F3)) 
    \grant_r[1]_i_3__0 
       (.I0(grant_config_r[2]),
        .I1(last_master_r[2]),
        .I2(\last_master_r_reg[3]_0 ),
        .I3(grant_config_r[1]),
        .I4(rnk_config_strobe),
        .I5(last_master_r[1]),
        .O(\grant_r[1]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000001550105)) 
    \grant_r[2]_i_1__1 
       (.I0(\grant_r[2]_i_2__0_n_0 ),
        .I1(\last_master_r[0]_i_1__0_n_0 ),
        .I2(\grant_r[2]_i_3__2_n_0 ),
        .I3(\grant_r_reg[1]_1 ),
        .I4(\grant_r_reg[0]_3 ),
        .I5(\grant_r_reg[0]_2 ),
        .O(\grant_r[2]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2000)) 
    \grant_r[2]_i_2__0 
       (.I0(\last_master_r[2]_i_1__1_n_0 ),
        .I1(\rnk_config_strobe_r_reg[0] ),
        .I2(\grant_r_reg[2]_0 ),
        .I3(req_bank_rdy_ns),
        .O(\grant_r[2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFCFAFAFFFC)) 
    \grant_r[2]_i_3__2 
       (.I0(grant_config_r[3]),
        .I1(last_master_r[3]),
        .I2(\last_master_r_reg[3]_0 ),
        .I3(last_master_r[2]),
        .I4(rnk_config_strobe),
        .I5(grant_config_r[2]),
        .O(\grant_r[2]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    \grant_r[2]_i_5 
       (.I0(\grant_r[2]_i_3 ),
        .I1(\grant_r[2]_i_3_0 ),
        .I2(\rnk_config_r_reg[0] ),
        .I3(Q[0]),
        .I4(ofs_rdy_r_3),
        .I5(\grant_r[3]_i_6 ),
        .O(\grant_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \grant_r[3]_i_12 
       (.I0(\grant_r[3]_i_4 ),
        .I1(\rnk_config_r_reg[0] ),
        .I2(Q[1]),
        .I3(ofs_rdy_r),
        .I4(\grant_r[3]_i_6 ),
        .I5(\grant_r[3]_i_4_0 ),
        .O(\grant_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h00101010FFFFFFFF)) 
    \grant_r[3]_i_12__1 
       (.I0(\rnk_config_r[0]_i_2_n_0 ),
        .I1(\last_master_r_reg[3]_0 ),
        .I2(rnk_config_r),
        .I3(grant_config_r[2]),
        .I4(rnk_config_strobe),
        .I5(rnk_config_valid_r),
        .O(\rnk_config_r_reg[0] ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF5DFFFF)) 
    \grant_r[3]_i_17 
       (.I0(rnk_config_valid_r),
        .I1(\grant_r[3]_i_23_n_0 ),
        .I2(\rnk_config_r[0]_i_2_n_0 ),
        .I3(Q[2]),
        .I4(ofs_rdy_r_7),
        .I5(\grant_r[3]_i_6 ),
        .O(rnk_config_valid_r_lcl_reg));
  LUT6 #(
    .INIT(64'h5010501000005000)) 
    \grant_r[3]_i_1__0 
       (.I0(\grant_r[3]_i_2__0_n_0 ),
        .I1(\last_master_r[1]_i_1__0_n_0 ),
        .I2(\grant_r_reg[0]_1 ),
        .I3(\grant_r_reg[0]_2 ),
        .I4(\grant_r_reg[1]_1 ),
        .I5(\grant_r[3]_i_6__1_n_0 ),
        .O(\grant_r[3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair568" *) 
  LUT4 #(
    .INIT(16'h0444)) 
    \grant_r[3]_i_23 
       (.I0(\last_master_r_reg[3]_0 ),
        .I1(rnk_config_r),
        .I2(grant_config_r[2]),
        .I3(rnk_config_strobe),
        .O(\grant_r[3]_i_23_n_0 ));
  LUT4 #(
    .INIT(16'h0800)) 
    \grant_r[3]_i_2__0 
       (.I0(\last_master_r[3]_i_1__0_n_0 ),
        .I1(req_bank_rdy_ns_4),
        .I2(\rnk_config_strobe_r_reg[0] ),
        .I3(\grant_r_reg[3]_0 ),
        .O(\grant_r[3]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0005000000050303)) 
    \grant_r[3]_i_6__1 
       (.I0(grant_config_r[3]),
        .I1(last_master_r[3]),
        .I2(\last_master_r_reg[3]_0 ),
        .I3(grant_config_r[0]),
        .I4(rnk_config_strobe),
        .I5(last_master_r[0]),
        .O(\grant_r[3]_i_6__1_n_0 ));
  LUT4 #(
    .INIT(16'hFEFF)) 
    \grant_r[3]_i_7__0 
       (.I0(rnk_config_strobe),
        .I1(\genblk3[2].rnk_config_strobe_r_reg ),
        .I2(\genblk3[1].rnk_config_strobe_r_reg ),
        .I3(\rnk_config_r_reg[0] ),
        .O(\rnk_config_strobe_r_reg[0] ));
  FDRE \grant_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[0]_i_1__1_n_0 ),
        .Q(grant_config_r[0]),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[1]_i_1__1_n_0 ),
        .Q(grant_config_r[1]),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[2]_i_1__1_n_0 ),
        .Q(grant_config_r[2]),
        .R(1'b0));
  FDRE \grant_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[3]_i_1__0_n_0 ),
        .Q(grant_config_r[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[0]_i_1__0 
       (.I0(last_master_r[0]),
        .I1(rnk_config_strobe),
        .I2(grant_config_r[0]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[0]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[1]_i_1__0 
       (.I0(last_master_r[1]),
        .I1(rnk_config_strobe),
        .I2(grant_config_r[1]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[1]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[2]_i_1__1 
       (.I0(last_master_r[2]),
        .I1(rnk_config_strobe),
        .I2(grant_config_r[2]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[2]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hFEAE)) 
    \last_master_r[3]_i_1__0 
       (.I0(\last_master_r_reg[3]_0 ),
        .I1(last_master_r[3]),
        .I2(rnk_config_strobe),
        .I3(grant_config_r[3]),
        .O(\last_master_r[3]_i_1__0_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[0]_i_1__0_n_0 ),
        .Q(last_master_r[0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[1]_i_1__0_n_0 ),
        .Q(last_master_r[1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[2]_i_1__1_n_0 ),
        .Q(last_master_r[2]),
        .R(1'b0));
  FDRE \last_master_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[3]_i_1__0_n_0 ),
        .Q(last_master_r[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair568" *) 
  LUT5 #(
    .INIT(32'h00000070)) 
    \rnk_config_r[0]_i_1 
       (.I0(rnk_config_strobe),
        .I1(grant_config_r[2]),
        .I2(rnk_config_r),
        .I3(\last_master_r_reg[3]_0 ),
        .I4(\rnk_config_r[0]_i_2_n_0 ),
        .O(rnk_config_0));
  LUT4 #(
    .INIT(16'hAAA8)) 
    \rnk_config_r[0]_i_2 
       (.I0(rnk_config_strobe),
        .I1(grant_config_r[1]),
        .I2(grant_config_r[0]),
        .I3(grant_config_r[3]),
        .O(\rnk_config_r[0]_i_2_n_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_round_robin_arb" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_round_robin_arb__parameterized1_4
   (Q,
    \grant_r_reg[3]_0 ,
    \grant_r_reg[3]_1 ,
    mc_cas_n_ns,
    D,
    \last_master_r_reg[0]_0 ,
    cs_en2,
    \grant_r_reg[0]_0 ,
    \grant_r_reg[0]_1 ,
    \grant_r_reg[0]_2 ,
    \grant_r_reg[1]_0 ,
    req_row_r,
    row_cmd_wr,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \cmd_pipe_plus.mc_bank_reg[8]_0 ,
    \cmd_pipe_plus.mc_bank_reg[8]_1 ,
    \cmd_pipe_plus.mc_bank_reg[8]_2 ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    CLK);
  output [3:0]Q;
  output [13:0]\grant_r_reg[3]_0 ;
  output [2:0]\grant_r_reg[3]_1 ;
  output [0:0]mc_cas_n_ns;
  output [0:0]D;
  input \last_master_r_reg[0]_0 ;
  input cs_en2;
  input \grant_r_reg[0]_0 ;
  input \grant_r_reg[0]_1 ;
  input \grant_r_reg[0]_2 ;
  input \grant_r_reg[1]_0 ;
  input [38:0]req_row_r;
  input [3:0]row_cmd_wr;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[8]_1 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[8]_2 ;
  input [16:0]\cmd_pipe_plus.mc_address_reg[41] ;
  input CLK;

  wire CLK;
  wire [0:0]D;
  wire [3:0]Q;
  wire \cmd_pipe_plus.mc_address[28]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[29]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[30]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[31]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[32]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[33]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[34]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[35]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[36]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[37]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[38]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[38]_i_3_n_0 ;
  wire \cmd_pipe_plus.mc_address[38]_i_4_n_0 ;
  wire \cmd_pipe_plus.mc_address[38]_i_5_n_0 ;
  wire \cmd_pipe_plus.mc_address[38]_i_6_n_0 ;
  wire \cmd_pipe_plus.mc_address[39]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[40]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[41]_i_2_n_0 ;
  wire [16:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire \cmd_pipe_plus.mc_bank[6]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[7]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[8]_i_2_n_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_1 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_2 ;
  wire \cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ;
  wire cs_en2;
  wire \grant_r[0]_i_1__3_n_0 ;
  wire \grant_r[1]_i_1__2_n_0 ;
  wire \grant_r[2]_i_1__3_n_0 ;
  wire \grant_r[2]_i_2__2_n_0 ;
  wire \grant_r[3]_i_1__1_n_0 ;
  wire \grant_r[3]_i_4__2_n_0 ;
  wire \grant_r[3]_i_6__0_n_0 ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[0]_2 ;
  wire \grant_r_reg[1]_0 ;
  wire [13:0]\grant_r_reg[3]_0 ;
  wire [2:0]\grant_r_reg[3]_1 ;
  wire [3:0]last_master_r;
  wire \last_master_r[0]_i_1__2_n_0 ;
  wire \last_master_r[1]_i_1__2_n_0 ;
  wire \last_master_r[2]_i_1__3_n_0 ;
  wire \last_master_r[3]_i_1__2_n_0 ;
  wire \last_master_r_reg[0]_0 ;
  wire [0:0]mc_cas_n_ns;
  wire [38:0]req_row_r;
  wire [3:0]row_cmd_wr;

  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[28]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(req_row_r[27]),
        .I3(\cmd_pipe_plus.mc_address[28]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [0]),
        .O(\grant_r_reg[3]_0 [0]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[28]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[3]),
        .I2(Q[2]),
        .I3(req_row_r[15]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_address[28]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[29]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(req_row_r[28]),
        .I3(\cmd_pipe_plus.mc_address[29]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [1]),
        .O(\grant_r_reg[3]_0 [1]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[29]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[4]),
        .I2(Q[2]),
        .I3(req_row_r[16]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_address[29]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[30]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(req_row_r[29]),
        .I3(\cmd_pipe_plus.mc_address[30]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [2]),
        .O(\grant_r_reg[3]_0 [2]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[30]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[5]),
        .I2(Q[2]),
        .I3(req_row_r[17]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_address[30]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[31]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(req_row_r[30]),
        .I3(\cmd_pipe_plus.mc_address[31]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [3]),
        .O(\grant_r_reg[3]_0 [3]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[31]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[6]),
        .I2(Q[2]),
        .I3(req_row_r[18]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_address[31]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[32]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(req_row_r[31]),
        .I3(\cmd_pipe_plus.mc_address[32]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [4]),
        .O(\grant_r_reg[3]_0 [4]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[32]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[7]),
        .I2(Q[2]),
        .I3(req_row_r[19]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_address[32]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[33]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(req_row_r[32]),
        .I3(\cmd_pipe_plus.mc_address[33]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [5]),
        .O(\grant_r_reg[3]_0 [5]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[33]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[8]),
        .I2(Q[2]),
        .I3(req_row_r[20]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_address[33]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[34]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(req_row_r[33]),
        .I3(\cmd_pipe_plus.mc_address[34]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [6]),
        .O(\grant_r_reg[3]_0 [6]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[34]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[9]),
        .I2(Q[2]),
        .I3(req_row_r[21]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_address[34]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[35]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(req_row_r[34]),
        .I3(\cmd_pipe_plus.mc_address[35]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [7]),
        .O(\grant_r_reg[3]_0 [7]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[35]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[10]),
        .I2(Q[2]),
        .I3(req_row_r[22]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_address[35]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[36]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(req_row_r[35]),
        .I3(\cmd_pipe_plus.mc_address[36]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [8]),
        .O(\grant_r_reg[3]_0 [8]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[36]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[11]),
        .I2(Q[2]),
        .I3(req_row_r[23]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_address[36]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[37]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(req_row_r[36]),
        .I3(\cmd_pipe_plus.mc_address[37]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(req_row_r[0]),
        .O(\grant_r_reg[3]_0 [9]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[37]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[12]),
        .I2(Q[2]),
        .I3(req_row_r[24]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_address[37]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEA000000EAEAEAEA)) 
    \cmd_pipe_plus.mc_address[38]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[38]_i_2_n_0 ),
        .I1(req_row_r[13]),
        .I2(\cmd_pipe_plus.mc_address[38]_i_3_n_0 ),
        .I3(row_cmd_wr[3]),
        .I4(req_row_r[37]),
        .I5(\cmd_pipe_plus.mc_address[38]_i_4_n_0 ),
        .O(\grant_r_reg[3]_0 [10]));
  LUT6 #(
    .INIT(64'hFFFFFF4040404040)) 
    \cmd_pipe_plus.mc_address[38]_i_2 
       (.I0(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I1(row_cmd_wr[0]),
        .I2(req_row_r[1]),
        .I3(req_row_r[25]),
        .I4(\cmd_pipe_plus.mc_address[38]_i_5_n_0 ),
        .I5(\cmd_pipe_plus.mc_address[38]_i_6_n_0 ),
        .O(\cmd_pipe_plus.mc_address[38]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h08)) 
    \cmd_pipe_plus.mc_address[38]_i_3 
       (.I0(row_cmd_wr[1]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(\cmd_pipe_plus.mc_address[38]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair572" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \cmd_pipe_plus.mc_address[38]_i_4 
       (.I0(Q[3]),
        .I1(cs_en2),
        .O(\cmd_pipe_plus.mc_address[38]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair571" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \cmd_pipe_plus.mc_address[38]_i_5 
       (.I0(Q[3]),
        .I1(cs_en2),
        .O(\cmd_pipe_plus.mc_address[38]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'hFDDD)) 
    \cmd_pipe_plus.mc_address[38]_i_6 
       (.I0(cs_en2),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(row_cmd_wr[2]),
        .O(\cmd_pipe_plus.mc_address[38]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[39]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(req_row_r[38]),
        .I3(\cmd_pipe_plus.mc_address[39]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(req_row_r[2]),
        .O(\grant_r_reg[3]_0 [11]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[39]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[14]),
        .I2(Q[2]),
        .I3(req_row_r[26]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_address[39]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[40]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(\cmd_pipe_plus.mc_address_reg[41] [15]),
        .I3(\cmd_pipe_plus.mc_address[40]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [9]),
        .O(\grant_r_reg[3]_0 [12]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[40]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_address_reg[41] [11]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_address_reg[41] [13]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_address[40]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_address[41]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(\cmd_pipe_plus.mc_address_reg[41] [16]),
        .I3(\cmd_pipe_plus.mc_address[41]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[41] [10]),
        .O(\grant_r_reg[3]_0 [13]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_address[41]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_address_reg[41] [12]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_address_reg[41] [14]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_address[41]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_bank[6]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(\cmd_pipe_plus.mc_bank_reg[8] [0]),
        .I3(\cmd_pipe_plus.mc_bank[6]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_bank_reg[8]_0 [0]),
        .O(\grant_r_reg[3]_1 [0]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_bank[6]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_bank_reg[8]_1 [0]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_bank_reg[8]_2 [0]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_bank[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_bank[7]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(\cmd_pipe_plus.mc_bank_reg[8] [1]),
        .I3(\cmd_pipe_plus.mc_bank[7]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_bank_reg[8]_0 [1]),
        .O(\grant_r_reg[3]_1 [1]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_bank[7]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_bank_reg[8]_1 [1]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_bank_reg[8]_2 [1]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_bank[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_bank[8]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(\cmd_pipe_plus.mc_bank_reg[8] [2]),
        .I3(\cmd_pipe_plus.mc_bank[8]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_bank_reg[8]_0 [2]),
        .O(\grant_r_reg[3]_1 [2]));
  LUT6 #(
    .INIT(64'hFFFFF808FFFFFFFF)) 
    \cmd_pipe_plus.mc_bank[8]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_bank_reg[8]_1 [2]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_bank_reg[8]_2 [2]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_bank[8]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair569" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFD)) 
    \cmd_pipe_plus.mc_cas_n[2]_i_1 
       (.I0(cs_en2),
        .I1(Q[3]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[0]),
        .O(mc_cas_n_ns));
  LUT6 #(
    .INIT(64'hF700F7F7F700F700)) 
    \cmd_pipe_plus.mc_we_n[2]_i_1 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(row_cmd_wr[3]),
        .I3(\cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ),
        .I5(row_cmd_wr[0]),
        .O(D));
  LUT6 #(
    .INIT(64'hFFFFF088FFFFFFFF)) 
    \cmd_pipe_plus.mc_we_n[2]_i_2 
       (.I0(Q[1]),
        .I1(row_cmd_wr[1]),
        .I2(row_cmd_wr[2]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(cs_en2),
        .O(\cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair569" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \cmd_pipe_plus.mc_we_n[2]_i_3 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\cmd_pipe_plus.mc_we_n[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h020202AA00000000)) 
    \grant_r[0]_i_1__3 
       (.I0(\grant_r[2]_i_2__2_n_0 ),
        .I1(\last_master_r[0]_i_1__2_n_0 ),
        .I2(\last_master_r[1]_i_1__2_n_0 ),
        .I3(\grant_r_reg[0]_0 ),
        .I4(\grant_r_reg[0]_1 ),
        .I5(\grant_r_reg[0]_2 ),
        .O(\grant_r[0]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h020202AA00000000)) 
    \grant_r[1]_i_1__2 
       (.I0(\grant_r[3]_i_6__0_n_0 ),
        .I1(\last_master_r[1]_i_1__2_n_0 ),
        .I2(\last_master_r[2]_i_1__3_n_0 ),
        .I3(\grant_r_reg[0]_0 ),
        .I4(\grant_r_reg[0]_2 ),
        .I5(\grant_r_reg[1]_0 ),
        .O(\grant_r[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h202020AA00000000)) 
    \grant_r[2]_i_1__3 
       (.I0(\grant_r[2]_i_2__2_n_0 ),
        .I1(\last_master_r[2]_i_1__3_n_0 ),
        .I2(\grant_r[3]_i_4__2_n_0 ),
        .I3(\grant_r_reg[0]_2 ),
        .I4(\grant_r_reg[1]_0 ),
        .I5(\grant_r_reg[0]_1 ),
        .O(\grant_r[2]_i_1__3_n_0 ));
  LUT4 #(
    .INIT(16'h0777)) 
    \grant_r[2]_i_2__2 
       (.I0(\grant_r_reg[1]_0 ),
        .I1(\last_master_r[0]_i_1__2_n_0 ),
        .I2(\grant_r_reg[0]_0 ),
        .I3(\last_master_r[2]_i_1__3_n_0 ),
        .O(\grant_r[2]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h11F1000000000000)) 
    \grant_r[3]_i_1__1 
       (.I0(\grant_r_reg[0]_1 ),
        .I1(\grant_r_reg[1]_0 ),
        .I2(\grant_r[3]_i_4__2_n_0 ),
        .I3(\last_master_r[0]_i_1__2_n_0 ),
        .I4(\grant_r_reg[0]_0 ),
        .I5(\grant_r[3]_i_6__0_n_0 ),
        .O(\grant_r[3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair570" *) 
  LUT4 #(
    .INIT(16'h0151)) 
    \grant_r[3]_i_4__2 
       (.I0(\last_master_r_reg[0]_0 ),
        .I1(last_master_r[3]),
        .I2(cs_en2),
        .I3(Q[3]),
        .O(\grant_r[3]_i_4__2_n_0 ));
  LUT4 #(
    .INIT(16'h7077)) 
    \grant_r[3]_i_6__0 
       (.I0(\grant_r_reg[0]_1 ),
        .I1(\last_master_r[1]_i_1__2_n_0 ),
        .I2(\grant_r[3]_i_4__2_n_0 ),
        .I3(\grant_r_reg[0]_2 ),
        .O(\grant_r[3]_i_6__0_n_0 ));
  FDRE \grant_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[0]_i_1__3_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[1]_i_1__2_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[2]_i_1__3_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \grant_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[3]_i_1__1_n_0 ),
        .Q(Q[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[0]_i_1__2 
       (.I0(last_master_r[0]),
        .I1(cs_en2),
        .I2(Q[0]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair572" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[1]_i_1__2 
       (.I0(last_master_r[1]),
        .I1(cs_en2),
        .I2(Q[1]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair571" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[2]_i_1__3 
       (.I0(last_master_r[2]),
        .I1(cs_en2),
        .I2(Q[2]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[2]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair570" *) 
  LUT4 #(
    .INIT(16'hFFB8)) 
    \last_master_r[3]_i_1__2 
       (.I0(Q[3]),
        .I1(cs_en2),
        .I2(last_master_r[3]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[3]_i_1__2_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[0]_i_1__2_n_0 ),
        .Q(last_master_r[0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[1]_i_1__2_n_0 ),
        .Q(last_master_r[1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[2]_i_1__3_n_0 ),
        .Q(last_master_r[2]),
        .R(1'b0));
  FDRE \last_master_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[3]_i_1__2_n_0 ),
        .Q(last_master_r[3]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_round_robin_arb" *) 
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_round_robin_arb__parameterized1_5
   (Q,
    granted_row_ns,
    \req_row_r_lcl_reg[13] ,
    \req_bank_r_lcl_reg[2] ,
    I118,
    mc_cas_n_ns,
    mc_ras_n_ns,
    D,
    act_this_rank,
    \grant_r_reg[0]_0 ,
    demand_act_priority_r,
    granted_row_r_reg,
    granted_row_r_reg_0,
    demand_act_priority_r_5,
    \grant_r_reg[3]_0 ,
    \grant_r_reg[3]_1 ,
    demand_act_priority_r_6,
    \grant_r_reg[3]_2 ,
    \grant_r_reg[3]_3 ,
    demand_act_priority_r_8,
    \grant_r_reg[3]_4 ,
    \grant_r_reg[3]_5 ,
    req_row_r,
    \cmd_pipe_plus.mc_address_reg[13] ,
    \cmd_pipe_plus.mc_address_reg[10] ,
    row_cmd_wr,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    \cmd_pipe_plus.mc_bank_reg[2]_0 ,
    \cmd_pipe_plus.mc_bank_reg[2]_1 ,
    \cmd_pipe_plus.mc_bank_reg[2]_2 ,
    maint_rank_r,
    \cmd_pipe_plus.mc_cas_n_reg[0] ,
    \cmd_pipe_plus.mc_ras_n_reg[0] ,
    sent_row,
    maint_srx_r,
    maint_zq_r,
    \cmd_pipe_plus.mc_we_n_reg[0] ,
    \grant_r[2]_i_3__0_0 ,
    inhbt_act_faw_r,
    \last_master_r_reg[0]_0 ,
    act_this_rank_r,
    CLK);
  output [3:0]Q;
  output granted_row_ns;
  output [13:0]\req_row_r_lcl_reg[13] ;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [0:0]I118;
  output [0:0]mc_cas_n_ns;
  output [0:0]mc_ras_n_ns;
  output [0:0]D;
  output act_this_rank;
  output \grant_r_reg[0]_0 ;
  input demand_act_priority_r;
  input granted_row_r_reg;
  input granted_row_r_reg_0;
  input demand_act_priority_r_5;
  input \grant_r_reg[3]_0 ;
  input \grant_r_reg[3]_1 ;
  input demand_act_priority_r_6;
  input \grant_r_reg[3]_2 ;
  input \grant_r_reg[3]_3 ;
  input demand_act_priority_r_8;
  input \grant_r_reg[3]_4 ;
  input \grant_r_reg[3]_5 ;
  input [36:0]req_row_r;
  input [16:0]\cmd_pipe_plus.mc_address_reg[13] ;
  input \cmd_pipe_plus.mc_address_reg[10] ;
  input [3:0]row_cmd_wr;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_2 ;
  input maint_rank_r;
  input \cmd_pipe_plus.mc_cas_n_reg[0] ;
  input \cmd_pipe_plus.mc_ras_n_reg[0] ;
  input sent_row;
  input maint_srx_r;
  input maint_zq_r;
  input \cmd_pipe_plus.mc_we_n_reg[0] ;
  input \grant_r[2]_i_3__0_0 ;
  input inhbt_act_faw_r;
  input \last_master_r_reg[0]_0 ;
  input [3:0]act_this_rank_r;
  input CLK;

  wire CLK;
  wire [0:0]D;
  wire [0:0]I118;
  wire [3:0]Q;
  wire act_this_rank;
  wire [3:0]act_this_rank_r;
  wire \cmd_pipe_plus.mc_address[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[10]_i_3_n_0 ;
  wire \cmd_pipe_plus.mc_address[11]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[12]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[13]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[13]_i_3_n_0 ;
  wire \cmd_pipe_plus.mc_address[1]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[2]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[3]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[4]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[5]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[6]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[7]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[8]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[9]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address_reg[10] ;
  wire [16:0]\cmd_pipe_plus.mc_address_reg[13] ;
  wire \cmd_pipe_plus.mc_bank[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[1]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[2]_i_2_n_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_2 ;
  wire \cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_cas_n_reg[0] ;
  wire \cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_ras_n_reg[0] ;
  wire \cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_we_n[0]_i_3_n_0 ;
  wire \cmd_pipe_plus.mc_we_n[0]_i_4_n_0 ;
  wire \cmd_pipe_plus.mc_we_n_reg[0] ;
  wire demand_act_priority_r;
  wire demand_act_priority_r_5;
  wire demand_act_priority_r_6;
  wire demand_act_priority_r_8;
  wire \grant_r[0]_i_1__2_n_0 ;
  wire \grant_r[1]_i_1__3_n_0 ;
  wire \grant_r[2]_i_1__2_n_0 ;
  wire \grant_r[2]_i_2__1_n_0 ;
  wire \grant_r[2]_i_3__0_0 ;
  wire \grant_r[2]_i_3__0_n_0 ;
  wire \grant_r[2]_i_4__1_n_0 ;
  wire \grant_r[3]_i_10__0_n_0 ;
  wire \grant_r[3]_i_11__0_n_0 ;
  wire \grant_r[3]_i_13__0_n_0 ;
  wire \grant_r[3]_i_1__2_n_0 ;
  wire \grant_r[3]_i_2__1_n_0 ;
  wire \grant_r[3]_i_3__1_n_0 ;
  wire \grant_r[3]_i_4__1_n_0 ;
  wire \grant_r[3]_i_5__1_n_0 ;
  wire \grant_r[3]_i_6__2_n_0 ;
  wire \grant_r[3]_i_9__0_n_0 ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[3]_0 ;
  wire \grant_r_reg[3]_1 ;
  wire \grant_r_reg[3]_2 ;
  wire \grant_r_reg[3]_3 ;
  wire \grant_r_reg[3]_4 ;
  wire \grant_r_reg[3]_5 ;
  wire granted_row_ns;
  wire granted_row_r_reg;
  wire granted_row_r_reg_0;
  wire \inhbt_act_faw.SRLC32E0_i_3_n_0 ;
  wire inhbt_act_faw_r;
  wire [3:0]last_master_r;
  wire \last_master_r[0]_i_1__1_n_0 ;
  wire \last_master_r[1]_i_1__1_n_0 ;
  wire \last_master_r[2]_i_1__2_n_0 ;
  wire \last_master_r[3]_i_1__1_n_0 ;
  wire \last_master_r_reg[0]_0 ;
  wire maint_rank_r;
  wire maint_srx_r;
  wire maint_zq_r;
  wire [0:0]mc_cas_n_ns;
  wire [0:0]mc_ras_n_ns;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [36:0]req_row_r;
  wire [13:0]\req_row_r_lcl_reg[13] ;
  wire [3:0]row_cmd_wr;
  wire sent_row;

  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_address[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[0]_i_2_n_0 ),
        .I1(req_row_r[3]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_address_reg[13] [0]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [0]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_address[0]_i_2 
       (.I0(req_row_r[14]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(req_row_r[26]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_address[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hE0000000EEEEEEEE)) 
    \cmd_pipe_plus.mc_address[10]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[10] ),
        .I1(\cmd_pipe_plus.mc_address[10]_i_3_n_0 ),
        .I2(Q[0]),
        .I3(req_row_r[1]),
        .I4(row_cmd_wr[0]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [10]));
  LUT5 #(
    .INIT(32'h55D55555)) 
    \cmd_pipe_plus.mc_address[10]_i_3 
       (.I0(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .I1(Q[2]),
        .I2(row_cmd_wr[2]),
        .I3(Q[3]),
        .I4(req_row_r[24]),
        .O(\cmd_pipe_plus.mc_address[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_address[11]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[11]_i_2_n_0 ),
        .I1(req_row_r[13]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(req_row_r[2]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [11]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_address[11]_i_2 
       (.I0(req_row_r[25]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(req_row_r[36]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_address[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_address[12]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[12]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[13] [11]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_address_reg[13] [9]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [12]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_address[12]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [13]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_address_reg[13] [15]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_address[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_address[13]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[13]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[13] [12]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_address_reg[13] [10]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [13]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_address[13]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [14]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_address_reg[13] [16]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_address[13]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair575" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \cmd_pipe_plus.mc_address[13]_i_3 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(Q[1]),
        .O(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_address[1]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[1]_i_2_n_0 ),
        .I1(req_row_r[4]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_address_reg[13] [1]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [1]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_address[1]_i_2 
       (.I0(req_row_r[15]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(req_row_r[27]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_address[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_address[2]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[2]_i_2_n_0 ),
        .I1(req_row_r[5]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_address_reg[13] [2]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [2]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_address[2]_i_2 
       (.I0(req_row_r[16]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(req_row_r[28]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_address[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_address[3]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[3]_i_2_n_0 ),
        .I1(req_row_r[6]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_address_reg[13] [3]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [3]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_address[3]_i_2 
       (.I0(req_row_r[17]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(req_row_r[29]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_address[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_address[4]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[4]_i_2_n_0 ),
        .I1(req_row_r[7]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_address_reg[13] [4]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [4]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_address[4]_i_2 
       (.I0(req_row_r[18]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(req_row_r[30]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_address[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_address[5]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[5]_i_2_n_0 ),
        .I1(req_row_r[8]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_address_reg[13] [5]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [5]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_address[5]_i_2 
       (.I0(req_row_r[19]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(req_row_r[31]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_address[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_address[6]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[6]_i_2_n_0 ),
        .I1(req_row_r[9]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_address_reg[13] [6]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [6]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_address[6]_i_2 
       (.I0(req_row_r[20]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(req_row_r[32]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_address[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_address[7]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[7]_i_2_n_0 ),
        .I1(req_row_r[10]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_address_reg[13] [7]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [7]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_address[7]_i_2 
       (.I0(req_row_r[21]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(req_row_r[33]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_address[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_address[8]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[8]_i_2_n_0 ),
        .I1(req_row_r[11]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_address_reg[13] [8]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [8]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_address[8]_i_2 
       (.I0(req_row_r[22]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(req_row_r[34]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_address[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_address[9]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[9]_i_2_n_0 ),
        .I1(req_row_r[12]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(req_row_r[0]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_row_r_lcl_reg[13] [9]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_address[9]_i_2 
       (.I0(req_row_r[23]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(req_row_r[35]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_address[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_bank[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[0]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_bank_reg[2] [0]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_bank_reg[2]_0 [0]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_bank_r_lcl_reg[2] [0]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_bank[0]_i_2 
       (.I0(\cmd_pipe_plus.mc_bank_reg[2]_1 [0]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_bank_reg[2]_2 [0]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_bank[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_bank[1]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[1]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_bank_reg[2] [1]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_bank_reg[2]_0 [1]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_bank_r_lcl_reg[2] [1]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_bank[1]_i_2 
       (.I0(\cmd_pipe_plus.mc_bank_reg[2]_1 [1]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_bank_reg[2]_2 [1]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_bank[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAE000000AEAEAEAE)) 
    \cmd_pipe_plus.mc_bank[2]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[2]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_bank_reg[2] [2]),
        .I2(\cmd_pipe_plus.mc_address[13]_i_3_n_0 ),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_bank_reg[2]_0 [2]),
        .I5(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .O(\req_bank_r_lcl_reg[2] [2]));
  LUT5 #(
    .INIT(32'hF808FFFF)) 
    \cmd_pipe_plus.mc_bank[2]_i_2 
       (.I0(\cmd_pipe_plus.mc_bank_reg[2]_1 [2]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_bank_reg[2]_2 [2]),
        .I4(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(\cmd_pipe_plus.mc_bank[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF55FF55FFFDFF55)) 
    \cmd_pipe_plus.mc_cas_n[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ),
        .I1(maint_srx_r),
        .I2(maint_zq_r),
        .I3(Q[0]),
        .I4(\cmd_pipe_plus.mc_ras_n_reg[0] ),
        .I5(\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .O(mc_cas_n_ns));
  (* SOFT_HLUTNM = "soft_lutpair573" *) 
  LUT5 #(
    .INIT(32'h01010100)) 
    \cmd_pipe_plus.mc_cas_n[0]_i_2 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(sent_row),
        .I4(\cmd_pipe_plus.mc_ras_n_reg[0] ),
        .O(\cmd_pipe_plus.mc_cas_n[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000200F2F)) 
    \cmd_pipe_plus.mc_cs_n[0]_i_1 
       (.I0(maint_rank_r),
        .I1(\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .I2(\cmd_pipe_plus.mc_ras_n_reg[0] ),
        .I3(Q[0]),
        .I4(sent_row),
        .I5(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ),
        .O(I118));
  (* SOFT_HLUTNM = "soft_lutpair573" *) 
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \cmd_pipe_plus.mc_cs_n[0]_i_2 
       (.I0(sent_row),
        .I1(\cmd_pipe_plus.mc_ras_n_reg[0] ),
        .I2(Q[3]),
        .I3(Q[2]),
        .I4(Q[1]),
        .O(\cmd_pipe_plus.mc_cs_n[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h11111111111111F1)) 
    \cmd_pipe_plus.mc_ras_n[0]_i_1 
       (.I0(sent_row),
        .I1(\cmd_pipe_plus.mc_ras_n_reg[0] ),
        .I2(\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(Q[3]),
        .O(mc_ras_n_ns));
  (* SOFT_HLUTNM = "soft_lutpair574" *) 
  LUT5 #(
    .INIT(32'h04040400)) 
    \cmd_pipe_plus.mc_ras_n[0]_i_2 
       (.I0(\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .I1(\cmd_pipe_plus.mc_ras_n_reg[0] ),
        .I2(Q[0]),
        .I3(maint_zq_r),
        .I4(maint_srx_r),
        .O(\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF2220000)) 
    \cmd_pipe_plus.mc_we_n[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ),
        .I1(maint_zq_r),
        .I2(Q[0]),
        .I3(row_cmd_wr[0]),
        .I4(\cmd_pipe_plus.mc_we_n[0]_i_3_n_0 ),
        .I5(\cmd_pipe_plus.mc_we_n[0]_i_4_n_0 ),
        .O(D));
  (* SOFT_HLUTNM = "soft_lutpair574" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \cmd_pipe_plus.mc_we_n[0]_i_2 
       (.I0(Q[0]),
        .I1(\cmd_pipe_plus.mc_ras_n_reg[0] ),
        .I2(\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .O(\cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \cmd_pipe_plus.mc_we_n[0]_i_3 
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[3]),
        .O(\cmd_pipe_plus.mc_we_n[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFCFFECEFCCCFECE)) 
    \cmd_pipe_plus.mc_we_n[0]_i_4 
       (.I0(granted_row_r_reg),
        .I1(\cmd_pipe_plus.mc_we_n_reg[0] ),
        .I2(Q[3]),
        .I3(row_cmd_wr[3]),
        .I4(Q[2]),
        .I5(row_cmd_wr[2]),
        .O(\cmd_pipe_plus.mc_we_n[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000002AA0202)) 
    \grant_r[0]_i_1__2 
       (.I0(\grant_r[2]_i_2__1_n_0 ),
        .I1(\last_master_r[0]_i_1__1_n_0 ),
        .I2(\last_master_r[1]_i_1__1_n_0 ),
        .I3(\grant_r[3]_i_5__1_n_0 ),
        .I4(\grant_r[3]_i_3__1_n_0 ),
        .I5(\grant_r[2]_i_3__0_n_0 ),
        .O(\grant_r[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h202020F000000000)) 
    \grant_r[1]_i_1__3 
       (.I0(\grant_r[2]_i_3__0_n_0 ),
        .I1(\grant_r[3]_i_5__1_n_0 ),
        .I2(\grant_r[3]_i_4__1_n_0 ),
        .I3(\last_master_r[1]_i_1__1_n_0 ),
        .I4(\last_master_r[2]_i_1__2_n_0 ),
        .I5(\grant_r[3]_i_2__1_n_0 ),
        .O(\grant_r[1]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000002AA0202)) 
    \grant_r[2]_i_1__2 
       (.I0(\grant_r[2]_i_2__1_n_0 ),
        .I1(\last_master_r[2]_i_1__2_n_0 ),
        .I2(\last_master_r[3]_i_1__1_n_0 ),
        .I3(\grant_r[3]_i_2__1_n_0 ),
        .I4(\grant_r[2]_i_3__0_n_0 ),
        .I5(\grant_r[3]_i_3__1_n_0 ),
        .O(\grant_r[2]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0777)) 
    \grant_r[2]_i_2__1 
       (.I0(\grant_r[3]_i_5__1_n_0 ),
        .I1(\last_master_r[2]_i_1__2_n_0 ),
        .I2(\grant_r[3]_i_2__1_n_0 ),
        .I3(\last_master_r[0]_i_1__1_n_0 ),
        .O(\grant_r[2]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF4)) 
    \grant_r[2]_i_3__0 
       (.I0(demand_act_priority_r),
        .I1(\grant_r[2]_i_4__1_n_0 ),
        .I2(\grant_r[3]_i_9__0_n_0 ),
        .I3(granted_row_r_reg),
        .I4(Q[0]),
        .I5(granted_row_r_reg_0),
        .O(\grant_r[2]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h44F444F4FFFF44F4)) 
    \grant_r[2]_i_4__1 
       (.I0(Q[3]),
        .I1(demand_act_priority_r_8),
        .I2(demand_act_priority_r_6),
        .I3(Q[2]),
        .I4(demand_act_priority_r_5),
        .I5(Q[1]),
        .O(\grant_r[2]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'hDD0D0000DD0DDD0D)) 
    \grant_r[3]_i_10__0 
       (.I0(demand_act_priority_r_8),
        .I1(Q[3]),
        .I2(demand_act_priority_r),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(demand_act_priority_r_5),
        .O(\grant_r[3]_i_10__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFF8FFF8FFF8)) 
    \grant_r[3]_i_11__0 
       (.I0(Q[0]),
        .I1(row_cmd_wr[0]),
        .I2(\grant_r[2]_i_3__0_0 ),
        .I3(inhbt_act_faw_r),
        .I4(row_cmd_wr[1]),
        .I5(Q[1]),
        .O(\grant_r[3]_i_11__0_n_0 ));
  LUT6 #(
    .INIT(64'hBB0BBB0B0000BB0B)) 
    \grant_r[3]_i_13__0 
       (.I0(Q[0]),
        .I1(demand_act_priority_r),
        .I2(demand_act_priority_r_6),
        .I3(Q[2]),
        .I4(demand_act_priority_r_5),
        .I5(Q[1]),
        .O(\grant_r[3]_i_13__0_n_0 ));
  LUT6 #(
    .INIT(64'h400040004000F000)) 
    \grant_r[3]_i_1__2 
       (.I0(\grant_r[3]_i_2__1_n_0 ),
        .I1(\grant_r[3]_i_3__1_n_0 ),
        .I2(\grant_r[3]_i_4__1_n_0 ),
        .I3(\grant_r[3]_i_5__1_n_0 ),
        .I4(\last_master_r[0]_i_1__1_n_0 ),
        .I5(\last_master_r[3]_i_1__1_n_0 ),
        .O(\grant_r[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000000E)) 
    \grant_r[3]_i_2__1 
       (.I0(\grant_r[3]_i_6__2_n_0 ),
        .I1(demand_act_priority_r_5),
        .I2(\grant_r_reg[3]_0 ),
        .I3(\grant_r_reg[3]_1 ),
        .I4(Q[1]),
        .I5(\grant_r[3]_i_9__0_n_0 ),
        .O(\grant_r[3]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF1)) 
    \grant_r[3]_i_3__1 
       (.I0(\grant_r[3]_i_10__0_n_0 ),
        .I1(demand_act_priority_r_6),
        .I2(\grant_r[3]_i_11__0_n_0 ),
        .I3(\grant_r_reg[3]_2 ),
        .I4(Q[2]),
        .I5(\grant_r_reg[3]_3 ),
        .O(\grant_r[3]_i_3__1_n_0 ));
  LUT4 #(
    .INIT(16'hD0DD)) 
    \grant_r[3]_i_4__1 
       (.I0(\last_master_r[1]_i_1__1_n_0 ),
        .I1(\grant_r[3]_i_3__1_n_0 ),
        .I2(\grant_r[2]_i_3__0_n_0 ),
        .I3(\last_master_r[3]_i_1__1_n_0 ),
        .O(\grant_r[3]_i_4__1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000000E)) 
    \grant_r[3]_i_5__1 
       (.I0(\grant_r[3]_i_13__0_n_0 ),
        .I1(demand_act_priority_r_8),
        .I2(\grant_r_reg[3]_4 ),
        .I3(\grant_r_reg[3]_5 ),
        .I4(Q[3]),
        .I5(\grant_r[3]_i_11__0_n_0 ),
        .O(\grant_r[3]_i_5__1_n_0 ));
  LUT6 #(
    .INIT(64'hDD0D0000DD0DDD0D)) 
    \grant_r[3]_i_6__2 
       (.I0(demand_act_priority_r_8),
        .I1(Q[3]),
        .I2(demand_act_priority_r),
        .I3(Q[0]),
        .I4(Q[2]),
        .I5(demand_act_priority_r_6),
        .O(\grant_r[3]_i_6__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFF8FFF8FFF8)) 
    \grant_r[3]_i_9__0 
       (.I0(Q[2]),
        .I1(row_cmd_wr[2]),
        .I2(\grant_r[2]_i_3__0_0 ),
        .I3(inhbt_act_faw_r),
        .I4(row_cmd_wr[3]),
        .I5(Q[3]),
        .O(\grant_r[3]_i_9__0_n_0 ));
  FDRE \grant_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[0]_i_1__2_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[1]_i_1__3_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[2]_i_1__2_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \grant_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\grant_r[3]_i_1__2_n_0 ),
        .Q(Q[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFBF)) 
    granted_row_r_i_1
       (.I0(\grant_r[3]_i_2__1_n_0 ),
        .I1(\grant_r[3]_i_3__1_n_0 ),
        .I2(\grant_r[2]_i_3__0_n_0 ),
        .I3(\grant_r[3]_i_5__1_n_0 ),
        .O(granted_row_ns));
  LUT1 #(
    .INIT(2'h1)) 
    \inhbt_act_faw.SRLC32E0_i_1 
       (.I0(\grant_r_reg[0]_0 ),
        .O(act_this_rank));
  LUT5 #(
    .INIT(32'h00000777)) 
    \inhbt_act_faw.SRLC32E0_i_2 
       (.I0(Q[0]),
        .I1(act_this_rank_r[0]),
        .I2(Q[3]),
        .I3(act_this_rank_r[3]),
        .I4(\inhbt_act_faw.SRLC32E0_i_3_n_0 ),
        .O(\grant_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair575" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    \inhbt_act_faw.SRLC32E0_i_3 
       (.I0(act_this_rank_r[1]),
        .I1(Q[1]),
        .I2(act_this_rank_r[2]),
        .I3(Q[2]),
        .O(\inhbt_act_faw.SRLC32E0_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[0]_i_1__1 
       (.I0(last_master_r[0]),
        .I1(sent_row),
        .I2(Q[0]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[0]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[1]_i_1__1 
       (.I0(last_master_r[1]),
        .I1(sent_row),
        .I2(Q[1]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[1]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[2]_i_1__2 
       (.I0(last_master_r[2]),
        .I1(sent_row),
        .I2(Q[2]),
        .I3(\last_master_r_reg[0]_0 ),
        .O(\last_master_r[2]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'hFEAE)) 
    \last_master_r[3]_i_1__1 
       (.I0(\last_master_r_reg[0]_0 ),
        .I1(last_master_r[3]),
        .I2(sent_row),
        .I3(Q[3]),
        .O(\last_master_r[3]_i_1__1_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[0]_i_1__1_n_0 ),
        .Q(last_master_r[0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[1]_i_1__1_n_0 ),
        .Q(last_master_r[1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[2]_i_1__2_n_0 ),
        .Q(last_master_r[2]),
        .R(1'b0));
  FDRE \last_master_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\last_master_r[3]_i_1__1_n_0 ),
        .Q(last_master_r[3]),
        .R(1'b0));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_tempmon
   (out,
    D,
    clk_ref_i,
    in0,
    \device_temp_r_reg[11]_0 );
  output [11:0]out;
  output [11:0]D;
  input clk_ref_i;
  input in0;
  input \device_temp_r_reg[11]_0 ;

  wire [11:0]D;
  wire \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ;
  wire \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ;
  wire \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ;
  wire clk_ref_i;
  wire \device_temp_101[11]_i_2_n_0 ;
  wire \device_temp_101[11]_i_4_n_0 ;
  wire \device_temp_101[11]_i_5_n_0 ;
  wire [11:0]device_temp_lcl;
  (* async_reg = "true" *) wire [11:0]device_temp_r;
  wire \device_temp_r[11]_i_1_n_0 ;
  wire \device_temp_r_reg[11]_0 ;
  (* async_reg = "true" *) wire [11:0]device_temp_sync_r1;
  (* async_reg = "true" *) wire [11:0]device_temp_sync_r2;
  (* async_reg = "true" *) (* syn_srlstyle = "registers" *) wire [11:0]device_temp_sync_r3;
  (* async_reg = "true" *) wire [11:0]device_temp_sync_r4;
  wire device_temp_sync_r4_neq_r3;
  wire device_temp_sync_r4_neq_r3_i_2_n_0;
  wire device_temp_sync_r4_neq_r3_i_3_n_0;
  wire device_temp_sync_r4_neq_r3_i_4_n_0;
  wire device_temp_sync_r4_neq_r3_i_5_n_0;
  wire device_temp_sync_r4_neq_r3_reg_i_1_n_0;
  wire device_temp_sync_r4_neq_r3_reg_i_1_n_1;
  wire device_temp_sync_r4_neq_r3_reg_i_1_n_2;
  wire device_temp_sync_r4_neq_r3_reg_i_1_n_3;
  (* async_reg = "true" *) wire [11:0]device_temp_sync_r5;
  wire in0;
  wire [11:0]p_0_in;
  wire [10:0]p_0_in__0;
  wire [3:0]p_0_in__1;
  wire sync_cntr0__4;
  wire \sync_cntr[2]_i_1_n_0 ;
  wire \sync_cntr[3]_i_2_n_0 ;
  wire [3:0]sync_cntr_reg;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ;
  (* async_reg = "true" *) wire \xadc_supplied_temperature.rst_r1 ;
  (* async_reg = "true" *) wire \xadc_supplied_temperature.rst_r2 ;
  wire \xadc_supplied_temperature.sample_en ;
  wire \xadc_supplied_temperature.sample_en_i_1_n_0 ;
  wire \xadc_supplied_temperature.sample_en_i_2_n_0 ;
  wire \xadc_supplied_temperature.sample_timer0__20 ;
  wire \xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ;
  wire \xadc_supplied_temperature.sample_timer_clr ;
  wire \xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ;
  wire \xadc_supplied_temperature.sample_timer_en ;
  wire \xadc_supplied_temperature.sample_timer_en_i_1_n_0 ;
  wire [10:0]\xadc_supplied_temperature.sample_timer_reg ;
  wire \xadc_supplied_temperature.temperature ;
  wire \xadc_supplied_temperature.xadc_den ;
  wire [15:0]\xadc_supplied_temperature.xadc_do ;
  wire \xadc_supplied_temperature.xadc_drdy ;
  wire \xadc_supplied_temperature.xadc_drdy_r ;
  wire [3:0]NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED;
  wire \NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ;
  wire [7:0]\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED ;
  wire [4:0]\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED ;
  wire [4:0]\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED ;

  assign out[11:0] = device_temp_r;
  LUT6 #(
    .INIT(64'hFFFFFEEEFEEEFEEE)) 
    \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1 
       (.I0(\xadc_supplied_temperature.temperature ),
        .I1(\xadc_supplied_temperature.sample_timer_clr ),
        .I2(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .I3(\xadc_supplied_temperature.sample_en ),
        .I4(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),
        .I5(\xadc_supplied_temperature.xadc_drdy_r ),
        .O(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ));
  (* FSM_ENCODED_STATES = "INIT_IDLE:0001,REQUEST_READ_TEMP:1000,WAIT_FOR_READ:0100,READ:0010," *) 
  FDSE #(
    .INIT(1'b1)) 
    \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[0] 
       (.C(clk_ref_i),
        .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),
        .D(\xadc_supplied_temperature.temperature ),
        .Q(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .S(\xadc_supplied_temperature.rst_r2 ));
  (* FSM_ENCODED_STATES = "INIT_IDLE:0001,REQUEST_READ_TEMP:1000,WAIT_FOR_READ:0100,READ:0010," *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1] 
       (.C(clk_ref_i),
        .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),
        .D(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),
        .Q(\xadc_supplied_temperature.temperature ),
        .R(\xadc_supplied_temperature.rst_r2 ));
  (* FSM_ENCODED_STATES = "INIT_IDLE:0001,REQUEST_READ_TEMP:1000,WAIT_FOR_READ:0100,READ:0010," *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[2] 
       (.C(clk_ref_i),
        .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),
        .D(\xadc_supplied_temperature.sample_timer_clr ),
        .Q(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),
        .R(\xadc_supplied_temperature.rst_r2 ));
  (* FSM_ENCODED_STATES = "INIT_IDLE:0001,REQUEST_READ_TEMP:1000,WAIT_FOR_READ:0100,READ:0010," *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[3] 
       (.C(clk_ref_i),
        .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),
        .D(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .Q(\xadc_supplied_temperature.sample_timer_clr ),
        .R(\xadc_supplied_temperature.rst_r2 ));
  LUT4 #(
    .INIT(16'h0700)) 
    \device_temp_101[0]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[0]),
        .O(D[0]));
  LUT3 #(
    .INIT(8'h8A)) 
    \device_temp_101[10]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .O(D[10]));
  LUT4 #(
    .INIT(16'hFFF8)) 
    \device_temp_101[11]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[11]),
        .O(D[11]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAA88888)) 
    \device_temp_101[11]_i_2 
       (.I0(device_temp_r[11]),
        .I1(device_temp_r[9]),
        .I2(device_temp_r[6]),
        .I3(\device_temp_101[11]_i_4_n_0 ),
        .I4(device_temp_r[7]),
        .I5(device_temp_r[8]),
        .O(\device_temp_101[11]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0100FFFF)) 
    \device_temp_101[11]_i_3 
       (.I0(device_temp_r[8]),
        .I1(device_temp_r[10]),
        .I2(device_temp_r[9]),
        .I3(\device_temp_101[11]_i_5_n_0 ),
        .I4(device_temp_r[11]),
        .O(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAA88888)) 
    \device_temp_101[11]_i_4 
       (.I0(device_temp_r[5]),
        .I1(device_temp_r[4]),
        .I2(device_temp_r[1]),
        .I3(device_temp_r[0]),
        .I4(device_temp_r[2]),
        .I5(device_temp_r[3]),
        .O(\device_temp_101[11]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00155555FFFFFFFF)) 
    \device_temp_101[11]_i_5 
       (.I0(device_temp_r[6]),
        .I1(device_temp_r[2]),
        .I2(device_temp_r[3]),
        .I3(device_temp_r[4]),
        .I4(device_temp_r[5]),
        .I5(device_temp_r[7]),
        .O(\device_temp_101[11]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h0700)) 
    \device_temp_101[1]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[1]),
        .O(D[1]));
  LUT4 #(
    .INIT(16'hFFF8)) 
    \device_temp_101[2]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[2]),
        .O(D[2]));
  LUT4 #(
    .INIT(16'hF7F0)) 
    \device_temp_101[3]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[3]),
        .O(D[3]));
  LUT4 #(
    .INIT(16'h0700)) 
    \device_temp_101[4]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[4]),
        .O(D[4]));
  LUT4 #(
    .INIT(16'hFFF8)) 
    \device_temp_101[5]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[5]),
        .O(D[5]));
  LUT4 #(
    .INIT(16'h0700)) 
    \device_temp_101[6]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[6]),
        .O(D[6]));
  LUT4 #(
    .INIT(16'hFFF8)) 
    \device_temp_101[7]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[7]),
        .O(D[7]));
  LUT4 #(
    .INIT(16'h0700)) 
    \device_temp_101[8]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[8]),
        .O(D[8]));
  LUT4 #(
    .INIT(16'h0700)) 
    \device_temp_101[9]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[9]),
        .O(D[9]));
  LUT4 #(
    .INIT(16'h8000)) 
    \device_temp_r[11]_i_1 
       (.I0(sync_cntr_reg[1]),
        .I1(sync_cntr_reg[0]),
        .I2(sync_cntr_reg[3]),
        .I3(sync_cntr_reg[2]),
        .O(\device_temp_r[11]_i_1_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[0] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[0]),
        .Q(device_temp_r[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[10] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[10]),
        .Q(device_temp_r[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[11] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[11]),
        .Q(device_temp_r[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[1] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[1]),
        .Q(device_temp_r[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[2] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[2]),
        .Q(device_temp_r[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[3] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[3]),
        .Q(device_temp_r[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[4] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[4]),
        .Q(device_temp_r[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[5] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[5]),
        .Q(device_temp_r[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[6] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[6]),
        .Q(device_temp_r[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[7] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[7]),
        .Q(device_temp_r[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[8] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[8]),
        .Q(device_temp_r[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[9] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[9]),
        .Q(device_temp_r[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[0] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[0]),
        .Q(device_temp_sync_r1[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[10] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[10]),
        .Q(device_temp_sync_r1[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[11] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[11]),
        .Q(device_temp_sync_r1[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[1] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[1]),
        .Q(device_temp_sync_r1[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[2] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[2]),
        .Q(device_temp_sync_r1[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[3] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[3]),
        .Q(device_temp_sync_r1[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[4] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[4]),
        .Q(device_temp_sync_r1[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[5] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[5]),
        .Q(device_temp_sync_r1[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[6] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[6]),
        .Q(device_temp_sync_r1[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[7] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[7]),
        .Q(device_temp_sync_r1[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[8] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[8]),
        .Q(device_temp_sync_r1[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[9] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[9]),
        .Q(device_temp_sync_r1[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[0] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[0]),
        .Q(device_temp_sync_r2[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[10] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[10]),
        .Q(device_temp_sync_r2[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[11] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[11]),
        .Q(device_temp_sync_r2[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[1] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[1]),
        .Q(device_temp_sync_r2[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[2] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[2]),
        .Q(device_temp_sync_r2[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[3] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[3]),
        .Q(device_temp_sync_r2[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[4] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[4]),
        .Q(device_temp_sync_r2[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[5] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[5]),
        .Q(device_temp_sync_r2[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[6] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[6]),
        .Q(device_temp_sync_r2[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[7] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[7]),
        .Q(device_temp_sync_r2[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[8] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[8]),
        .Q(device_temp_sync_r2[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[9] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[9]),
        .Q(device_temp_sync_r2[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[0] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[0]),
        .Q(device_temp_sync_r3[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[10] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[10]),
        .Q(device_temp_sync_r3[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[11] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[11]),
        .Q(device_temp_sync_r3[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[1] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[1]),
        .Q(device_temp_sync_r3[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[2] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[2]),
        .Q(device_temp_sync_r3[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[3] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[3]),
        .Q(device_temp_sync_r3[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[4] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[4]),
        .Q(device_temp_sync_r3[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[5] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[5]),
        .Q(device_temp_sync_r3[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[6] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[6]),
        .Q(device_temp_sync_r3[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[7] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[7]),
        .Q(device_temp_sync_r3[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[8] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[8]),
        .Q(device_temp_sync_r3[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[9] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[9]),
        .Q(device_temp_sync_r3[9]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    device_temp_sync_r4_neq_r3_i_2
       (.I0(device_temp_sync_r4[9]),
        .I1(device_temp_sync_r3[9]),
        .I2(device_temp_sync_r3[11]),
        .I3(device_temp_sync_r4[11]),
        .I4(device_temp_sync_r3[10]),
        .I5(device_temp_sync_r4[10]),
        .O(device_temp_sync_r4_neq_r3_i_2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    device_temp_sync_r4_neq_r3_i_3
       (.I0(device_temp_sync_r4[6]),
        .I1(device_temp_sync_r3[6]),
        .I2(device_temp_sync_r3[8]),
        .I3(device_temp_sync_r4[8]),
        .I4(device_temp_sync_r3[7]),
        .I5(device_temp_sync_r4[7]),
        .O(device_temp_sync_r4_neq_r3_i_3_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    device_temp_sync_r4_neq_r3_i_4
       (.I0(device_temp_sync_r4[3]),
        .I1(device_temp_sync_r3[3]),
        .I2(device_temp_sync_r3[5]),
        .I3(device_temp_sync_r4[5]),
        .I4(device_temp_sync_r3[4]),
        .I5(device_temp_sync_r4[4]),
        .O(device_temp_sync_r4_neq_r3_i_4_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    device_temp_sync_r4_neq_r3_i_5
       (.I0(device_temp_sync_r4[0]),
        .I1(device_temp_sync_r3[0]),
        .I2(device_temp_sync_r3[2]),
        .I3(device_temp_sync_r4[2]),
        .I4(device_temp_sync_r3[1]),
        .I5(device_temp_sync_r4[1]),
        .O(device_temp_sync_r4_neq_r3_i_5_n_0));
  FDRE device_temp_sync_r4_neq_r3_reg
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4_neq_r3_reg_i_1_n_0),
        .Q(device_temp_sync_r4_neq_r3),
        .R(1'b0));
  CARRY4 device_temp_sync_r4_neq_r3_reg_i_1
       (.CI(1'b0),
        .CO({device_temp_sync_r4_neq_r3_reg_i_1_n_0,device_temp_sync_r4_neq_r3_reg_i_1_n_1,device_temp_sync_r4_neq_r3_reg_i_1_n_2,device_temp_sync_r4_neq_r3_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O(NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED[3:0]),
        .S({device_temp_sync_r4_neq_r3_i_2_n_0,device_temp_sync_r4_neq_r3_i_3_n_0,device_temp_sync_r4_neq_r3_i_4_n_0,device_temp_sync_r4_neq_r3_i_5_n_0}));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[0] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[0]),
        .Q(device_temp_sync_r4[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[10] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[10]),
        .Q(device_temp_sync_r4[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[11] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[11]),
        .Q(device_temp_sync_r4[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[1] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[1]),
        .Q(device_temp_sync_r4[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[2] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[2]),
        .Q(device_temp_sync_r4[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[3] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[3]),
        .Q(device_temp_sync_r4[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[4] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[4]),
        .Q(device_temp_sync_r4[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[5] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[5]),
        .Q(device_temp_sync_r4[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[6] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[6]),
        .Q(device_temp_sync_r4[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[7] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[7]),
        .Q(device_temp_sync_r4[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[8] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[8]),
        .Q(device_temp_sync_r4[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[9] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[9]),
        .Q(device_temp_sync_r4[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[0] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[0]),
        .Q(device_temp_sync_r5[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[10] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[10]),
        .Q(device_temp_sync_r5[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[11] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[11]),
        .Q(device_temp_sync_r5[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[1] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[1]),
        .Q(device_temp_sync_r5[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[2] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[2]),
        .Q(device_temp_sync_r5[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[3] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[3]),
        .Q(device_temp_sync_r5[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[4] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[4]),
        .Q(device_temp_sync_r5[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[5] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[5]),
        .Q(device_temp_sync_r5[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[6] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[6]),
        .Q(device_temp_sync_r5[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[7] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[7]),
        .Q(device_temp_sync_r5[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[8] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[8]),
        .Q(device_temp_sync_r5[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[9] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[9]),
        .Q(device_temp_sync_r5[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \sync_cntr[0]_i_1 
       (.I0(sync_cntr_reg[0]),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \sync_cntr[1]_i_1 
       (.I0(sync_cntr_reg[0]),
        .I1(sync_cntr_reg[1]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \sync_cntr[2]_i_1 
       (.I0(sync_cntr_reg[1]),
        .I1(sync_cntr_reg[0]),
        .I2(sync_cntr_reg[2]),
        .O(\sync_cntr[2]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \sync_cntr[3]_i_1 
       (.I0(in0),
        .I1(device_temp_sync_r4_neq_r3),
        .O(sync_cntr0__4));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \sync_cntr[3]_i_2 
       (.I0(sync_cntr_reg[2]),
        .I1(sync_cntr_reg[3]),
        .I2(sync_cntr_reg[0]),
        .I3(sync_cntr_reg[1]),
        .O(\sync_cntr[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \sync_cntr[3]_i_3 
       (.I0(sync_cntr_reg[0]),
        .I1(sync_cntr_reg[1]),
        .I2(sync_cntr_reg[2]),
        .I3(sync_cntr_reg[3]),
        .O(p_0_in__1[3]));
  FDRE #(
    .INIT(1'b0)) 
    \sync_cntr_reg[0] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\sync_cntr[3]_i_2_n_0 ),
        .D(p_0_in__1[0]),
        .Q(sync_cntr_reg[0]),
        .R(sync_cntr0__4));
  FDRE #(
    .INIT(1'b0)) 
    \sync_cntr_reg[1] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\sync_cntr[3]_i_2_n_0 ),
        .D(p_0_in__1[1]),
        .Q(sync_cntr_reg[1]),
        .R(sync_cntr0__4));
  FDRE #(
    .INIT(1'b0)) 
    \sync_cntr_reg[2] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\sync_cntr[3]_i_2_n_0 ),
        .D(\sync_cntr[2]_i_1_n_0 ),
        .Q(sync_cntr_reg[2]),
        .R(sync_cntr0__4));
  FDRE #(
    .INIT(1'b0)) 
    \sync_cntr_reg[3] 
       (.C(\device_temp_r_reg[11]_0 ),
        .CE(\sync_cntr[3]_i_2_n_0 ),
        .D(p_0_in__1[3]),
        .Q(sync_cntr_reg[3]),
        .R(sync_cntr0__4));
  (* BOX_TYPE = "PRIMITIVE" *) 
  XADC #(
    .INIT_40(16'h1000),
    .INIT_41(16'h2FFF),
    .INIT_42(16'h0800),
    .INIT_43(16'h0000),
    .INIT_44(16'h0000),
    .INIT_45(16'h0000),
    .INIT_46(16'h0000),
    .INIT_47(16'h0000),
    .INIT_48(16'h0101),
    .INIT_49(16'h0000),
    .INIT_4A(16'h0100),
    .INIT_4B(16'h0000),
    .INIT_4C(16'h0000),
    .INIT_4D(16'h0000),
    .INIT_4E(16'h0000),
    .INIT_4F(16'h0000),
    .INIT_50(16'hB5ED),
    .INIT_51(16'h57E4),
    .INIT_52(16'hA147),
    .INIT_53(16'hCA33),
    .INIT_54(16'hA93A),
    .INIT_55(16'h52C6),
    .INIT_56(16'h9555),
    .INIT_57(16'hAE4E),
    .INIT_58(16'h5999),
    .INIT_59(16'h0000),
    .INIT_5A(16'h0000),
    .INIT_5B(16'h0000),
    .INIT_5C(16'h5111),
    .INIT_5D(16'h0000),
    .INIT_5E(16'h0000),
    .INIT_5F(16'h0000),
    .IS_CONVSTCLK_INVERTED(1'b0),
    .IS_DCLK_INVERTED(1'b0),
    .SIM_DEVICE("7SERIES"),
    .SIM_MONITOR_FILE("design.txt")) 
    \xadc_supplied_temperature.XADC_inst 
       (.ALM(\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED [7:0]),
        .BUSY(\NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ),
        .CHANNEL(\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED [4:0]),
        .CONVST(1'b0),
        .CONVSTCLK(1'b0),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(clk_ref_i),
        .DEN(\xadc_supplied_temperature.xadc_den ),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(\xadc_supplied_temperature.xadc_do ),
        .DRDY(\xadc_supplied_temperature.xadc_drdy ),
        .DWE(1'b0),
        .EOC(\NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ),
        .EOS(\NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ),
        .JTAGBUSY(\NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ),
        .JTAGLOCKED(\NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ),
        .JTAGMODIFIED(\NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ),
        .MUXADDR(\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED [4:0]),
        .OT(\NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ),
        .RESET(1'b0),
        .VAUXN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .VAUXP({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .VN(1'b0),
        .VP(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \xadc_supplied_temperature.rst_r1_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(in0),
        .Q(\xadc_supplied_temperature.rst_r1 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \xadc_supplied_temperature.rst_r2_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.rst_r1 ),
        .Q(\xadc_supplied_temperature.rst_r2 ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \xadc_supplied_temperature.sample_en_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [10]),
        .I1(\xadc_supplied_temperature.sample_en_i_2_n_0 ),
        .I2(\xadc_supplied_temperature.sample_timer_reg [6]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [8]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [7]),
        .I5(\xadc_supplied_temperature.sample_timer_reg [9]),
        .O(\xadc_supplied_temperature.sample_en_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \xadc_supplied_temperature.sample_en_i_2 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [1]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [2]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [3]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [5]),
        .I5(\xadc_supplied_temperature.sample_timer_reg [4]),
        .O(\xadc_supplied_temperature.sample_en_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_en_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.sample_en_i_1_n_0 ),
        .Q(\xadc_supplied_temperature.sample_en ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \xadc_supplied_temperature.sample_timer[0]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [0]),
        .O(p_0_in__0[0]));
  LUT2 #(
    .INIT(4'hE)) 
    \xadc_supplied_temperature.sample_timer[10]_i_1 
       (.I0(\xadc_supplied_temperature.rst_r2 ),
        .I1(\xadc_supplied_temperature.xadc_den ),
        .O(\xadc_supplied_temperature.sample_timer0__20 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \xadc_supplied_temperature.sample_timer[10]_i_2 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [8]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [6]),
        .I2(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I3(\xadc_supplied_temperature.sample_timer_reg [7]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [9]),
        .I5(\xadc_supplied_temperature.sample_timer_reg [10]),
        .O(p_0_in__0[10]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \xadc_supplied_temperature.sample_timer[10]_i_3 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [5]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [3]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [1]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [2]),
        .I5(\xadc_supplied_temperature.sample_timer_reg [4]),
        .O(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \xadc_supplied_temperature.sample_timer[1]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \xadc_supplied_temperature.sample_timer[2]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [1]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [2]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \xadc_supplied_temperature.sample_timer[3]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [1]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [2]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [3]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \xadc_supplied_temperature.sample_timer[4]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [2]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [1]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [3]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [4]),
        .O(p_0_in__0[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \xadc_supplied_temperature.sample_timer[5]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [3]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [1]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [2]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [4]),
        .I5(\xadc_supplied_temperature.sample_timer_reg [5]),
        .O(p_0_in__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \xadc_supplied_temperature.sample_timer[6]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I1(\xadc_supplied_temperature.sample_timer_reg [6]),
        .O(p_0_in__0[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \xadc_supplied_temperature.sample_timer[7]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I1(\xadc_supplied_temperature.sample_timer_reg [6]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [7]),
        .O(p_0_in__0[7]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \xadc_supplied_temperature.sample_timer[8]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [6]),
        .I1(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I2(\xadc_supplied_temperature.sample_timer_reg [7]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [8]),
        .O(p_0_in__0[8]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \xadc_supplied_temperature.sample_timer[9]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [7]),
        .I1(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I2(\xadc_supplied_temperature.sample_timer_reg [6]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [8]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [9]),
        .O(p_0_in__0[9]));
  LUT4 #(
    .INIT(16'h000E)) 
    \xadc_supplied_temperature.sample_timer_clr_i_1 
       (.I0(\xadc_supplied_temperature.xadc_den ),
        .I1(\xadc_supplied_temperature.sample_timer_clr ),
        .I2(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),
        .I3(\xadc_supplied_temperature.rst_r2 ),
        .O(\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_clr_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ),
        .Q(\xadc_supplied_temperature.xadc_den ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h000000FE)) 
    \xadc_supplied_temperature.sample_timer_en_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_en ),
        .I1(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .I2(\xadc_supplied_temperature.temperature ),
        .I3(\xadc_supplied_temperature.sample_timer_clr ),
        .I4(\xadc_supplied_temperature.rst_r2 ),
        .O(\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_en_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ),
        .Q(\xadc_supplied_temperature.sample_timer_en ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[0] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__0[0]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [0]),
        .R(\xadc_supplied_temperature.sample_timer0__20 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[10] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__0[10]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [10]),
        .R(\xadc_supplied_temperature.sample_timer0__20 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[1] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__0[1]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [1]),
        .R(\xadc_supplied_temperature.sample_timer0__20 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[2] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__0[2]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [2]),
        .R(\xadc_supplied_temperature.sample_timer0__20 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[3] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__0[3]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [3]),
        .R(\xadc_supplied_temperature.sample_timer0__20 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[4] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__0[4]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [4]),
        .R(\xadc_supplied_temperature.sample_timer0__20 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[5] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__0[5]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [5]),
        .R(\xadc_supplied_temperature.sample_timer0__20 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[6] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__0[6]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [6]),
        .R(\xadc_supplied_temperature.sample_timer0__20 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[7] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__0[7]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [7]),
        .R(\xadc_supplied_temperature.sample_timer0__20 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[8] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__0[8]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [8]),
        .R(\xadc_supplied_temperature.sample_timer0__20 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[9] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__0[9]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [9]),
        .R(\xadc_supplied_temperature.sample_timer0__20 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[0] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(p_0_in[0]),
        .Q(device_temp_lcl[0]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[10] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(p_0_in[10]),
        .Q(device_temp_lcl[10]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[11] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(p_0_in[11]),
        .Q(device_temp_lcl[11]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[1] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(p_0_in[1]),
        .Q(device_temp_lcl[1]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[2] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(p_0_in[2]),
        .Q(device_temp_lcl[2]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[3] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(p_0_in[3]),
        .Q(device_temp_lcl[3]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[4] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(p_0_in[4]),
        .Q(device_temp_lcl[4]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[5] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(p_0_in[5]),
        .Q(device_temp_lcl[5]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[6] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(p_0_in[6]),
        .Q(device_temp_lcl[6]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[7] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(p_0_in[7]),
        .Q(device_temp_lcl[7]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[8] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(p_0_in[8]),
        .Q(device_temp_lcl[8]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[9] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(p_0_in[9]),
        .Q(device_temp_lcl[9]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[10] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [10]),
        .Q(p_0_in[6]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[11] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [11]),
        .Q(p_0_in[7]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[12] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [12]),
        .Q(p_0_in[8]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[13] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [13]),
        .Q(p_0_in[9]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[14] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [14]),
        .Q(p_0_in[10]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[15] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [15]),
        .Q(p_0_in[11]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[4] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [4]),
        .Q(p_0_in[0]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[5] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [5]),
        .Q(p_0_in[1]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[6] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [6]),
        .Q(p_0_in[2]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[7] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [7]),
        .Q(p_0_in[3]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[8] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [8]),
        .Q(p_0_in[4]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[9] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [9]),
        .Q(p_0_in[5]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_drdy_r_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_drdy ),
        .Q(\xadc_supplied_temperature.xadc_drdy_r ),
        .R(\xadc_supplied_temperature.rst_r2 ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ui_cmd
   (E,
    app_en_r2_reg_0,
    \app_addr_r2_reg[24]_0 ,
    \req_bank_r_lcl_reg[0] ,
    \app_addr_r2_reg[26]_0 ,
    \app_addr_r2_reg[24]_1 ,
    app_cmd_r2,
    \app_cmd_r2_reg[0]_0 ,
    S,
    row,
    \app_addr_r1_reg[22]_0 ,
    \req_row_r_lcl_reg[12] ,
    \req_row_r_lcl_reg[12]_0 ,
    \req_row_r_lcl_reg[12]_1 ,
    was_wr0,
    \app_addr_r1_reg[26]_0 ,
    bank,
    req_wr_r_lcl0,
    D,
    use_addr,
    app_en_r2_reg_1,
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0] ,
    \strict_mode.rd_data_buf_addr_r_lcl_reg[1] ,
    \wr_req_counter.wr_req_cnt_r_reg[0] ,
    \read_data_indx.rd_data_upd_indx_r_reg ,
    wr_accepted,
    \app_addr_r1_reg[9]_0 ,
    app_rdy_ns,
    CLK,
    rb_hit_busy_r_reg,
    req_bank_r,
    rb_hit_busy_r_reg_0,
    rb_hit_busy_r_reg_1,
    rb_hit_busy_r_reg_2,
    periodic_rd_ack_r,
    periodic_rd_cntr_r,
    periodic_rd_r,
    row_hit_r_reg,
    app_en,
    \app_addr_r1_reg[0]_0 ,
    wr_data_buf_addr,
    \strict_mode.rd_data_buf_addr_r_lcl ,
    \wr_req_counter.wr_req_cnt_r ,
    p_0_in,
    app_addr,
    app_cmd);
  output [0:0]E;
  output app_en_r2_reg_0;
  output \app_addr_r2_reg[24]_0 ;
  output \req_bank_r_lcl_reg[0] ;
  output \app_addr_r2_reg[26]_0 ;
  output \app_addr_r2_reg[24]_1 ;
  output [1:0]app_cmd_r2;
  output \app_cmd_r2_reg[0]_0 ;
  output [2:0]S;
  output [13:0]row;
  output [0:0]\app_addr_r1_reg[22]_0 ;
  output [0:0]\req_row_r_lcl_reg[12] ;
  output [0:0]\req_row_r_lcl_reg[12]_0 ;
  output [0:0]\req_row_r_lcl_reg[12]_1 ;
  output was_wr0;
  output \app_addr_r1_reg[26]_0 ;
  output [1:0]bank;
  output req_wr_r_lcl0;
  output [3:0]D;
  output use_addr;
  output app_en_r2_reg_1;
  output \strict_mode.rd_data_buf_addr_r_lcl_reg[0] ;
  output \strict_mode.rd_data_buf_addr_r_lcl_reg[1] ;
  output \wr_req_counter.wr_req_cnt_r_reg[0] ;
  output \read_data_indx.rd_data_upd_indx_r_reg ;
  output wr_accepted;
  output [9:0]\app_addr_r1_reg[9]_0 ;
  input app_rdy_ns;
  input CLK;
  input rb_hit_busy_r_reg;
  input [11:0]req_bank_r;
  input rb_hit_busy_r_reg_0;
  input rb_hit_busy_r_reg_1;
  input rb_hit_busy_r_reg_2;
  input periodic_rd_ack_r;
  input periodic_rd_cntr_r;
  input periodic_rd_r;
  input [16:0]row_hit_r_reg;
  input app_en;
  input \app_addr_r1_reg[0]_0 ;
  input [3:0]wr_data_buf_addr;
  input [3:0]\strict_mode.rd_data_buf_addr_r_lcl ;
  input [0:0]\wr_req_counter.wr_req_cnt_r ;
  input [0:0]p_0_in;
  input [26:0]app_addr;
  input [1:0]app_cmd;

  wire CLK;
  wire [3:0]D;
  wire [0:0]E;
  wire [2:0]S;
  wire [26:0]app_addr;
  wire app_addr_r10;
  wire \app_addr_r1_reg[0]_0 ;
  wire [0:0]\app_addr_r1_reg[22]_0 ;
  wire \app_addr_r1_reg[26]_0 ;
  wire [9:0]\app_addr_r1_reg[9]_0 ;
  wire \app_addr_r1_reg_n_0_[0] ;
  wire \app_addr_r1_reg_n_0_[10] ;
  wire \app_addr_r1_reg_n_0_[11] ;
  wire \app_addr_r1_reg_n_0_[12] ;
  wire \app_addr_r1_reg_n_0_[13] ;
  wire \app_addr_r1_reg_n_0_[14] ;
  wire \app_addr_r1_reg_n_0_[15] ;
  wire \app_addr_r1_reg_n_0_[16] ;
  wire \app_addr_r1_reg_n_0_[17] ;
  wire \app_addr_r1_reg_n_0_[18] ;
  wire \app_addr_r1_reg_n_0_[19] ;
  wire \app_addr_r1_reg_n_0_[1] ;
  wire \app_addr_r1_reg_n_0_[20] ;
  wire \app_addr_r1_reg_n_0_[21] ;
  wire \app_addr_r1_reg_n_0_[22] ;
  wire \app_addr_r1_reg_n_0_[23] ;
  wire \app_addr_r1_reg_n_0_[2] ;
  wire \app_addr_r1_reg_n_0_[3] ;
  wire \app_addr_r1_reg_n_0_[4] ;
  wire \app_addr_r1_reg_n_0_[5] ;
  wire \app_addr_r1_reg_n_0_[6] ;
  wire \app_addr_r1_reg_n_0_[7] ;
  wire \app_addr_r1_reg_n_0_[8] ;
  wire \app_addr_r1_reg_n_0_[9] ;
  wire \app_addr_r2_reg[24]_0 ;
  wire \app_addr_r2_reg[24]_1 ;
  wire \app_addr_r2_reg[26]_0 ;
  wire \app_addr_r2_reg_n_0_[0] ;
  wire \app_addr_r2_reg_n_0_[10] ;
  wire \app_addr_r2_reg_n_0_[11] ;
  wire \app_addr_r2_reg_n_0_[12] ;
  wire \app_addr_r2_reg_n_0_[13] ;
  wire \app_addr_r2_reg_n_0_[14] ;
  wire \app_addr_r2_reg_n_0_[15] ;
  wire \app_addr_r2_reg_n_0_[16] ;
  wire \app_addr_r2_reg_n_0_[17] ;
  wire \app_addr_r2_reg_n_0_[18] ;
  wire \app_addr_r2_reg_n_0_[19] ;
  wire \app_addr_r2_reg_n_0_[1] ;
  wire \app_addr_r2_reg_n_0_[20] ;
  wire \app_addr_r2_reg_n_0_[21] ;
  wire \app_addr_r2_reg_n_0_[22] ;
  wire \app_addr_r2_reg_n_0_[23] ;
  wire \app_addr_r2_reg_n_0_[2] ;
  wire \app_addr_r2_reg_n_0_[3] ;
  wire \app_addr_r2_reg_n_0_[4] ;
  wire \app_addr_r2_reg_n_0_[5] ;
  wire \app_addr_r2_reg_n_0_[6] ;
  wire \app_addr_r2_reg_n_0_[7] ;
  wire \app_addr_r2_reg_n_0_[8] ;
  wire \app_addr_r2_reg_n_0_[9] ;
  wire [1:0]app_cmd;
  wire [1:0]app_cmd_r1;
  wire [1:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0]_0 ;
  wire app_en;
  wire app_en_ns1;
  wire app_en_ns2;
  wire app_en_r1;
  wire app_en_r2_reg_0;
  wire app_en_r2_reg_1;
  wire app_rdy_ns;
  wire [1:0]bank;
  wire [0:0]p_0_in;
  wire [2:0]p_0_in_0;
  wire [2:0]p_1_in;
  wire periodic_rd_ack_r;
  wire periodic_rd_cntr_r;
  wire periodic_rd_r;
  wire rb_hit_busy_r_i_2__0_n_0;
  wire rb_hit_busy_r_i_2__1_n_0;
  wire rb_hit_busy_r_i_2__2_n_0;
  wire rb_hit_busy_r_i_2_n_0;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rb_hit_busy_r_reg_2;
  wire \read_data_indx.rd_data_upd_indx_r_reg ;
  wire [11:0]req_bank_r;
  wire \req_bank_r_lcl_reg[0] ;
  wire [0:0]\req_row_r_lcl_reg[12] ;
  wire [0:0]\req_row_r_lcl_reg[12]_0 ;
  wire [0:0]\req_row_r_lcl_reg[12]_1 ;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_i_2_n_0;
  wire [13:0]row;
  wire [16:0]row_hit_r_reg;
  wire [3:0]\strict_mode.rd_data_buf_addr_r_lcl ;
  wire \strict_mode.rd_data_buf_addr_r_lcl_reg[0] ;
  wire \strict_mode.rd_data_buf_addr_r_lcl_reg[1] ;
  wire use_addr;
  wire was_wr0;
  wire wr_accepted;
  wire [3:0]wr_data_buf_addr;
  wire [0:0]\wr_req_counter.wr_req_cnt_r ;
  wire \wr_req_counter.wr_req_cnt_r_reg[0] ;
  wire write__0;

  LUT2 #(
    .INIT(4'h8)) 
    \app_addr_r1[26]_i_1 
       (.I0(E),
        .I1(app_en),
        .O(app_addr_r10));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[0] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[0]),
        .Q(\app_addr_r1_reg_n_0_[0] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[10] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[10]),
        .Q(\app_addr_r1_reg_n_0_[10] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[11] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[11]),
        .Q(\app_addr_r1_reg_n_0_[11] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[12] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[12]),
        .Q(\app_addr_r1_reg_n_0_[12] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[13] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[13]),
        .Q(\app_addr_r1_reg_n_0_[13] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[14] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[14]),
        .Q(\app_addr_r1_reg_n_0_[14] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[15] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[15]),
        .Q(\app_addr_r1_reg_n_0_[15] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[16] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[16]),
        .Q(\app_addr_r1_reg_n_0_[16] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[17] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[17]),
        .Q(\app_addr_r1_reg_n_0_[17] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[18] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[18]),
        .Q(\app_addr_r1_reg_n_0_[18] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[19] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[19]),
        .Q(\app_addr_r1_reg_n_0_[19] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[1] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[1]),
        .Q(\app_addr_r1_reg_n_0_[1] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[20] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[20]),
        .Q(\app_addr_r1_reg_n_0_[20] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[21] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[21]),
        .Q(\app_addr_r1_reg_n_0_[21] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[22] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[22]),
        .Q(\app_addr_r1_reg_n_0_[22] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[23] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[23]),
        .Q(\app_addr_r1_reg_n_0_[23] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[24] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[24]),
        .Q(p_1_in[0]),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[25] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[25]),
        .Q(p_1_in[1]),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[26] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[26]),
        .Q(p_1_in[2]),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[2] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[2]),
        .Q(\app_addr_r1_reg_n_0_[2] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[3] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[3]),
        .Q(\app_addr_r1_reg_n_0_[3] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[4] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[4]),
        .Q(\app_addr_r1_reg_n_0_[4] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[5] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[5]),
        .Q(\app_addr_r1_reg_n_0_[5] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[6] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[6]),
        .Q(\app_addr_r1_reg_n_0_[6] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[7] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[7]),
        .Q(\app_addr_r1_reg_n_0_[7] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[8] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[8]),
        .Q(\app_addr_r1_reg_n_0_[8] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[9] 
       (.C(CLK),
        .CE(app_addr_r10),
        .D(app_addr[9]),
        .Q(\app_addr_r1_reg_n_0_[9] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[0] ),
        .Q(\app_addr_r2_reg_n_0_[0] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[10] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[10] ),
        .Q(\app_addr_r2_reg_n_0_[10] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[11] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[11] ),
        .Q(\app_addr_r2_reg_n_0_[11] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[12] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[12] ),
        .Q(\app_addr_r2_reg_n_0_[12] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[13] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[13] ),
        .Q(\app_addr_r2_reg_n_0_[13] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[14] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[14] ),
        .Q(\app_addr_r2_reg_n_0_[14] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[15] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[15] ),
        .Q(\app_addr_r2_reg_n_0_[15] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[16] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[16] ),
        .Q(\app_addr_r2_reg_n_0_[16] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[17] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[17] ),
        .Q(\app_addr_r2_reg_n_0_[17] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[18] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[18] ),
        .Q(\app_addr_r2_reg_n_0_[18] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[19] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[19] ),
        .Q(\app_addr_r2_reg_n_0_[19] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[1] ),
        .Q(\app_addr_r2_reg_n_0_[1] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[20] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[20] ),
        .Q(\app_addr_r2_reg_n_0_[20] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[21] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[21] ),
        .Q(\app_addr_r2_reg_n_0_[21] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[22] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[22] ),
        .Q(\app_addr_r2_reg_n_0_[22] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[23] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[23] ),
        .Q(\app_addr_r2_reg_n_0_[23] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[24] 
       (.C(CLK),
        .CE(E),
        .D(p_1_in[0]),
        .Q(p_0_in_0[0]),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[25] 
       (.C(CLK),
        .CE(E),
        .D(p_1_in[1]),
        .Q(p_0_in_0[1]),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[26] 
       (.C(CLK),
        .CE(E),
        .D(p_1_in[2]),
        .Q(p_0_in_0[2]),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[2] ),
        .Q(\app_addr_r2_reg_n_0_[2] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[3] ),
        .Q(\app_addr_r2_reg_n_0_[3] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[4] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[4] ),
        .Q(\app_addr_r2_reg_n_0_[4] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[5] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[5] ),
        .Q(\app_addr_r2_reg_n_0_[5] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[6] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[6] ),
        .Q(\app_addr_r2_reg_n_0_[6] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[7] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[7] ),
        .Q(\app_addr_r2_reg_n_0_[7] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[8] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[8] ),
        .Q(\app_addr_r2_reg_n_0_[8] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[9] 
       (.C(CLK),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[9] ),
        .Q(\app_addr_r2_reg_n_0_[9] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE \app_cmd_r1_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(app_cmd[0]),
        .Q(app_cmd_r1[0]),
        .R(1'b0));
  FDRE \app_cmd_r1_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(app_cmd[1]),
        .Q(app_cmd_r1[1]),
        .R(1'b0));
  FDRE \app_cmd_r2_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(app_cmd_r1[0]),
        .Q(app_cmd_r2[0]),
        .R(1'b0));
  FDRE \app_cmd_r2_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(app_cmd_r1[1]),
        .Q(app_cmd_r2[1]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair633" *) 
  LUT4 #(
    .INIT(16'h2230)) 
    app_en_r1_i_1
       (.I0(app_en),
        .I1(\app_addr_r1_reg[0]_0 ),
        .I2(app_en_r1),
        .I3(E),
        .O(app_en_ns1));
  FDRE app_en_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_en_ns1),
        .Q(app_en_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair633" *) 
  LUT4 #(
    .INIT(16'h2230)) 
    app_en_r2_i_1
       (.I0(app_en_r1),
        .I1(\app_addr_r1_reg[0]_0 ),
        .I2(app_en_r2_reg_0),
        .I3(E),
        .O(app_en_ns2));
  FDRE app_en_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_en_ns2),
        .Q(app_en_r2_reg_0),
        .R(1'b0));
  (* syn_maxfan = "10" *) 
  FDRE #(
    .INIT(1'b0)) 
    app_rdy_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_rdy_ns),
        .Q(E),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair631" *) 
  LUT4 #(
    .INIT(16'h8008)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1 
       (.I0(E),
        .I1(app_en_r2_reg_0),
        .I2(app_cmd_r2[0]),
        .I3(app_cmd_r2[1]),
        .O(wr_accepted));
  LUT6 #(
    .INIT(64'h2220002000022202)) 
    rb_hit_busy_r_i_1
       (.I0(rb_hit_busy_r_reg),
        .I1(rb_hit_busy_r_i_2__0_n_0),
        .I2(p_0_in_0[0]),
        .I3(E),
        .I4(p_1_in[0]),
        .I5(req_bank_r[0]),
        .O(\app_addr_r2_reg[24]_0 ));
  LUT6 #(
    .INIT(64'h2020200202022002)) 
    rb_hit_busy_r_i_1__0
       (.I0(rb_hit_busy_r_reg_0),
        .I1(rb_hit_busy_r_i_2_n_0),
        .I2(req_bank_r[3]),
        .I3(p_0_in_0[0]),
        .I4(E),
        .I5(p_1_in[0]),
        .O(\req_bank_r_lcl_reg[0] ));
  LUT6 #(
    .INIT(64'h00000000A80802A2)) 
    rb_hit_busy_r_i_1__1
       (.I0(rb_hit_busy_r_reg_1),
        .I1(p_0_in_0[2]),
        .I2(E),
        .I3(p_1_in[2]),
        .I4(req_bank_r[8]),
        .I5(rb_hit_busy_r_i_2__2_n_0),
        .O(\app_addr_r2_reg[26]_0 ));
  LUT6 #(
    .INIT(64'h2220002000022202)) 
    rb_hit_busy_r_i_1__2
       (.I0(rb_hit_busy_r_reg_2),
        .I1(rb_hit_busy_r_i_2__1_n_0),
        .I2(p_0_in_0[0]),
        .I3(E),
        .I4(p_1_in[0]),
        .I5(req_bank_r[9]),
        .O(\app_addr_r2_reg[24]_1 ));
  LUT6 #(
    .INIT(64'h47B8FFFFFFFF47B8)) 
    rb_hit_busy_r_i_2
       (.I0(p_1_in[1]),
        .I1(E),
        .I2(p_0_in_0[1]),
        .I3(req_bank_r[4]),
        .I4(\app_addr_r1_reg[26]_0 ),
        .I5(req_bank_r[5]),
        .O(rb_hit_busy_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h656AFFFFFFFF656A)) 
    rb_hit_busy_r_i_2__0
       (.I0(req_bank_r[1]),
        .I1(p_1_in[1]),
        .I2(E),
        .I3(p_0_in_0[1]),
        .I4(req_bank_r[2]),
        .I5(\app_addr_r1_reg[26]_0 ),
        .O(rb_hit_busy_r_i_2__0_n_0));
  LUT6 #(
    .INIT(64'h656AFFFFFFFF656A)) 
    rb_hit_busy_r_i_2__1
       (.I0(req_bank_r[10]),
        .I1(p_1_in[1]),
        .I2(E),
        .I3(p_0_in_0[1]),
        .I4(req_bank_r[11]),
        .I5(\app_addr_r1_reg[26]_0 ),
        .O(rb_hit_busy_r_i_2__1_n_0));
  LUT6 #(
    .INIT(64'h656AFFFFFFFF656A)) 
    rb_hit_busy_r_i_2__2
       (.I0(req_bank_r[6]),
        .I1(p_1_in[0]),
        .I2(E),
        .I3(p_0_in_0[0]),
        .I4(req_bank_r[7]),
        .I5(bank[1]),
        .O(rb_hit_busy_r_i_2__2_n_0));
  LUT6 #(
    .INIT(64'hE2FFFFFFE2E2E2E2)) 
    rd_wr_r_lcl_i_2
       (.I0(app_cmd_r2[0]),
        .I1(E),
        .I2(app_cmd_r1[0]),
        .I3(periodic_rd_ack_r),
        .I4(periodic_rd_cntr_r),
        .I5(periodic_rd_r),
        .O(\app_cmd_r2_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair641" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_bank_r_lcl[0]_i_1 
       (.I0(p_1_in[0]),
        .I1(E),
        .I2(p_0_in_0[0]),
        .O(bank[0]));
  (* SOFT_HLUTNM = "soft_lutpair640" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_bank_r_lcl[1]_i_1 
       (.I0(p_1_in[1]),
        .I1(E),
        .I2(p_0_in_0[1]),
        .O(bank[1]));
  (* SOFT_HLUTNM = "soft_lutpair640" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_bank_r_lcl[2]_i_1 
       (.I0(p_1_in[2]),
        .I1(E),
        .I2(p_0_in_0[2]),
        .O(\app_addr_r1_reg[26]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[0]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[0] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[0] ),
        .O(\app_addr_r1_reg[9]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair646" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[1]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[1] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[1] ),
        .O(\app_addr_r1_reg[9]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair646" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[2]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[2] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[2] ),
        .O(\app_addr_r1_reg[9]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair645" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[3]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[3] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[3] ),
        .O(\app_addr_r1_reg[9]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair645" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[4]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[4] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[4] ),
        .O(\app_addr_r1_reg[9]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair644" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[5]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[5] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[5] ),
        .O(\app_addr_r1_reg[9]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair644" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[6]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[6] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[6] ),
        .O(\app_addr_r1_reg[9]_0 [6]));
  (* SOFT_HLUTNM = "soft_lutpair643" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[7]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[7] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[7] ),
        .O(\app_addr_r1_reg[9]_0 [7]));
  (* SOFT_HLUTNM = "soft_lutpair643" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[8]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[8] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[8] ),
        .O(\app_addr_r1_reg[9]_0 [8]));
  (* SOFT_HLUTNM = "soft_lutpair642" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[9]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[9] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[9] ),
        .O(\app_addr_r1_reg[9]_0 [9]));
  LUT6 #(
    .INIT(64'h82B282BE828E8282)) 
    \req_data_buf_addr_r[0]_i_1 
       (.I0(wr_data_buf_addr[0]),
        .I1(app_cmd_r2[0]),
        .I2(app_cmd_r2[1]),
        .I3(\app_addr_r1_reg[0]_0 ),
        .I4(use_addr),
        .I5(\strict_mode.rd_data_buf_addr_r_lcl [0]),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair632" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \req_data_buf_addr_r[0]_i_2 
       (.I0(app_en_r2_reg_0),
        .I1(E),
        .O(use_addr));
  (* SOFT_HLUTNM = "soft_lutpair630" *) 
  LUT5 #(
    .INIT(32'h82BE8282)) 
    \req_data_buf_addr_r[1]_i_1 
       (.I0(wr_data_buf_addr[1]),
        .I1(app_cmd_r2[0]),
        .I2(app_cmd_r2[1]),
        .I3(\app_addr_r1_reg[0]_0 ),
        .I4(\strict_mode.rd_data_buf_addr_r_lcl_reg[0] ),
        .O(D[1]));
  LUT6 #(
    .INIT(64'h828282BE82BE8282)) 
    \req_data_buf_addr_r[2]_i_1 
       (.I0(wr_data_buf_addr[2]),
        .I1(app_cmd_r2[0]),
        .I2(app_cmd_r2[1]),
        .I3(\app_addr_r1_reg[0]_0 ),
        .I4(\strict_mode.rd_data_buf_addr_r_lcl [2]),
        .I5(\strict_mode.rd_data_buf_addr_r_lcl_reg[1] ),
        .O(D[2]));
  LUT6 #(
    .INIT(64'h888B8B8B8B888888)) 
    \req_data_buf_addr_r[3]_i_1 
       (.I0(wr_data_buf_addr[3]),
        .I1(write__0),
        .I2(\app_addr_r1_reg[0]_0 ),
        .I3(\strict_mode.rd_data_buf_addr_r_lcl_reg[1] ),
        .I4(\strict_mode.rd_data_buf_addr_r_lcl [2]),
        .I5(\strict_mode.rd_data_buf_addr_r_lcl [3]),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair630" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \req_data_buf_addr_r[3]_i_2 
       (.I0(app_cmd_r2[1]),
        .I1(app_cmd_r2[0]),
        .O(write__0));
  LUT6 #(
    .INIT(64'h0800000000000000)) 
    \req_data_buf_addr_r[3]_i_3 
       (.I0(\strict_mode.rd_data_buf_addr_r_lcl [1]),
        .I1(\strict_mode.rd_data_buf_addr_r_lcl [0]),
        .I2(app_cmd_r2[1]),
        .I3(app_cmd_r2[0]),
        .I4(E),
        .I5(app_en_r2_reg_0),
        .O(\strict_mode.rd_data_buf_addr_r_lcl_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair636" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[0]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[10] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[10] ),
        .O(row[0]));
  (* SOFT_HLUTNM = "soft_lutpair637" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[10]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[20] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[20] ),
        .O(row[10]));
  (* SOFT_HLUTNM = "soft_lutpair637" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[11]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[21] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[21] ),
        .O(row[11]));
  (* SOFT_HLUTNM = "soft_lutpair642" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[12]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[22] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[22] ),
        .O(row[12]));
  (* SOFT_HLUTNM = "soft_lutpair641" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[13]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[23] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[23] ),
        .O(row[13]));
  (* SOFT_HLUTNM = "soft_lutpair636" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[1]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[11] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[11] ),
        .O(row[1]));
  (* SOFT_HLUTNM = "soft_lutpair635" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[2]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[12] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[12] ),
        .O(row[2]));
  (* SOFT_HLUTNM = "soft_lutpair635" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[3]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[13] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[13] ),
        .O(row[3]));
  (* SOFT_HLUTNM = "soft_lutpair634" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[4]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[14] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[14] ),
        .O(row[4]));
  (* SOFT_HLUTNM = "soft_lutpair634" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[5]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[15] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[15] ),
        .O(row[5]));
  (* SOFT_HLUTNM = "soft_lutpair639" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[6]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[16] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[16] ),
        .O(row[6]));
  (* SOFT_HLUTNM = "soft_lutpair639" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[7]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[17] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[17] ),
        .O(row[7]));
  (* SOFT_HLUTNM = "soft_lutpair638" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[8]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[18] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[18] ),
        .O(row[8]));
  (* SOFT_HLUTNM = "soft_lutpair638" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[9]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[19] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[19] ),
        .O(row[9]));
  LUT2 #(
    .INIT(4'hB)) 
    req_wr_r_lcl_i_1
       (.I0(req_wr_r_lcl_i_2_n_0),
        .I1(\app_cmd_r2_reg[0]_0 ),
        .O(req_wr_r_lcl0));
  LUT6 #(
    .INIT(64'hE2000000E2E2E2E2)) 
    req_wr_r_lcl_i_2
       (.I0(app_cmd_r2[1]),
        .I1(E),
        .I2(app_cmd_r1[1]),
        .I3(periodic_rd_ack_r),
        .I4(periodic_rd_cntr_r),
        .I5(periodic_rd_r),
        .O(req_wr_r_lcl_i_2_n_0));
  LUT6 #(
    .INIT(64'hB84700000000B847)) 
    row_hit_ns_carry__0_i_1
       (.I0(\app_addr_r1_reg_n_0_[22] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[22] ),
        .I3(row_hit_r_reg[9]),
        .I4(row[13]),
        .I5(row_hit_r_reg[10]),
        .O(\app_addr_r1_reg[22]_0 ));
  LUT6 #(
    .INIT(64'h9A95000000009A95)) 
    row_hit_ns_carry__0_i_1__0
       (.I0(row_hit_r_reg[11]),
        .I1(\app_addr_r1_reg_n_0_[22] ),
        .I2(E),
        .I3(\app_addr_r2_reg_n_0_[22] ),
        .I4(row_hit_r_reg[12]),
        .I5(row[13]),
        .O(\req_row_r_lcl_reg[12] ));
  LUT6 #(
    .INIT(64'h9A95000000009A95)) 
    row_hit_ns_carry__0_i_1__1
       (.I0(row_hit_r_reg[13]),
        .I1(\app_addr_r1_reg_n_0_[22] ),
        .I2(E),
        .I3(\app_addr_r2_reg_n_0_[22] ),
        .I4(row_hit_r_reg[14]),
        .I5(row[13]),
        .O(\req_row_r_lcl_reg[12]_0 ));
  LUT6 #(
    .INIT(64'h9A95000000009A95)) 
    row_hit_ns_carry__0_i_1__2
       (.I0(row_hit_r_reg[15]),
        .I1(\app_addr_r1_reg_n_0_[22] ),
        .I2(E),
        .I3(\app_addr_r2_reg_n_0_[22] ),
        .I4(row_hit_r_reg[16]),
        .I5(row[13]),
        .O(\req_row_r_lcl_reg[12]_1 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_2
       (.I0(row[8]),
        .I1(row_hit_r_reg[8]),
        .I2(row_hit_r_reg[7]),
        .I3(row[7]),
        .I4(row[6]),
        .I5(row_hit_r_reg[6]),
        .O(S[2]));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_3
       (.I0(row[5]),
        .I1(row_hit_r_reg[5]),
        .I2(row_hit_r_reg[3]),
        .I3(row[3]),
        .I4(row[4]),
        .I5(row_hit_r_reg[4]),
        .O(S[1]));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_4
       (.I0(row[2]),
        .I1(row_hit_r_reg[2]),
        .I2(row_hit_r_reg[0]),
        .I3(row[0]),
        .I4(row[1]),
        .I5(row_hit_r_reg[1]),
        .O(S[0]));
  (* SOFT_HLUTNM = "soft_lutpair632" *) 
  LUT5 #(
    .INIT(32'hFF7F0080)) 
    \strict_mode.rd_data_buf_addr_r_lcl[0]_i_1 
       (.I0(app_en_r2_reg_0),
        .I1(E),
        .I2(app_cmd_r2[0]),
        .I3(app_cmd_r2[1]),
        .I4(\strict_mode.rd_data_buf_addr_r_lcl [0]),
        .O(app_en_r2_reg_1));
  LUT6 #(
    .INIT(64'hDFFFFFFF20000000)) 
    \strict_mode.rd_data_buf_addr_r_lcl[1]_i_1 
       (.I0(\strict_mode.rd_data_buf_addr_r_lcl [0]),
        .I1(app_cmd_r2[1]),
        .I2(app_cmd_r2[0]),
        .I3(E),
        .I4(app_en_r2_reg_0),
        .I5(\strict_mode.rd_data_buf_addr_r_lcl [1]),
        .O(\strict_mode.rd_data_buf_addr_r_lcl_reg[0] ));
  LUT5 #(
    .INIT(32'hE200E2E2)) 
    was_wr_i_1
       (.I0(app_cmd_r2[0]),
        .I1(E),
        .I2(app_cmd_r1[0]),
        .I3(periodic_rd_ack_r),
        .I4(periodic_rd_r),
        .O(was_wr0));
  LUT6 #(
    .INIT(64'h955555956AAAAA6A)) 
    \wr_req_counter.wr_req_cnt_r[0]_i_1 
       (.I0(\wr_req_counter.wr_req_cnt_r ),
        .I1(E),
        .I2(app_en_r2_reg_0),
        .I3(app_cmd_r2[0]),
        .I4(app_cmd_r2[1]),
        .I5(p_0_in),
        .O(\wr_req_counter.wr_req_cnt_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair631" *) 
  LUT5 #(
    .INIT(32'h69AAAAAA)) 
    \wr_req_counter.wr_req_cnt_r[4]_i_3 
       (.I0(p_0_in),
        .I1(app_cmd_r2[1]),
        .I2(app_cmd_r2[0]),
        .I3(app_en_r2_reg_0),
        .I4(E),
        .O(\read_data_indx.rd_data_upd_indx_r_reg ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ui_rd_data
   (\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ,
    \strict_mode.rd_data_buf_addr_r_lcl ,
    ADDRD,
    \pointer_ram.pointer_wr_data ,
    CLK,
    use_addr,
    app_cmd_r2,
    \strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0 ,
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ,
    Q,
    wr_data_addr,
    \strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0 ,
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 );
  output \rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ;
  output [3:0]\strict_mode.rd_data_buf_addr_r_lcl ;
  output [3:0]ADDRD;
  output [3:0]\pointer_ram.pointer_wr_data ;
  input CLK;
  input use_addr;
  input [1:0]app_cmd_r2;
  input \strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0 ;
  input \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ;
  input [3:0]Q;
  input [3:0]wr_data_addr;
  input \strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0 ;
  input \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ;

  wire [3:0]ADDRD;
  wire CLK;
  wire [3:0]Q;
  wire [1:0]app_cmd_r2;
  wire [4:0]p_0_in__2;
  wire [3:0]\pointer_ram.pointer_wr_data ;
  wire [3:0]ram_init_addr;
  wire \rd_buf_indx.ram_init_done_ns ;
  wire \rd_buf_indx.ram_init_done_r_lcl_inv_i_2_n_0 ;
  wire \rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ;
  wire [4:4]\rd_buf_indx.rd_buf_indx_r_reg ;
  wire [3:0]\strict_mode.rd_data_buf_addr_r_lcl ;
  wire \strict_mode.rd_data_buf_addr_r_lcl[2]_i_1_n_0 ;
  wire \strict_mode.rd_data_buf_addr_r_lcl[3]_i_1_n_0 ;
  wire \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ;
  wire \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ;
  wire \strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0 ;
  wire \strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0 ;
  wire use_addr;
  wire [3:0]wr_data_addr;

  LUT3 #(
    .INIT(8'hE2)) 
    \pointer_ram.rams[0].RAM32M0_i_2 
       (.I0(wr_data_addr[1]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .I2(ram_init_addr[1]),
        .O(\pointer_ram.pointer_wr_data [1]));
  LUT3 #(
    .INIT(8'hE2)) 
    \pointer_ram.rams[0].RAM32M0_i_3 
       (.I0(wr_data_addr[0]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .I2(ram_init_addr[0]),
        .O(\pointer_ram.pointer_wr_data [0]));
  LUT3 #(
    .INIT(8'hE2)) 
    \pointer_ram.rams[0].RAM32M0_i_4 
       (.I0(Q[3]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .I2(ram_init_addr[3]),
        .O(ADDRD[3]));
  LUT3 #(
    .INIT(8'hE2)) 
    \pointer_ram.rams[0].RAM32M0_i_5 
       (.I0(Q[2]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .I2(ram_init_addr[2]),
        .O(ADDRD[2]));
  LUT3 #(
    .INIT(8'hE2)) 
    \pointer_ram.rams[0].RAM32M0_i_6 
       (.I0(Q[1]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .I2(ram_init_addr[1]),
        .O(ADDRD[1]));
  LUT3 #(
    .INIT(8'hE2)) 
    \pointer_ram.rams[0].RAM32M0_i_7 
       (.I0(Q[0]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .I2(ram_init_addr[0]),
        .O(ADDRD[0]));
  LUT3 #(
    .INIT(8'hE2)) 
    \pointer_ram.rams[1].RAM32M0_i_1 
       (.I0(wr_data_addr[3]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .I2(ram_init_addr[3]),
        .O(\pointer_ram.pointer_wr_data [3]));
  LUT3 #(
    .INIT(8'hE2)) 
    \pointer_ram.rams[1].RAM32M0_i_2 
       (.I0(wr_data_addr[2]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .I2(ram_init_addr[2]),
        .O(\pointer_ram.pointer_wr_data [2]));
  LUT4 #(
    .INIT(16'hFBF0)) 
    \rd_buf_indx.ram_init_done_r_lcl_inv_i_1 
       (.I0(\rd_buf_indx.ram_init_done_r_lcl_inv_i_2_n_0 ),
        .I1(\rd_buf_indx.rd_buf_indx_r_reg ),
        .I2(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ),
        .I3(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .O(\rd_buf_indx.ram_init_done_ns ));
  (* SOFT_HLUTNM = "soft_lutpair647" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \rd_buf_indx.ram_init_done_r_lcl_inv_i_2 
       (.I0(ram_init_addr[2]),
        .I1(ram_init_addr[1]),
        .I2(ram_init_addr[0]),
        .I3(ram_init_addr[3]),
        .O(\rd_buf_indx.ram_init_done_r_lcl_inv_i_2_n_0 ));
  (* inverted = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE #(
    .INIT(1'b1)) 
    \rd_buf_indx.ram_init_done_r_lcl_reg_inv 
       (.C(CLK),
        .CE(1'b1),
        .D(\rd_buf_indx.ram_init_done_ns ),
        .Q(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair649" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rd_buf_indx.rd_buf_indx_r[0]_i_1 
       (.I0(ram_init_addr[0]),
        .O(p_0_in__2[0]));
  (* SOFT_HLUTNM = "soft_lutpair649" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_buf_indx.rd_buf_indx_r[1]_i_1 
       (.I0(ram_init_addr[0]),
        .I1(ram_init_addr[1]),
        .O(p_0_in__2[1]));
  (* SOFT_HLUTNM = "soft_lutpair648" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rd_buf_indx.rd_buf_indx_r[2]_i_1 
       (.I0(ram_init_addr[0]),
        .I1(ram_init_addr[1]),
        .I2(ram_init_addr[2]),
        .O(p_0_in__2[2]));
  (* SOFT_HLUTNM = "soft_lutpair648" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \rd_buf_indx.rd_buf_indx_r[3]_i_1 
       (.I0(ram_init_addr[2]),
        .I1(ram_init_addr[1]),
        .I2(ram_init_addr[0]),
        .I3(ram_init_addr[3]),
        .O(p_0_in__2[3]));
  (* SOFT_HLUTNM = "soft_lutpair647" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \rd_buf_indx.rd_buf_indx_r[4]_i_1 
       (.I0(ram_init_addr[3]),
        .I1(ram_init_addr[0]),
        .I2(ram_init_addr[1]),
        .I3(ram_init_addr[2]),
        .I4(\rd_buf_indx.rd_buf_indx_r_reg ),
        .O(p_0_in__2[4]));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[0] 
       (.C(CLK),
        .CE(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .D(p_0_in__2[0]),
        .Q(ram_init_addr[0]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[1] 
       (.C(CLK),
        .CE(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .D(p_0_in__2[1]),
        .Q(ram_init_addr[1]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[2] 
       (.C(CLK),
        .CE(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .D(p_0_in__2[2]),
        .Q(ram_init_addr[2]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[3] 
       (.C(CLK),
        .CE(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .D(p_0_in__2[3]),
        .Q(ram_init_addr[3]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[4] 
       (.C(CLK),
        .CE(\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 ),
        .D(p_0_in__2[4]),
        .Q(\rd_buf_indx.rd_buf_indx_r_reg ),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hAA6AAAAAAAAAAAAA)) 
    \strict_mode.rd_data_buf_addr_r_lcl[2]_i_1 
       (.I0(\strict_mode.rd_data_buf_addr_r_lcl [2]),
        .I1(use_addr),
        .I2(app_cmd_r2[0]),
        .I3(app_cmd_r2[1]),
        .I4(\strict_mode.rd_data_buf_addr_r_lcl [0]),
        .I5(\strict_mode.rd_data_buf_addr_r_lcl [1]),
        .O(\strict_mode.rd_data_buf_addr_r_lcl[2]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \strict_mode.rd_data_buf_addr_r_lcl[3]_i_1 
       (.I0(\strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0 ),
        .I1(\strict_mode.rd_data_buf_addr_r_lcl [2]),
        .I2(\strict_mode.rd_data_buf_addr_r_lcl [3]),
        .O(\strict_mode.rd_data_buf_addr_r_lcl[3]_i_1_n_0 ));
  FDRE \strict_mode.rd_data_buf_addr_r_lcl_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ),
        .Q(\strict_mode.rd_data_buf_addr_r_lcl [0]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ));
  FDRE \strict_mode.rd_data_buf_addr_r_lcl_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0 ),
        .Q(\strict_mode.rd_data_buf_addr_r_lcl [1]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ));
  FDRE \strict_mode.rd_data_buf_addr_r_lcl_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\strict_mode.rd_data_buf_addr_r_lcl[2]_i_1_n_0 ),
        .Q(\strict_mode.rd_data_buf_addr_r_lcl [2]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ));
  FDRE \strict_mode.rd_data_buf_addr_r_lcl_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\strict_mode.rd_data_buf_addr_r_lcl[3]_i_1_n_0 ),
        .Q(\strict_mode.rd_data_buf_addr_r_lcl [3]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ui_top
   (app_rdy_r_reg,
    app_en_r2,
    \rd_buf_indx.ram_init_done_r_lcl_reg_inv ,
    app_wdf_rdy,
    \app_addr_r2_reg[24] ,
    \req_bank_r_lcl_reg[0] ,
    \app_addr_r2_reg[26] ,
    \app_addr_r2_reg[24]_0 ,
    \app_cmd_r2_reg[0] ,
    S,
    row,
    \app_addr_r1_reg[22] ,
    \req_row_r_lcl_reg[12] ,
    \req_row_r_lcl_reg[12]_0 ,
    \req_row_r_lcl_reg[12]_1 ,
    was_wr0,
    bank,
    req_wr_r_lcl0,
    D,
    \app_addr_r1_reg[9] ,
    \write_buffer.wr_buf_out_data_reg[0] ,
    Q,
    \write_buffer.wr_buf_out_data_reg[74] ,
    CLK,
    \pointer_ram.pointer_we ,
    wr_data_addr,
    E,
    rb_hit_busy_r_reg,
    req_bank_r,
    rb_hit_busy_r_reg_0,
    rb_hit_busy_r_reg_1,
    rb_hit_busy_r_reg_2,
    periodic_rd_ack_r,
    periodic_rd_cntr_r,
    periodic_rd_r,
    row_hit_r_reg,
    accept_ns,
    app_en,
    \wr_req_counter.wr_req_cnt_r_reg[0] ,
    app_wdf_wren,
    app_wdf_end,
    app_wdf_mask,
    app_wdf_data,
    \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ,
    \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ,
    \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ,
    app_addr,
    app_cmd);
  output app_rdy_r_reg;
  output app_en_r2;
  output [0:0]\rd_buf_indx.ram_init_done_r_lcl_reg_inv ;
  output app_wdf_rdy;
  output \app_addr_r2_reg[24] ;
  output \req_bank_r_lcl_reg[0] ;
  output \app_addr_r2_reg[26] ;
  output \app_addr_r2_reg[24]_0 ;
  output \app_cmd_r2_reg[0] ;
  output [2:0]S;
  output [13:0]row;
  output [0:0]\app_addr_r1_reg[22] ;
  output [0:0]\req_row_r_lcl_reg[12] ;
  output [0:0]\req_row_r_lcl_reg[12]_0 ;
  output [0:0]\req_row_r_lcl_reg[12]_1 ;
  output was_wr0;
  output [2:0]bank;
  output req_wr_r_lcl0;
  output [3:0]D;
  output [9:0]\app_addr_r1_reg[9] ;
  output [11:0]\write_buffer.wr_buf_out_data_reg[0] ;
  output [143:0]Q;
  output [11:0]\write_buffer.wr_buf_out_data_reg[74] ;
  input CLK;
  input \pointer_ram.pointer_we ;
  input [3:0]wr_data_addr;
  input [0:0]E;
  input rb_hit_busy_r_reg;
  input [11:0]req_bank_r;
  input rb_hit_busy_r_reg_0;
  input rb_hit_busy_r_reg_1;
  input rb_hit_busy_r_reg_2;
  input periodic_rd_ack_r;
  input periodic_rd_cntr_r;
  input periodic_rd_r;
  input [16:0]row_hit_r_reg;
  input accept_ns;
  input app_en;
  input \wr_req_counter.wr_req_cnt_r_reg[0] ;
  input app_wdf_wren;
  input app_wdf_end;
  input [15:0]app_wdf_mask;
  input [127:0]app_wdf_data;
  input \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ;
  input \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ;
  input \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ;
  input [26:0]app_addr;
  input [1:0]app_cmd;

  wire CLK;
  wire [3:0]D;
  wire [0:0]E;
  wire [143:0]Q;
  wire [2:0]S;
  wire accept_ns;
  wire [26:0]app_addr;
  wire [0:0]\app_addr_r1_reg[22] ;
  wire [9:0]\app_addr_r1_reg[9] ;
  wire \app_addr_r2_reg[24] ;
  wire \app_addr_r2_reg[24]_0 ;
  wire \app_addr_r2_reg[26] ;
  wire [1:0]app_cmd;
  wire [1:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0] ;
  wire app_en;
  wire app_en_r2;
  wire app_rdy_ns;
  wire app_rdy_r_reg;
  wire [127:0]app_wdf_data;
  wire app_wdf_end;
  wire [15:0]app_wdf_mask;
  wire app_wdf_rdy;
  wire app_wdf_wren;
  wire [2:0]bank;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ;
  wire [0:0]p_0_in;
  wire periodic_rd_ack_r;
  wire periodic_rd_cntr_r;
  wire periodic_rd_r;
  wire \pointer_ram.pointer_we ;
  wire [3:0]\pointer_ram.pointer_wr_addr ;
  wire [3:0]\pointer_ram.pointer_wr_data ;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rb_hit_busy_r_reg_2;
  wire [0:0]\rd_buf_indx.ram_init_done_r_lcl_reg_inv ;
  wire [3:0]\read_data_indx.rd_data_indx_r_reg ;
  wire [11:0]req_bank_r;
  wire \req_bank_r_lcl_reg[0] ;
  wire [0:0]\req_row_r_lcl_reg[12] ;
  wire [0:0]\req_row_r_lcl_reg[12]_0 ;
  wire [0:0]\req_row_r_lcl_reg[12]_1 ;
  wire req_wr_r_lcl0;
  wire [13:0]row;
  wire [16:0]row_hit_r_reg;
  wire [3:0]\strict_mode.rd_data_buf_addr_r_lcl ;
  wire ui_cmd0_n_40;
  wire ui_cmd0_n_41;
  wire ui_cmd0_n_42;
  wire ui_cmd0_n_43;
  wire ui_cmd0_n_44;
  wire use_addr;
  wire was_wr0;
  wire wr_accepted;
  wire [3:0]wr_data_addr;
  wire [3:0]wr_data_buf_addr;
  wire [0:0]\wr_req_counter.wr_req_cnt_r ;
  wire \wr_req_counter.wr_req_cnt_r_reg[0] ;
  wire [11:0]\write_buffer.wr_buf_out_data_reg[0] ;
  wire [11:0]\write_buffer.wr_buf_out_data_reg[74] ;

  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ui_cmd ui_cmd0
       (.CLK(CLK),
        .D(D),
        .E(app_rdy_r_reg),
        .S(S),
        .app_addr(app_addr),
        .\app_addr_r1_reg[0]_0 (\wr_req_counter.wr_req_cnt_r_reg[0] ),
        .\app_addr_r1_reg[22]_0 (\app_addr_r1_reg[22] ),
        .\app_addr_r1_reg[26]_0 (bank[2]),
        .\app_addr_r1_reg[9]_0 (\app_addr_r1_reg[9] ),
        .\app_addr_r2_reg[24]_0 (\app_addr_r2_reg[24] ),
        .\app_addr_r2_reg[24]_1 (\app_addr_r2_reg[24]_0 ),
        .\app_addr_r2_reg[26]_0 (\app_addr_r2_reg[26] ),
        .app_cmd(app_cmd),
        .app_cmd_r2(app_cmd_r2),
        .\app_cmd_r2_reg[0]_0 (\app_cmd_r2_reg[0] ),
        .app_en(app_en),
        .app_en_r2_reg_0(app_en_r2),
        .app_en_r2_reg_1(ui_cmd0_n_40),
        .app_rdy_ns(app_rdy_ns),
        .bank(bank[1:0]),
        .p_0_in(p_0_in),
        .periodic_rd_ack_r(periodic_rd_ack_r),
        .periodic_rd_cntr_r(periodic_rd_cntr_r),
        .periodic_rd_r(periodic_rd_r),
        .rb_hit_busy_r_reg(rb_hit_busy_r_reg),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_0),
        .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_1),
        .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg_2),
        .\read_data_indx.rd_data_upd_indx_r_reg (ui_cmd0_n_44),
        .req_bank_r(req_bank_r),
        .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0] ),
        .\req_row_r_lcl_reg[12] (\req_row_r_lcl_reg[12] ),
        .\req_row_r_lcl_reg[12]_0 (\req_row_r_lcl_reg[12]_0 ),
        .\req_row_r_lcl_reg[12]_1 (\req_row_r_lcl_reg[12]_1 ),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .row(row),
        .row_hit_r_reg(row_hit_r_reg),
        .\strict_mode.rd_data_buf_addr_r_lcl (\strict_mode.rd_data_buf_addr_r_lcl ),
        .\strict_mode.rd_data_buf_addr_r_lcl_reg[0] (ui_cmd0_n_41),
        .\strict_mode.rd_data_buf_addr_r_lcl_reg[1] (ui_cmd0_n_42),
        .use_addr(use_addr),
        .was_wr0(was_wr0),
        .wr_accepted(wr_accepted),
        .wr_data_buf_addr(wr_data_buf_addr),
        .\wr_req_counter.wr_req_cnt_r (\wr_req_counter.wr_req_cnt_r ),
        .\wr_req_counter.wr_req_cnt_r_reg[0] (ui_cmd0_n_43));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ui_rd_data ui_rd_data0
       (.ADDRD(\pointer_ram.pointer_wr_addr ),
        .CLK(CLK),
        .Q(\read_data_indx.rd_data_indx_r_reg ),
        .app_cmd_r2(app_cmd_r2),
        .\pointer_ram.pointer_wr_data (\pointer_ram.pointer_wr_data ),
        .\rd_buf_indx.ram_init_done_r_lcl_reg_inv_0 (\rd_buf_indx.ram_init_done_r_lcl_reg_inv ),
        .\strict_mode.rd_data_buf_addr_r_lcl (\strict_mode.rd_data_buf_addr_r_lcl ),
        .\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 (\wr_req_counter.wr_req_cnt_r_reg[0] ),
        .\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 (ui_cmd0_n_40),
        .\strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0 (ui_cmd0_n_41),
        .\strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0 (ui_cmd0_n_42),
        .use_addr(use_addr),
        .wr_data_addr(wr_data_addr));
  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ui_wr_data ui_wr_data0
       (.ADDRD(\pointer_ram.pointer_wr_addr ),
        .CLK(CLK),
        .E(E),
        .Q(\read_data_indx.rd_data_indx_r_reg ),
        .accept_ns(accept_ns),
        .app_rdy_ns(app_rdy_ns),
        .app_wdf_data(app_wdf_data),
        .app_wdf_end(app_wdf_end),
        .app_wdf_mask(app_wdf_mask),
        .app_wdf_rdy(app_wdf_rdy),
        .app_wdf_rdy_r_copy3_reg_0(\rd_buf_indx.ram_init_done_r_lcl_reg_inv ),
        .app_wdf_wren(app_wdf_wren),
        .\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 (\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ),
        .\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 (\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ),
        .\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 (\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ),
        .p_0_in(p_0_in),
        .\pointer_ram.pointer_we (\pointer_ram.pointer_we ),
        .\pointer_ram.pointer_wr_data (\pointer_ram.pointer_wr_data ),
        .wr_accepted(wr_accepted),
        .wr_data_addr(wr_data_addr),
        .wr_data_buf_addr(wr_data_buf_addr),
        .\wr_req_counter.wr_req_cnt_r_reg[0]_0 (\wr_req_counter.wr_req_cnt_r ),
        .\wr_req_counter.wr_req_cnt_r_reg[0]_1 (ui_cmd0_n_43),
        .\wr_req_counter.wr_req_cnt_r_reg[0]_2 (\wr_req_counter.wr_req_cnt_r_reg[0] ),
        .\wr_req_counter.wr_req_cnt_r_reg[4]_0 (ui_cmd0_n_44),
        .\write_buffer.wr_buf_out_data_reg[0]_0 (\write_buffer.wr_buf_out_data_reg[0] ),
        .\write_buffer.wr_buf_out_data_reg[143]_0 (Q),
        .\write_buffer.wr_buf_out_data_reg[74]_0 (\write_buffer.wr_buf_out_data_reg[74] ));
endmodule

module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mig_7series_v4_2_ui_wr_data
   (wr_data_buf_addr,
    p_0_in,
    app_wdf_rdy,
    app_rdy_ns,
    \wr_req_counter.wr_req_cnt_r_reg[0]_0 ,
    Q,
    \write_buffer.wr_buf_out_data_reg[0]_0 ,
    \write_buffer.wr_buf_out_data_reg[143]_0 ,
    \write_buffer.wr_buf_out_data_reg[74]_0 ,
    CLK,
    \pointer_ram.pointer_we ,
    \pointer_ram.pointer_wr_data ,
    ADDRD,
    wr_data_addr,
    E,
    \wr_req_counter.wr_req_cnt_r_reg[0]_1 ,
    accept_ns,
    wr_accepted,
    \wr_req_counter.wr_req_cnt_r_reg[4]_0 ,
    \wr_req_counter.wr_req_cnt_r_reg[0]_2 ,
    app_wdf_wren,
    app_wdf_end,
    app_wdf_rdy_r_copy3_reg_0,
    app_wdf_mask,
    app_wdf_data,
    \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ,
    \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ,
    \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 );
  output [3:0]wr_data_buf_addr;
  output [0:0]p_0_in;
  output app_wdf_rdy;
  output app_rdy_ns;
  output [0:0]\wr_req_counter.wr_req_cnt_r_reg[0]_0 ;
  output [3:0]Q;
  output [11:0]\write_buffer.wr_buf_out_data_reg[0]_0 ;
  output [143:0]\write_buffer.wr_buf_out_data_reg[143]_0 ;
  output [11:0]\write_buffer.wr_buf_out_data_reg[74]_0 ;
  input CLK;
  input \pointer_ram.pointer_we ;
  input [3:0]\pointer_ram.pointer_wr_data ;
  input [3:0]ADDRD;
  input [3:0]wr_data_addr;
  input [0:0]E;
  input \wr_req_counter.wr_req_cnt_r_reg[0]_1 ;
  input accept_ns;
  input wr_accepted;
  input \wr_req_counter.wr_req_cnt_r_reg[4]_0 ;
  input \wr_req_counter.wr_req_cnt_r_reg[0]_2 ;
  input app_wdf_wren;
  input app_wdf_end;
  input [0:0]app_wdf_rdy_r_copy3_reg_0;
  input [15:0]app_wdf_mask;
  input [127:0]app_wdf_data;
  input \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ;
  input \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ;
  input \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ;

  wire [3:0]ADDRD;
  wire CLK;
  wire [0:0]E;
  wire [3:0]Q;
  wire accept_ns;
  wire app_rdy_ns;
  wire app_rdy_r_i_2_n_0;
  wire [127:0]app_wdf_data;
  wire [127:0]app_wdf_data_r1;
  wire app_wdf_end;
  wire app_wdf_end_ns1;
  wire app_wdf_end_r1;
  wire [15:0]app_wdf_mask;
  wire [15:0]app_wdf_mask_r1;
  wire app_wdf_rdy;
  wire app_wdf_rdy_r_copy1;
  wire app_wdf_rdy_r_copy2;
  wire app_wdf_rdy_r_copy3;
  wire [0:0]app_wdf_rdy_r_copy3_reg_0;
  wire app_wdf_wren;
  wire app_wdf_wren_ns1;
  wire app_wdf_wren_r1;
  wire [3:0]\data_buf_address_counter.data_buf_addr_cnt_r_reg ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ;
  wire \occupied_counter.occ_cnt[15]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt_reg_n_0_[0] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[10] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[11] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[12] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[13] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[15] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[1] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[2] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[3] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[4] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[5] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[6] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[7] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[8] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[9] ;
  wire [0:0]p_0_in;
  wire [3:0]p_0_in__0;
  wire [1:1]p_0_in__0_0;
  wire [3:0]p_0_in__0__0;
  wire [3:0]p_0_in__1;
  wire [15:0]p_1_in_0;
  wire p_4_in;
  wire \pointer_ram.pointer_we ;
  wire [3:0]\pointer_ram.pointer_wr_data ;
  wire [4:1]wb_wr_data_addr_w;
  wire wdf_rdy_ns;
  wire wr_accepted;
  wire [143:0]wr_buf_out_data_w;
  wire [3:0]wr_data_addr;
  wire [3:0]wr_data_buf_addr;
  wire [3:0]wr_data_pntr;
  wire [4:1]\wr_req_counter.wr_req_cnt_r ;
  wire \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ;
  wire [0:0]\wr_req_counter.wr_req_cnt_r_reg[0]_0 ;
  wire \wr_req_counter.wr_req_cnt_r_reg[0]_1 ;
  wire \wr_req_counter.wr_req_cnt_r_reg[0]_2 ;
  wire \wr_req_counter.wr_req_cnt_r_reg[4]_0 ;
  wire [143:0]\write_buffer.wr_buf_in_data ;
  wire [11:0]\write_buffer.wr_buf_out_data_reg[0]_0 ;
  wire [143:0]\write_buffer.wr_buf_out_data_reg[143]_0 ;
  wire [11:0]\write_buffer.wr_buf_out_data_reg[74]_0 ;
  wire \write_data_control.wb_wr_data_addr0_ns ;
  wire \write_data_control.wb_wr_data_addr0_r ;
  wire [4:1]\write_data_control.wb_wr_data_addr_r ;
  wire \write_data_control.wr_data_addr_le ;
  wire \write_data_control.wr_data_indx_r[3]_i_3_n_0 ;
  wire [3:0]\write_data_control.wr_data_indx_r_reg ;
  wire [1:0]\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED ;
  wire [1:0]\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED ;
  wire [1:0]\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ;

  LUT6 #(
    .INIT(64'hFFFF0000FFFE0000)) 
    app_rdy_r_i_1
       (.I0(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ),
        .I2(\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ),
        .I3(app_rdy_r_i_2_n_0),
        .I4(accept_ns),
        .I5(\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ),
        .O(app_rdy_ns));
  LUT6 #(
    .INIT(64'hEAAAAAAEBFFFFFFB)) 
    app_rdy_r_i_2
       (.I0(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[4]_0 ),
        .I2(\wr_req_counter.wr_req_cnt_r [3]),
        .I3(\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ),
        .I4(\wr_req_counter.wr_req_cnt_r [2]),
        .I5(\wr_req_counter.wr_req_cnt_r [4]),
        .O(app_rdy_r_i_2_n_0));
  FDRE \app_wdf_data_r1_reg[0] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[0]),
        .Q(app_wdf_data_r1[0]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[100] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[100]),
        .Q(app_wdf_data_r1[100]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[101] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[101]),
        .Q(app_wdf_data_r1[101]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[102] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[102]),
        .Q(app_wdf_data_r1[102]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[103] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[103]),
        .Q(app_wdf_data_r1[103]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[104] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[104]),
        .Q(app_wdf_data_r1[104]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[105] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[105]),
        .Q(app_wdf_data_r1[105]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[106] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[106]),
        .Q(app_wdf_data_r1[106]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[107] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[107]),
        .Q(app_wdf_data_r1[107]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[108] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[108]),
        .Q(app_wdf_data_r1[108]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[109] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[109]),
        .Q(app_wdf_data_r1[109]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[10] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[10]),
        .Q(app_wdf_data_r1[10]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[110] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[110]),
        .Q(app_wdf_data_r1[110]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[111] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[111]),
        .Q(app_wdf_data_r1[111]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[112] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[112]),
        .Q(app_wdf_data_r1[112]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[113] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[113]),
        .Q(app_wdf_data_r1[113]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[114] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[114]),
        .Q(app_wdf_data_r1[114]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[115] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[115]),
        .Q(app_wdf_data_r1[115]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[116] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[116]),
        .Q(app_wdf_data_r1[116]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[117] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[117]),
        .Q(app_wdf_data_r1[117]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[118] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[118]),
        .Q(app_wdf_data_r1[118]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[119] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[119]),
        .Q(app_wdf_data_r1[119]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[11] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[11]),
        .Q(app_wdf_data_r1[11]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[120] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[120]),
        .Q(app_wdf_data_r1[120]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[121] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[121]),
        .Q(app_wdf_data_r1[121]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[122] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[122]),
        .Q(app_wdf_data_r1[122]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[123] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[123]),
        .Q(app_wdf_data_r1[123]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[124] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[124]),
        .Q(app_wdf_data_r1[124]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[125] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[125]),
        .Q(app_wdf_data_r1[125]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[126] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[126]),
        .Q(app_wdf_data_r1[126]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[127] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[127]),
        .Q(app_wdf_data_r1[127]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[12] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[12]),
        .Q(app_wdf_data_r1[12]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[13] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[13]),
        .Q(app_wdf_data_r1[13]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[14] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[14]),
        .Q(app_wdf_data_r1[14]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[15] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[15]),
        .Q(app_wdf_data_r1[15]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[16] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[16]),
        .Q(app_wdf_data_r1[16]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[17] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[17]),
        .Q(app_wdf_data_r1[17]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[18] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[18]),
        .Q(app_wdf_data_r1[18]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[19] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[19]),
        .Q(app_wdf_data_r1[19]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[1] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[1]),
        .Q(app_wdf_data_r1[1]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[20] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[20]),
        .Q(app_wdf_data_r1[20]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[21] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[21]),
        .Q(app_wdf_data_r1[21]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[22] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[22]),
        .Q(app_wdf_data_r1[22]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[23] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[23]),
        .Q(app_wdf_data_r1[23]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[24] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[24]),
        .Q(app_wdf_data_r1[24]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[25] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[25]),
        .Q(app_wdf_data_r1[25]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[26] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[26]),
        .Q(app_wdf_data_r1[26]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[27] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[27]),
        .Q(app_wdf_data_r1[27]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[28] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[28]),
        .Q(app_wdf_data_r1[28]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[29] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[29]),
        .Q(app_wdf_data_r1[29]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[2] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[2]),
        .Q(app_wdf_data_r1[2]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[30] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[30]),
        .Q(app_wdf_data_r1[30]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[31] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[31]),
        .Q(app_wdf_data_r1[31]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[32] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[32]),
        .Q(app_wdf_data_r1[32]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[33] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[33]),
        .Q(app_wdf_data_r1[33]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[34] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[34]),
        .Q(app_wdf_data_r1[34]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[35] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[35]),
        .Q(app_wdf_data_r1[35]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[36] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[36]),
        .Q(app_wdf_data_r1[36]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[37] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[37]),
        .Q(app_wdf_data_r1[37]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[38] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[38]),
        .Q(app_wdf_data_r1[38]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[39] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[39]),
        .Q(app_wdf_data_r1[39]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[3] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[3]),
        .Q(app_wdf_data_r1[3]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[40] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[40]),
        .Q(app_wdf_data_r1[40]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[41] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[41]),
        .Q(app_wdf_data_r1[41]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[42] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[42]),
        .Q(app_wdf_data_r1[42]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[43] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[43]),
        .Q(app_wdf_data_r1[43]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[44] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[44]),
        .Q(app_wdf_data_r1[44]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[45] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[45]),
        .Q(app_wdf_data_r1[45]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[46] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[46]),
        .Q(app_wdf_data_r1[46]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[47] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[47]),
        .Q(app_wdf_data_r1[47]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[48] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[48]),
        .Q(app_wdf_data_r1[48]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[49] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[49]),
        .Q(app_wdf_data_r1[49]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[4] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[4]),
        .Q(app_wdf_data_r1[4]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[50] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[50]),
        .Q(app_wdf_data_r1[50]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[51] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[51]),
        .Q(app_wdf_data_r1[51]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[52] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[52]),
        .Q(app_wdf_data_r1[52]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[53] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[53]),
        .Q(app_wdf_data_r1[53]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[54] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[54]),
        .Q(app_wdf_data_r1[54]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[55] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[55]),
        .Q(app_wdf_data_r1[55]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[56] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[56]),
        .Q(app_wdf_data_r1[56]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[57] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[57]),
        .Q(app_wdf_data_r1[57]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[58] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[58]),
        .Q(app_wdf_data_r1[58]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[59] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[59]),
        .Q(app_wdf_data_r1[59]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[5] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[5]),
        .Q(app_wdf_data_r1[5]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[60] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[60]),
        .Q(app_wdf_data_r1[60]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[61] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[61]),
        .Q(app_wdf_data_r1[61]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[62] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[62]),
        .Q(app_wdf_data_r1[62]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[63] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[63]),
        .Q(app_wdf_data_r1[63]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[64] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[64]),
        .Q(app_wdf_data_r1[64]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[65] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[65]),
        .Q(app_wdf_data_r1[65]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[66] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[66]),
        .Q(app_wdf_data_r1[66]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[67] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[67]),
        .Q(app_wdf_data_r1[67]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[68] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[68]),
        .Q(app_wdf_data_r1[68]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[69] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[69]),
        .Q(app_wdf_data_r1[69]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[6] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[6]),
        .Q(app_wdf_data_r1[6]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[70] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[70]),
        .Q(app_wdf_data_r1[70]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[71] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[71]),
        .Q(app_wdf_data_r1[71]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[72] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[72]),
        .Q(app_wdf_data_r1[72]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[73] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[73]),
        .Q(app_wdf_data_r1[73]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[74] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[74]),
        .Q(app_wdf_data_r1[74]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[75] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[75]),
        .Q(app_wdf_data_r1[75]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[76] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[76]),
        .Q(app_wdf_data_r1[76]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[77] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[77]),
        .Q(app_wdf_data_r1[77]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[78] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[78]),
        .Q(app_wdf_data_r1[78]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[79] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[79]),
        .Q(app_wdf_data_r1[79]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[7] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[7]),
        .Q(app_wdf_data_r1[7]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[80] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[80]),
        .Q(app_wdf_data_r1[80]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[81] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[81]),
        .Q(app_wdf_data_r1[81]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[82] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[82]),
        .Q(app_wdf_data_r1[82]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[83] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[83]),
        .Q(app_wdf_data_r1[83]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[84] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[84]),
        .Q(app_wdf_data_r1[84]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[85] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[85]),
        .Q(app_wdf_data_r1[85]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[86] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[86]),
        .Q(app_wdf_data_r1[86]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[87] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[87]),
        .Q(app_wdf_data_r1[87]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[88] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[88]),
        .Q(app_wdf_data_r1[88]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[89] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[89]),
        .Q(app_wdf_data_r1[89]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[8] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[8]),
        .Q(app_wdf_data_r1[8]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[90] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[90]),
        .Q(app_wdf_data_r1[90]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[91] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[91]),
        .Q(app_wdf_data_r1[91]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[92] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[92]),
        .Q(app_wdf_data_r1[92]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[93] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[93]),
        .Q(app_wdf_data_r1[93]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[94] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[94]),
        .Q(app_wdf_data_r1[94]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[95] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[95]),
        .Q(app_wdf_data_r1[95]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[96] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[96]),
        .Q(app_wdf_data_r1[96]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[97] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[97]),
        .Q(app_wdf_data_r1[97]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[98] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[98]),
        .Q(app_wdf_data_r1[98]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[99] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[99]),
        .Q(app_wdf_data_r1[99]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[9] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[9]),
        .Q(app_wdf_data_r1[9]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h2230)) 
    app_wdf_end_r1_i_1
       (.I0(app_wdf_end),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy2),
        .O(app_wdf_end_ns1));
  FDRE app_wdf_end_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_wdf_end_ns1),
        .Q(app_wdf_end_r1),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[0] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[0]),
        .Q(app_wdf_mask_r1[0]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[10] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[10]),
        .Q(app_wdf_mask_r1[10]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[11] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[11]),
        .Q(app_wdf_mask_r1[11]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[12] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[12]),
        .Q(app_wdf_mask_r1[12]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[13] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[13]),
        .Q(app_wdf_mask_r1[13]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[14] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[14]),
        .Q(app_wdf_mask_r1[14]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[15] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[15]),
        .Q(app_wdf_mask_r1[15]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[1] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[1]),
        .Q(app_wdf_mask_r1[1]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[2] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[2]),
        .Q(app_wdf_mask_r1[2]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[3] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[3]),
        .Q(app_wdf_mask_r1[3]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[4] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[4]),
        .Q(app_wdf_mask_r1[4]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[5] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[5]),
        .Q(app_wdf_mask_r1[5]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[6] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[6]),
        .Q(app_wdf_mask_r1[6]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[7] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[7]),
        .Q(app_wdf_mask_r1[7]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[8] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[8]),
        .Q(app_wdf_mask_r1[8]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[9] 
       (.C(CLK),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[9]),
        .Q(app_wdf_mask_r1[9]),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE app_wdf_rdy_r_copy1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wdf_rdy_ns),
        .Q(app_wdf_rdy_r_copy1),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE app_wdf_rdy_r_copy2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wdf_rdy_ns),
        .Q(app_wdf_rdy_r_copy2),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE app_wdf_rdy_r_copy3_reg
       (.C(CLK),
        .CE(1'b1),
        .D(wdf_rdy_ns),
        .Q(app_wdf_rdy_r_copy3),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h2230)) 
    app_wdf_wren_r1_i_1
       (.I0(app_wdf_wren),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_rdy_r_copy2),
        .O(app_wdf_wren_ns1));
  FDRE app_wdf_wren_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(app_wdf_wren_ns1),
        .Q(app_wdf_wren_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair657" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1 
       (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg [0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair657" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1 
       (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg [0]),
        .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg [1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair654" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1 
       (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg [0]),
        .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg [1]),
        .I2(\data_buf_address_counter.data_buf_addr_cnt_r_reg [2]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair654" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2 
       (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg [2]),
        .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg [1]),
        .I2(\data_buf_address_counter.data_buf_addr_cnt_r_reg [0]),
        .I3(\data_buf_address_counter.data_buf_addr_cnt_r_reg [3]),
        .O(p_0_in__0[3]));
  FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[0] 
       (.C(CLK),
        .CE(wr_accepted),
        .D(p_0_in__0[0]),
        .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg [0]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[1] 
       (.C(CLK),
        .CE(wr_accepted),
        .D(p_0_in__0[1]),
        .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg [1]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[2] 
       (.C(CLK),
        .CE(wr_accepted),
        .D(p_0_in__0[2]),
        .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg [2]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[3] 
       (.C(CLK),
        .CE(wr_accepted),
        .D(p_0_in__0[3]),
        .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg [3]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_0_5_i_3
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [4]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ),
        .O(\write_buffer.wr_buf_out_data_reg[0]_0 [0]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_12_17_i_6
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [12]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ),
        .O(\write_buffer.wr_buf_out_data_reg[74]_0 [1]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_1
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [54]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ),
        .O(\write_buffer.wr_buf_out_data_reg[0]_0 [1]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_18_23_i_4
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [70]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[0]_0 [2]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_24_29_i_2__1
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [3]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ),
        .O(\write_buffer.wr_buf_out_data_reg[0]_0 [3]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_24_29_i_3__0
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [62]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ),
        .O(\write_buffer.wr_buf_out_data_reg[74]_0 [2]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_24_29_i_5
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [83]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[0]_0 [4]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_24_29_i_6__0
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [78]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[74]_0 [3]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_30_35_i_6
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [33]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ),
        .O(\write_buffer.wr_buf_out_data_reg[0]_0 [5]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_30_35_i_6__0
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [41]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ),
        .O(\write_buffer.wr_buf_out_data_reg[74]_0 [4]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_36_41_i_6__0
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [11]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ),
        .O(\write_buffer.wr_buf_out_data_reg[74]_0 [5]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_2__1
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [37]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ),
        .O(\write_buffer.wr_buf_out_data_reg[0]_0 [6]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_3__0
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [91]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[74]_0 [6]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_2__1
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [15]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ),
        .O(\write_buffer.wr_buf_out_data_reg[74]_0 [7]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_3
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [50]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ),
        .O(\write_buffer.wr_buf_out_data_reg[0]_0 [7]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_5__0
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [95]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[74]_0 [8]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_6
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [66]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[0]_0 [8]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_4__0
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [7]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ),
        .O(\write_buffer.wr_buf_out_data_reg[0]_0 [9]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_6__0
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [45]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ),
        .O(\write_buffer.wr_buf_out_data_reg[74]_0 [9]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_60_65_i_1__1
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [87]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[0]_0 [10]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_6_11_i_3__0
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [8]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ),
        .O(\write_buffer.wr_buf_out_data_reg[74]_0 [0]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_72_77_i_2__1
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [0]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53 ),
        .O(\write_buffer.wr_buf_out_data_reg[0]_0 [11]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_72_77_i_3__0
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [58]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_24_29 ),
        .O(\write_buffer.wr_buf_out_data_reg[74]_0 [10]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_72_77_i_6__0
       (.I0(\write_buffer.wr_buf_out_data_reg[143]_0 [74]),
        .I1(\ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg_0_15_48_53_0 ),
        .O(\write_buffer.wr_buf_out_data_reg[74]_0 [11]));
  LUT6 #(
    .INIT(64'h0500050105010501)) 
    \occupied_counter.app_wdf_rdy_r_i_1 
       (.I0(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ),
        .I1(\occupied_counter.occ_cnt_reg_n_0_[15] ),
        .I2(app_wdf_rdy_r_copy3_reg_0),
        .I3(p_0_in),
        .I4(p_4_in),
        .I5(p_0_in__0_0),
        .O(wdf_rdy_ns));
  (* SOFT_HLUTNM = "soft_lutpair651" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \occupied_counter.app_wdf_rdy_r_i_2 
       (.I0(app_wdf_wren_r1),
        .I1(app_wdf_end_r1),
        .I2(app_wdf_rdy_r_copy1),
        .O(p_0_in__0_0));
  (* equivalent_register_removal = "no" *) 
  FDRE \occupied_counter.app_wdf_rdy_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(wdf_rdy_ns),
        .Q(app_wdf_rdy),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair652" *) 
  LUT4 #(
    .INIT(16'hFF80)) 
    \occupied_counter.occ_cnt[0]_i_1 
       (.I0(app_wdf_rdy_r_copy1),
        .I1(app_wdf_end_r1),
        .I2(app_wdf_wren_r1),
        .I3(\occupied_counter.occ_cnt_reg_n_0_[1] ),
        .O(p_1_in_0[0]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[10]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[9] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[11] ),
        .O(p_1_in_0[10]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[11]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[10] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[12] ),
        .O(p_1_in_0[11]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[12]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[11] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[13] ),
        .O(p_1_in_0[12]));
  (* SOFT_HLUTNM = "soft_lutpair653" *) 
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[13]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[12] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(p_4_in),
        .O(p_1_in_0[13]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[14]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[13] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[15] ),
        .O(p_1_in_0[14]));
  LUT4 #(
    .INIT(16'h6AAA)) 
    \occupied_counter.occ_cnt[15]_i_1 
       (.I0(p_0_in),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_wren_r1),
        .O(\occupied_counter.occ_cnt[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair653" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \occupied_counter.occ_cnt[15]_i_2 
       (.I0(app_wdf_rdy_r_copy1),
        .I1(app_wdf_end_r1),
        .I2(app_wdf_wren_r1),
        .I3(p_4_in),
        .O(p_1_in_0[15]));
  (* SOFT_HLUTNM = "soft_lutpair651" *) 
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[1]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[0] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[2] ),
        .O(p_1_in_0[1]));
  (* SOFT_HLUTNM = "soft_lutpair652" *) 
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[2]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[1] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[3] ),
        .O(p_1_in_0[2]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[3]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[2] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[4] ),
        .O(p_1_in_0[3]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[4]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[3] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[5] ),
        .O(p_1_in_0[4]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[5]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[4] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[6] ),
        .O(p_1_in_0[5]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[6]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[5] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[7] ),
        .O(p_1_in_0[6]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[7]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[6] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[8] ),
        .O(p_1_in_0[7]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[8]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[7] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[9] ),
        .O(p_1_in_0[8]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[9]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[8] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[10] ),
        .O(p_1_in_0[9]));
  FDRE \occupied_counter.occ_cnt_reg[0] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[0]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[0] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[10] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[10]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[10] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[11] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[11]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[11] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[12] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[12]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[12] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[13] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[13]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[13] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[14] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[14]),
        .Q(p_4_in),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[15] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[15]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[15] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[1] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[1]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[1] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[2] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[2]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[2] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[3] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[3]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[3] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[4] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[4]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[4] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[5] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[5]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[5] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[6] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[6]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[6] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[7] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[7]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[7] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[8] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[8]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[8] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \occupied_counter.occ_cnt_reg[9] 
       (.C(CLK),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in_0[9]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[9] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \pointer_ram.rams[0].RAM32M0 
       (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ADDRB({1'b0,\data_buf_address_counter.data_buf_addr_cnt_r_reg }),
        .ADDRC({1'b0,\write_data_control.wr_data_indx_r_reg }),
        .ADDRD({1'b0,ADDRD}),
        .DIA({1'b0,1'b0}),
        .DIB(\pointer_ram.pointer_wr_data [1:0]),
        .DIC(\pointer_ram.pointer_wr_data [1:0]),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED [1:0]),
        .DOB(wr_data_buf_addr[1:0]),
        .DOC(wr_data_pntr[1:0]),
        .DOD(\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(\pointer_ram.pointer_we ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \pointer_ram.rams[1].RAM32M0 
       (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ADDRB({1'b0,\data_buf_address_counter.data_buf_addr_cnt_r_reg }),
        .ADDRC({1'b0,\write_data_control.wr_data_indx_r_reg }),
        .ADDRD({1'b0,ADDRD}),
        .DIA({1'b0,1'b0}),
        .DIB(\pointer_ram.pointer_wr_data [3:2]),
        .DIC(\pointer_ram.pointer_wr_data [3:2]),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED [1:0]),
        .DOB(wr_data_buf_addr[3:2]),
        .DOC(wr_data_pntr[3:2]),
        .DOD(\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(\pointer_ram.pointer_we ));
  (* SOFT_HLUTNM = "soft_lutpair658" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \read_data_indx.rd_data_indx_r[0]_i_1 
       (.I0(Q[0]),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair658" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \read_data_indx.rd_data_indx_r[1]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair656" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \read_data_indx.rd_data_indx_r[2]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair656" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \read_data_indx.rd_data_indx_r[3]_i_1 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(p_0_in__1[3]));
  FDRE \read_data_indx.rd_data_indx_r_reg[0] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in__1[0]),
        .Q(Q[0]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \read_data_indx.rd_data_indx_r_reg[1] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in__1[1]),
        .Q(Q[1]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \read_data_indx.rd_data_indx_r_reg[2] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in__1[2]),
        .Q(Q[2]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \read_data_indx.rd_data_indx_r_reg[3] 
       (.C(CLK),
        .CE(E),
        .D(p_0_in__1[3]),
        .Q(Q[3]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \read_data_indx.rd_data_upd_indx_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(E),
        .Q(p_0_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair650" *) 
  LUT4 #(
    .INIT(16'hDB24)) 
    \wr_req_counter.wr_req_cnt_r[1]_i_1 
       (.I0(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .I1(p_0_in),
        .I2(wr_accepted),
        .I3(\wr_req_counter.wr_req_cnt_r [1]),
        .O(\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair650" *) 
  LUT5 #(
    .INIT(32'hF7EF0810)) 
    \wr_req_counter.wr_req_cnt_r[2]_i_1 
       (.I0(\wr_req_counter.wr_req_cnt_r [1]),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .I2(p_0_in),
        .I3(wr_accepted),
        .I4(\wr_req_counter.wr_req_cnt_r [2]),
        .O(\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF7FFEFF00800100)) 
    \wr_req_counter.wr_req_cnt_r[3]_i_1 
       (.I0(\wr_req_counter.wr_req_cnt_r [1]),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .I2(\wr_req_counter.wr_req_cnt_r [2]),
        .I3(p_0_in),
        .I4(wr_accepted),
        .I5(\wr_req_counter.wr_req_cnt_r [3]),
        .O(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000006AA9AAAA)) 
    \wr_req_counter.wr_req_cnt_r[4]_i_1 
       (.I0(\wr_req_counter.wr_req_cnt_r [4]),
        .I1(\wr_req_counter.wr_req_cnt_r [2]),
        .I2(\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ),
        .I3(\wr_req_counter.wr_req_cnt_r [3]),
        .I4(\wr_req_counter.wr_req_cnt_r_reg[4]_0 ),
        .I5(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ),
        .O(\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hD554)) 
    \wr_req_counter.wr_req_cnt_r[4]_i_2 
       (.I0(\wr_req_counter.wr_req_cnt_r [2]),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .I2(\wr_req_counter.wr_req_cnt_r [1]),
        .I3(wr_accepted),
        .O(\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ),
        .Q(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ),
        .Q(\wr_req_counter.wr_req_cnt_r [1]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ),
        .Q(\wr_req_counter.wr_req_cnt_r [2]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ),
        .Q(\wr_req_counter.wr_req_cnt_r [3]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ),
        .Q(\wr_req_counter.wr_req_cnt_r [4]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[0]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [0]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[100] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[100]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [100]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[101] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[101]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [101]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[102] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[102]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [102]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[103] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[103]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [103]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[104] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[104]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [104]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[105] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[105]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [105]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[106] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[106]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [106]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[107] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[107]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [107]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[108] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[108]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [108]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[109] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[109]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [109]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[10]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [10]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[110] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[110]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [110]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[111] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[111]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [111]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[112] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[112]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [112]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[113] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[113]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [113]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[114] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[114]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [114]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[115] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[115]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [115]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[116] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[116]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [116]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[117] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[117]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [117]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[118] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[118]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [118]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[119] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[119]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [119]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[11]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [11]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[120] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[120]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [120]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[121] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[121]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [121]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[122] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[122]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [122]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[123] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[123]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [123]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[124] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[124]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [124]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[125] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[125]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [125]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[126] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[126]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [126]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[127] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[127]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [127]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[128] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[128]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [128]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[129] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[129]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [129]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[12]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [12]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[130] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[130]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [130]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[131] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[131]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [131]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[132] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[132]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [132]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[133] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[133]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [133]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[134] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[134]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [134]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[135] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[135]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [135]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[136] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[136]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [136]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[137] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[137]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [137]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[138] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[138]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [138]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[139] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[139]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [139]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[13]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [13]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[140] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[140]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [140]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[141] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[141]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [141]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[142] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[142]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [142]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[143] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[143]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [143]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[14]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [14]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[15]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [15]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[16]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [16]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[17]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [17]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[18]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [18]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[19]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [19]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[1]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [1]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[20]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [20]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[21]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [21]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[22]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [22]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[23]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [23]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[24]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [24]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[25]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [25]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[26]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [26]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[27]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [27]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[28]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [28]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[29]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [29]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[2]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [2]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[30]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [30]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[31]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [31]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[32] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[32]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [32]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[33] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[33]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [33]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[34] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[34]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [34]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[35] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[35]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [35]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[36] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[36]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [36]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[37] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[37]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [37]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[38] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[38]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [38]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[39] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[39]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [39]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[3]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [3]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[40] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[40]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [40]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[41] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[41]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [41]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[42] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[42]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [42]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[43] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[43]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [43]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[44] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[44]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [44]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[45] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[45]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [45]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[46] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[46]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [46]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[47] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[47]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [47]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[48] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[48]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [48]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[49] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[49]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [49]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[4]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [4]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[50] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[50]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [50]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[51] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[51]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [51]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[52] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[52]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [52]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[53] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[53]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [53]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[54] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[54]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [54]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[55] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[55]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [55]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[56] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[56]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [56]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[57] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[57]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [57]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[58] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[58]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [58]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[59] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[59]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [59]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[5]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [5]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[60] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[60]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [60]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[61] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[61]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [61]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[62] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[62]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [62]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[63] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[63]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [63]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[64] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[64]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [64]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[65] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[65]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [65]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[66] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[66]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [66]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[67] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[67]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [67]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[68] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[68]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [68]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[69] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[69]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [69]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[6]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [6]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[70] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[70]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [70]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[71] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[71]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [71]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[72] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[72]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [72]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[73] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[73]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [73]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[74] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[74]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [74]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[75] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[75]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [75]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[76] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[76]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [76]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[77] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[77]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [77]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[78] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[78]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [78]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[79] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[79]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [79]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[7]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [7]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[80] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[80]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [80]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[81] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[81]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [81]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[82] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[82]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [82]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[83] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[83]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [83]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[84] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[84]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [84]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[85] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[85]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [85]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[86] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[86]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [86]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[87] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[87]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [87]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[88] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[88]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [88]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[89] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[89]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [89]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[8]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [8]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[90] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[90]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [90]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[91] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[91]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [91]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[92] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[92]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [92]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[93] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[93]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [93]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[94] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[94]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [94]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[95] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[95]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [95]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[96] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[96]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [96]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[97] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[97]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [97]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[98] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[98]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [98]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[99] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[99]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [99]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(wr_buf_out_data_w[9]),
        .Q(\write_buffer.wr_buf_out_data_reg[143]_0 [9]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [5:4]),
        .DIB(\write_buffer.wr_buf_in_data [3:2]),
        .DIC(\write_buffer.wr_buf_in_data [1:0]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[5:4]),
        .DOB(wr_buf_out_data_w[3:2]),
        .DOC(wr_buf_out_data_w[1:0]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_1 
       (.I0(app_wdf_data[5]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[5]),
        .O(\write_buffer.wr_buf_in_data [5]));
  LUT4 #(
    .INIT(16'h00AC)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_10 
       (.I0(wr_data_pntr[0]),
        .I1(\write_data_control.wb_wr_data_addr_r [1]),
        .I2(\write_data_control.wr_data_addr_le ),
        .I3(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ),
        .O(wb_wr_data_addr_w[1]));
  LUT5 #(
    .INIT(32'h02020F00)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_11 
       (.I0(app_wdf_rdy_r_copy3),
        .I1(app_wdf_end_r1),
        .I2(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ),
        .I3(\write_data_control.wb_wr_data_addr0_r ),
        .I4(app_wdf_wren_r1),
        .O(\write_data_control.wb_wr_data_addr0_ns ));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_2 
       (.I0(app_wdf_data[4]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[4]),
        .O(\write_buffer.wr_buf_in_data [4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_3 
       (.I0(app_wdf_data[3]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[3]),
        .O(\write_buffer.wr_buf_in_data [3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_4 
       (.I0(app_wdf_data[2]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[2]),
        .O(\write_buffer.wr_buf_in_data [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_5 
       (.I0(app_wdf_data[1]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[1]),
        .O(\write_buffer.wr_buf_in_data [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_6 
       (.I0(app_wdf_data[0]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[0]),
        .O(\write_buffer.wr_buf_in_data [0]));
  LUT4 #(
    .INIT(16'h00AC)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_7 
       (.I0(wr_data_pntr[3]),
        .I1(\write_data_control.wb_wr_data_addr_r [4]),
        .I2(\write_data_control.wr_data_addr_le ),
        .I3(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ),
        .O(wb_wr_data_addr_w[4]));
  LUT4 #(
    .INIT(16'h00AC)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_8 
       (.I0(wr_data_pntr[2]),
        .I1(\write_data_control.wb_wr_data_addr_r [3]),
        .I2(\write_data_control.wr_data_addr_le ),
        .I3(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ),
        .O(wb_wr_data_addr_w[3]));
  LUT4 #(
    .INIT(16'h00AC)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_9 
       (.I0(wr_data_pntr[1]),
        .I1(\write_data_control.wb_wr_data_addr_r [2]),
        .I2(\write_data_control.wr_data_addr_le ),
        .I3(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ),
        .O(wb_wr_data_addr_w[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [65:64]),
        .DIB(\write_buffer.wr_buf_in_data [63:62]),
        .DIC(\write_buffer.wr_buf_in_data [61:60]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[65:64]),
        .DOB(wr_buf_out_data_w[63:62]),
        .DOC(wr_buf_out_data_w[61:60]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_1 
       (.I0(app_wdf_data[65]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[65]),
        .O(\write_buffer.wr_buf_in_data [65]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_2 
       (.I0(app_wdf_data[64]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[64]),
        .O(\write_buffer.wr_buf_in_data [64]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_3 
       (.I0(app_wdf_data[63]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[63]),
        .O(\write_buffer.wr_buf_in_data [63]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_4 
       (.I0(app_wdf_data[62]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[62]),
        .O(\write_buffer.wr_buf_in_data [62]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_5 
       (.I0(app_wdf_data[61]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[61]),
        .O(\write_buffer.wr_buf_in_data [61]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_6 
       (.I0(app_wdf_data[60]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[60]),
        .O(\write_buffer.wr_buf_in_data [60]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [71:70]),
        .DIB(\write_buffer.wr_buf_in_data [69:68]),
        .DIC(\write_buffer.wr_buf_in_data [67:66]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[71:70]),
        .DOB(wr_buf_out_data_w[69:68]),
        .DOC(wr_buf_out_data_w[67:66]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_1 
       (.I0(app_wdf_data[71]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[71]),
        .O(\write_buffer.wr_buf_in_data [71]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_2 
       (.I0(app_wdf_data[70]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[70]),
        .O(\write_buffer.wr_buf_in_data [70]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_3 
       (.I0(app_wdf_data[69]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[69]),
        .O(\write_buffer.wr_buf_in_data [69]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_4 
       (.I0(app_wdf_data[68]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[68]),
        .O(\write_buffer.wr_buf_in_data [68]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_5 
       (.I0(app_wdf_data[67]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[67]),
        .O(\write_buffer.wr_buf_in_data [67]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_6 
       (.I0(app_wdf_data[66]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[66]),
        .O(\write_buffer.wr_buf_in_data [66]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [77:76]),
        .DIB(\write_buffer.wr_buf_in_data [75:74]),
        .DIC(\write_buffer.wr_buf_in_data [73:72]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[77:76]),
        .DOB(wr_buf_out_data_w[75:74]),
        .DOC(wr_buf_out_data_w[73:72]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_1 
       (.I0(app_wdf_data[77]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[77]),
        .O(\write_buffer.wr_buf_in_data [77]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_2 
       (.I0(app_wdf_data[76]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[76]),
        .O(\write_buffer.wr_buf_in_data [76]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_3 
       (.I0(app_wdf_data[75]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[75]),
        .O(\write_buffer.wr_buf_in_data [75]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_4 
       (.I0(app_wdf_data[74]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[74]),
        .O(\write_buffer.wr_buf_in_data [74]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_5 
       (.I0(app_wdf_data[73]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[73]),
        .O(\write_buffer.wr_buf_in_data [73]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_6 
       (.I0(app_wdf_data[72]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[72]),
        .O(\write_buffer.wr_buf_in_data [72]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [83:82]),
        .DIB(\write_buffer.wr_buf_in_data [81:80]),
        .DIC(\write_buffer.wr_buf_in_data [79:78]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[83:82]),
        .DOB(wr_buf_out_data_w[81:80]),
        .DOC(wr_buf_out_data_w[79:78]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_1 
       (.I0(app_wdf_data[83]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[83]),
        .O(\write_buffer.wr_buf_in_data [83]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_2 
       (.I0(app_wdf_data[82]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[82]),
        .O(\write_buffer.wr_buf_in_data [82]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_3 
       (.I0(app_wdf_data[81]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[81]),
        .O(\write_buffer.wr_buf_in_data [81]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_4 
       (.I0(app_wdf_data[80]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[80]),
        .O(\write_buffer.wr_buf_in_data [80]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_5 
       (.I0(app_wdf_data[79]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[79]),
        .O(\write_buffer.wr_buf_in_data [79]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_6 
       (.I0(app_wdf_data[78]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[78]),
        .O(\write_buffer.wr_buf_in_data [78]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [89:88]),
        .DIB(\write_buffer.wr_buf_in_data [87:86]),
        .DIC(\write_buffer.wr_buf_in_data [85:84]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[89:88]),
        .DOB(wr_buf_out_data_w[87:86]),
        .DOC(wr_buf_out_data_w[85:84]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_1 
       (.I0(app_wdf_data[89]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[89]),
        .O(\write_buffer.wr_buf_in_data [89]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_2 
       (.I0(app_wdf_data[88]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[88]),
        .O(\write_buffer.wr_buf_in_data [88]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_3 
       (.I0(app_wdf_data[87]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[87]),
        .O(\write_buffer.wr_buf_in_data [87]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_4 
       (.I0(app_wdf_data[86]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[86]),
        .O(\write_buffer.wr_buf_in_data [86]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_5 
       (.I0(app_wdf_data[85]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[85]),
        .O(\write_buffer.wr_buf_in_data [85]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_6 
       (.I0(app_wdf_data[84]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[84]),
        .O(\write_buffer.wr_buf_in_data [84]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [95:94]),
        .DIB(\write_buffer.wr_buf_in_data [93:92]),
        .DIC(\write_buffer.wr_buf_in_data [91:90]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[95:94]),
        .DOB(wr_buf_out_data_w[93:92]),
        .DOC(wr_buf_out_data_w[91:90]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_1 
       (.I0(app_wdf_data[95]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[95]),
        .O(\write_buffer.wr_buf_in_data [95]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_2 
       (.I0(app_wdf_data[94]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[94]),
        .O(\write_buffer.wr_buf_in_data [94]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_3 
       (.I0(app_wdf_data[93]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[93]),
        .O(\write_buffer.wr_buf_in_data [93]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_4 
       (.I0(app_wdf_data[92]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[92]),
        .O(\write_buffer.wr_buf_in_data [92]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_5 
       (.I0(app_wdf_data[91]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[91]),
        .O(\write_buffer.wr_buf_in_data [91]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_6 
       (.I0(app_wdf_data[90]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[90]),
        .O(\write_buffer.wr_buf_in_data [90]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [101:100]),
        .DIB(\write_buffer.wr_buf_in_data [99:98]),
        .DIC(\write_buffer.wr_buf_in_data [97:96]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[101:100]),
        .DOB(wr_buf_out_data_w[99:98]),
        .DOC(wr_buf_out_data_w[97:96]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_1 
       (.I0(app_wdf_data[101]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[101]),
        .O(\write_buffer.wr_buf_in_data [101]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_2 
       (.I0(app_wdf_data[100]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[100]),
        .O(\write_buffer.wr_buf_in_data [100]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_3 
       (.I0(app_wdf_data[99]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[99]),
        .O(\write_buffer.wr_buf_in_data [99]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_4 
       (.I0(app_wdf_data[98]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[98]),
        .O(\write_buffer.wr_buf_in_data [98]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_5 
       (.I0(app_wdf_data[97]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[97]),
        .O(\write_buffer.wr_buf_in_data [97]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_6 
       (.I0(app_wdf_data[96]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[96]),
        .O(\write_buffer.wr_buf_in_data [96]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [107:106]),
        .DIB(\write_buffer.wr_buf_in_data [105:104]),
        .DIC(\write_buffer.wr_buf_in_data [103:102]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[107:106]),
        .DOB(wr_buf_out_data_w[105:104]),
        .DOC(wr_buf_out_data_w[103:102]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_1 
       (.I0(app_wdf_data[107]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[107]),
        .O(\write_buffer.wr_buf_in_data [107]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_2 
       (.I0(app_wdf_data[106]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[106]),
        .O(\write_buffer.wr_buf_in_data [106]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_3 
       (.I0(app_wdf_data[105]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[105]),
        .O(\write_buffer.wr_buf_in_data [105]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_4 
       (.I0(app_wdf_data[104]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[104]),
        .O(\write_buffer.wr_buf_in_data [104]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_5 
       (.I0(app_wdf_data[103]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[103]),
        .O(\write_buffer.wr_buf_in_data [103]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_6 
       (.I0(app_wdf_data[102]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[102]),
        .O(\write_buffer.wr_buf_in_data [102]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [113:112]),
        .DIB(\write_buffer.wr_buf_in_data [111:110]),
        .DIC(\write_buffer.wr_buf_in_data [109:108]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[113:112]),
        .DOB(wr_buf_out_data_w[111:110]),
        .DOC(wr_buf_out_data_w[109:108]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_1 
       (.I0(app_wdf_data[113]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[113]),
        .O(\write_buffer.wr_buf_in_data [113]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_2 
       (.I0(app_wdf_data[112]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[112]),
        .O(\write_buffer.wr_buf_in_data [112]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_3 
       (.I0(app_wdf_data[111]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[111]),
        .O(\write_buffer.wr_buf_in_data [111]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_4 
       (.I0(app_wdf_data[110]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[110]),
        .O(\write_buffer.wr_buf_in_data [110]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_5 
       (.I0(app_wdf_data[109]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[109]),
        .O(\write_buffer.wr_buf_in_data [109]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_6 
       (.I0(app_wdf_data[108]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[108]),
        .O(\write_buffer.wr_buf_in_data [108]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [119:118]),
        .DIB(\write_buffer.wr_buf_in_data [117:116]),
        .DIC(\write_buffer.wr_buf_in_data [115:114]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[119:118]),
        .DOB(wr_buf_out_data_w[117:116]),
        .DOC(wr_buf_out_data_w[115:114]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_1 
       (.I0(app_wdf_data[119]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[119]),
        .O(\write_buffer.wr_buf_in_data [119]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_2 
       (.I0(app_wdf_data[118]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[118]),
        .O(\write_buffer.wr_buf_in_data [118]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_3 
       (.I0(app_wdf_data[117]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[117]),
        .O(\write_buffer.wr_buf_in_data [117]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_4 
       (.I0(app_wdf_data[116]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[116]),
        .O(\write_buffer.wr_buf_in_data [116]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_5 
       (.I0(app_wdf_data[115]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[115]),
        .O(\write_buffer.wr_buf_in_data [115]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_6 
       (.I0(app_wdf_data[114]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[114]),
        .O(\write_buffer.wr_buf_in_data [114]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [11:10]),
        .DIB(\write_buffer.wr_buf_in_data [9:8]),
        .DIC(\write_buffer.wr_buf_in_data [7:6]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[11:10]),
        .DOB(wr_buf_out_data_w[9:8]),
        .DOC(wr_buf_out_data_w[7:6]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_1 
       (.I0(app_wdf_data[11]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[11]),
        .O(\write_buffer.wr_buf_in_data [11]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_2 
       (.I0(app_wdf_data[10]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[10]),
        .O(\write_buffer.wr_buf_in_data [10]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_3 
       (.I0(app_wdf_data[9]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[9]),
        .O(\write_buffer.wr_buf_in_data [9]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_4 
       (.I0(app_wdf_data[8]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[8]),
        .O(\write_buffer.wr_buf_in_data [8]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_5 
       (.I0(app_wdf_data[7]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[7]),
        .O(\write_buffer.wr_buf_in_data [7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_6 
       (.I0(app_wdf_data[6]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[6]),
        .O(\write_buffer.wr_buf_in_data [6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [125:124]),
        .DIB(\write_buffer.wr_buf_in_data [123:122]),
        .DIC(\write_buffer.wr_buf_in_data [121:120]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[125:124]),
        .DOB(wr_buf_out_data_w[123:122]),
        .DOC(wr_buf_out_data_w[121:120]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_1 
       (.I0(app_wdf_data[125]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[125]),
        .O(\write_buffer.wr_buf_in_data [125]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_2 
       (.I0(app_wdf_data[124]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[124]),
        .O(\write_buffer.wr_buf_in_data [124]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_3 
       (.I0(app_wdf_data[123]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[123]),
        .O(\write_buffer.wr_buf_in_data [123]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_4 
       (.I0(app_wdf_data[122]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[122]),
        .O(\write_buffer.wr_buf_in_data [122]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_5 
       (.I0(app_wdf_data[121]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[121]),
        .O(\write_buffer.wr_buf_in_data [121]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_6 
       (.I0(app_wdf_data[120]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[120]),
        .O(\write_buffer.wr_buf_in_data [120]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [131:130]),
        .DIB(\write_buffer.wr_buf_in_data [129:128]),
        .DIC(\write_buffer.wr_buf_in_data [127:126]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[131:130]),
        .DOB(wr_buf_out_data_w[129:128]),
        .DOC(wr_buf_out_data_w[127:126]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_1 
       (.I0(app_wdf_mask[3]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[3]),
        .O(\write_buffer.wr_buf_in_data [131]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_2 
       (.I0(app_wdf_mask[2]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[2]),
        .O(\write_buffer.wr_buf_in_data [130]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_3 
       (.I0(app_wdf_mask[1]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[1]),
        .O(\write_buffer.wr_buf_in_data [129]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_4 
       (.I0(app_wdf_mask[0]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[0]),
        .O(\write_buffer.wr_buf_in_data [128]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_5 
       (.I0(app_wdf_data[127]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[127]),
        .O(\write_buffer.wr_buf_in_data [127]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_6 
       (.I0(app_wdf_data[126]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[126]),
        .O(\write_buffer.wr_buf_in_data [126]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [137:136]),
        .DIB(\write_buffer.wr_buf_in_data [135:134]),
        .DIC(\write_buffer.wr_buf_in_data [133:132]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[137:136]),
        .DOB(wr_buf_out_data_w[135:134]),
        .DOC(wr_buf_out_data_w[133:132]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_1 
       (.I0(app_wdf_mask[9]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[9]),
        .O(\write_buffer.wr_buf_in_data [137]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_2 
       (.I0(app_wdf_mask[8]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[8]),
        .O(\write_buffer.wr_buf_in_data [136]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_3 
       (.I0(app_wdf_mask[7]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[7]),
        .O(\write_buffer.wr_buf_in_data [135]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_4 
       (.I0(app_wdf_mask[6]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[6]),
        .O(\write_buffer.wr_buf_in_data [134]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_5 
       (.I0(app_wdf_mask[5]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[5]),
        .O(\write_buffer.wr_buf_in_data [133]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_6 
       (.I0(app_wdf_mask[4]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[4]),
        .O(\write_buffer.wr_buf_in_data [132]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [143:142]),
        .DIB(\write_buffer.wr_buf_in_data [141:140]),
        .DIC(\write_buffer.wr_buf_in_data [139:138]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[143:142]),
        .DOB(wr_buf_out_data_w[141:140]),
        .DOC(wr_buf_out_data_w[139:138]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_1 
       (.I0(app_wdf_mask[15]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[15]),
        .O(\write_buffer.wr_buf_in_data [143]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_2 
       (.I0(app_wdf_mask[14]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[14]),
        .O(\write_buffer.wr_buf_in_data [142]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_3 
       (.I0(app_wdf_mask[13]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[13]),
        .O(\write_buffer.wr_buf_in_data [141]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_4 
       (.I0(app_wdf_mask[12]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[12]),
        .O(\write_buffer.wr_buf_in_data [140]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_5 
       (.I0(app_wdf_mask[11]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[11]),
        .O(\write_buffer.wr_buf_in_data [139]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_6 
       (.I0(app_wdf_mask[10]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[10]),
        .O(\write_buffer.wr_buf_in_data [138]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [17:16]),
        .DIB(\write_buffer.wr_buf_in_data [15:14]),
        .DIC(\write_buffer.wr_buf_in_data [13:12]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[17:16]),
        .DOB(wr_buf_out_data_w[15:14]),
        .DOC(wr_buf_out_data_w[13:12]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_1 
       (.I0(app_wdf_data[17]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[17]),
        .O(\write_buffer.wr_buf_in_data [17]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_2 
       (.I0(app_wdf_data[16]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[16]),
        .O(\write_buffer.wr_buf_in_data [16]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_3 
       (.I0(app_wdf_data[15]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[15]),
        .O(\write_buffer.wr_buf_in_data [15]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_4 
       (.I0(app_wdf_data[14]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[14]),
        .O(\write_buffer.wr_buf_in_data [14]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_5 
       (.I0(app_wdf_data[13]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[13]),
        .O(\write_buffer.wr_buf_in_data [13]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_6 
       (.I0(app_wdf_data[12]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[12]),
        .O(\write_buffer.wr_buf_in_data [12]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [23:22]),
        .DIB(\write_buffer.wr_buf_in_data [21:20]),
        .DIC(\write_buffer.wr_buf_in_data [19:18]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[23:22]),
        .DOB(wr_buf_out_data_w[21:20]),
        .DOC(wr_buf_out_data_w[19:18]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_1 
       (.I0(app_wdf_data[23]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[23]),
        .O(\write_buffer.wr_buf_in_data [23]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_2 
       (.I0(app_wdf_data[22]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[22]),
        .O(\write_buffer.wr_buf_in_data [22]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_3 
       (.I0(app_wdf_data[21]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[21]),
        .O(\write_buffer.wr_buf_in_data [21]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_4 
       (.I0(app_wdf_data[20]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[20]),
        .O(\write_buffer.wr_buf_in_data [20]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_5 
       (.I0(app_wdf_data[19]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[19]),
        .O(\write_buffer.wr_buf_in_data [19]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_6 
       (.I0(app_wdf_data[18]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[18]),
        .O(\write_buffer.wr_buf_in_data [18]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [29:28]),
        .DIB(\write_buffer.wr_buf_in_data [27:26]),
        .DIC(\write_buffer.wr_buf_in_data [25:24]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[29:28]),
        .DOB(wr_buf_out_data_w[27:26]),
        .DOC(wr_buf_out_data_w[25:24]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_1 
       (.I0(app_wdf_data[29]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[29]),
        .O(\write_buffer.wr_buf_in_data [29]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_2 
       (.I0(app_wdf_data[28]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[28]),
        .O(\write_buffer.wr_buf_in_data [28]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_3 
       (.I0(app_wdf_data[27]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[27]),
        .O(\write_buffer.wr_buf_in_data [27]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_4 
       (.I0(app_wdf_data[26]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[26]),
        .O(\write_buffer.wr_buf_in_data [26]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_5 
       (.I0(app_wdf_data[25]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[25]),
        .O(\write_buffer.wr_buf_in_data [25]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_6 
       (.I0(app_wdf_data[24]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[24]),
        .O(\write_buffer.wr_buf_in_data [24]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [35:34]),
        .DIB(\write_buffer.wr_buf_in_data [33:32]),
        .DIC(\write_buffer.wr_buf_in_data [31:30]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[35:34]),
        .DOB(wr_buf_out_data_w[33:32]),
        .DOC(wr_buf_out_data_w[31:30]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_1 
       (.I0(app_wdf_data[35]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[35]),
        .O(\write_buffer.wr_buf_in_data [35]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_2 
       (.I0(app_wdf_data[34]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[34]),
        .O(\write_buffer.wr_buf_in_data [34]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_3 
       (.I0(app_wdf_data[33]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[33]),
        .O(\write_buffer.wr_buf_in_data [33]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_4 
       (.I0(app_wdf_data[32]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[32]),
        .O(\write_buffer.wr_buf_in_data [32]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_5 
       (.I0(app_wdf_data[31]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[31]),
        .O(\write_buffer.wr_buf_in_data [31]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_6 
       (.I0(app_wdf_data[30]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[30]),
        .O(\write_buffer.wr_buf_in_data [30]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [41:40]),
        .DIB(\write_buffer.wr_buf_in_data [39:38]),
        .DIC(\write_buffer.wr_buf_in_data [37:36]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[41:40]),
        .DOB(wr_buf_out_data_w[39:38]),
        .DOC(wr_buf_out_data_w[37:36]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_1 
       (.I0(app_wdf_data[41]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[41]),
        .O(\write_buffer.wr_buf_in_data [41]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_2 
       (.I0(app_wdf_data[40]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[40]),
        .O(\write_buffer.wr_buf_in_data [40]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_3 
       (.I0(app_wdf_data[39]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[39]),
        .O(\write_buffer.wr_buf_in_data [39]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_4 
       (.I0(app_wdf_data[38]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[38]),
        .O(\write_buffer.wr_buf_in_data [38]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_5 
       (.I0(app_wdf_data[37]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[37]),
        .O(\write_buffer.wr_buf_in_data [37]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_6 
       (.I0(app_wdf_data[36]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[36]),
        .O(\write_buffer.wr_buf_in_data [36]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [47:46]),
        .DIB(\write_buffer.wr_buf_in_data [45:44]),
        .DIC(\write_buffer.wr_buf_in_data [43:42]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[47:46]),
        .DOB(wr_buf_out_data_w[45:44]),
        .DOC(wr_buf_out_data_w[43:42]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_1 
       (.I0(app_wdf_data[47]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[47]),
        .O(\write_buffer.wr_buf_in_data [47]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_2 
       (.I0(app_wdf_data[46]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[46]),
        .O(\write_buffer.wr_buf_in_data [46]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_3 
       (.I0(app_wdf_data[45]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[45]),
        .O(\write_buffer.wr_buf_in_data [45]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_4 
       (.I0(app_wdf_data[44]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[44]),
        .O(\write_buffer.wr_buf_in_data [44]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_5 
       (.I0(app_wdf_data[43]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[43]),
        .O(\write_buffer.wr_buf_in_data [43]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_6 
       (.I0(app_wdf_data[42]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[42]),
        .O(\write_buffer.wr_buf_in_data [42]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [53:52]),
        .DIB(\write_buffer.wr_buf_in_data [51:50]),
        .DIC(\write_buffer.wr_buf_in_data [49:48]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[53:52]),
        .DOB(wr_buf_out_data_w[51:50]),
        .DOC(wr_buf_out_data_w[49:48]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_1 
       (.I0(app_wdf_data[53]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[53]),
        .O(\write_buffer.wr_buf_in_data [53]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_2 
       (.I0(app_wdf_data[52]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[52]),
        .O(\write_buffer.wr_buf_in_data [52]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_3 
       (.I0(app_wdf_data[51]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[51]),
        .O(\write_buffer.wr_buf_in_data [51]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_4 
       (.I0(app_wdf_data[50]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[50]),
        .O(\write_buffer.wr_buf_in_data [50]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_5 
       (.I0(app_wdf_data[49]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[49]),
        .O(\write_buffer.wr_buf_in_data [49]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_6 
       (.I0(app_wdf_data[48]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[48]),
        .O(\write_buffer.wr_buf_in_data [48]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [59:58]),
        .DIB(\write_buffer.wr_buf_in_data [57:56]),
        .DIC(\write_buffer.wr_buf_in_data [55:54]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[59:58]),
        .DOB(wr_buf_out_data_w[57:56]),
        .DOC(wr_buf_out_data_w[55:54]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(CLK),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_1 
       (.I0(app_wdf_data[59]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[59]),
        .O(\write_buffer.wr_buf_in_data [59]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_2 
       (.I0(app_wdf_data[58]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[58]),
        .O(\write_buffer.wr_buf_in_data [58]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_3 
       (.I0(app_wdf_data[57]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[57]),
        .O(\write_buffer.wr_buf_in_data [57]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_4 
       (.I0(app_wdf_data[56]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[56]),
        .O(\write_buffer.wr_buf_in_data [56]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_5 
       (.I0(app_wdf_data[55]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[55]),
        .O(\write_buffer.wr_buf_in_data [55]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_6 
       (.I0(app_wdf_data[54]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[54]),
        .O(\write_buffer.wr_buf_in_data [54]));
  FDRE \write_data_control.wb_wr_data_addr0_r_reg 
       (.C(CLK),
        .CE(1'b1),
        .D(\write_data_control.wb_wr_data_addr0_ns ),
        .Q(\write_data_control.wb_wr_data_addr0_r ),
        .R(1'b0));
  FDRE \write_data_control.wb_wr_data_addr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(wb_wr_data_addr_w[1]),
        .Q(\write_data_control.wb_wr_data_addr_r [1]),
        .R(1'b0));
  FDRE \write_data_control.wb_wr_data_addr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(wb_wr_data_addr_w[2]),
        .Q(\write_data_control.wb_wr_data_addr_r [2]),
        .R(1'b0));
  FDRE \write_data_control.wb_wr_data_addr_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(wb_wr_data_addr_w[3]),
        .Q(\write_data_control.wb_wr_data_addr_r [3]),
        .R(1'b0));
  FDRE \write_data_control.wb_wr_data_addr_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(wb_wr_data_addr_w[4]),
        .Q(\write_data_control.wb_wr_data_addr_r [4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \write_data_control.wr_data_indx_r[0]_i_1 
       (.I0(\write_data_control.wr_data_indx_r_reg [0]),
        .O(p_0_in__0__0[0]));
  LUT2 #(
    .INIT(4'h6)) 
    \write_data_control.wr_data_indx_r[1]_i_1 
       (.I0(\write_data_control.wr_data_indx_r_reg [0]),
        .I1(\write_data_control.wr_data_indx_r_reg [1]),
        .O(p_0_in__0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair655" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \write_data_control.wr_data_indx_r[2]_i_1 
       (.I0(\write_data_control.wr_data_indx_r_reg [0]),
        .I1(\write_data_control.wr_data_indx_r_reg [1]),
        .I2(\write_data_control.wr_data_indx_r_reg [2]),
        .O(p_0_in__0__0[2]));
  LUT6 #(
    .INIT(64'h1100FFFF01000100)) 
    \write_data_control.wr_data_indx_r[3]_i_1 
       (.I0(\write_data_control.wr_data_indx_r[3]_i_3_n_0 ),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ),
        .I2(\occupied_counter.occ_cnt_reg_n_0_[15] ),
        .I3(p_0_in__0_0),
        .I4(app_wdf_rdy_r_copy1),
        .I5(p_0_in),
        .O(\write_data_control.wr_data_addr_le ));
  (* SOFT_HLUTNM = "soft_lutpair655" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \write_data_control.wr_data_indx_r[3]_i_2 
       (.I0(\write_data_control.wr_data_indx_r_reg [2]),
        .I1(\write_data_control.wr_data_indx_r_reg [1]),
        .I2(\write_data_control.wr_data_indx_r_reg [0]),
        .I3(\write_data_control.wr_data_indx_r_reg [3]),
        .O(p_0_in__0__0[3]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00008000)) 
    \write_data_control.wr_data_indx_r[3]_i_3 
       (.I0(app_wdf_wren_r1),
        .I1(app_wdf_end_r1),
        .I2(app_wdf_rdy_r_copy1),
        .I3(p_4_in),
        .I4(p_0_in),
        .I5(app_wdf_rdy_r_copy3_reg_0),
        .O(\write_data_control.wr_data_indx_r[3]_i_3_n_0 ));
  FDSE \write_data_control.wr_data_indx_r_reg[0] 
       (.C(CLK),
        .CE(\write_data_control.wr_data_addr_le ),
        .D(p_0_in__0__0[0]),
        .Q(\write_data_control.wr_data_indx_r_reg [0]),
        .S(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \write_data_control.wr_data_indx_r_reg[1] 
       (.C(CLK),
        .CE(\write_data_control.wr_data_addr_le ),
        .D(p_0_in__0__0[1]),
        .Q(\write_data_control.wr_data_indx_r_reg [1]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \write_data_control.wr_data_indx_r_reg[2] 
       (.C(CLK),
        .CE(\write_data_control.wr_data_addr_le ),
        .D(p_0_in__0__0[2]),
        .Q(\write_data_control.wr_data_indx_r_reg [2]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
  FDRE \write_data_control.wr_data_indx_r_reg[3] 
       (.C(CLK),
        .CE(\write_data_control.wr_data_addr_le ),
        .D(p_0_in__0__0[3]),
        .Q(\write_data_control.wr_data_indx_r_reg [3]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
